1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller 4 * 5 * Copyright (C) 2015 Endless Mobile, Inc. 6 * Author: Carlo Caione <carlo@endlessm.com> 7 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/ioport.h> 20 #include <linux/platform_device.h> 21 #include <linux/of_platform.h> 22 #include <linux/timer.h> 23 #include <linux/types.h> 24 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/mmc.h> 27 #include <linux/mmc/sdio.h> 28 #include <linux/mmc/slot-gpio.h> 29 30 #define MESON_MX_SDIO_ARGU 0x00 31 32 #define MESON_MX_SDIO_SEND 0x04 33 #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0) 34 #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8) 35 #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16) 36 #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17) 37 #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18) 38 #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19) 39 #define MESON_MX_SDIO_SEND_DATA BIT(20) 40 #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21) 41 #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24) 42 43 #define MESON_MX_SDIO_CONF 0x08 44 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0 45 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10 46 #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10) 47 #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11) 48 #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12) 49 #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18) 50 #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19) 51 #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20) 52 #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21) 53 #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23) 54 #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29) 55 56 #define MESON_MX_SDIO_IRQS 0x0c 57 #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0) 58 #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4) 59 #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5) 60 #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6) 61 #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7) 62 #define MESON_MX_SDIO_IRQS_IF_INT BIT(8) 63 #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9) 64 #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12) 65 #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16) 66 #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17) 67 #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18) 68 #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19) 69 70 #define MESON_MX_SDIO_IRQC 0x10 71 #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3) 72 #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4) 73 #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6) 74 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8) 75 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9) 76 #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10) 77 #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15) 78 #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30) 79 #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31) 80 81 #define MESON_MX_SDIO_MULT 0x14 82 #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0) 83 #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2) 84 #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3) 85 #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4) 86 #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5) 87 #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8) 88 #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10) 89 #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11) 90 #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12) 91 92 #define MESON_MX_SDIO_ADDR 0x18 93 94 #define MESON_MX_SDIO_EXT 0x1c 95 #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16) 96 97 #define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024) 98 #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1) 99 #define MESON_MX_SDIO_MAX_SLOTS 3 100 101 struct meson_mx_mmc_host { 102 struct device *controller_dev; 103 104 struct clk *parent_clk; 105 struct clk *core_clk; 106 struct clk_divider cfg_div; 107 struct clk *cfg_div_clk; 108 struct clk_fixed_factor fixed_factor; 109 struct clk *fixed_factor_clk; 110 111 void __iomem *base; 112 int irq; 113 spinlock_t irq_lock; 114 115 struct timer_list cmd_timeout; 116 117 unsigned int slot_id; 118 struct mmc_host *mmc; 119 120 struct mmc_request *mrq; 121 struct mmc_command *cmd; 122 int error; 123 }; 124 125 static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask, 126 u32 val) 127 { 128 struct meson_mx_mmc_host *host = mmc_priv(mmc); 129 u32 regval; 130 131 regval = readl(host->base + reg); 132 regval &= ~mask; 133 regval |= (val & mask); 134 135 writel(regval, host->base + reg); 136 } 137 138 static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host) 139 { 140 writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC); 141 udelay(2); 142 } 143 144 static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd) 145 { 146 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 147 return cmd->mrq->cmd; 148 else if (mmc_op_multi(cmd->opcode) && 149 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 150 return cmd->mrq->stop; 151 else 152 return NULL; 153 } 154 155 static void meson_mx_mmc_start_cmd(struct mmc_host *mmc, 156 struct mmc_command *cmd) 157 { 158 struct meson_mx_mmc_host *host = mmc_priv(mmc); 159 unsigned int pack_size; 160 unsigned long irqflags, timeout; 161 u32 mult, send = 0, ext = 0; 162 163 host->cmd = cmd; 164 165 if (cmd->busy_timeout) 166 timeout = msecs_to_jiffies(cmd->busy_timeout); 167 else 168 timeout = msecs_to_jiffies(1000); 169 170 switch (mmc_resp_type(cmd)) { 171 case MMC_RSP_R1: 172 case MMC_RSP_R1B: 173 case MMC_RSP_R3: 174 /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */ 175 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45); 176 break; 177 case MMC_RSP_R2: 178 /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */ 179 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133); 180 send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8; 181 break; 182 default: 183 break; 184 } 185 186 if (!(cmd->flags & MMC_RSP_CRC)) 187 send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7; 188 189 if (cmd->flags & MMC_RSP_BUSY) 190 send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY; 191 192 if (cmd->data) { 193 send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, 194 (cmd->data->blocks - 1)); 195 196 pack_size = cmd->data->blksz * BITS_PER_BYTE; 197 if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 198 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4; 199 else 200 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1; 201 202 ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, 203 pack_size); 204 205 if (cmd->data->flags & MMC_DATA_WRITE) 206 send |= MESON_MX_SDIO_SEND_DATA; 207 else 208 send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA; 209 210 cmd->data->bytes_xfered = 0; 211 } 212 213 send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK, 214 (0x40 | cmd->opcode)); 215 216 spin_lock_irqsave(&host->irq_lock, irqflags); 217 218 mult = readl(host->base + MESON_MX_SDIO_MULT); 219 mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK; 220 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id); 221 mult |= BIT(31); 222 writel(mult, host->base + MESON_MX_SDIO_MULT); 223 224 /* enable the CMD done interrupt */ 225 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC, 226 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN, 227 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN); 228 229 /* clear pending interrupts */ 230 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS, 231 MESON_MX_SDIO_IRQS_CMD_INT, 232 MESON_MX_SDIO_IRQS_CMD_INT); 233 234 writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU); 235 writel(ext, host->base + MESON_MX_SDIO_EXT); 236 writel(send, host->base + MESON_MX_SDIO_SEND); 237 238 spin_unlock_irqrestore(&host->irq_lock, irqflags); 239 240 mod_timer(&host->cmd_timeout, jiffies + timeout); 241 } 242 243 static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host) 244 { 245 struct mmc_request *mrq; 246 247 mrq = host->mrq; 248 249 host->mrq = NULL; 250 host->cmd = NULL; 251 252 mmc_request_done(host->mmc, mrq); 253 } 254 255 static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 256 { 257 struct meson_mx_mmc_host *host = mmc_priv(mmc); 258 unsigned short vdd = ios->vdd; 259 unsigned long clk_rate = ios->clock; 260 261 switch (ios->bus_width) { 262 case MMC_BUS_WIDTH_1: 263 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, 264 MESON_MX_SDIO_CONF_BUS_WIDTH, 0); 265 break; 266 267 case MMC_BUS_WIDTH_4: 268 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, 269 MESON_MX_SDIO_CONF_BUS_WIDTH, 270 MESON_MX_SDIO_CONF_BUS_WIDTH); 271 break; 272 273 case MMC_BUS_WIDTH_8: 274 default: 275 dev_err(mmc_dev(mmc), "unsupported bus width: %d\n", 276 ios->bus_width); 277 host->error = -EINVAL; 278 return; 279 } 280 281 host->error = clk_set_rate(host->cfg_div_clk, ios->clock); 282 if (host->error) { 283 dev_warn(mmc_dev(mmc), 284 "failed to set MMC clock to %lu: %d\n", 285 clk_rate, host->error); 286 return; 287 } 288 289 mmc->actual_clock = clk_get_rate(host->cfg_div_clk); 290 291 switch (ios->power_mode) { 292 case MMC_POWER_OFF: 293 vdd = 0; 294 /* fall through */ 295 case MMC_POWER_UP: 296 if (!IS_ERR(mmc->supply.vmmc)) { 297 host->error = mmc_regulator_set_ocr(mmc, 298 mmc->supply.vmmc, 299 vdd); 300 if (host->error) 301 return; 302 } 303 break; 304 } 305 } 306 307 static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq) 308 { 309 struct mmc_data *data = mrq->data; 310 int dma_len; 311 struct scatterlist *sg; 312 313 if (!data) 314 return 0; 315 316 sg = data->sg; 317 if (sg->offset & 3 || sg->length & 3) { 318 dev_err(mmc_dev(mmc), 319 "unaligned scatterlist: offset %x length %d\n", 320 sg->offset, sg->length); 321 return -EINVAL; 322 } 323 324 dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 325 mmc_get_dma_dir(data)); 326 if (dma_len <= 0) { 327 dev_err(mmc_dev(mmc), "dma_map_sg failed\n"); 328 return -ENOMEM; 329 } 330 331 return 0; 332 } 333 334 static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 335 { 336 struct meson_mx_mmc_host *host = mmc_priv(mmc); 337 struct mmc_command *cmd = mrq->cmd; 338 339 if (!host->error) 340 host->error = meson_mx_mmc_map_dma(mmc, mrq); 341 342 if (host->error) { 343 cmd->error = host->error; 344 mmc_request_done(mmc, mrq); 345 return; 346 } 347 348 host->mrq = mrq; 349 350 if (mrq->data) 351 writel(sg_dma_address(mrq->data->sg), 352 host->base + MESON_MX_SDIO_ADDR); 353 354 if (mrq->sbc) 355 meson_mx_mmc_start_cmd(mmc, mrq->sbc); 356 else 357 meson_mx_mmc_start_cmd(mmc, mrq->cmd); 358 } 359 360 static void meson_mx_mmc_read_response(struct mmc_host *mmc, 361 struct mmc_command *cmd) 362 { 363 struct meson_mx_mmc_host *host = mmc_priv(mmc); 364 u32 mult; 365 int i, resp[4]; 366 367 mult = readl(host->base + MESON_MX_SDIO_MULT); 368 mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX; 369 mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK; 370 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0); 371 writel(mult, host->base + MESON_MX_SDIO_MULT); 372 373 if (cmd->flags & MMC_RSP_136) { 374 for (i = 0; i <= 3; i++) 375 resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU); 376 cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff); 377 cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff); 378 cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff); 379 cmd->resp[3] = (resp[3] << 8); 380 } else if (cmd->flags & MMC_RSP_PRESENT) { 381 cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU); 382 } 383 } 384 385 static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host, 386 u32 irqs, u32 send) 387 { 388 struct mmc_command *cmd = host->cmd; 389 390 /* 391 * NOTE: even though it shouldn't happen we sometimes get command 392 * interrupts twice (at least this is what it looks like). Ideally 393 * we find out why this happens and warn here as soon as it occurs. 394 */ 395 if (!cmd) 396 return IRQ_HANDLED; 397 398 cmd->error = 0; 399 meson_mx_mmc_read_response(host->mmc, cmd); 400 401 if (cmd->data) { 402 if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) || 403 (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK))) 404 cmd->error = -EILSEQ; 405 } else { 406 if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) || 407 (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7))) 408 cmd->error = -EILSEQ; 409 } 410 411 return IRQ_WAKE_THREAD; 412 } 413 414 static irqreturn_t meson_mx_mmc_irq(int irq, void *data) 415 { 416 struct meson_mx_mmc_host *host = (void *) data; 417 u32 irqs, send; 418 unsigned long irqflags; 419 irqreturn_t ret; 420 421 spin_lock_irqsave(&host->irq_lock, irqflags); 422 423 irqs = readl(host->base + MESON_MX_SDIO_IRQS); 424 send = readl(host->base + MESON_MX_SDIO_SEND); 425 426 if (irqs & MESON_MX_SDIO_IRQS_CMD_INT) 427 ret = meson_mx_mmc_process_cmd_irq(host, irqs, send); 428 else 429 ret = IRQ_HANDLED; 430 431 /* finally ACK all pending interrupts */ 432 writel(irqs, host->base + MESON_MX_SDIO_IRQS); 433 434 spin_unlock_irqrestore(&host->irq_lock, irqflags); 435 436 return ret; 437 } 438 439 static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data) 440 { 441 struct meson_mx_mmc_host *host = (void *) irq_data; 442 struct mmc_command *cmd = host->cmd, *next_cmd; 443 444 if (WARN_ON(!cmd)) 445 return IRQ_HANDLED; 446 447 del_timer_sync(&host->cmd_timeout); 448 449 if (cmd->data) { 450 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg, 451 cmd->data->sg_len, 452 mmc_get_dma_dir(cmd->data)); 453 454 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks; 455 } 456 457 next_cmd = meson_mx_mmc_get_next_cmd(cmd); 458 if (next_cmd) 459 meson_mx_mmc_start_cmd(host->mmc, next_cmd); 460 else 461 meson_mx_mmc_request_done(host); 462 463 return IRQ_HANDLED; 464 } 465 466 static void meson_mx_mmc_timeout(struct timer_list *t) 467 { 468 struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout); 469 unsigned long irqflags; 470 u32 irqc; 471 472 spin_lock_irqsave(&host->irq_lock, irqflags); 473 474 /* disable the CMD interrupt */ 475 irqc = readl(host->base + MESON_MX_SDIO_IRQC); 476 irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN; 477 writel(irqc, host->base + MESON_MX_SDIO_IRQC); 478 479 spin_unlock_irqrestore(&host->irq_lock, irqflags); 480 481 /* 482 * skip the timeout handling if the interrupt handler already processed 483 * the command. 484 */ 485 if (!host->cmd) 486 return; 487 488 dev_dbg(mmc_dev(host->mmc), 489 "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n", 490 host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS), 491 readl(host->base + MESON_MX_SDIO_ARGU)); 492 493 host->cmd->error = -ETIMEDOUT; 494 495 meson_mx_mmc_request_done(host); 496 } 497 498 static struct mmc_host_ops meson_mx_mmc_ops = { 499 .request = meson_mx_mmc_request, 500 .set_ios = meson_mx_mmc_set_ios, 501 .get_cd = mmc_gpio_get_cd, 502 .get_ro = mmc_gpio_get_ro, 503 }; 504 505 static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent) 506 { 507 struct device_node *slot_node; 508 struct platform_device *pdev; 509 510 /* 511 * TODO: the MMC core framework currently does not support 512 * controllers with multiple slots properly. So we only register 513 * the first slot for now 514 */ 515 slot_node = of_get_compatible_child(parent->of_node, "mmc-slot"); 516 if (!slot_node) { 517 dev_warn(parent, "no 'mmc-slot' sub-node found\n"); 518 return ERR_PTR(-ENOENT); 519 } 520 521 pdev = of_platform_device_create(slot_node, NULL, parent); 522 of_node_put(slot_node); 523 524 return pdev; 525 } 526 527 static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host) 528 { 529 struct mmc_host *mmc = host->mmc; 530 struct device *slot_dev = mmc_dev(mmc); 531 int ret; 532 533 if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) { 534 dev_err(slot_dev, "missing 'reg' property\n"); 535 return -EINVAL; 536 } 537 538 if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) { 539 dev_err(slot_dev, "invalid 'reg' property value %d\n", 540 host->slot_id); 541 return -EINVAL; 542 } 543 544 /* Get regulators and the supported OCR mask */ 545 ret = mmc_regulator_get_supply(mmc); 546 if (ret) 547 return ret; 548 549 mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE; 550 mmc->max_seg_size = mmc->max_req_size; 551 mmc->max_blk_count = 552 FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, 553 0xffffffff); 554 mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, 555 0xffffffff); 556 mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS); 557 mmc->max_blk_size /= BITS_PER_BYTE; 558 559 /* Get the min and max supported clock rates */ 560 mmc->f_min = clk_round_rate(host->cfg_div_clk, 1); 561 mmc->f_max = clk_round_rate(host->cfg_div_clk, 562 clk_get_rate(host->parent_clk)); 563 564 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY; 565 mmc->ops = &meson_mx_mmc_ops; 566 567 ret = mmc_of_parse(mmc); 568 if (ret) 569 return ret; 570 571 ret = mmc_add_host(mmc); 572 if (ret) 573 return ret; 574 575 return 0; 576 } 577 578 static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host) 579 { 580 struct clk_init_data init; 581 const char *clk_div_parent, *clk_fixed_factor_parent; 582 583 clk_fixed_factor_parent = __clk_get_name(host->parent_clk); 584 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, 585 "%s#fixed_factor", 586 dev_name(host->controller_dev)); 587 if (!init.name) 588 return -ENOMEM; 589 590 init.ops = &clk_fixed_factor_ops; 591 init.flags = 0; 592 init.parent_names = &clk_fixed_factor_parent; 593 init.num_parents = 1; 594 host->fixed_factor.div = 2; 595 host->fixed_factor.mult = 1; 596 host->fixed_factor.hw.init = &init; 597 598 host->fixed_factor_clk = devm_clk_register(host->controller_dev, 599 &host->fixed_factor.hw); 600 if (WARN_ON(IS_ERR(host->fixed_factor_clk))) 601 return PTR_ERR(host->fixed_factor_clk); 602 603 clk_div_parent = __clk_get_name(host->fixed_factor_clk); 604 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, 605 "%s#div", dev_name(host->controller_dev)); 606 if (!init.name) 607 return -ENOMEM; 608 609 init.ops = &clk_divider_ops; 610 init.flags = CLK_SET_RATE_PARENT; 611 init.parent_names = &clk_div_parent; 612 init.num_parents = 1; 613 host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF; 614 host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; 615 host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; 616 host->cfg_div.hw.init = &init; 617 host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO; 618 619 host->cfg_div_clk = devm_clk_register(host->controller_dev, 620 &host->cfg_div.hw); 621 if (WARN_ON(IS_ERR(host->cfg_div_clk))) 622 return PTR_ERR(host->cfg_div_clk); 623 624 return 0; 625 } 626 627 static int meson_mx_mmc_probe(struct platform_device *pdev) 628 { 629 struct platform_device *slot_pdev; 630 struct mmc_host *mmc; 631 struct meson_mx_mmc_host *host; 632 int ret, irq; 633 u32 conf; 634 635 slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev); 636 if (!slot_pdev) 637 return -ENODEV; 638 else if (IS_ERR(slot_pdev)) 639 return PTR_ERR(slot_pdev); 640 641 mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev); 642 if (!mmc) { 643 ret = -ENOMEM; 644 goto error_unregister_slot_pdev; 645 } 646 647 host = mmc_priv(mmc); 648 host->mmc = mmc; 649 host->controller_dev = &pdev->dev; 650 651 spin_lock_init(&host->irq_lock); 652 timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0); 653 654 platform_set_drvdata(pdev, host); 655 656 host->base = devm_platform_ioremap_resource(pdev, 0); 657 if (IS_ERR(host->base)) { 658 ret = PTR_ERR(host->base); 659 goto error_free_mmc; 660 } 661 662 irq = platform_get_irq(pdev, 0); 663 ret = devm_request_threaded_irq(host->controller_dev, irq, 664 meson_mx_mmc_irq, 665 meson_mx_mmc_irq_thread, IRQF_ONESHOT, 666 NULL, host); 667 if (ret) 668 goto error_free_mmc; 669 670 host->core_clk = devm_clk_get(host->controller_dev, "core"); 671 if (IS_ERR(host->core_clk)) { 672 ret = PTR_ERR(host->core_clk); 673 goto error_free_mmc; 674 } 675 676 host->parent_clk = devm_clk_get(host->controller_dev, "clkin"); 677 if (IS_ERR(host->parent_clk)) { 678 ret = PTR_ERR(host->parent_clk); 679 goto error_free_mmc; 680 } 681 682 ret = meson_mx_mmc_register_clks(host); 683 if (ret) 684 goto error_free_mmc; 685 686 ret = clk_prepare_enable(host->core_clk); 687 if (ret) { 688 dev_err(host->controller_dev, "Failed to enable core clock\n"); 689 goto error_free_mmc; 690 } 691 692 ret = clk_prepare_enable(host->cfg_div_clk); 693 if (ret) { 694 dev_err(host->controller_dev, "Failed to enable MMC clock\n"); 695 goto error_disable_core_clk; 696 } 697 698 conf = 0; 699 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39); 700 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3); 701 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2); 702 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2); 703 writel(conf, host->base + MESON_MX_SDIO_CONF); 704 705 meson_mx_mmc_soft_reset(host); 706 707 ret = meson_mx_mmc_add_host(host); 708 if (ret) 709 goto error_disable_clks; 710 711 return 0; 712 713 error_disable_clks: 714 clk_disable_unprepare(host->cfg_div_clk); 715 error_disable_core_clk: 716 clk_disable_unprepare(host->core_clk); 717 error_free_mmc: 718 mmc_free_host(mmc); 719 error_unregister_slot_pdev: 720 of_platform_device_destroy(&slot_pdev->dev, NULL); 721 return ret; 722 } 723 724 static int meson_mx_mmc_remove(struct platform_device *pdev) 725 { 726 struct meson_mx_mmc_host *host = platform_get_drvdata(pdev); 727 struct device *slot_dev = mmc_dev(host->mmc); 728 729 del_timer_sync(&host->cmd_timeout); 730 731 mmc_remove_host(host->mmc); 732 733 of_platform_device_destroy(slot_dev, NULL); 734 735 clk_disable_unprepare(host->cfg_div_clk); 736 clk_disable_unprepare(host->core_clk); 737 738 mmc_free_host(host->mmc); 739 740 return 0; 741 } 742 743 static const struct of_device_id meson_mx_mmc_of_match[] = { 744 { .compatible = "amlogic,meson8-sdio", }, 745 { .compatible = "amlogic,meson8b-sdio", }, 746 { /* sentinel */ } 747 }; 748 MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match); 749 750 static struct platform_driver meson_mx_mmc_driver = { 751 .probe = meson_mx_mmc_probe, 752 .remove = meson_mx_mmc_remove, 753 .driver = { 754 .name = "meson-mx-sdio", 755 .of_match_table = of_match_ptr(meson_mx_mmc_of_match), 756 }, 757 }; 758 759 module_platform_driver(meson_mx_mmc_driver); 760 761 MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver"); 762 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>"); 763 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 764 MODULE_LICENSE("GPL v2"); 765