1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ioport.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/slot-gpio.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitfield.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "meson-gx-mmc" 32 33 #define SD_EMMC_CLOCK 0x0 34 #define CLK_DIV_MASK GENMASK(5, 0) 35 #define CLK_SRC_MASK GENMASK(7, 6) 36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 39 #define CLK_PHASE_0 0 40 #define CLK_PHASE_180 2 41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43 #define CLK_V2_ALWAYS_ON BIT(24) 44 45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 47 #define CLK_V3_ALWAYS_ON BIT(28) 48 49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 51 #define CLK_ALWAYS_ON(h) (h->data->always_on) 52 53 #define SD_EMMC_DELAY 0x4 54 #define SD_EMMC_ADJUST 0x8 55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 56 #define ADJUST_DS_EN BIT(15) 57 #define ADJUST_ADJ_EN BIT(13) 58 59 #define SD_EMMC_DELAY1 0x4 60 #define SD_EMMC_DELAY2 0x8 61 #define SD_EMMC_V3_ADJUST 0xc 62 63 #define SD_EMMC_CALOUT 0x10 64 #define SD_EMMC_START 0x40 65 #define START_DESC_INIT BIT(0) 66 #define START_DESC_BUSY BIT(1) 67 #define START_DESC_ADDR_MASK GENMASK(31, 2) 68 69 #define SD_EMMC_CFG 0x44 70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 71 #define CFG_BUS_WIDTH_1 0x0 72 #define CFG_BUS_WIDTH_4 0x1 73 #define CFG_BUS_WIDTH_8 0x2 74 #define CFG_DDR BIT(2) 75 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 77 #define CFG_RC_CC_MASK GENMASK(15, 12) 78 #define CFG_STOP_CLOCK BIT(22) 79 #define CFG_CLK_ALWAYS_ON BIT(18) 80 #define CFG_CHK_DS BIT(20) 81 #define CFG_AUTO_CLK BIT(23) 82 #define CFG_ERR_ABORT BIT(27) 83 84 #define SD_EMMC_STATUS 0x48 85 #define STATUS_BUSY BIT(31) 86 #define STATUS_DESC_BUSY BIT(30) 87 #define STATUS_DATI GENMASK(23, 16) 88 89 #define SD_EMMC_IRQ_EN 0x4c 90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 91 #define IRQ_TXD_ERR BIT(8) 92 #define IRQ_DESC_ERR BIT(9) 93 #define IRQ_RESP_ERR BIT(10) 94 #define IRQ_CRC_ERR \ 95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 96 #define IRQ_RESP_TIMEOUT BIT(11) 97 #define IRQ_DESC_TIMEOUT BIT(12) 98 #define IRQ_TIMEOUTS \ 99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 100 #define IRQ_END_OF_CHAIN BIT(13) 101 #define IRQ_RESP_STATUS BIT(14) 102 #define IRQ_SDIO BIT(15) 103 #define IRQ_EN_MASK \ 104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 105 IRQ_SDIO) 106 107 #define SD_EMMC_CMD_CFG 0x50 108 #define SD_EMMC_CMD_ARG 0x54 109 #define SD_EMMC_CMD_DAT 0x58 110 #define SD_EMMC_CMD_RSP 0x5c 111 #define SD_EMMC_CMD_RSP1 0x60 112 #define SD_EMMC_CMD_RSP2 0x64 113 #define SD_EMMC_CMD_RSP3 0x68 114 115 #define SD_EMMC_RXD 0x94 116 #define SD_EMMC_TXD 0x94 117 #define SD_EMMC_LAST_REG SD_EMMC_TXD 118 119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536 120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 121 122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 128 129 #define SD_EMMC_PRE_REQ_DONE BIT(0) 130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 131 132 #define MUX_CLK_NUM_PARENTS 2 133 134 struct meson_mmc_data { 135 unsigned int tx_delay_mask; 136 unsigned int rx_delay_mask; 137 unsigned int always_on; 138 unsigned int adjust; 139 }; 140 141 struct sd_emmc_desc { 142 u32 cmd_cfg; 143 u32 cmd_arg; 144 u32 cmd_data; 145 u32 cmd_resp; 146 }; 147 148 struct meson_host { 149 struct device *dev; 150 struct meson_mmc_data *data; 151 struct mmc_host *mmc; 152 struct mmc_command *cmd; 153 154 void __iomem *regs; 155 struct clk *core_clk; 156 struct clk *mux_clk; 157 struct clk *mmc_clk; 158 unsigned long req_rate; 159 bool ddr; 160 161 bool dram_access_quirk; 162 163 struct pinctrl *pinctrl; 164 struct pinctrl_state *pins_clk_gate; 165 166 unsigned int bounce_buf_size; 167 void *bounce_buf; 168 dma_addr_t bounce_dma_addr; 169 struct sd_emmc_desc *descs; 170 dma_addr_t descs_dma_addr; 171 172 int irq; 173 174 bool vqmmc_enabled; 175 }; 176 177 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 178 #define CMD_CFG_BLOCK_MODE BIT(9) 179 #define CMD_CFG_R1B BIT(10) 180 #define CMD_CFG_END_OF_CHAIN BIT(11) 181 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 182 #define CMD_CFG_NO_RESP BIT(16) 183 #define CMD_CFG_NO_CMD BIT(17) 184 #define CMD_CFG_DATA_IO BIT(18) 185 #define CMD_CFG_DATA_WR BIT(19) 186 #define CMD_CFG_RESP_NOCRC BIT(20) 187 #define CMD_CFG_RESP_128 BIT(21) 188 #define CMD_CFG_RESP_NUM BIT(22) 189 #define CMD_CFG_DATA_NUM BIT(23) 190 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 191 #define CMD_CFG_ERROR BIT(30) 192 #define CMD_CFG_OWNER BIT(31) 193 194 #define CMD_DATA_MASK GENMASK(31, 2) 195 #define CMD_DATA_BIG_ENDIAN BIT(1) 196 #define CMD_DATA_SRAM BIT(0) 197 #define CMD_RESP_MASK GENMASK(31, 1) 198 #define CMD_RESP_SRAM BIT(0) 199 200 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 201 { 202 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 203 204 if (!timeout) 205 return SD_EMMC_CMD_TIMEOUT_DATA; 206 207 timeout = roundup_pow_of_two(timeout); 208 209 return min(timeout, 32768U); /* max. 2^15 ms */ 210 } 211 212 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 213 { 214 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 215 return cmd->mrq->cmd; 216 else if (mmc_op_multi(cmd->opcode) && 217 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 218 return cmd->mrq->stop; 219 else 220 return NULL; 221 } 222 223 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 224 struct mmc_request *mrq) 225 { 226 struct meson_host *host = mmc_priv(mmc); 227 struct mmc_data *data = mrq->data; 228 struct scatterlist *sg; 229 int i; 230 231 /* 232 * When Controller DMA cannot directly access DDR memory, disable 233 * support for Chain Mode to directly use the internal SRAM using 234 * the bounce buffer mode. 235 */ 236 if (host->dram_access_quirk) 237 return; 238 239 if (data->blocks > 1) { 240 /* 241 * In block mode DMA descriptor format, "length" field indicates 242 * number of blocks and there is no way to pass DMA size that 243 * is not multiple of SDIO block size, making it impossible to 244 * tie more than one memory buffer with single SDIO block. 245 * Block mode sg buffer size should be aligned with SDIO block 246 * size, otherwise chain mode could not be used. 247 */ 248 for_each_sg(data->sg, sg, data->sg_len, i) { 249 if (sg->length % data->blksz) { 250 WARN_ONCE(1, "unaligned sg len %u blksize %u\n", 251 sg->length, data->blksz); 252 return; 253 } 254 } 255 } 256 257 for_each_sg(data->sg, sg, data->sg_len, i) { 258 /* check for 8 byte alignment */ 259 if (sg->offset % 8) { 260 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 261 return; 262 } 263 } 264 265 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 266 } 267 268 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 269 { 270 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 271 } 272 273 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 274 { 275 return data && data->flags & MMC_DATA_READ && 276 !meson_mmc_desc_chain_mode(data); 277 } 278 279 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 280 { 281 struct mmc_data *data = mrq->data; 282 283 if (!data) 284 return; 285 286 meson_mmc_get_transfer_mode(mmc, mrq); 287 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 288 289 if (!meson_mmc_desc_chain_mode(data)) 290 return; 291 292 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 293 mmc_get_dma_dir(data)); 294 if (!data->sg_count) 295 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 296 } 297 298 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 299 int err) 300 { 301 struct mmc_data *data = mrq->data; 302 303 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 304 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 305 mmc_get_dma_dir(data)); 306 } 307 308 /* 309 * Gating the clock on this controller is tricky. It seems the mmc clock 310 * is also used by the controller. It may crash during some operation if the 311 * clock is stopped. The safest thing to do, whenever possible, is to keep 312 * clock running at stop it at the pad using the pinmux. 313 */ 314 static void meson_mmc_clk_gate(struct meson_host *host) 315 { 316 u32 cfg; 317 318 if (host->pins_clk_gate) { 319 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 320 } else { 321 /* 322 * If the pinmux is not provided - default to the classic and 323 * unsafe method 324 */ 325 cfg = readl(host->regs + SD_EMMC_CFG); 326 cfg |= CFG_STOP_CLOCK; 327 writel(cfg, host->regs + SD_EMMC_CFG); 328 } 329 } 330 331 static void meson_mmc_clk_ungate(struct meson_host *host) 332 { 333 u32 cfg; 334 335 if (host->pins_clk_gate) 336 pinctrl_select_default_state(host->dev); 337 338 /* Make sure the clock is not stopped in the controller */ 339 cfg = readl(host->regs + SD_EMMC_CFG); 340 cfg &= ~CFG_STOP_CLOCK; 341 writel(cfg, host->regs + SD_EMMC_CFG); 342 } 343 344 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 345 bool ddr) 346 { 347 struct mmc_host *mmc = host->mmc; 348 int ret; 349 u32 cfg; 350 351 /* Same request - bail-out */ 352 if (host->ddr == ddr && host->req_rate == rate) 353 return 0; 354 355 /* stop clock */ 356 meson_mmc_clk_gate(host); 357 host->req_rate = 0; 358 mmc->actual_clock = 0; 359 360 /* return with clock being stopped */ 361 if (!rate) 362 return 0; 363 364 /* Stop the clock during rate change to avoid glitches */ 365 cfg = readl(host->regs + SD_EMMC_CFG); 366 cfg |= CFG_STOP_CLOCK; 367 writel(cfg, host->regs + SD_EMMC_CFG); 368 369 if (ddr) { 370 /* DDR modes require higher module clock */ 371 rate <<= 1; 372 cfg |= CFG_DDR; 373 } else { 374 cfg &= ~CFG_DDR; 375 } 376 writel(cfg, host->regs + SD_EMMC_CFG); 377 host->ddr = ddr; 378 379 ret = clk_set_rate(host->mmc_clk, rate); 380 if (ret) { 381 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 382 rate, ret); 383 return ret; 384 } 385 386 host->req_rate = rate; 387 mmc->actual_clock = clk_get_rate(host->mmc_clk); 388 389 /* We should report the real output frequency of the controller */ 390 if (ddr) { 391 host->req_rate >>= 1; 392 mmc->actual_clock >>= 1; 393 } 394 395 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 396 if (rate != mmc->actual_clock) 397 dev_dbg(host->dev, "requested rate was %lu\n", rate); 398 399 /* (re)start clock */ 400 meson_mmc_clk_ungate(host); 401 402 return 0; 403 } 404 405 /* 406 * The SD/eMMC IP block has an internal mux and divider used for 407 * generating the MMC clock. Use the clock framework to create and 408 * manage these clocks. 409 */ 410 static int meson_mmc_clk_init(struct meson_host *host) 411 { 412 struct clk_init_data init; 413 struct clk_mux *mux; 414 struct clk_divider *div; 415 char clk_name[32]; 416 int i, ret = 0; 417 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 418 const char *clk_parent[1]; 419 u32 clk_reg; 420 421 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 422 clk_reg = CLK_ALWAYS_ON(host); 423 clk_reg |= CLK_DIV_MASK; 424 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 425 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 426 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 427 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 428 429 /* get the mux parents */ 430 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 431 struct clk *clk; 432 char name[16]; 433 434 snprintf(name, sizeof(name), "clkin%d", i); 435 clk = devm_clk_get(host->dev, name); 436 if (IS_ERR(clk)) 437 return dev_err_probe(host->dev, PTR_ERR(clk), 438 "Missing clock %s\n", name); 439 440 mux_parent_names[i] = __clk_get_name(clk); 441 } 442 443 /* create the mux */ 444 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 445 if (!mux) 446 return -ENOMEM; 447 448 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 449 init.name = clk_name; 450 init.ops = &clk_mux_ops; 451 init.flags = 0; 452 init.parent_names = mux_parent_names; 453 init.num_parents = MUX_CLK_NUM_PARENTS; 454 455 mux->reg = host->regs + SD_EMMC_CLOCK; 456 mux->shift = __ffs(CLK_SRC_MASK); 457 mux->mask = CLK_SRC_MASK >> mux->shift; 458 mux->hw.init = &init; 459 460 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 461 if (WARN_ON(IS_ERR(host->mux_clk))) 462 return PTR_ERR(host->mux_clk); 463 464 /* create the divider */ 465 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 466 if (!div) 467 return -ENOMEM; 468 469 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 470 init.name = clk_name; 471 init.ops = &clk_divider_ops; 472 init.flags = CLK_SET_RATE_PARENT; 473 clk_parent[0] = __clk_get_name(host->mux_clk); 474 init.parent_names = clk_parent; 475 init.num_parents = 1; 476 477 div->reg = host->regs + SD_EMMC_CLOCK; 478 div->shift = __ffs(CLK_DIV_MASK); 479 div->width = __builtin_popcountl(CLK_DIV_MASK); 480 div->hw.init = &init; 481 div->flags = CLK_DIVIDER_ONE_BASED; 482 483 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 484 if (WARN_ON(IS_ERR(host->mmc_clk))) 485 return PTR_ERR(host->mmc_clk); 486 487 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 488 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 489 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 490 if (ret) 491 return ret; 492 493 return clk_prepare_enable(host->mmc_clk); 494 } 495 496 static void meson_mmc_disable_resampling(struct meson_host *host) 497 { 498 unsigned int val = readl(host->regs + host->data->adjust); 499 500 val &= ~ADJUST_ADJ_EN; 501 writel(val, host->regs + host->data->adjust); 502 } 503 504 static void meson_mmc_reset_resampling(struct meson_host *host) 505 { 506 unsigned int val; 507 508 meson_mmc_disable_resampling(host); 509 510 val = readl(host->regs + host->data->adjust); 511 val &= ~ADJUST_ADJ_DELAY_MASK; 512 writel(val, host->regs + host->data->adjust); 513 } 514 515 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 516 { 517 struct meson_host *host = mmc_priv(mmc); 518 unsigned int val, dly, max_dly, i; 519 int ret; 520 521 /* Resampling is done using the source clock */ 522 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 523 clk_get_rate(host->mmc_clk)); 524 525 val = readl(host->regs + host->data->adjust); 526 val |= ADJUST_ADJ_EN; 527 writel(val, host->regs + host->data->adjust); 528 529 if (mmc_doing_retune(mmc)) 530 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 531 else 532 dly = 0; 533 534 for (i = 0; i < max_dly; i++) { 535 val &= ~ADJUST_ADJ_DELAY_MASK; 536 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 537 writel(val, host->regs + host->data->adjust); 538 539 ret = mmc_send_tuning(mmc, opcode, NULL); 540 if (!ret) { 541 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 542 (dly + i) % max_dly); 543 return 0; 544 } 545 } 546 547 meson_mmc_reset_resampling(host); 548 return -EIO; 549 } 550 551 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 552 struct mmc_ios *ios) 553 { 554 bool ddr; 555 556 switch (ios->timing) { 557 case MMC_TIMING_MMC_DDR52: 558 case MMC_TIMING_UHS_DDR50: 559 ddr = true; 560 break; 561 562 default: 563 ddr = false; 564 break; 565 } 566 567 return meson_mmc_clk_set(host, ios->clock, ddr); 568 } 569 570 static void meson_mmc_check_resampling(struct meson_host *host, 571 struct mmc_ios *ios) 572 { 573 switch (ios->timing) { 574 case MMC_TIMING_LEGACY: 575 case MMC_TIMING_MMC_HS: 576 case MMC_TIMING_SD_HS: 577 case MMC_TIMING_MMC_DDR52: 578 meson_mmc_disable_resampling(host); 579 break; 580 } 581 } 582 583 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 584 { 585 struct meson_host *host = mmc_priv(mmc); 586 u32 bus_width, val; 587 int err; 588 589 /* 590 * GPIO regulator, only controls switching between 1v8 and 591 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 592 */ 593 switch (ios->power_mode) { 594 case MMC_POWER_OFF: 595 if (!IS_ERR(mmc->supply.vmmc)) 596 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 597 598 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 599 regulator_disable(mmc->supply.vqmmc); 600 host->vqmmc_enabled = false; 601 } 602 603 break; 604 605 case MMC_POWER_UP: 606 if (!IS_ERR(mmc->supply.vmmc)) 607 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 608 609 break; 610 611 case MMC_POWER_ON: 612 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 613 int ret = regulator_enable(mmc->supply.vqmmc); 614 615 if (ret < 0) 616 dev_err(host->dev, 617 "failed to enable vqmmc regulator\n"); 618 else 619 host->vqmmc_enabled = true; 620 } 621 622 break; 623 } 624 625 /* Bus width */ 626 switch (ios->bus_width) { 627 case MMC_BUS_WIDTH_1: 628 bus_width = CFG_BUS_WIDTH_1; 629 break; 630 case MMC_BUS_WIDTH_4: 631 bus_width = CFG_BUS_WIDTH_4; 632 break; 633 case MMC_BUS_WIDTH_8: 634 bus_width = CFG_BUS_WIDTH_8; 635 break; 636 default: 637 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 638 ios->bus_width); 639 bus_width = CFG_BUS_WIDTH_4; 640 } 641 642 val = readl(host->regs + SD_EMMC_CFG); 643 val &= ~CFG_BUS_WIDTH_MASK; 644 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 645 writel(val, host->regs + SD_EMMC_CFG); 646 647 meson_mmc_check_resampling(host, ios); 648 err = meson_mmc_prepare_ios_clock(host, ios); 649 if (err) 650 dev_err(host->dev, "Failed to set clock: %d\n,", err); 651 652 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 653 } 654 655 static void meson_mmc_request_done(struct mmc_host *mmc, 656 struct mmc_request *mrq) 657 { 658 struct meson_host *host = mmc_priv(mmc); 659 660 host->cmd = NULL; 661 mmc_request_done(host->mmc, mrq); 662 } 663 664 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 665 { 666 struct meson_host *host = mmc_priv(mmc); 667 u32 cfg, blksz_old; 668 669 cfg = readl(host->regs + SD_EMMC_CFG); 670 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 671 672 if (!is_power_of_2(blksz)) 673 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 674 675 blksz = ilog2(blksz); 676 677 /* check if block-size matches, if not update */ 678 if (blksz == blksz_old) 679 return; 680 681 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 682 blksz_old, blksz); 683 684 cfg &= ~CFG_BLK_LEN_MASK; 685 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 686 writel(cfg, host->regs + SD_EMMC_CFG); 687 } 688 689 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 690 { 691 if (cmd->flags & MMC_RSP_PRESENT) { 692 if (cmd->flags & MMC_RSP_136) 693 *cmd_cfg |= CMD_CFG_RESP_128; 694 *cmd_cfg |= CMD_CFG_RESP_NUM; 695 696 if (!(cmd->flags & MMC_RSP_CRC)) 697 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 698 699 if (cmd->flags & MMC_RSP_BUSY) 700 *cmd_cfg |= CMD_CFG_R1B; 701 } else { 702 *cmd_cfg |= CMD_CFG_NO_RESP; 703 } 704 } 705 706 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 707 { 708 struct meson_host *host = mmc_priv(mmc); 709 struct sd_emmc_desc *desc = host->descs; 710 struct mmc_data *data = host->cmd->data; 711 struct scatterlist *sg; 712 u32 start; 713 int i; 714 715 if (data->flags & MMC_DATA_WRITE) 716 cmd_cfg |= CMD_CFG_DATA_WR; 717 718 if (data->blocks > 1) { 719 cmd_cfg |= CMD_CFG_BLOCK_MODE; 720 meson_mmc_set_blksz(mmc, data->blksz); 721 } 722 723 for_each_sg(data->sg, sg, data->sg_count, i) { 724 unsigned int len = sg_dma_len(sg); 725 726 if (data->blocks > 1) 727 len /= data->blksz; 728 729 desc[i].cmd_cfg = cmd_cfg; 730 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 731 if (i > 0) 732 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 733 desc[i].cmd_arg = host->cmd->arg; 734 desc[i].cmd_resp = 0; 735 desc[i].cmd_data = sg_dma_address(sg); 736 } 737 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 738 739 dma_wmb(); /* ensure descriptor is written before kicked */ 740 start = host->descs_dma_addr | START_DESC_BUSY; 741 writel(start, host->regs + SD_EMMC_START); 742 } 743 744 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 745 { 746 struct meson_host *host = mmc_priv(mmc); 747 struct mmc_data *data = cmd->data; 748 u32 cmd_cfg = 0, cmd_data = 0; 749 unsigned int xfer_bytes = 0; 750 751 /* Setup descriptors */ 752 dma_rmb(); 753 754 host->cmd = cmd; 755 756 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 757 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 758 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 759 760 meson_mmc_set_response_bits(cmd, &cmd_cfg); 761 762 /* data? */ 763 if (data) { 764 data->bytes_xfered = 0; 765 cmd_cfg |= CMD_CFG_DATA_IO; 766 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 767 ilog2(meson_mmc_get_timeout_msecs(data))); 768 769 if (meson_mmc_desc_chain_mode(data)) { 770 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 771 return; 772 } 773 774 if (data->blocks > 1) { 775 cmd_cfg |= CMD_CFG_BLOCK_MODE; 776 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 777 data->blocks); 778 meson_mmc_set_blksz(mmc, data->blksz); 779 } else { 780 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 781 } 782 783 xfer_bytes = data->blksz * data->blocks; 784 if (data->flags & MMC_DATA_WRITE) { 785 cmd_cfg |= CMD_CFG_DATA_WR; 786 WARN_ON(xfer_bytes > host->bounce_buf_size); 787 sg_copy_to_buffer(data->sg, data->sg_len, 788 host->bounce_buf, xfer_bytes); 789 dma_wmb(); 790 } 791 792 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 793 } else { 794 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 795 ilog2(SD_EMMC_CMD_TIMEOUT)); 796 } 797 798 /* Last descriptor */ 799 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 800 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 801 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 802 writel(0, host->regs + SD_EMMC_CMD_RSP); 803 wmb(); /* ensure descriptor is written before kicked */ 804 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 805 } 806 807 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 808 { 809 struct meson_host *host = mmc_priv(mmc); 810 bool needs_pre_post_req = mrq->data && 811 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 812 813 if (needs_pre_post_req) { 814 meson_mmc_get_transfer_mode(mmc, mrq); 815 if (!meson_mmc_desc_chain_mode(mrq->data)) 816 needs_pre_post_req = false; 817 } 818 819 if (needs_pre_post_req) 820 meson_mmc_pre_req(mmc, mrq); 821 822 /* Stop execution */ 823 writel(0, host->regs + SD_EMMC_START); 824 825 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 826 827 if (needs_pre_post_req) 828 meson_mmc_post_req(mmc, mrq, 0); 829 } 830 831 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 832 { 833 struct meson_host *host = mmc_priv(mmc); 834 835 if (cmd->flags & MMC_RSP_136) { 836 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 837 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 838 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 839 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 840 } else if (cmd->flags & MMC_RSP_PRESENT) { 841 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 842 } 843 } 844 845 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 846 { 847 struct meson_host *host = dev_id; 848 struct mmc_command *cmd; 849 struct mmc_data *data; 850 u32 irq_en, status, raw_status; 851 irqreturn_t ret = IRQ_NONE; 852 853 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 854 raw_status = readl(host->regs + SD_EMMC_STATUS); 855 status = raw_status & irq_en; 856 857 if (!status) { 858 dev_dbg(host->dev, 859 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 860 irq_en, raw_status); 861 return IRQ_NONE; 862 } 863 864 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 865 return IRQ_NONE; 866 867 /* ack all raised interrupts */ 868 writel(status, host->regs + SD_EMMC_STATUS); 869 870 cmd = host->cmd; 871 data = cmd->data; 872 cmd->error = 0; 873 if (status & IRQ_CRC_ERR) { 874 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 875 cmd->error = -EILSEQ; 876 ret = IRQ_WAKE_THREAD; 877 goto out; 878 } 879 880 if (status & IRQ_TIMEOUTS) { 881 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 882 cmd->error = -ETIMEDOUT; 883 ret = IRQ_WAKE_THREAD; 884 goto out; 885 } 886 887 meson_mmc_read_resp(host->mmc, cmd); 888 889 if (status & IRQ_SDIO) { 890 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 891 ret = IRQ_HANDLED; 892 } 893 894 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 895 if (data && !cmd->error) 896 data->bytes_xfered = data->blksz * data->blocks; 897 if (meson_mmc_bounce_buf_read(data) || 898 meson_mmc_get_next_command(cmd)) 899 ret = IRQ_WAKE_THREAD; 900 else 901 ret = IRQ_HANDLED; 902 } 903 904 out: 905 if (cmd->error) { 906 /* Stop desc in case of errors */ 907 u32 start = readl(host->regs + SD_EMMC_START); 908 909 start &= ~START_DESC_BUSY; 910 writel(start, host->regs + SD_EMMC_START); 911 } 912 913 if (ret == IRQ_HANDLED) 914 meson_mmc_request_done(host->mmc, cmd->mrq); 915 916 return ret; 917 } 918 919 static int meson_mmc_wait_desc_stop(struct meson_host *host) 920 { 921 u32 status; 922 923 /* 924 * It may sometimes take a while for it to actually halt. Here, we 925 * are giving it 5ms to comply 926 * 927 * If we don't confirm the descriptor is stopped, it might raise new 928 * IRQs after we have called mmc_request_done() which is bad. 929 */ 930 931 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 932 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 933 100, 5000); 934 } 935 936 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 937 { 938 struct meson_host *host = dev_id; 939 struct mmc_command *next_cmd, *cmd = host->cmd; 940 struct mmc_data *data; 941 unsigned int xfer_bytes; 942 943 if (WARN_ON(!cmd)) 944 return IRQ_NONE; 945 946 if (cmd->error) { 947 meson_mmc_wait_desc_stop(host); 948 meson_mmc_request_done(host->mmc, cmd->mrq); 949 950 return IRQ_HANDLED; 951 } 952 953 data = cmd->data; 954 if (meson_mmc_bounce_buf_read(data)) { 955 xfer_bytes = data->blksz * data->blocks; 956 WARN_ON(xfer_bytes > host->bounce_buf_size); 957 sg_copy_from_buffer(data->sg, data->sg_len, 958 host->bounce_buf, xfer_bytes); 959 } 960 961 next_cmd = meson_mmc_get_next_command(cmd); 962 if (next_cmd) 963 meson_mmc_start_cmd(host->mmc, next_cmd); 964 else 965 meson_mmc_request_done(host->mmc, cmd->mrq); 966 967 return IRQ_HANDLED; 968 } 969 970 /* 971 * NOTE: we only need this until the GPIO/pinctrl driver can handle 972 * interrupts. For now, the MMC core will use this for polling. 973 */ 974 static int meson_mmc_get_cd(struct mmc_host *mmc) 975 { 976 int status = mmc_gpio_get_cd(mmc); 977 978 if (status == -ENOSYS) 979 return 1; /* assume present */ 980 981 return status; 982 } 983 984 static void meson_mmc_cfg_init(struct meson_host *host) 985 { 986 u32 cfg = 0; 987 988 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 989 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 990 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 991 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 992 993 /* abort chain on R/W errors */ 994 cfg |= CFG_ERR_ABORT; 995 996 writel(cfg, host->regs + SD_EMMC_CFG); 997 } 998 999 static int meson_mmc_card_busy(struct mmc_host *mmc) 1000 { 1001 struct meson_host *host = mmc_priv(mmc); 1002 u32 regval; 1003 1004 regval = readl(host->regs + SD_EMMC_STATUS); 1005 1006 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1007 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1008 } 1009 1010 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1011 { 1012 int ret; 1013 1014 /* vqmmc regulator is available */ 1015 if (!IS_ERR(mmc->supply.vqmmc)) { 1016 /* 1017 * The usual amlogic setup uses a GPIO to switch from one 1018 * regulator to the other. While the voltage ramp up is 1019 * pretty fast, care must be taken when switching from 3.3v 1020 * to 1.8v. Please make sure the regulator framework is aware 1021 * of your own regulator constraints 1022 */ 1023 ret = mmc_regulator_set_vqmmc(mmc, ios); 1024 return ret < 0 ? ret : 0; 1025 } 1026 1027 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1028 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1029 return 0; 1030 1031 return -EINVAL; 1032 } 1033 1034 static const struct mmc_host_ops meson_mmc_ops = { 1035 .request = meson_mmc_request, 1036 .set_ios = meson_mmc_set_ios, 1037 .get_cd = meson_mmc_get_cd, 1038 .pre_req = meson_mmc_pre_req, 1039 .post_req = meson_mmc_post_req, 1040 .execute_tuning = meson_mmc_resampling_tuning, 1041 .card_busy = meson_mmc_card_busy, 1042 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1043 }; 1044 1045 static int meson_mmc_probe(struct platform_device *pdev) 1046 { 1047 struct resource *res; 1048 struct meson_host *host; 1049 struct mmc_host *mmc; 1050 int ret; 1051 1052 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1053 if (!mmc) 1054 return -ENOMEM; 1055 host = mmc_priv(mmc); 1056 host->mmc = mmc; 1057 host->dev = &pdev->dev; 1058 dev_set_drvdata(&pdev->dev, host); 1059 1060 /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1061 host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1062 "amlogic,dram-access-quirk"); 1063 1064 /* Get regulators and the supported OCR mask */ 1065 host->vqmmc_enabled = false; 1066 ret = mmc_regulator_get_supply(mmc); 1067 if (ret) 1068 goto free_host; 1069 1070 ret = mmc_of_parse(mmc); 1071 if (ret) { 1072 if (ret != -EPROBE_DEFER) 1073 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1074 goto free_host; 1075 } 1076 1077 host->data = (struct meson_mmc_data *) 1078 of_device_get_match_data(&pdev->dev); 1079 if (!host->data) { 1080 ret = -EINVAL; 1081 goto free_host; 1082 } 1083 1084 ret = device_reset_optional(&pdev->dev); 1085 if (ret) 1086 return dev_err_probe(&pdev->dev, ret, "device reset failed\n"); 1087 1088 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1089 host->regs = devm_ioremap_resource(&pdev->dev, res); 1090 if (IS_ERR(host->regs)) { 1091 ret = PTR_ERR(host->regs); 1092 goto free_host; 1093 } 1094 1095 host->irq = platform_get_irq(pdev, 0); 1096 if (host->irq <= 0) { 1097 ret = -EINVAL; 1098 goto free_host; 1099 } 1100 1101 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1102 if (IS_ERR(host->pinctrl)) { 1103 ret = PTR_ERR(host->pinctrl); 1104 goto free_host; 1105 } 1106 1107 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1108 "clk-gate"); 1109 if (IS_ERR(host->pins_clk_gate)) { 1110 dev_warn(&pdev->dev, 1111 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1112 host->pins_clk_gate = NULL; 1113 } 1114 1115 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1116 if (IS_ERR(host->core_clk)) { 1117 ret = PTR_ERR(host->core_clk); 1118 goto free_host; 1119 } 1120 1121 ret = clk_prepare_enable(host->core_clk); 1122 if (ret) 1123 goto free_host; 1124 1125 ret = meson_mmc_clk_init(host); 1126 if (ret) 1127 goto err_core_clk; 1128 1129 /* set config to sane default */ 1130 meson_mmc_cfg_init(host); 1131 1132 /* Stop execution */ 1133 writel(0, host->regs + SD_EMMC_START); 1134 1135 /* clear, ack and enable interrupts */ 1136 writel(0, host->regs + SD_EMMC_IRQ_EN); 1137 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1138 host->regs + SD_EMMC_STATUS); 1139 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1140 host->regs + SD_EMMC_IRQ_EN); 1141 1142 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1143 meson_mmc_irq_thread, IRQF_ONESHOT, 1144 dev_name(&pdev->dev), host); 1145 if (ret) 1146 goto err_init_clk; 1147 1148 mmc->caps |= MMC_CAP_CMD23; 1149 if (host->dram_access_quirk) { 1150 /* Limit segments to 1 due to low available sram memory */ 1151 mmc->max_segs = 1; 1152 /* Limit to the available sram memory */ 1153 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 1154 mmc->max_blk_size; 1155 } else { 1156 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1157 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1158 sizeof(struct sd_emmc_desc); 1159 } 1160 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1161 mmc->max_seg_size = mmc->max_req_size; 1162 1163 /* 1164 * At the moment, we don't know how to reliably enable HS400. 1165 * From the different datasheets, it is not even clear if this mode 1166 * is officially supported by any of the SoCs 1167 */ 1168 mmc->caps2 &= ~MMC_CAP2_HS400; 1169 1170 if (host->dram_access_quirk) { 1171 /* 1172 * The MMC Controller embeds 1,5KiB of internal SRAM 1173 * that can be used to be used as bounce buffer. 1174 * In the case of the G12A SDIO controller, use these 1175 * instead of the DDR memory 1176 */ 1177 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1178 host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1179 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1180 } else { 1181 /* data bounce buffer */ 1182 host->bounce_buf_size = mmc->max_req_size; 1183 host->bounce_buf = 1184 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1185 &host->bounce_dma_addr, GFP_KERNEL); 1186 if (host->bounce_buf == NULL) { 1187 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1188 ret = -ENOMEM; 1189 goto err_free_irq; 1190 } 1191 } 1192 1193 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1194 &host->descs_dma_addr, GFP_KERNEL); 1195 if (!host->descs) { 1196 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1197 ret = -ENOMEM; 1198 goto err_bounce_buf; 1199 } 1200 1201 mmc->ops = &meson_mmc_ops; 1202 mmc_add_host(mmc); 1203 1204 return 0; 1205 1206 err_bounce_buf: 1207 if (!host->dram_access_quirk) 1208 dma_free_coherent(host->dev, host->bounce_buf_size, 1209 host->bounce_buf, host->bounce_dma_addr); 1210 err_free_irq: 1211 free_irq(host->irq, host); 1212 err_init_clk: 1213 clk_disable_unprepare(host->mmc_clk); 1214 err_core_clk: 1215 clk_disable_unprepare(host->core_clk); 1216 free_host: 1217 mmc_free_host(mmc); 1218 return ret; 1219 } 1220 1221 static int meson_mmc_remove(struct platform_device *pdev) 1222 { 1223 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1224 1225 mmc_remove_host(host->mmc); 1226 1227 /* disable interrupts */ 1228 writel(0, host->regs + SD_EMMC_IRQ_EN); 1229 free_irq(host->irq, host); 1230 1231 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1232 host->descs, host->descs_dma_addr); 1233 1234 if (!host->dram_access_quirk) 1235 dma_free_coherent(host->dev, host->bounce_buf_size, 1236 host->bounce_buf, host->bounce_dma_addr); 1237 1238 clk_disable_unprepare(host->mmc_clk); 1239 clk_disable_unprepare(host->core_clk); 1240 1241 mmc_free_host(host->mmc); 1242 return 0; 1243 } 1244 1245 static const struct meson_mmc_data meson_gx_data = { 1246 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1247 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1248 .always_on = CLK_V2_ALWAYS_ON, 1249 .adjust = SD_EMMC_ADJUST, 1250 }; 1251 1252 static const struct meson_mmc_data meson_axg_data = { 1253 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1254 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1255 .always_on = CLK_V3_ALWAYS_ON, 1256 .adjust = SD_EMMC_V3_ADJUST, 1257 }; 1258 1259 static const struct of_device_id meson_mmc_of_match[] = { 1260 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1261 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1262 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1263 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1264 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1265 {} 1266 }; 1267 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1268 1269 static struct platform_driver meson_mmc_driver = { 1270 .probe = meson_mmc_probe, 1271 .remove = meson_mmc_remove, 1272 .driver = { 1273 .name = DRIVER_NAME, 1274 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1275 .of_match_table = meson_mmc_of_match, 1276 }, 1277 }; 1278 1279 module_platform_driver(meson_mmc_driver); 1280 1281 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1282 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1283 MODULE_LICENSE("GPL v2"); 1284