xref: /linux/drivers/mmc/host/meson-gx-mmc.c (revision 585a78c1f77be305b1f6adad392f16047fb66ffd)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4  *
5  * Copyright (c) 2016 BayLibre, SAS.
6  * Author: Kevin Hilman <khilman@baylibre.com>
7  */
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/iopoll.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/ioport.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/mmc/host.h>
19 #include <linux/mmc/mmc.h>
20 #include <linux/mmc/sdio.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/interrupt.h>
28 #include <linux/bitfield.h>
29 #include <linux/pinctrl/consumer.h>
30 
31 #define DRIVER_NAME "meson-gx-mmc"
32 
33 #define SD_EMMC_CLOCK 0x0
34 #define   CLK_DIV_MASK GENMASK(5, 0)
35 #define   CLK_SRC_MASK GENMASK(7, 6)
36 #define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
37 #define   CLK_TX_PHASE_MASK GENMASK(11, 10)
38 #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
39 #define   CLK_PHASE_0 0
40 #define   CLK_PHASE_180 2
41 #define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
42 #define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
43 #define   CLK_V2_ALWAYS_ON BIT(24)
44 #define   CLK_V2_IRQ_SDIO_SLEEP BIT(25)
45 
46 #define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
47 #define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
48 #define   CLK_V3_ALWAYS_ON BIT(28)
49 #define   CLK_V3_IRQ_SDIO_SLEEP BIT(29)
50 
51 #define   CLK_TX_DELAY_MASK(h)		(h->data->tx_delay_mask)
52 #define   CLK_RX_DELAY_MASK(h)		(h->data->rx_delay_mask)
53 #define   CLK_ALWAYS_ON(h)		(h->data->always_on)
54 #define   CLK_IRQ_SDIO_SLEEP(h)		(h->data->irq_sdio_sleep)
55 
56 #define SD_EMMC_DELAY 0x4
57 #define SD_EMMC_ADJUST 0x8
58 #define   ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
59 #define   ADJUST_DS_EN BIT(15)
60 #define   ADJUST_ADJ_EN BIT(13)
61 
62 #define SD_EMMC_DELAY1 0x4
63 #define SD_EMMC_DELAY2 0x8
64 #define SD_EMMC_V3_ADJUST 0xc
65 
66 #define SD_EMMC_CALOUT 0x10
67 #define SD_EMMC_START 0x40
68 #define   START_DESC_INIT BIT(0)
69 #define   START_DESC_BUSY BIT(1)
70 #define   START_DESC_ADDR_MASK GENMASK(31, 2)
71 
72 #define SD_EMMC_CFG 0x44
73 #define   CFG_BUS_WIDTH_MASK GENMASK(1, 0)
74 #define   CFG_BUS_WIDTH_1 0x0
75 #define   CFG_BUS_WIDTH_4 0x1
76 #define   CFG_BUS_WIDTH_8 0x2
77 #define   CFG_DDR BIT(2)
78 #define   CFG_BLK_LEN_MASK GENMASK(7, 4)
79 #define   CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
80 #define   CFG_RC_CC_MASK GENMASK(15, 12)
81 #define   CFG_STOP_CLOCK BIT(22)
82 #define   CFG_CLK_ALWAYS_ON BIT(18)
83 #define   CFG_CHK_DS BIT(20)
84 #define   CFG_AUTO_CLK BIT(23)
85 #define   CFG_ERR_ABORT BIT(27)
86 
87 #define SD_EMMC_STATUS 0x48
88 #define   STATUS_BUSY BIT(31)
89 #define   STATUS_DESC_BUSY BIT(30)
90 #define   STATUS_DATI GENMASK(23, 16)
91 
92 #define SD_EMMC_IRQ_EN 0x4c
93 #define   IRQ_RXD_ERR_MASK GENMASK(7, 0)
94 #define   IRQ_TXD_ERR BIT(8)
95 #define   IRQ_DESC_ERR BIT(9)
96 #define   IRQ_RESP_ERR BIT(10)
97 #define   IRQ_CRC_ERR \
98 	(IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
99 #define   IRQ_RESP_TIMEOUT BIT(11)
100 #define   IRQ_DESC_TIMEOUT BIT(12)
101 #define   IRQ_TIMEOUTS \
102 	(IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
103 #define   IRQ_END_OF_CHAIN BIT(13)
104 #define   IRQ_RESP_STATUS BIT(14)
105 #define   IRQ_SDIO BIT(15)
106 #define   IRQ_EN_MASK \
107 	(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN)
108 
109 #define SD_EMMC_CMD_CFG 0x50
110 #define SD_EMMC_CMD_ARG 0x54
111 #define SD_EMMC_CMD_DAT 0x58
112 #define SD_EMMC_CMD_RSP 0x5c
113 #define SD_EMMC_CMD_RSP1 0x60
114 #define SD_EMMC_CMD_RSP2 0x64
115 #define SD_EMMC_CMD_RSP3 0x68
116 
117 #define SD_EMMC_RXD 0x94
118 #define SD_EMMC_TXD 0x94
119 #define SD_EMMC_LAST_REG SD_EMMC_TXD
120 
121 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536
122 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
123 
124 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
125 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
126 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
127 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
128 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
129 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
130 
131 #define SD_EMMC_PRE_REQ_DONE BIT(0)
132 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
133 
134 #define MUX_CLK_NUM_PARENTS 2
135 
136 struct meson_mmc_data {
137 	unsigned int tx_delay_mask;
138 	unsigned int rx_delay_mask;
139 	unsigned int always_on;
140 	unsigned int adjust;
141 	unsigned int irq_sdio_sleep;
142 };
143 
144 struct sd_emmc_desc {
145 	u32 cmd_cfg;
146 	u32 cmd_arg;
147 	u32 cmd_data;
148 	u32 cmd_resp;
149 };
150 
151 struct meson_host {
152 	struct	device		*dev;
153 	struct	meson_mmc_data *data;
154 	struct	mmc_host	*mmc;
155 	struct	mmc_command	*cmd;
156 
157 	void __iomem *regs;
158 	struct clk *core_clk;
159 	struct clk *mux_clk;
160 	struct clk *mmc_clk;
161 	unsigned long req_rate;
162 	bool ddr;
163 
164 	bool dram_access_quirk;
165 
166 	struct pinctrl *pinctrl;
167 	struct pinctrl_state *pins_clk_gate;
168 
169 	unsigned int bounce_buf_size;
170 	void *bounce_buf;
171 	void __iomem *bounce_iomem_buf;
172 	dma_addr_t bounce_dma_addr;
173 	struct sd_emmc_desc *descs;
174 	dma_addr_t descs_dma_addr;
175 
176 	int irq;
177 
178 	bool vqmmc_enabled;
179 	bool needs_pre_post_req;
180 
181 	spinlock_t lock;
182 };
183 
184 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
185 #define CMD_CFG_BLOCK_MODE BIT(9)
186 #define CMD_CFG_R1B BIT(10)
187 #define CMD_CFG_END_OF_CHAIN BIT(11)
188 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
189 #define CMD_CFG_NO_RESP BIT(16)
190 #define CMD_CFG_NO_CMD BIT(17)
191 #define CMD_CFG_DATA_IO BIT(18)
192 #define CMD_CFG_DATA_WR BIT(19)
193 #define CMD_CFG_RESP_NOCRC BIT(20)
194 #define CMD_CFG_RESP_128 BIT(21)
195 #define CMD_CFG_RESP_NUM BIT(22)
196 #define CMD_CFG_DATA_NUM BIT(23)
197 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
198 #define CMD_CFG_ERROR BIT(30)
199 #define CMD_CFG_OWNER BIT(31)
200 
201 #define CMD_DATA_MASK GENMASK(31, 2)
202 #define CMD_DATA_BIG_ENDIAN BIT(1)
203 #define CMD_DATA_SRAM BIT(0)
204 #define CMD_RESP_MASK GENMASK(31, 1)
205 #define CMD_RESP_SRAM BIT(0)
206 
207 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
208 {
209 	unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
210 
211 	if (!timeout)
212 		return SD_EMMC_CMD_TIMEOUT_DATA;
213 
214 	timeout = roundup_pow_of_two(timeout);
215 
216 	return min(timeout, 32768U); /* max. 2^15 ms */
217 }
218 
219 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
220 {
221 	if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
222 		return cmd->mrq->cmd;
223 	else if (mmc_op_multi(cmd->opcode) &&
224 		 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
225 		return cmd->mrq->stop;
226 	else
227 		return NULL;
228 }
229 
230 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
231 					struct mmc_request *mrq)
232 {
233 	struct meson_host *host = mmc_priv(mmc);
234 	struct mmc_data *data = mrq->data;
235 	struct scatterlist *sg;
236 	int i;
237 
238 	/*
239 	 * When Controller DMA cannot directly access DDR memory, disable
240 	 * support for Chain Mode to directly use the internal SRAM using
241 	 * the bounce buffer mode.
242 	 */
243 	if (host->dram_access_quirk)
244 		return;
245 
246 	/* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */
247 	if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
248 		/*
249 		 * In block mode DMA descriptor format, "length" field indicates
250 		 * number of blocks and there is no way to pass DMA size that
251 		 * is not multiple of SDIO block size, making it impossible to
252 		 * tie more than one memory buffer with single SDIO block.
253 		 * Block mode sg buffer size should be aligned with SDIO block
254 		 * size, otherwise chain mode could not be used.
255 		 */
256 		for_each_sg(data->sg, sg, data->sg_len, i) {
257 			if (sg->length % data->blksz) {
258 				dev_warn_once(mmc_dev(mmc),
259 					      "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n",
260 					      sg->length, data->blksz);
261 				return;
262 			}
263 		}
264 	}
265 
266 	for_each_sg(data->sg, sg, data->sg_len, i) {
267 		/* check for 8 byte alignment */
268 		if (sg->offset % 8) {
269 			dev_warn_once(mmc_dev(mmc),
270 				      "unaligned sg offset %u, disabling descriptor DMA for transfer\n",
271 				      sg->offset);
272 			return;
273 		}
274 	}
275 
276 	data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
277 }
278 
279 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
280 {
281 	return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
282 }
283 
284 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
285 {
286 	return data && data->flags & MMC_DATA_READ &&
287 	       !meson_mmc_desc_chain_mode(data);
288 }
289 
290 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
291 {
292 	struct mmc_data *data = mrq->data;
293 
294 	if (!data)
295 		return;
296 
297 	meson_mmc_get_transfer_mode(mmc, mrq);
298 	data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
299 
300 	if (!meson_mmc_desc_chain_mode(data))
301 		return;
302 
303 	data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
304                                    mmc_get_dma_dir(data));
305 	if (!data->sg_count)
306 		dev_err(mmc_dev(mmc), "dma_map_sg failed");
307 }
308 
309 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
310 			       int err)
311 {
312 	struct mmc_data *data = mrq->data;
313 
314 	if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
315 		dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
316 			     mmc_get_dma_dir(data));
317 }
318 
319 /*
320  * Gating the clock on this controller is tricky.  It seems the mmc clock
321  * is also used by the controller.  It may crash during some operation if the
322  * clock is stopped.  The safest thing to do, whenever possible, is to keep
323  * clock running at stop it at the pad using the pinmux.
324  */
325 static void meson_mmc_clk_gate(struct meson_host *host)
326 {
327 	u32 cfg;
328 
329 	if (host->pins_clk_gate) {
330 		pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
331 	} else {
332 		/*
333 		 * If the pinmux is not provided - default to the classic and
334 		 * unsafe method
335 		 */
336 		cfg = readl(host->regs + SD_EMMC_CFG);
337 		cfg |= CFG_STOP_CLOCK;
338 		writel(cfg, host->regs + SD_EMMC_CFG);
339 	}
340 }
341 
342 static void meson_mmc_clk_ungate(struct meson_host *host)
343 {
344 	u32 cfg;
345 
346 	if (host->pins_clk_gate)
347 		pinctrl_select_default_state(host->dev);
348 
349 	/* Make sure the clock is not stopped in the controller */
350 	cfg = readl(host->regs + SD_EMMC_CFG);
351 	cfg &= ~CFG_STOP_CLOCK;
352 	writel(cfg, host->regs + SD_EMMC_CFG);
353 }
354 
355 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
356 			     bool ddr)
357 {
358 	struct mmc_host *mmc = host->mmc;
359 	int ret;
360 	u32 cfg;
361 
362 	/* Same request - bail-out */
363 	if (host->ddr == ddr && host->req_rate == rate)
364 		return 0;
365 
366 	/* stop clock */
367 	meson_mmc_clk_gate(host);
368 	host->req_rate = 0;
369 	mmc->actual_clock = 0;
370 
371 	/* return with clock being stopped */
372 	if (!rate)
373 		return 0;
374 
375 	/* Stop the clock during rate change to avoid glitches */
376 	cfg = readl(host->regs + SD_EMMC_CFG);
377 	cfg |= CFG_STOP_CLOCK;
378 	writel(cfg, host->regs + SD_EMMC_CFG);
379 
380 	if (ddr) {
381 		/* DDR modes require higher module clock */
382 		rate <<= 1;
383 		cfg |= CFG_DDR;
384 	} else {
385 		cfg &= ~CFG_DDR;
386 	}
387 	writel(cfg, host->regs + SD_EMMC_CFG);
388 	host->ddr = ddr;
389 
390 	ret = clk_set_rate(host->mmc_clk, rate);
391 	if (ret) {
392 		dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
393 			rate, ret);
394 		return ret;
395 	}
396 
397 	host->req_rate = rate;
398 	mmc->actual_clock = clk_get_rate(host->mmc_clk);
399 
400 	/* We should report the real output frequency of the controller */
401 	if (ddr) {
402 		host->req_rate >>= 1;
403 		mmc->actual_clock >>= 1;
404 	}
405 
406 	dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
407 	if (rate != mmc->actual_clock)
408 		dev_dbg(host->dev, "requested rate was %lu\n", rate);
409 
410 	/* (re)start clock */
411 	meson_mmc_clk_ungate(host);
412 
413 	return 0;
414 }
415 
416 /*
417  * The SD/eMMC IP block has an internal mux and divider used for
418  * generating the MMC clock.  Use the clock framework to create and
419  * manage these clocks.
420  */
421 static int meson_mmc_clk_init(struct meson_host *host)
422 {
423 	struct clk_init_data init;
424 	struct clk_mux *mux;
425 	struct clk_divider *div;
426 	char clk_name[32];
427 	int i, ret = 0;
428 	const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
429 	const char *clk_parent[1];
430 	u32 clk_reg;
431 
432 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
433 	clk_reg = CLK_ALWAYS_ON(host);
434 	clk_reg |= CLK_DIV_MASK;
435 	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
436 	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
437 	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
438 	if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
439 		clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
440 	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
441 
442 	/* get the mux parents */
443 	for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
444 		struct clk *clk;
445 		char name[16];
446 
447 		snprintf(name, sizeof(name), "clkin%d", i);
448 		clk = devm_clk_get(host->dev, name);
449 		if (IS_ERR(clk))
450 			return dev_err_probe(host->dev, PTR_ERR(clk),
451 					     "Missing clock %s\n", name);
452 
453 		mux_parent_names[i] = __clk_get_name(clk);
454 	}
455 
456 	/* create the mux */
457 	mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
458 	if (!mux)
459 		return -ENOMEM;
460 
461 	snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
462 	init.name = clk_name;
463 	init.ops = &clk_mux_ops;
464 	init.flags = 0;
465 	init.parent_names = mux_parent_names;
466 	init.num_parents = MUX_CLK_NUM_PARENTS;
467 
468 	mux->reg = host->regs + SD_EMMC_CLOCK;
469 	mux->shift = __ffs(CLK_SRC_MASK);
470 	mux->mask = CLK_SRC_MASK >> mux->shift;
471 	mux->hw.init = &init;
472 
473 	host->mux_clk = devm_clk_register(host->dev, &mux->hw);
474 	if (WARN_ON(IS_ERR(host->mux_clk)))
475 		return PTR_ERR(host->mux_clk);
476 
477 	/* create the divider */
478 	div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
479 	if (!div)
480 		return -ENOMEM;
481 
482 	snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
483 	init.name = clk_name;
484 	init.ops = &clk_divider_ops;
485 	init.flags = CLK_SET_RATE_PARENT;
486 	clk_parent[0] = __clk_get_name(host->mux_clk);
487 	init.parent_names = clk_parent;
488 	init.num_parents = 1;
489 
490 	div->reg = host->regs + SD_EMMC_CLOCK;
491 	div->shift = __ffs(CLK_DIV_MASK);
492 	div->width = __builtin_popcountl(CLK_DIV_MASK);
493 	div->hw.init = &init;
494 	div->flags = CLK_DIVIDER_ONE_BASED;
495 
496 	host->mmc_clk = devm_clk_register(host->dev, &div->hw);
497 	if (WARN_ON(IS_ERR(host->mmc_clk)))
498 		return PTR_ERR(host->mmc_clk);
499 
500 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
501 	host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
502 	ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
503 	if (ret)
504 		return ret;
505 
506 	return clk_prepare_enable(host->mmc_clk);
507 }
508 
509 static void meson_mmc_disable_resampling(struct meson_host *host)
510 {
511 	unsigned int val = readl(host->regs + host->data->adjust);
512 
513 	val &= ~ADJUST_ADJ_EN;
514 	writel(val, host->regs + host->data->adjust);
515 }
516 
517 static void meson_mmc_reset_resampling(struct meson_host *host)
518 {
519 	unsigned int val;
520 
521 	meson_mmc_disable_resampling(host);
522 
523 	val = readl(host->regs + host->data->adjust);
524 	val &= ~ADJUST_ADJ_DELAY_MASK;
525 	writel(val, host->regs + host->data->adjust);
526 }
527 
528 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
529 {
530 	struct meson_host *host = mmc_priv(mmc);
531 	unsigned int val, dly, max_dly, i;
532 	int ret;
533 
534 	/* Resampling is done using the source clock */
535 	max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
536 			       clk_get_rate(host->mmc_clk));
537 
538 	val = readl(host->regs + host->data->adjust);
539 	val |= ADJUST_ADJ_EN;
540 	writel(val, host->regs + host->data->adjust);
541 
542 	if (mmc_doing_retune(mmc))
543 		dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
544 	else
545 		dly = 0;
546 
547 	for (i = 0; i < max_dly; i++) {
548 		val &= ~ADJUST_ADJ_DELAY_MASK;
549 		val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
550 		writel(val, host->regs + host->data->adjust);
551 
552 		ret = mmc_send_tuning(mmc, opcode, NULL);
553 		if (!ret) {
554 			dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
555 				(dly + i) % max_dly);
556 			return 0;
557 		}
558 	}
559 
560 	meson_mmc_reset_resampling(host);
561 	return -EIO;
562 }
563 
564 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
565 				       struct mmc_ios *ios)
566 {
567 	bool ddr;
568 
569 	switch (ios->timing) {
570 	case MMC_TIMING_MMC_DDR52:
571 	case MMC_TIMING_UHS_DDR50:
572 		ddr = true;
573 		break;
574 
575 	default:
576 		ddr = false;
577 		break;
578 	}
579 
580 	return meson_mmc_clk_set(host, ios->clock, ddr);
581 }
582 
583 static void meson_mmc_check_resampling(struct meson_host *host,
584 				       struct mmc_ios *ios)
585 {
586 	switch (ios->timing) {
587 	case MMC_TIMING_LEGACY:
588 	case MMC_TIMING_MMC_HS:
589 	case MMC_TIMING_SD_HS:
590 	case MMC_TIMING_MMC_DDR52:
591 		meson_mmc_disable_resampling(host);
592 		break;
593 	}
594 }
595 
596 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
597 {
598 	struct meson_host *host = mmc_priv(mmc);
599 	u32 bus_width, val;
600 	int err;
601 
602 	/*
603 	 * GPIO regulator, only controls switching between 1v8 and
604 	 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
605 	 */
606 	switch (ios->power_mode) {
607 	case MMC_POWER_OFF:
608 		if (!IS_ERR(mmc->supply.vmmc))
609 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
610 
611 		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
612 			regulator_disable(mmc->supply.vqmmc);
613 			host->vqmmc_enabled = false;
614 		}
615 
616 		break;
617 
618 	case MMC_POWER_UP:
619 		if (!IS_ERR(mmc->supply.vmmc))
620 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
621 
622 		break;
623 
624 	case MMC_POWER_ON:
625 		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
626 			int ret = regulator_enable(mmc->supply.vqmmc);
627 
628 			if (ret < 0)
629 				dev_err(host->dev,
630 					"failed to enable vqmmc regulator\n");
631 			else
632 				host->vqmmc_enabled = true;
633 		}
634 
635 		break;
636 	}
637 
638 	/* Bus width */
639 	switch (ios->bus_width) {
640 	case MMC_BUS_WIDTH_1:
641 		bus_width = CFG_BUS_WIDTH_1;
642 		break;
643 	case MMC_BUS_WIDTH_4:
644 		bus_width = CFG_BUS_WIDTH_4;
645 		break;
646 	case MMC_BUS_WIDTH_8:
647 		bus_width = CFG_BUS_WIDTH_8;
648 		break;
649 	default:
650 		dev_err(host->dev, "Invalid ios->bus_width: %u.  Setting to 4.\n",
651 			ios->bus_width);
652 		bus_width = CFG_BUS_WIDTH_4;
653 	}
654 
655 	val = readl(host->regs + SD_EMMC_CFG);
656 	val &= ~CFG_BUS_WIDTH_MASK;
657 	val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
658 	writel(val, host->regs + SD_EMMC_CFG);
659 
660 	meson_mmc_check_resampling(host, ios);
661 	err = meson_mmc_prepare_ios_clock(host, ios);
662 	if (err)
663 		dev_err(host->dev, "Failed to set clock: %d\n,", err);
664 
665 	dev_dbg(host->dev, "SD_EMMC_CFG:  0x%08x\n", val);
666 }
667 
668 static void meson_mmc_request_done(struct mmc_host *mmc,
669 				   struct mmc_request *mrq)
670 {
671 	struct meson_host *host = mmc_priv(mmc);
672 
673 	host->cmd = NULL;
674 	if (host->needs_pre_post_req)
675 		meson_mmc_post_req(mmc, mrq, 0);
676 	mmc_request_done(host->mmc, mrq);
677 }
678 
679 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
680 {
681 	struct meson_host *host = mmc_priv(mmc);
682 	u32 cfg, blksz_old;
683 
684 	cfg = readl(host->regs + SD_EMMC_CFG);
685 	blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
686 
687 	if (!is_power_of_2(blksz))
688 		dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
689 
690 	blksz = ilog2(blksz);
691 
692 	/* check if block-size matches, if not update */
693 	if (blksz == blksz_old)
694 		return;
695 
696 	dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
697 		blksz_old, blksz);
698 
699 	cfg &= ~CFG_BLK_LEN_MASK;
700 	cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
701 	writel(cfg, host->regs + SD_EMMC_CFG);
702 }
703 
704 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
705 {
706 	if (cmd->flags & MMC_RSP_PRESENT) {
707 		if (cmd->flags & MMC_RSP_136)
708 			*cmd_cfg |= CMD_CFG_RESP_128;
709 		*cmd_cfg |= CMD_CFG_RESP_NUM;
710 
711 		if (!(cmd->flags & MMC_RSP_CRC))
712 			*cmd_cfg |= CMD_CFG_RESP_NOCRC;
713 
714 		if (cmd->flags & MMC_RSP_BUSY)
715 			*cmd_cfg |= CMD_CFG_R1B;
716 	} else {
717 		*cmd_cfg |= CMD_CFG_NO_RESP;
718 	}
719 }
720 
721 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
722 {
723 	struct meson_host *host = mmc_priv(mmc);
724 	struct sd_emmc_desc *desc = host->descs;
725 	struct mmc_data *data = host->cmd->data;
726 	struct scatterlist *sg;
727 	u32 start;
728 	int i;
729 
730 	if (data->flags & MMC_DATA_WRITE)
731 		cmd_cfg |= CMD_CFG_DATA_WR;
732 
733 	if (data->blocks > 1) {
734 		cmd_cfg |= CMD_CFG_BLOCK_MODE;
735 		meson_mmc_set_blksz(mmc, data->blksz);
736 	}
737 
738 	for_each_sg(data->sg, sg, data->sg_count, i) {
739 		unsigned int len = sg_dma_len(sg);
740 
741 		if (data->blocks > 1)
742 			len /= data->blksz;
743 
744 		desc[i].cmd_cfg = cmd_cfg;
745 		desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
746 		if (i > 0)
747 			desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
748 		desc[i].cmd_arg = host->cmd->arg;
749 		desc[i].cmd_resp = 0;
750 		desc[i].cmd_data = sg_dma_address(sg);
751 	}
752 	desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
753 
754 	dma_wmb(); /* ensure descriptor is written before kicked */
755 	start = host->descs_dma_addr | START_DESC_BUSY;
756 	writel(start, host->regs + SD_EMMC_START);
757 }
758 
759 /* local sg copy for dram_access_quirk */
760 static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
761 				  size_t buflen, bool to_buffer)
762 {
763 	unsigned int sg_flags = SG_MITER_ATOMIC;
764 	struct scatterlist *sgl = data->sg;
765 	unsigned int nents = data->sg_len;
766 	struct sg_mapping_iter miter;
767 	unsigned int offset = 0;
768 
769 	if (to_buffer)
770 		sg_flags |= SG_MITER_FROM_SG;
771 	else
772 		sg_flags |= SG_MITER_TO_SG;
773 
774 	sg_miter_start(&miter, sgl, nents, sg_flags);
775 
776 	while ((offset < buflen) && sg_miter_next(&miter)) {
777 		unsigned int buf_offset = 0;
778 		unsigned int len, left;
779 		u32 *buf = miter.addr;
780 
781 		len = min(miter.length, buflen - offset);
782 		left = len;
783 
784 		if (to_buffer) {
785 			do {
786 				writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
787 
788 				buf_offset += 4;
789 				left -= 4;
790 			} while (left);
791 		} else {
792 			do {
793 				*buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
794 
795 				buf_offset += 4;
796 				left -= 4;
797 			} while (left);
798 		}
799 
800 		offset += len;
801 	}
802 
803 	sg_miter_stop(&miter);
804 }
805 
806 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
807 {
808 	struct meson_host *host = mmc_priv(mmc);
809 	struct mmc_data *data = cmd->data;
810 	u32 cmd_cfg = 0, cmd_data = 0;
811 	unsigned int xfer_bytes = 0;
812 
813 	/* Setup descriptors */
814 	dma_rmb();
815 
816 	host->cmd = cmd;
817 
818 	cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
819 	cmd_cfg |= CMD_CFG_OWNER;  /* owned by CPU */
820 	cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
821 
822 	meson_mmc_set_response_bits(cmd, &cmd_cfg);
823 
824 	/* data? */
825 	if (data) {
826 		data->bytes_xfered = 0;
827 		cmd_cfg |= CMD_CFG_DATA_IO;
828 		cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
829 				      ilog2(meson_mmc_get_timeout_msecs(data)));
830 
831 		if (meson_mmc_desc_chain_mode(data)) {
832 			meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
833 			return;
834 		}
835 
836 		if (data->blocks > 1) {
837 			cmd_cfg |= CMD_CFG_BLOCK_MODE;
838 			cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
839 					      data->blocks);
840 			meson_mmc_set_blksz(mmc, data->blksz);
841 		} else {
842 			cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
843 		}
844 
845 		xfer_bytes = data->blksz * data->blocks;
846 		if (data->flags & MMC_DATA_WRITE) {
847 			cmd_cfg |= CMD_CFG_DATA_WR;
848 			WARN_ON(xfer_bytes > host->bounce_buf_size);
849 			if (host->dram_access_quirk)
850 				meson_mmc_copy_buffer(host, data, xfer_bytes, true);
851 			else
852 				sg_copy_to_buffer(data->sg, data->sg_len,
853 						  host->bounce_buf, xfer_bytes);
854 			dma_wmb();
855 		}
856 
857 		cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
858 	} else {
859 		cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
860 				      ilog2(SD_EMMC_CMD_TIMEOUT));
861 	}
862 
863 	/* Last descriptor */
864 	cmd_cfg |= CMD_CFG_END_OF_CHAIN;
865 	writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
866 	writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
867 	writel(0, host->regs + SD_EMMC_CMD_RSP);
868 	wmb(); /* ensure descriptor is written before kicked */
869 	writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
870 }
871 
872 static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
873 {
874 	struct scatterlist *sg;
875 	int i;
876 
877 	/* Reject request if any element offset or size is not 32bit aligned */
878 	for_each_sg(data->sg, sg, data->sg_len, i) {
879 		if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
880 		    !IS_ALIGNED(sg->length, sizeof(u32))) {
881 			dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
882 				data->sg->offset, data->sg->length);
883 			return -EINVAL;
884 		}
885 	}
886 
887 	return 0;
888 }
889 
890 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
891 {
892 	struct meson_host *host = mmc_priv(mmc);
893 	host->needs_pre_post_req = mrq->data &&
894 			!(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
895 
896 	/*
897 	 * The memory at the end of the controller used as bounce buffer for
898 	 * the dram_access_quirk only accepts 32bit read/write access,
899 	 * check the aligment and length of the data before starting the request.
900 	 */
901 	if (host->dram_access_quirk && mrq->data) {
902 		mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
903 		if (mrq->cmd->error) {
904 			mmc_request_done(mmc, mrq);
905 			return;
906 		}
907 	}
908 
909 	if (host->needs_pre_post_req) {
910 		meson_mmc_get_transfer_mode(mmc, mrq);
911 		if (!meson_mmc_desc_chain_mode(mrq->data))
912 			host->needs_pre_post_req = false;
913 	}
914 
915 	if (host->needs_pre_post_req)
916 		meson_mmc_pre_req(mmc, mrq);
917 
918 	/* Stop execution */
919 	writel(0, host->regs + SD_EMMC_START);
920 
921 	meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
922 }
923 
924 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
925 {
926 	struct meson_host *host = mmc_priv(mmc);
927 
928 	if (cmd->flags & MMC_RSP_136) {
929 		cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
930 		cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
931 		cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
932 		cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
933 	} else if (cmd->flags & MMC_RSP_PRESENT) {
934 		cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
935 	}
936 }
937 
938 static void __meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
939 {
940 	struct meson_host *host = mmc_priv(mmc);
941 	u32 reg_irqen = IRQ_EN_MASK;
942 
943 	if (enable)
944 		reg_irqen |= IRQ_SDIO;
945 	writel(reg_irqen, host->regs + SD_EMMC_IRQ_EN);
946 }
947 
948 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
949 {
950 	struct meson_host *host = dev_id;
951 	struct mmc_command *cmd;
952 	u32 status, raw_status, irq_mask = IRQ_EN_MASK;
953 	irqreturn_t ret = IRQ_NONE;
954 
955 	if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
956 		irq_mask |= IRQ_SDIO;
957 	raw_status = readl(host->regs + SD_EMMC_STATUS);
958 	status = raw_status & irq_mask;
959 
960 	if (!status) {
961 		dev_dbg(host->dev,
962 			"Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
963 			 irq_mask, raw_status);
964 		return IRQ_NONE;
965 	}
966 
967 	if (WARN_ON(!host))
968 		return IRQ_NONE;
969 
970 	/* ack all raised interrupts */
971 	writel(status, host->regs + SD_EMMC_STATUS);
972 
973 	cmd = host->cmd;
974 
975 	if (status & IRQ_SDIO) {
976 		spin_lock(&host->lock);
977 		__meson_mmc_enable_sdio_irq(host->mmc, 0);
978 		sdio_signal_irq(host->mmc);
979 		spin_unlock(&host->lock);
980 		status &= ~IRQ_SDIO;
981 		if (!status)
982 			return IRQ_HANDLED;
983 	}
984 
985 	if (WARN_ON(!cmd))
986 		return IRQ_NONE;
987 
988 	cmd->error = 0;
989 	if (status & IRQ_CRC_ERR) {
990 		dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
991 		cmd->error = -EILSEQ;
992 		ret = IRQ_WAKE_THREAD;
993 		goto out;
994 	}
995 
996 	if (status & IRQ_TIMEOUTS) {
997 		dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
998 		cmd->error = -ETIMEDOUT;
999 		ret = IRQ_WAKE_THREAD;
1000 		goto out;
1001 	}
1002 
1003 	meson_mmc_read_resp(host->mmc, cmd);
1004 
1005 	if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
1006 		struct mmc_data *data = cmd->data;
1007 
1008 		if (data && !cmd->error)
1009 			data->bytes_xfered = data->blksz * data->blocks;
1010 		if (meson_mmc_bounce_buf_read(data) ||
1011 		    meson_mmc_get_next_command(cmd))
1012 			ret = IRQ_WAKE_THREAD;
1013 		else
1014 			ret = IRQ_HANDLED;
1015 	}
1016 
1017 out:
1018 	if (cmd->error) {
1019 		/* Stop desc in case of errors */
1020 		u32 start = readl(host->regs + SD_EMMC_START);
1021 
1022 		start &= ~START_DESC_BUSY;
1023 		writel(start, host->regs + SD_EMMC_START);
1024 	}
1025 
1026 	if (ret == IRQ_HANDLED)
1027 		meson_mmc_request_done(host->mmc, cmd->mrq);
1028 
1029 	return ret;
1030 }
1031 
1032 static int meson_mmc_wait_desc_stop(struct meson_host *host)
1033 {
1034 	u32 status;
1035 
1036 	/*
1037 	 * It may sometimes take a while for it to actually halt. Here, we
1038 	 * are giving it 5ms to comply
1039 	 *
1040 	 * If we don't confirm the descriptor is stopped, it might raise new
1041 	 * IRQs after we have called mmc_request_done() which is bad.
1042 	 */
1043 
1044 	return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
1045 				  !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
1046 				  100, 5000);
1047 }
1048 
1049 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1050 {
1051 	struct meson_host *host = dev_id;
1052 	struct mmc_command *next_cmd, *cmd = host->cmd;
1053 	struct mmc_data *data;
1054 	unsigned int xfer_bytes;
1055 
1056 	if (WARN_ON(!cmd))
1057 		return IRQ_NONE;
1058 
1059 	if (cmd->error) {
1060 		meson_mmc_wait_desc_stop(host);
1061 		meson_mmc_request_done(host->mmc, cmd->mrq);
1062 
1063 		return IRQ_HANDLED;
1064 	}
1065 
1066 	data = cmd->data;
1067 	if (meson_mmc_bounce_buf_read(data)) {
1068 		xfer_bytes = data->blksz * data->blocks;
1069 		WARN_ON(xfer_bytes > host->bounce_buf_size);
1070 		if (host->dram_access_quirk)
1071 			meson_mmc_copy_buffer(host, data, xfer_bytes, false);
1072 		else
1073 			sg_copy_from_buffer(data->sg, data->sg_len,
1074 					    host->bounce_buf, xfer_bytes);
1075 	}
1076 
1077 	next_cmd = meson_mmc_get_next_command(cmd);
1078 	if (next_cmd)
1079 		meson_mmc_start_cmd(host->mmc, next_cmd);
1080 	else
1081 		meson_mmc_request_done(host->mmc, cmd->mrq);
1082 
1083 	return IRQ_HANDLED;
1084 }
1085 
1086 /*
1087  * NOTE: we only need this until the GPIO/pinctrl driver can handle
1088  * interrupts.  For now, the MMC core will use this for polling.
1089  */
1090 static int meson_mmc_get_cd(struct mmc_host *mmc)
1091 {
1092 	int status = mmc_gpio_get_cd(mmc);
1093 
1094 	if (status == -ENOSYS)
1095 		return 1; /* assume present */
1096 
1097 	return status;
1098 }
1099 
1100 static void meson_mmc_cfg_init(struct meson_host *host)
1101 {
1102 	u32 cfg = 0;
1103 
1104 	cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1105 			  ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1106 	cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1107 	cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1108 
1109 	/* abort chain on R/W errors */
1110 	cfg |= CFG_ERR_ABORT;
1111 
1112 	writel(cfg, host->regs + SD_EMMC_CFG);
1113 }
1114 
1115 static int meson_mmc_card_busy(struct mmc_host *mmc)
1116 {
1117 	struct meson_host *host = mmc_priv(mmc);
1118 	u32 regval;
1119 
1120 	regval = readl(host->regs + SD_EMMC_STATUS);
1121 
1122 	/* We are only interrested in lines 0 to 3, so mask the other ones */
1123 	return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1124 }
1125 
1126 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1127 {
1128 	int ret;
1129 
1130 	/* vqmmc regulator is available */
1131 	if (!IS_ERR(mmc->supply.vqmmc)) {
1132 		/*
1133 		 * The usual amlogic setup uses a GPIO to switch from one
1134 		 * regulator to the other. While the voltage ramp up is
1135 		 * pretty fast, care must be taken when switching from 3.3v
1136 		 * to 1.8v. Please make sure the regulator framework is aware
1137 		 * of your own regulator constraints
1138 		 */
1139 		ret = mmc_regulator_set_vqmmc(mmc, ios);
1140 		return ret < 0 ? ret : 0;
1141 	}
1142 
1143 	/* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1144 	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1145 		return 0;
1146 
1147 	return -EINVAL;
1148 }
1149 
1150 static void meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1151 {
1152 	struct meson_host *host = mmc_priv(mmc);
1153 	unsigned long flags;
1154 
1155 	spin_lock_irqsave(&host->lock, flags);
1156 	__meson_mmc_enable_sdio_irq(mmc, enable);
1157 	spin_unlock_irqrestore(&host->lock, flags);
1158 }
1159 
1160 static void meson_mmc_ack_sdio_irq(struct mmc_host *mmc)
1161 {
1162 	meson_mmc_enable_sdio_irq(mmc, 1);
1163 }
1164 
1165 static const struct mmc_host_ops meson_mmc_ops = {
1166 	.request	= meson_mmc_request,
1167 	.set_ios	= meson_mmc_set_ios,
1168 	.get_cd         = meson_mmc_get_cd,
1169 	.pre_req	= meson_mmc_pre_req,
1170 	.post_req	= meson_mmc_post_req,
1171 	.execute_tuning = meson_mmc_resampling_tuning,
1172 	.card_busy	= meson_mmc_card_busy,
1173 	.start_signal_voltage_switch = meson_mmc_voltage_switch,
1174 	.enable_sdio_irq = meson_mmc_enable_sdio_irq,
1175 	.ack_sdio_irq	= meson_mmc_ack_sdio_irq,
1176 };
1177 
1178 static int meson_mmc_probe(struct platform_device *pdev)
1179 {
1180 	struct resource *res;
1181 	struct meson_host *host;
1182 	struct mmc_host *mmc;
1183 	int ret;
1184 
1185 	mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1186 	if (!mmc)
1187 		return -ENOMEM;
1188 	host = mmc_priv(mmc);
1189 	host->mmc = mmc;
1190 	host->dev = &pdev->dev;
1191 	dev_set_drvdata(&pdev->dev, host);
1192 
1193 	/* The G12A SDIO Controller needs an SRAM bounce buffer */
1194 	host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1195 					"amlogic,dram-access-quirk");
1196 
1197 	/* Get regulators and the supported OCR mask */
1198 	host->vqmmc_enabled = false;
1199 	ret = mmc_regulator_get_supply(mmc);
1200 	if (ret)
1201 		goto free_host;
1202 
1203 	ret = mmc_of_parse(mmc);
1204 	if (ret) {
1205 		if (ret != -EPROBE_DEFER)
1206 			dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1207 		goto free_host;
1208 	}
1209 
1210 	mmc->caps |= MMC_CAP_CMD23;
1211 
1212 	if (mmc->caps & MMC_CAP_SDIO_IRQ)
1213 		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
1214 
1215 	host->data = (struct meson_mmc_data *)
1216 		of_device_get_match_data(&pdev->dev);
1217 	if (!host->data) {
1218 		ret = -EINVAL;
1219 		goto free_host;
1220 	}
1221 
1222 	ret = device_reset_optional(&pdev->dev);
1223 	if (ret) {
1224 		dev_err_probe(&pdev->dev, ret, "device reset failed\n");
1225 		goto free_host;
1226 	}
1227 
1228 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1229 	host->regs = devm_ioremap_resource(&pdev->dev, res);
1230 	if (IS_ERR(host->regs)) {
1231 		ret = PTR_ERR(host->regs);
1232 		goto free_host;
1233 	}
1234 
1235 	host->irq = platform_get_irq(pdev, 0);
1236 	if (host->irq <= 0) {
1237 		ret = -EINVAL;
1238 		goto free_host;
1239 	}
1240 
1241 	host->pinctrl = devm_pinctrl_get(&pdev->dev);
1242 	if (IS_ERR(host->pinctrl)) {
1243 		ret = PTR_ERR(host->pinctrl);
1244 		goto free_host;
1245 	}
1246 
1247 	host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1248 						   "clk-gate");
1249 	if (IS_ERR(host->pins_clk_gate)) {
1250 		dev_warn(&pdev->dev,
1251 			 "can't get clk-gate pinctrl, using clk_stop bit\n");
1252 		host->pins_clk_gate = NULL;
1253 	}
1254 
1255 	host->core_clk = devm_clk_get(&pdev->dev, "core");
1256 	if (IS_ERR(host->core_clk)) {
1257 		ret = PTR_ERR(host->core_clk);
1258 		goto free_host;
1259 	}
1260 
1261 	ret = clk_prepare_enable(host->core_clk);
1262 	if (ret)
1263 		goto free_host;
1264 
1265 	ret = meson_mmc_clk_init(host);
1266 	if (ret)
1267 		goto err_core_clk;
1268 
1269 	/* set config to sane default */
1270 	meson_mmc_cfg_init(host);
1271 
1272 	/* Stop execution */
1273 	writel(0, host->regs + SD_EMMC_START);
1274 
1275 	/* clear, ack and enable interrupts */
1276 	writel(0, host->regs + SD_EMMC_IRQ_EN);
1277 	writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
1278 	writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);
1279 
1280 	ret = request_threaded_irq(host->irq, meson_mmc_irq,
1281 				   meson_mmc_irq_thread, IRQF_ONESHOT,
1282 				   dev_name(&pdev->dev), host);
1283 	if (ret)
1284 		goto err_init_clk;
1285 
1286 	spin_lock_init(&host->lock);
1287 
1288 	if (host->dram_access_quirk) {
1289 		/* Limit segments to 1 due to low available sram memory */
1290 		mmc->max_segs = 1;
1291 		/* Limit to the available sram memory */
1292 		mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
1293 				     mmc->max_blk_size;
1294 	} else {
1295 		mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1296 		mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1297 				sizeof(struct sd_emmc_desc);
1298 	}
1299 	mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1300 	mmc->max_seg_size = mmc->max_req_size;
1301 
1302 	/*
1303 	 * At the moment, we don't know how to reliably enable HS400.
1304 	 * From the different datasheets, it is not even clear if this mode
1305 	 * is officially supported by any of the SoCs
1306 	 */
1307 	mmc->caps2 &= ~MMC_CAP2_HS400;
1308 
1309 	if (host->dram_access_quirk) {
1310 		/*
1311 		 * The MMC Controller embeds 1,5KiB of internal SRAM
1312 		 * that can be used to be used as bounce buffer.
1313 		 * In the case of the G12A SDIO controller, use these
1314 		 * instead of the DDR memory
1315 		 */
1316 		host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1317 		host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1318 		host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1319 	} else {
1320 		/* data bounce buffer */
1321 		host->bounce_buf_size = mmc->max_req_size;
1322 		host->bounce_buf =
1323 			dmam_alloc_coherent(host->dev, host->bounce_buf_size,
1324 					    &host->bounce_dma_addr, GFP_KERNEL);
1325 		if (host->bounce_buf == NULL) {
1326 			dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1327 			ret = -ENOMEM;
1328 			goto err_free_irq;
1329 		}
1330 	}
1331 
1332 	host->descs = dmam_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1333 					  &host->descs_dma_addr, GFP_KERNEL);
1334 	if (!host->descs) {
1335 		dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1336 		ret = -ENOMEM;
1337 		goto err_free_irq;
1338 	}
1339 
1340 	mmc->ops = &meson_mmc_ops;
1341 	ret = mmc_add_host(mmc);
1342 	if (ret)
1343 		goto err_free_irq;
1344 
1345 	return 0;
1346 
1347 err_free_irq:
1348 	free_irq(host->irq, host);
1349 err_init_clk:
1350 	clk_disable_unprepare(host->mmc_clk);
1351 err_core_clk:
1352 	clk_disable_unprepare(host->core_clk);
1353 free_host:
1354 	mmc_free_host(mmc);
1355 	return ret;
1356 }
1357 
1358 static int meson_mmc_remove(struct platform_device *pdev)
1359 {
1360 	struct meson_host *host = dev_get_drvdata(&pdev->dev);
1361 
1362 	mmc_remove_host(host->mmc);
1363 
1364 	/* disable interrupts */
1365 	writel(0, host->regs + SD_EMMC_IRQ_EN);
1366 	free_irq(host->irq, host);
1367 
1368 	clk_disable_unprepare(host->mmc_clk);
1369 	clk_disable_unprepare(host->core_clk);
1370 
1371 	mmc_free_host(host->mmc);
1372 	return 0;
1373 }
1374 
1375 static const struct meson_mmc_data meson_gx_data = {
1376 	.tx_delay_mask	= CLK_V2_TX_DELAY_MASK,
1377 	.rx_delay_mask	= CLK_V2_RX_DELAY_MASK,
1378 	.always_on	= CLK_V2_ALWAYS_ON,
1379 	.adjust		= SD_EMMC_ADJUST,
1380 	.irq_sdio_sleep	= CLK_V2_IRQ_SDIO_SLEEP,
1381 };
1382 
1383 static const struct meson_mmc_data meson_axg_data = {
1384 	.tx_delay_mask	= CLK_V3_TX_DELAY_MASK,
1385 	.rx_delay_mask	= CLK_V3_RX_DELAY_MASK,
1386 	.always_on	= CLK_V3_ALWAYS_ON,
1387 	.adjust		= SD_EMMC_V3_ADJUST,
1388 	.irq_sdio_sleep	= CLK_V3_IRQ_SDIO_SLEEP,
1389 };
1390 
1391 static const struct of_device_id meson_mmc_of_match[] = {
1392 	{ .compatible = "amlogic,meson-gx-mmc",		.data = &meson_gx_data },
1393 	{ .compatible = "amlogic,meson-gxbb-mmc", 	.data = &meson_gx_data },
1394 	{ .compatible = "amlogic,meson-gxl-mmc",	.data = &meson_gx_data },
1395 	{ .compatible = "amlogic,meson-gxm-mmc",	.data = &meson_gx_data },
1396 	{ .compatible = "amlogic,meson-axg-mmc",	.data = &meson_axg_data },
1397 	{}
1398 };
1399 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1400 
1401 static struct platform_driver meson_mmc_driver = {
1402 	.probe		= meson_mmc_probe,
1403 	.remove		= meson_mmc_remove,
1404 	.driver		= {
1405 		.name = DRIVER_NAME,
1406 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1407 		.of_match_table = meson_mmc_of_match,
1408 	},
1409 };
1410 
1411 module_platform_driver(meson_mmc_driver);
1412 
1413 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1414 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1415 MODULE_LICENSE("GPL v2");
1416