1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ioport.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/slot-gpio.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitfield.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "meson-gx-mmc" 32 33 #define SD_EMMC_CLOCK 0x0 34 #define CLK_DIV_MASK GENMASK(5, 0) 35 #define CLK_SRC_MASK GENMASK(7, 6) 36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 39 #define CLK_PHASE_0 0 40 #define CLK_PHASE_180 2 41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43 #define CLK_V2_ALWAYS_ON BIT(24) 44 #define CLK_V2_IRQ_SDIO_SLEEP BIT(25) 45 46 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 47 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 48 #define CLK_V3_ALWAYS_ON BIT(28) 49 #define CLK_V3_IRQ_SDIO_SLEEP BIT(29) 50 51 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 52 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 53 #define CLK_ALWAYS_ON(h) (h->data->always_on) 54 #define CLK_IRQ_SDIO_SLEEP(h) (h->data->irq_sdio_sleep) 55 56 #define SD_EMMC_DELAY 0x4 57 #define SD_EMMC_ADJUST 0x8 58 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 59 #define ADJUST_DS_EN BIT(15) 60 #define ADJUST_ADJ_EN BIT(13) 61 62 #define SD_EMMC_DELAY1 0x4 63 #define SD_EMMC_DELAY2 0x8 64 #define SD_EMMC_V3_ADJUST 0xc 65 66 #define SD_EMMC_CALOUT 0x10 67 #define SD_EMMC_START 0x40 68 #define START_DESC_INIT BIT(0) 69 #define START_DESC_BUSY BIT(1) 70 #define START_DESC_ADDR_MASK GENMASK(31, 2) 71 72 #define SD_EMMC_CFG 0x44 73 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 74 #define CFG_BUS_WIDTH_1 0x0 75 #define CFG_BUS_WIDTH_4 0x1 76 #define CFG_BUS_WIDTH_8 0x2 77 #define CFG_DDR BIT(2) 78 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 79 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 80 #define CFG_RC_CC_MASK GENMASK(15, 12) 81 #define CFG_STOP_CLOCK BIT(22) 82 #define CFG_CLK_ALWAYS_ON BIT(18) 83 #define CFG_CHK_DS BIT(20) 84 #define CFG_AUTO_CLK BIT(23) 85 #define CFG_ERR_ABORT BIT(27) 86 87 #define SD_EMMC_STATUS 0x48 88 #define STATUS_BUSY BIT(31) 89 #define STATUS_DESC_BUSY BIT(30) 90 #define STATUS_DATI GENMASK(23, 16) 91 92 #define SD_EMMC_IRQ_EN 0x4c 93 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 94 #define IRQ_TXD_ERR BIT(8) 95 #define IRQ_DESC_ERR BIT(9) 96 #define IRQ_RESP_ERR BIT(10) 97 #define IRQ_CRC_ERR \ 98 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 99 #define IRQ_RESP_TIMEOUT BIT(11) 100 #define IRQ_DESC_TIMEOUT BIT(12) 101 #define IRQ_TIMEOUTS \ 102 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 103 #define IRQ_END_OF_CHAIN BIT(13) 104 #define IRQ_RESP_STATUS BIT(14) 105 #define IRQ_SDIO BIT(15) 106 #define IRQ_EN_MASK \ 107 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN) 108 109 #define SD_EMMC_CMD_CFG 0x50 110 #define SD_EMMC_CMD_ARG 0x54 111 #define SD_EMMC_CMD_DAT 0x58 112 #define SD_EMMC_CMD_RSP 0x5c 113 #define SD_EMMC_CMD_RSP1 0x60 114 #define SD_EMMC_CMD_RSP2 0x64 115 #define SD_EMMC_CMD_RSP3 0x68 116 117 #define SD_EMMC_RXD 0x94 118 #define SD_EMMC_TXD 0x94 119 #define SD_EMMC_LAST_REG SD_EMMC_TXD 120 121 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536 122 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 123 124 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 125 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 126 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 127 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 128 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 129 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 130 131 #define SD_EMMC_PRE_REQ_DONE BIT(0) 132 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 133 134 #define MUX_CLK_NUM_PARENTS 2 135 136 struct meson_mmc_data { 137 unsigned int tx_delay_mask; 138 unsigned int rx_delay_mask; 139 unsigned int always_on; 140 unsigned int adjust; 141 unsigned int irq_sdio_sleep; 142 }; 143 144 struct sd_emmc_desc { 145 u32 cmd_cfg; 146 u32 cmd_arg; 147 u32 cmd_data; 148 u32 cmd_resp; 149 }; 150 151 struct meson_host { 152 struct device *dev; 153 struct meson_mmc_data *data; 154 struct mmc_host *mmc; 155 struct mmc_command *cmd; 156 157 void __iomem *regs; 158 struct clk *mux_clk; 159 struct clk *mmc_clk; 160 unsigned long req_rate; 161 bool ddr; 162 163 bool dram_access_quirk; 164 165 struct pinctrl *pinctrl; 166 struct pinctrl_state *pins_clk_gate; 167 168 unsigned int bounce_buf_size; 169 void *bounce_buf; 170 void __iomem *bounce_iomem_buf; 171 dma_addr_t bounce_dma_addr; 172 struct sd_emmc_desc *descs; 173 dma_addr_t descs_dma_addr; 174 175 int irq; 176 177 bool vqmmc_enabled; 178 bool needs_pre_post_req; 179 180 spinlock_t lock; 181 }; 182 183 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 184 #define CMD_CFG_BLOCK_MODE BIT(9) 185 #define CMD_CFG_R1B BIT(10) 186 #define CMD_CFG_END_OF_CHAIN BIT(11) 187 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 188 #define CMD_CFG_NO_RESP BIT(16) 189 #define CMD_CFG_NO_CMD BIT(17) 190 #define CMD_CFG_DATA_IO BIT(18) 191 #define CMD_CFG_DATA_WR BIT(19) 192 #define CMD_CFG_RESP_NOCRC BIT(20) 193 #define CMD_CFG_RESP_128 BIT(21) 194 #define CMD_CFG_RESP_NUM BIT(22) 195 #define CMD_CFG_DATA_NUM BIT(23) 196 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 197 #define CMD_CFG_ERROR BIT(30) 198 #define CMD_CFG_OWNER BIT(31) 199 200 #define CMD_DATA_MASK GENMASK(31, 2) 201 #define CMD_DATA_BIG_ENDIAN BIT(1) 202 #define CMD_DATA_SRAM BIT(0) 203 #define CMD_RESP_MASK GENMASK(31, 1) 204 #define CMD_RESP_SRAM BIT(0) 205 206 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 207 { 208 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 209 210 if (!timeout) 211 return SD_EMMC_CMD_TIMEOUT_DATA; 212 213 timeout = roundup_pow_of_two(timeout); 214 215 return min(timeout, 32768U); /* max. 2^15 ms */ 216 } 217 218 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 219 { 220 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 221 return cmd->mrq->cmd; 222 else if (mmc_op_multi(cmd->opcode) && 223 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 224 return cmd->mrq->stop; 225 else 226 return NULL; 227 } 228 229 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 230 struct mmc_request *mrq) 231 { 232 struct meson_host *host = mmc_priv(mmc); 233 struct mmc_data *data = mrq->data; 234 struct scatterlist *sg; 235 int i; 236 237 /* 238 * When Controller DMA cannot directly access DDR memory, disable 239 * support for Chain Mode to directly use the internal SRAM using 240 * the bounce buffer mode. 241 */ 242 if (host->dram_access_quirk) 243 return; 244 245 /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */ 246 if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) { 247 /* 248 * In block mode DMA descriptor format, "length" field indicates 249 * number of blocks and there is no way to pass DMA size that 250 * is not multiple of SDIO block size, making it impossible to 251 * tie more than one memory buffer with single SDIO block. 252 * Block mode sg buffer size should be aligned with SDIO block 253 * size, otherwise chain mode could not be used. 254 */ 255 for_each_sg(data->sg, sg, data->sg_len, i) { 256 if (sg->length % data->blksz) { 257 dev_warn_once(mmc_dev(mmc), 258 "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n", 259 sg->length, data->blksz); 260 return; 261 } 262 } 263 } 264 265 for_each_sg(data->sg, sg, data->sg_len, i) { 266 /* check for 8 byte alignment */ 267 if (sg->offset % 8) { 268 dev_warn_once(mmc_dev(mmc), 269 "unaligned sg offset %u, disabling descriptor DMA for transfer\n", 270 sg->offset); 271 return; 272 } 273 } 274 275 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 276 } 277 278 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 279 { 280 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 281 } 282 283 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 284 { 285 return data && data->flags & MMC_DATA_READ && 286 !meson_mmc_desc_chain_mode(data); 287 } 288 289 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 290 { 291 struct mmc_data *data = mrq->data; 292 293 if (!data) 294 return; 295 296 meson_mmc_get_transfer_mode(mmc, mrq); 297 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 298 299 if (!meson_mmc_desc_chain_mode(data)) 300 return; 301 302 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 303 mmc_get_dma_dir(data)); 304 if (!data->sg_count) 305 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 306 } 307 308 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 309 int err) 310 { 311 struct mmc_data *data = mrq->data; 312 313 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 314 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 315 mmc_get_dma_dir(data)); 316 } 317 318 /* 319 * Gating the clock on this controller is tricky. It seems the mmc clock 320 * is also used by the controller. It may crash during some operation if the 321 * clock is stopped. The safest thing to do, whenever possible, is to keep 322 * clock running at stop it at the pad using the pinmux. 323 */ 324 static void meson_mmc_clk_gate(struct meson_host *host) 325 { 326 u32 cfg; 327 328 if (host->pins_clk_gate) { 329 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 330 } else { 331 /* 332 * If the pinmux is not provided - default to the classic and 333 * unsafe method 334 */ 335 cfg = readl(host->regs + SD_EMMC_CFG); 336 cfg |= CFG_STOP_CLOCK; 337 writel(cfg, host->regs + SD_EMMC_CFG); 338 } 339 } 340 341 static void meson_mmc_clk_ungate(struct meson_host *host) 342 { 343 u32 cfg; 344 345 if (host->pins_clk_gate) 346 pinctrl_select_default_state(host->dev); 347 348 /* Make sure the clock is not stopped in the controller */ 349 cfg = readl(host->regs + SD_EMMC_CFG); 350 cfg &= ~CFG_STOP_CLOCK; 351 writel(cfg, host->regs + SD_EMMC_CFG); 352 } 353 354 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 355 bool ddr) 356 { 357 struct mmc_host *mmc = host->mmc; 358 int ret; 359 u32 cfg; 360 361 /* Same request - bail-out */ 362 if (host->ddr == ddr && host->req_rate == rate) 363 return 0; 364 365 /* stop clock */ 366 meson_mmc_clk_gate(host); 367 host->req_rate = 0; 368 mmc->actual_clock = 0; 369 370 /* return with clock being stopped */ 371 if (!rate) 372 return 0; 373 374 /* Stop the clock during rate change to avoid glitches */ 375 cfg = readl(host->regs + SD_EMMC_CFG); 376 cfg |= CFG_STOP_CLOCK; 377 writel(cfg, host->regs + SD_EMMC_CFG); 378 379 if (ddr) { 380 /* DDR modes require higher module clock */ 381 rate <<= 1; 382 cfg |= CFG_DDR; 383 } else { 384 cfg &= ~CFG_DDR; 385 } 386 writel(cfg, host->regs + SD_EMMC_CFG); 387 host->ddr = ddr; 388 389 ret = clk_set_rate(host->mmc_clk, rate); 390 if (ret) { 391 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 392 rate, ret); 393 return ret; 394 } 395 396 host->req_rate = rate; 397 mmc->actual_clock = clk_get_rate(host->mmc_clk); 398 399 /* We should report the real output frequency of the controller */ 400 if (ddr) { 401 host->req_rate >>= 1; 402 mmc->actual_clock >>= 1; 403 } 404 405 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 406 if (rate != mmc->actual_clock) 407 dev_dbg(host->dev, "requested rate was %lu\n", rate); 408 409 /* (re)start clock */ 410 meson_mmc_clk_ungate(host); 411 412 return 0; 413 } 414 415 /* 416 * The SD/eMMC IP block has an internal mux and divider used for 417 * generating the MMC clock. Use the clock framework to create and 418 * manage these clocks. 419 */ 420 static int meson_mmc_clk_init(struct meson_host *host) 421 { 422 struct clk_init_data init; 423 struct clk_mux *mux; 424 struct clk_divider *div; 425 char clk_name[32]; 426 int i, ret = 0; 427 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 428 const char *clk_parent[1]; 429 u32 clk_reg; 430 431 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 432 clk_reg = CLK_ALWAYS_ON(host); 433 clk_reg |= CLK_DIV_MASK; 434 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 435 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 436 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 437 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 438 clk_reg |= CLK_IRQ_SDIO_SLEEP(host); 439 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 440 441 /* get the mux parents */ 442 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 443 struct clk *clk; 444 char name[16]; 445 446 snprintf(name, sizeof(name), "clkin%d", i); 447 clk = devm_clk_get(host->dev, name); 448 if (IS_ERR(clk)) 449 return dev_err_probe(host->dev, PTR_ERR(clk), 450 "Missing clock %s\n", name); 451 452 mux_parent_names[i] = __clk_get_name(clk); 453 } 454 455 /* create the mux */ 456 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 457 if (!mux) 458 return -ENOMEM; 459 460 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 461 init.name = clk_name; 462 init.ops = &clk_mux_ops; 463 init.flags = 0; 464 init.parent_names = mux_parent_names; 465 init.num_parents = MUX_CLK_NUM_PARENTS; 466 467 mux->reg = host->regs + SD_EMMC_CLOCK; 468 mux->shift = __ffs(CLK_SRC_MASK); 469 mux->mask = CLK_SRC_MASK >> mux->shift; 470 mux->hw.init = &init; 471 472 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 473 if (WARN_ON(IS_ERR(host->mux_clk))) 474 return PTR_ERR(host->mux_clk); 475 476 /* create the divider */ 477 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 478 if (!div) 479 return -ENOMEM; 480 481 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 482 init.name = clk_name; 483 init.ops = &clk_divider_ops; 484 init.flags = CLK_SET_RATE_PARENT; 485 clk_parent[0] = __clk_get_name(host->mux_clk); 486 init.parent_names = clk_parent; 487 init.num_parents = 1; 488 489 div->reg = host->regs + SD_EMMC_CLOCK; 490 div->shift = __ffs(CLK_DIV_MASK); 491 div->width = __builtin_popcountl(CLK_DIV_MASK); 492 div->hw.init = &init; 493 div->flags = CLK_DIVIDER_ONE_BASED; 494 495 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 496 if (WARN_ON(IS_ERR(host->mmc_clk))) 497 return PTR_ERR(host->mmc_clk); 498 499 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 500 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 501 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 502 if (ret) 503 return ret; 504 505 return clk_prepare_enable(host->mmc_clk); 506 } 507 508 static void meson_mmc_disable_resampling(struct meson_host *host) 509 { 510 unsigned int val = readl(host->regs + host->data->adjust); 511 512 val &= ~ADJUST_ADJ_EN; 513 writel(val, host->regs + host->data->adjust); 514 } 515 516 static void meson_mmc_reset_resampling(struct meson_host *host) 517 { 518 unsigned int val; 519 520 meson_mmc_disable_resampling(host); 521 522 val = readl(host->regs + host->data->adjust); 523 val &= ~ADJUST_ADJ_DELAY_MASK; 524 writel(val, host->regs + host->data->adjust); 525 } 526 527 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 528 { 529 struct meson_host *host = mmc_priv(mmc); 530 unsigned int val, dly, max_dly, i; 531 int ret; 532 533 /* Resampling is done using the source clock */ 534 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 535 clk_get_rate(host->mmc_clk)); 536 537 val = readl(host->regs + host->data->adjust); 538 val |= ADJUST_ADJ_EN; 539 writel(val, host->regs + host->data->adjust); 540 541 if (mmc_doing_retune(mmc)) 542 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 543 else 544 dly = 0; 545 546 for (i = 0; i < max_dly; i++) { 547 val &= ~ADJUST_ADJ_DELAY_MASK; 548 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 549 writel(val, host->regs + host->data->adjust); 550 551 ret = mmc_send_tuning(mmc, opcode, NULL); 552 if (!ret) { 553 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 554 (dly + i) % max_dly); 555 return 0; 556 } 557 } 558 559 meson_mmc_reset_resampling(host); 560 return -EIO; 561 } 562 563 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 564 struct mmc_ios *ios) 565 { 566 bool ddr; 567 568 switch (ios->timing) { 569 case MMC_TIMING_MMC_DDR52: 570 case MMC_TIMING_UHS_DDR50: 571 ddr = true; 572 break; 573 574 default: 575 ddr = false; 576 break; 577 } 578 579 return meson_mmc_clk_set(host, ios->clock, ddr); 580 } 581 582 static void meson_mmc_check_resampling(struct meson_host *host, 583 struct mmc_ios *ios) 584 { 585 switch (ios->timing) { 586 case MMC_TIMING_LEGACY: 587 case MMC_TIMING_MMC_HS: 588 case MMC_TIMING_SD_HS: 589 case MMC_TIMING_MMC_DDR52: 590 meson_mmc_disable_resampling(host); 591 break; 592 } 593 } 594 595 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 596 { 597 struct meson_host *host = mmc_priv(mmc); 598 u32 bus_width, val; 599 int err; 600 601 /* 602 * GPIO regulator, only controls switching between 1v8 and 603 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 604 */ 605 switch (ios->power_mode) { 606 case MMC_POWER_OFF: 607 if (!IS_ERR(mmc->supply.vmmc)) 608 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 609 610 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 611 regulator_disable(mmc->supply.vqmmc); 612 host->vqmmc_enabled = false; 613 } 614 615 break; 616 617 case MMC_POWER_UP: 618 if (!IS_ERR(mmc->supply.vmmc)) 619 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 620 621 break; 622 623 case MMC_POWER_ON: 624 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 625 int ret = regulator_enable(mmc->supply.vqmmc); 626 627 if (ret < 0) 628 dev_err(host->dev, 629 "failed to enable vqmmc regulator\n"); 630 else 631 host->vqmmc_enabled = true; 632 } 633 634 break; 635 } 636 637 /* Bus width */ 638 switch (ios->bus_width) { 639 case MMC_BUS_WIDTH_1: 640 bus_width = CFG_BUS_WIDTH_1; 641 break; 642 case MMC_BUS_WIDTH_4: 643 bus_width = CFG_BUS_WIDTH_4; 644 break; 645 case MMC_BUS_WIDTH_8: 646 bus_width = CFG_BUS_WIDTH_8; 647 break; 648 default: 649 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 650 ios->bus_width); 651 bus_width = CFG_BUS_WIDTH_4; 652 } 653 654 val = readl(host->regs + SD_EMMC_CFG); 655 val &= ~CFG_BUS_WIDTH_MASK; 656 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 657 writel(val, host->regs + SD_EMMC_CFG); 658 659 meson_mmc_check_resampling(host, ios); 660 err = meson_mmc_prepare_ios_clock(host, ios); 661 if (err) 662 dev_err(host->dev, "Failed to set clock: %d\n,", err); 663 664 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 665 } 666 667 static void meson_mmc_request_done(struct mmc_host *mmc, 668 struct mmc_request *mrq) 669 { 670 struct meson_host *host = mmc_priv(mmc); 671 672 host->cmd = NULL; 673 if (host->needs_pre_post_req) 674 meson_mmc_post_req(mmc, mrq, 0); 675 mmc_request_done(host->mmc, mrq); 676 } 677 678 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 679 { 680 struct meson_host *host = mmc_priv(mmc); 681 u32 cfg, blksz_old; 682 683 cfg = readl(host->regs + SD_EMMC_CFG); 684 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 685 686 if (!is_power_of_2(blksz)) 687 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 688 689 blksz = ilog2(blksz); 690 691 /* check if block-size matches, if not update */ 692 if (blksz == blksz_old) 693 return; 694 695 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 696 blksz_old, blksz); 697 698 cfg &= ~CFG_BLK_LEN_MASK; 699 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 700 writel(cfg, host->regs + SD_EMMC_CFG); 701 } 702 703 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 704 { 705 if (cmd->flags & MMC_RSP_PRESENT) { 706 if (cmd->flags & MMC_RSP_136) 707 *cmd_cfg |= CMD_CFG_RESP_128; 708 *cmd_cfg |= CMD_CFG_RESP_NUM; 709 710 if (!(cmd->flags & MMC_RSP_CRC)) 711 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 712 713 if (cmd->flags & MMC_RSP_BUSY) 714 *cmd_cfg |= CMD_CFG_R1B; 715 } else { 716 *cmd_cfg |= CMD_CFG_NO_RESP; 717 } 718 } 719 720 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 721 { 722 struct meson_host *host = mmc_priv(mmc); 723 struct sd_emmc_desc *desc = host->descs; 724 struct mmc_data *data = host->cmd->data; 725 struct scatterlist *sg; 726 u32 start; 727 int i; 728 729 if (data->flags & MMC_DATA_WRITE) 730 cmd_cfg |= CMD_CFG_DATA_WR; 731 732 if (data->blocks > 1) { 733 cmd_cfg |= CMD_CFG_BLOCK_MODE; 734 meson_mmc_set_blksz(mmc, data->blksz); 735 } 736 737 for_each_sg(data->sg, sg, data->sg_count, i) { 738 unsigned int len = sg_dma_len(sg); 739 740 if (data->blocks > 1) 741 len /= data->blksz; 742 743 desc[i].cmd_cfg = cmd_cfg; 744 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 745 if (i > 0) 746 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 747 desc[i].cmd_arg = host->cmd->arg; 748 desc[i].cmd_resp = 0; 749 desc[i].cmd_data = sg_dma_address(sg); 750 } 751 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 752 753 dma_wmb(); /* ensure descriptor is written before kicked */ 754 start = host->descs_dma_addr | START_DESC_BUSY; 755 writel(start, host->regs + SD_EMMC_START); 756 } 757 758 /* local sg copy for dram_access_quirk */ 759 static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data, 760 size_t buflen, bool to_buffer) 761 { 762 unsigned int sg_flags = SG_MITER_ATOMIC; 763 struct scatterlist *sgl = data->sg; 764 unsigned int nents = data->sg_len; 765 struct sg_mapping_iter miter; 766 unsigned int offset = 0; 767 768 if (to_buffer) 769 sg_flags |= SG_MITER_FROM_SG; 770 else 771 sg_flags |= SG_MITER_TO_SG; 772 773 sg_miter_start(&miter, sgl, nents, sg_flags); 774 775 while ((offset < buflen) && sg_miter_next(&miter)) { 776 unsigned int buf_offset = 0; 777 unsigned int len, left; 778 u32 *buf = miter.addr; 779 780 len = min(miter.length, buflen - offset); 781 left = len; 782 783 if (to_buffer) { 784 do { 785 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset); 786 787 buf_offset += 4; 788 left -= 4; 789 } while (left); 790 } else { 791 do { 792 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset); 793 794 buf_offset += 4; 795 left -= 4; 796 } while (left); 797 } 798 799 offset += len; 800 } 801 802 sg_miter_stop(&miter); 803 } 804 805 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 806 { 807 struct meson_host *host = mmc_priv(mmc); 808 struct mmc_data *data = cmd->data; 809 u32 cmd_cfg = 0, cmd_data = 0; 810 unsigned int xfer_bytes = 0; 811 812 /* Setup descriptors */ 813 dma_rmb(); 814 815 host->cmd = cmd; 816 817 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 818 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 819 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 820 821 meson_mmc_set_response_bits(cmd, &cmd_cfg); 822 823 /* data? */ 824 if (data) { 825 data->bytes_xfered = 0; 826 cmd_cfg |= CMD_CFG_DATA_IO; 827 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 828 ilog2(meson_mmc_get_timeout_msecs(data))); 829 830 if (meson_mmc_desc_chain_mode(data)) { 831 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 832 return; 833 } 834 835 if (data->blocks > 1) { 836 cmd_cfg |= CMD_CFG_BLOCK_MODE; 837 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 838 data->blocks); 839 meson_mmc_set_blksz(mmc, data->blksz); 840 } else { 841 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 842 } 843 844 xfer_bytes = data->blksz * data->blocks; 845 if (data->flags & MMC_DATA_WRITE) { 846 cmd_cfg |= CMD_CFG_DATA_WR; 847 WARN_ON(xfer_bytes > host->bounce_buf_size); 848 if (host->dram_access_quirk) 849 meson_mmc_copy_buffer(host, data, xfer_bytes, true); 850 else 851 sg_copy_to_buffer(data->sg, data->sg_len, 852 host->bounce_buf, xfer_bytes); 853 dma_wmb(); 854 } 855 856 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 857 } else { 858 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 859 ilog2(SD_EMMC_CMD_TIMEOUT)); 860 } 861 862 /* Last descriptor */ 863 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 864 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 865 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 866 writel(0, host->regs + SD_EMMC_CMD_RSP); 867 wmb(); /* ensure descriptor is written before kicked */ 868 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 869 } 870 871 static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data) 872 { 873 struct scatterlist *sg; 874 int i; 875 876 /* Reject request if any element offset or size is not 32bit aligned */ 877 for_each_sg(data->sg, sg, data->sg_len, i) { 878 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || 879 !IS_ALIGNED(sg->length, sizeof(u32))) { 880 dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n", 881 data->sg->offset, data->sg->length); 882 return -EINVAL; 883 } 884 } 885 886 return 0; 887 } 888 889 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 890 { 891 struct meson_host *host = mmc_priv(mmc); 892 host->needs_pre_post_req = mrq->data && 893 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 894 895 /* 896 * The memory at the end of the controller used as bounce buffer for 897 * the dram_access_quirk only accepts 32bit read/write access, 898 * check the aligment and length of the data before starting the request. 899 */ 900 if (host->dram_access_quirk && mrq->data) { 901 mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data); 902 if (mrq->cmd->error) { 903 mmc_request_done(mmc, mrq); 904 return; 905 } 906 } 907 908 if (host->needs_pre_post_req) { 909 meson_mmc_get_transfer_mode(mmc, mrq); 910 if (!meson_mmc_desc_chain_mode(mrq->data)) 911 host->needs_pre_post_req = false; 912 } 913 914 if (host->needs_pre_post_req) 915 meson_mmc_pre_req(mmc, mrq); 916 917 /* Stop execution */ 918 writel(0, host->regs + SD_EMMC_START); 919 920 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 921 } 922 923 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 924 { 925 struct meson_host *host = mmc_priv(mmc); 926 927 if (cmd->flags & MMC_RSP_136) { 928 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 929 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 930 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 931 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 932 } else if (cmd->flags & MMC_RSP_PRESENT) { 933 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 934 } 935 } 936 937 static void __meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 938 { 939 struct meson_host *host = mmc_priv(mmc); 940 u32 reg_irqen = IRQ_EN_MASK; 941 942 if (enable) 943 reg_irqen |= IRQ_SDIO; 944 writel(reg_irqen, host->regs + SD_EMMC_IRQ_EN); 945 } 946 947 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 948 { 949 struct meson_host *host = dev_id; 950 struct mmc_command *cmd; 951 u32 status, raw_status, irq_mask = IRQ_EN_MASK; 952 irqreturn_t ret = IRQ_NONE; 953 954 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 955 irq_mask |= IRQ_SDIO; 956 raw_status = readl(host->regs + SD_EMMC_STATUS); 957 status = raw_status & irq_mask; 958 959 if (!status) { 960 dev_dbg(host->dev, 961 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 962 irq_mask, raw_status); 963 return IRQ_NONE; 964 } 965 966 if (WARN_ON(!host)) 967 return IRQ_NONE; 968 969 /* ack all raised interrupts */ 970 writel(status, host->regs + SD_EMMC_STATUS); 971 972 cmd = host->cmd; 973 974 if (status & IRQ_SDIO) { 975 spin_lock(&host->lock); 976 __meson_mmc_enable_sdio_irq(host->mmc, 0); 977 sdio_signal_irq(host->mmc); 978 spin_unlock(&host->lock); 979 status &= ~IRQ_SDIO; 980 if (!status) 981 return IRQ_HANDLED; 982 } 983 984 if (WARN_ON(!cmd)) 985 return IRQ_NONE; 986 987 cmd->error = 0; 988 if (status & IRQ_CRC_ERR) { 989 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 990 cmd->error = -EILSEQ; 991 ret = IRQ_WAKE_THREAD; 992 goto out; 993 } 994 995 if (status & IRQ_TIMEOUTS) { 996 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 997 cmd->error = -ETIMEDOUT; 998 ret = IRQ_WAKE_THREAD; 999 goto out; 1000 } 1001 1002 meson_mmc_read_resp(host->mmc, cmd); 1003 1004 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 1005 struct mmc_data *data = cmd->data; 1006 1007 if (data && !cmd->error) 1008 data->bytes_xfered = data->blksz * data->blocks; 1009 if (meson_mmc_bounce_buf_read(data) || 1010 meson_mmc_get_next_command(cmd)) 1011 ret = IRQ_WAKE_THREAD; 1012 else 1013 ret = IRQ_HANDLED; 1014 } 1015 1016 out: 1017 if (cmd->error) { 1018 /* Stop desc in case of errors */ 1019 u32 start = readl(host->regs + SD_EMMC_START); 1020 1021 start &= ~START_DESC_BUSY; 1022 writel(start, host->regs + SD_EMMC_START); 1023 } 1024 1025 if (ret == IRQ_HANDLED) 1026 meson_mmc_request_done(host->mmc, cmd->mrq); 1027 1028 return ret; 1029 } 1030 1031 static int meson_mmc_wait_desc_stop(struct meson_host *host) 1032 { 1033 u32 status; 1034 1035 /* 1036 * It may sometimes take a while for it to actually halt. Here, we 1037 * are giving it 5ms to comply 1038 * 1039 * If we don't confirm the descriptor is stopped, it might raise new 1040 * IRQs after we have called mmc_request_done() which is bad. 1041 */ 1042 1043 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 1044 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 1045 100, 5000); 1046 } 1047 1048 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 1049 { 1050 struct meson_host *host = dev_id; 1051 struct mmc_command *next_cmd, *cmd = host->cmd; 1052 struct mmc_data *data; 1053 unsigned int xfer_bytes; 1054 1055 if (WARN_ON(!cmd)) 1056 return IRQ_NONE; 1057 1058 if (cmd->error) { 1059 meson_mmc_wait_desc_stop(host); 1060 meson_mmc_request_done(host->mmc, cmd->mrq); 1061 1062 return IRQ_HANDLED; 1063 } 1064 1065 data = cmd->data; 1066 if (meson_mmc_bounce_buf_read(data)) { 1067 xfer_bytes = data->blksz * data->blocks; 1068 WARN_ON(xfer_bytes > host->bounce_buf_size); 1069 if (host->dram_access_quirk) 1070 meson_mmc_copy_buffer(host, data, xfer_bytes, false); 1071 else 1072 sg_copy_from_buffer(data->sg, data->sg_len, 1073 host->bounce_buf, xfer_bytes); 1074 } 1075 1076 next_cmd = meson_mmc_get_next_command(cmd); 1077 if (next_cmd) 1078 meson_mmc_start_cmd(host->mmc, next_cmd); 1079 else 1080 meson_mmc_request_done(host->mmc, cmd->mrq); 1081 1082 return IRQ_HANDLED; 1083 } 1084 1085 static void meson_mmc_cfg_init(struct meson_host *host) 1086 { 1087 u32 cfg = 0; 1088 1089 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 1090 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 1091 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 1092 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 1093 1094 /* abort chain on R/W errors */ 1095 cfg |= CFG_ERR_ABORT; 1096 1097 writel(cfg, host->regs + SD_EMMC_CFG); 1098 } 1099 1100 static int meson_mmc_card_busy(struct mmc_host *mmc) 1101 { 1102 struct meson_host *host = mmc_priv(mmc); 1103 u32 regval; 1104 1105 regval = readl(host->regs + SD_EMMC_STATUS); 1106 1107 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1108 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1109 } 1110 1111 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1112 { 1113 int ret; 1114 1115 /* vqmmc regulator is available */ 1116 if (!IS_ERR(mmc->supply.vqmmc)) { 1117 /* 1118 * The usual amlogic setup uses a GPIO to switch from one 1119 * regulator to the other. While the voltage ramp up is 1120 * pretty fast, care must be taken when switching from 3.3v 1121 * to 1.8v. Please make sure the regulator framework is aware 1122 * of your own regulator constraints 1123 */ 1124 ret = mmc_regulator_set_vqmmc(mmc, ios); 1125 return ret < 0 ? ret : 0; 1126 } 1127 1128 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1129 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1130 return 0; 1131 1132 return -EINVAL; 1133 } 1134 1135 static void meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 1136 { 1137 struct meson_host *host = mmc_priv(mmc); 1138 unsigned long flags; 1139 1140 spin_lock_irqsave(&host->lock, flags); 1141 __meson_mmc_enable_sdio_irq(mmc, enable); 1142 spin_unlock_irqrestore(&host->lock, flags); 1143 } 1144 1145 static void meson_mmc_ack_sdio_irq(struct mmc_host *mmc) 1146 { 1147 meson_mmc_enable_sdio_irq(mmc, 1); 1148 } 1149 1150 static const struct mmc_host_ops meson_mmc_ops = { 1151 .request = meson_mmc_request, 1152 .set_ios = meson_mmc_set_ios, 1153 .get_cd = mmc_gpio_get_cd, 1154 .pre_req = meson_mmc_pre_req, 1155 .post_req = meson_mmc_post_req, 1156 .execute_tuning = meson_mmc_resampling_tuning, 1157 .card_busy = meson_mmc_card_busy, 1158 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1159 .enable_sdio_irq = meson_mmc_enable_sdio_irq, 1160 .ack_sdio_irq = meson_mmc_ack_sdio_irq, 1161 }; 1162 1163 static int meson_mmc_probe(struct platform_device *pdev) 1164 { 1165 struct resource *res; 1166 struct meson_host *host; 1167 struct mmc_host *mmc; 1168 struct clk *core_clk; 1169 int cd_irq, ret; 1170 1171 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct meson_host)); 1172 if (!mmc) 1173 return -ENOMEM; 1174 host = mmc_priv(mmc); 1175 host->mmc = mmc; 1176 host->dev = &pdev->dev; 1177 dev_set_drvdata(&pdev->dev, host); 1178 1179 /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1180 host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1181 "amlogic,dram-access-quirk"); 1182 1183 /* Get regulators and the supported OCR mask */ 1184 host->vqmmc_enabled = false; 1185 ret = mmc_regulator_get_supply(mmc); 1186 if (ret) 1187 return ret; 1188 1189 ret = mmc_of_parse(mmc); 1190 if (ret) 1191 return dev_err_probe(&pdev->dev, ret, "error parsing DT\n"); 1192 1193 mmc->caps |= MMC_CAP_CMD23; 1194 1195 if (mmc->caps & MMC_CAP_SDIO_IRQ) 1196 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 1197 1198 host->data = (struct meson_mmc_data *) 1199 of_device_get_match_data(&pdev->dev); 1200 if (!host->data) 1201 return -EINVAL; 1202 1203 ret = device_reset_optional(&pdev->dev); 1204 if (ret) 1205 return dev_err_probe(&pdev->dev, ret, "device reset failed\n"); 1206 1207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1208 host->regs = devm_ioremap_resource(&pdev->dev, res); 1209 if (IS_ERR(host->regs)) 1210 return PTR_ERR(host->regs); 1211 1212 host->irq = platform_get_irq(pdev, 0); 1213 if (host->irq <= 0) 1214 return -EINVAL; 1215 1216 cd_irq = platform_get_irq_optional(pdev, 1); 1217 mmc_gpio_set_cd_irq(mmc, cd_irq); 1218 1219 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1220 if (IS_ERR(host->pinctrl)) 1221 return PTR_ERR(host->pinctrl); 1222 1223 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1224 "clk-gate"); 1225 if (IS_ERR(host->pins_clk_gate)) { 1226 dev_warn(&pdev->dev, 1227 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1228 host->pins_clk_gate = NULL; 1229 } 1230 1231 core_clk = devm_clk_get_enabled(&pdev->dev, "core"); 1232 if (IS_ERR(core_clk)) 1233 return PTR_ERR(core_clk); 1234 1235 ret = meson_mmc_clk_init(host); 1236 if (ret) 1237 return ret; 1238 1239 /* set config to sane default */ 1240 meson_mmc_cfg_init(host); 1241 1242 /* Stop execution */ 1243 writel(0, host->regs + SD_EMMC_START); 1244 1245 /* clear, ack and enable interrupts */ 1246 writel(0, host->regs + SD_EMMC_IRQ_EN); 1247 writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); 1248 writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); 1249 1250 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1251 meson_mmc_irq_thread, IRQF_ONESHOT, 1252 dev_name(&pdev->dev), host); 1253 if (ret) 1254 goto err_init_clk; 1255 1256 spin_lock_init(&host->lock); 1257 1258 if (host->dram_access_quirk) { 1259 /* Limit segments to 1 due to low available sram memory */ 1260 mmc->max_segs = 1; 1261 /* Limit to the available sram memory */ 1262 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 1263 mmc->max_blk_size; 1264 } else { 1265 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1266 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1267 sizeof(struct sd_emmc_desc); 1268 } 1269 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1270 mmc->max_seg_size = mmc->max_req_size; 1271 1272 /* 1273 * At the moment, we don't know how to reliably enable HS400. 1274 * From the different datasheets, it is not even clear if this mode 1275 * is officially supported by any of the SoCs 1276 */ 1277 mmc->caps2 &= ~MMC_CAP2_HS400; 1278 1279 if (host->dram_access_quirk) { 1280 /* 1281 * The MMC Controller embeds 1,5KiB of internal SRAM 1282 * that can be used to be used as bounce buffer. 1283 * In the case of the G12A SDIO controller, use these 1284 * instead of the DDR memory 1285 */ 1286 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1287 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1288 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1289 } else { 1290 /* data bounce buffer */ 1291 host->bounce_buf_size = mmc->max_req_size; 1292 host->bounce_buf = 1293 dmam_alloc_coherent(host->dev, host->bounce_buf_size, 1294 &host->bounce_dma_addr, GFP_KERNEL); 1295 if (host->bounce_buf == NULL) { 1296 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1297 ret = -ENOMEM; 1298 goto err_free_irq; 1299 } 1300 } 1301 1302 host->descs = dmam_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1303 &host->descs_dma_addr, GFP_KERNEL); 1304 if (!host->descs) { 1305 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1306 ret = -ENOMEM; 1307 goto err_free_irq; 1308 } 1309 1310 mmc->ops = &meson_mmc_ops; 1311 ret = mmc_add_host(mmc); 1312 if (ret) 1313 goto err_free_irq; 1314 1315 return 0; 1316 1317 err_free_irq: 1318 free_irq(host->irq, host); 1319 err_init_clk: 1320 clk_disable_unprepare(host->mmc_clk); 1321 return ret; 1322 } 1323 1324 static int meson_mmc_remove(struct platform_device *pdev) 1325 { 1326 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1327 1328 mmc_remove_host(host->mmc); 1329 1330 /* disable interrupts */ 1331 writel(0, host->regs + SD_EMMC_IRQ_EN); 1332 free_irq(host->irq, host); 1333 1334 clk_disable_unprepare(host->mmc_clk); 1335 1336 return 0; 1337 } 1338 1339 static const struct meson_mmc_data meson_gx_data = { 1340 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1341 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1342 .always_on = CLK_V2_ALWAYS_ON, 1343 .adjust = SD_EMMC_ADJUST, 1344 .irq_sdio_sleep = CLK_V2_IRQ_SDIO_SLEEP, 1345 }; 1346 1347 static const struct meson_mmc_data meson_axg_data = { 1348 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1349 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1350 .always_on = CLK_V3_ALWAYS_ON, 1351 .adjust = SD_EMMC_V3_ADJUST, 1352 .irq_sdio_sleep = CLK_V3_IRQ_SDIO_SLEEP, 1353 }; 1354 1355 static const struct of_device_id meson_mmc_of_match[] = { 1356 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1357 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1358 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1359 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1360 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1361 {} 1362 }; 1363 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1364 1365 static struct platform_driver meson_mmc_driver = { 1366 .probe = meson_mmc_probe, 1367 .remove = meson_mmc_remove, 1368 .driver = { 1369 .name = DRIVER_NAME, 1370 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1371 .of_match_table = meson_mmc_of_match, 1372 }, 1373 }; 1374 1375 module_platform_driver(meson_mmc_driver); 1376 1377 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1378 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1379 MODULE_LICENSE("GPL v2"); 1380