1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Loongson-2K MMC/SDIO controller driver 4 * 5 * Copyright (C) 2018-2025 Loongson Technology Corporation Limited. 6 * 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/bitrev.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/mmc/core.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sd.h> 21 #include <linux/mmc/sdio.h> 22 #include <linux/mmc/slot-gpio.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 28 #define LOONGSON2_MMC_REG_CTL 0x00 /* Control Register */ 29 #define LOONGSON2_MMC_REG_PRE 0x04 /* Prescaler Register */ 30 #define LOONGSON2_MMC_REG_CARG 0x08 /* Command Register */ 31 #define LOONGSON2_MMC_REG_CCTL 0x0c /* Command Control Register */ 32 #define LOONGSON2_MMC_REG_CSTS 0x10 /* Command Status Register */ 33 #define LOONGSON2_MMC_REG_RSP0 0x14 /* Command Response Register 0 */ 34 #define LOONGSON2_MMC_REG_RSP1 0x18 /* Command Response Register 1 */ 35 #define LOONGSON2_MMC_REG_RSP2 0x1c /* Command Response Register 2 */ 36 #define LOONGSON2_MMC_REG_RSP3 0x20 /* Command Response Register 3 */ 37 #define LOONGSON2_MMC_REG_TIMER 0x24 /* Data Timeout Register */ 38 #define LOONGSON2_MMC_REG_BSIZE 0x28 /* Block Size Register */ 39 #define LOONGSON2_MMC_REG_DCTL 0x2c /* Data Control Register */ 40 #define LOONGSON2_MMC_REG_DCNT 0x30 /* Data Counter Register */ 41 #define LOONGSON2_MMC_REG_DSTS 0x34 /* Data Status Register */ 42 #define LOONGSON2_MMC_REG_FSTS 0x38 /* FIFO Status Register */ 43 #define LOONGSON2_MMC_REG_INT 0x3c /* Interrupt Register */ 44 #define LOONGSON2_MMC_REG_DATA 0x40 /* Data Register */ 45 #define LOONGSON2_MMC_REG_IEN 0x64 /* Interrupt Enable Register */ 46 47 /* EMMC DLL Mode Registers */ 48 #define LOONGSON2_MMC_REG_DLLVAL 0xf0 /* DLL Master Lock-value Register */ 49 #define LOONGSON2_MMC_REG_DLLCTL 0xf4 /* DLL Control Register */ 50 #define LOONGSON2_MMC_REG_DELAY 0xf8 /* DLL Delayed Parameter Register */ 51 #define LOONGSON2_MMC_REG_SEL 0xfc /* Bus Mode Selection Register */ 52 53 /* Exclusive DMA R/W Registers */ 54 #define LOONGSON2_MMC_REG_WDMA_LO 0x400 55 #define LOONGSON2_MMC_REG_WDMA_HI 0x404 56 #define LOONGSON2_MMC_REG_RDMA_LO 0x800 57 #define LOONGSON2_MMC_REG_RDMA_HI 0x804 58 59 /* Bitfields of control register */ 60 #define LOONGSON2_MMC_CTL_ENCLK BIT(0) 61 #define LOONGSON2_MMC_CTL_EXTCLK BIT(1) 62 #define LOONGSON2_MMC_CTL_RESET BIT(8) 63 64 /* Bitfields of prescaler register */ 65 #define LOONGSON2_MMC_PRE GENMASK(9, 0) 66 #define LOONGSON2_MMC_PRE_EN BIT(31) 67 68 /* Bitfields of command control register */ 69 #define LOONGSON2_MMC_CCTL_INDEX GENMASK(5, 0) 70 #define LOONGSON2_MMC_CCTL_HOST BIT(6) 71 #define LOONGSON2_MMC_CCTL_START BIT(8) 72 #define LOONGSON2_MMC_CCTL_WAIT_RSP BIT(9) 73 #define LOONGSON2_MMC_CCTL_LONG_RSP BIT(10) 74 #define LOONGSON2_MMC_CCTL_ABORT BIT(12) 75 #define LOONGSON2_MMC_CCTL_CHECK BIT(13) 76 #define LOONGSON2_MMC_CCTL_SDIO BIT(14) 77 #define LOONGSON2_MMC_CCTL_CMD6 BIT(18) 78 79 /* Bitfields of command status register */ 80 #define LOONGSON2_MMC_CSTS_INDEX GENMASK(7, 0) 81 #define LOONGSON2_MMC_CSTS_ON BIT(8) 82 #define LOONGSON2_MMC_CSTS_RSP BIT(9) 83 #define LOONGSON2_MMC_CSTS_TIMEOUT BIT(10) 84 #define LOONGSON2_MMC_CSTS_END BIT(11) 85 #define LOONGSON2_MMC_CSTS_CRC_ERR BIT(12) 86 #define LOONGSON2_MMC_CSTS_AUTO_STOP BIT(13) 87 #define LOONGSON2_MMC_CSTS_FIN BIT(14) 88 89 /* Bitfields of data timeout register */ 90 #define LOONGSON2_MMC_DTIMR GENMASK(23, 0) 91 92 /* Bitfields of block size register */ 93 #define LOONGSON2_MMC_BSIZE GENMASK(11, 0) 94 95 /* Bitfields of data control register */ 96 #define LOONGSON2_MMC_DCTL_BNUM GENMASK(11, 0) 97 #define LOONGSON2_MMC_DCTL_START BIT(14) 98 #define LOONGSON2_MMC_DCTL_ENDMA BIT(15) 99 #define LOONGSON2_MMC_DCTL_WIDE BIT(16) 100 #define LOONGSON2_MMC_DCTL_RWAIT BIT(17) 101 #define LOONGSON2_MMC_DCTL_IO_SUSPEND BIT(18) 102 #define LOONGSON2_MMC_DCTL_IO_RESUME BIT(19) 103 #define LOONGSON2_MMC_DCTL_RW_RESUME BIT(20) 104 #define LOONGSON2_MMC_DCTL_8BIT_BUS BIT(26) 105 106 /* Bitfields of sata counter register */ 107 #define LOONGSON2_MMC_DCNT_BNUM GENMASK(11, 0) 108 #define LOONGSON2_MMC_DCNT_BYTE GENMASK(23, 12) 109 110 /* Bitfields of command status register */ 111 #define LOONGSON2_MMC_DSTS_RXON BIT(0) 112 #define LOONGSON2_MMC_DSTS_TXON BIT(1) 113 #define LOONGSON2_MMC_DSTS_SBITERR BIT(2) 114 #define LOONGSON2_MMC_DSTS_BUSYFIN BIT(3) 115 #define LOONGSON2_MMC_DSTS_XFERFIN BIT(4) 116 #define LOONGSON2_MMC_DSTS_DTIMEOUT BIT(5) 117 #define LOONGSON2_MMC_DSTS_RXCRC BIT(6) 118 #define LOONGSON2_MMC_DSTS_TXCRC BIT(7) 119 #define LOONGSON2_MMC_DSTS_IRQ BIT(8) 120 #define LOONGSON2_MMC_DSTS_START BIT(13) 121 #define LOONGSON2_MMC_DSTS_RESUME BIT(15) 122 #define LOONGSON2_MMC_DSTS_SUSPEND BIT(16) 123 124 /* Bitfields of FIFO Status Register */ 125 #define LOONGSON2_MMC_FSTS_TXFULL BIT(11) 126 127 /* Bitfields of interrupt register */ 128 #define LOONGSON2_MMC_INT_DFIN BIT(0) 129 #define LOONGSON2_MMC_INT_DTIMEOUT BIT(1) 130 #define LOONGSON2_MMC_INT_RXCRC BIT(2) 131 #define LOONGSON2_MMC_INT_TXCRC BIT(3) 132 #define LOONGSON2_MMC_INT_PROGERR BIT(4) 133 #define LOONGSON2_MMC_INT_SDIOIRQ BIT(5) 134 #define LOONGSON2_MMC_INT_CSENT BIT(6) 135 #define LOONGSON2_MMC_INT_CTIMEOUT BIT(7) 136 #define LOONGSON2_MMC_INT_RESPCRC BIT(8) 137 #define LOONGSON2_MMC_INT_BUSYEND BIT(9) 138 139 /* Bitfields of interrupt enable register */ 140 #define LOONGSON2_MMC_IEN_DFIN BIT(0) 141 #define LOONGSON2_MMC_IEN_DTIMEOUT BIT(1) 142 #define LOONGSON2_MMC_IEN_RXCRC BIT(2) 143 #define LOONGSON2_MMC_IEN_TXCRC BIT(3) 144 #define LOONGSON2_MMC_IEN_PROGERR BIT(4) 145 #define LOONGSON2_MMC_IEN_SDIOIRQ BIT(5) 146 #define LOONGSON2_MMC_IEN_CSENT BIT(6) 147 #define LOONGSON2_MMC_IEN_CTIMEOUT BIT(7) 148 #define LOONGSON2_MMC_IEN_RESPCRC BIT(8) 149 #define LOONGSON2_MMC_IEN_BUSYEND BIT(9) 150 151 #define LOONGSON2_MMC_IEN_ALL GENMASK(9, 0) 152 #define LOONGSON2_MMC_INT_CLEAR GENMASK(9, 0) 153 154 /* Bitfields of DLL master lock-value register */ 155 #define LOONGSON2_MMC_DLLVAL_DONE BIT(8) 156 157 /* Bitfields of DLL control register */ 158 #define LOONGSON2_MMC_DLLCTL_TIME GENMASK(7, 0) 159 #define LOONGSON2_MMC_DLLCTL_INCRE GENMASK(15, 8) 160 #define LOONGSON2_MMC_DLLCTL_START GENMASK(23, 16) 161 #define LOONGSON2_MMC_DLLCTL_CLK_MODE BIT(24) 162 #define LOONGSON2_MMC_DLLCTL_START_BIT BIT(25) 163 #define LOONGSON2_MMC_DLLCTL_TIME_BPASS GENMASK(29, 26) 164 165 #define LOONGSON2_MMC_DELAY_PAD GENMASK(7, 0) 166 #define LOONGSON2_MMC_DELAY_RD GENMASK(15, 8) 167 168 #define LOONGSON2_MMC_SEL_DATA BIT(0) /* 0: SDR, 1: DDR */ 169 #define LOONGSON2_MMC_SEL_BUS BIT(0) /* 0: EMMC, 1: SDIO */ 170 171 /* Internal dma controller registers */ 172 173 /* Bitfields of Global Configuration Register */ 174 #define LOONGSON2_MMC_DMA_64BIT_EN BIT(0) /* 1: 64 bit support */ 175 #define LOONGSON2_MMC_DMA_UNCOHERENT_EN BIT(1) /* 0: cache, 1: uncache */ 176 #define LOONGSON2_MMC_DMA_ASK_VALID BIT(2) 177 #define LOONGSON2_MMC_DMA_START BIT(3) /* DMA start operation */ 178 #define LOONGSON2_MMC_DMA_STOP BIT(4) /* DMA stop operation */ 179 #define LOONGSON2_MMC_DMA_CONFIG_MASK GENMASK_ULL(4, 0) /* DMA controller config bits mask */ 180 181 /* Bitfields of ndesc_addr field of HW descriptor */ 182 #define LOONGSON2_MMC_DMA_DESC_EN BIT(0) /*1: The next descriptor is valid */ 183 #define LOONGSON2_MMC_DMA_DESC_ADDR_LOW GENMASK(31, 1) 184 185 /* Bitfields of cmd field of HW descriptor */ 186 #define LOONGSON2_MMC_DMA_INT BIT(1) /* Enable DMA interrupts */ 187 #define LOONGSON2_MMC_DMA_DATA_DIR BIT(12) /* 1: write to device, 0: read from device */ 188 189 #define LOONGSON2_MMC_DLLVAL_TIMEOUT_US 4000 190 #define LOONGSON2_MMC_TXFULL_TIMEOUT_US 500 191 192 /* 193 * Due to a hardware design flaw, the Loongson-2K0300 may fail to recognize the 194 * CMD48 (SD_READ_EXTR_SINGLE) interrupt. 195 */ 196 #define LOONGSON2_MMC_CMD48_QUIRK BIT(0) 197 198 /* Loongson-2K1000 SDIO2 DMA routing register */ 199 #define LS2K1000_SDIO_DMA_MASK GENMASK(17, 15) 200 #define LS2K1000_DMA0_CONF 0x0 201 #define LS2K1000_DMA1_CONF 0x1 202 #define LS2K1000_DMA2_CONF 0x2 203 #define LS2K1000_DMA3_CONF 0x3 204 #define LS2K1000_DMA4_CONF 0x4 205 206 /* Loongson-2K0500 SDIO2 DMA routing register */ 207 #define LS2K0500_SDIO_DMA_MASK GENMASK(15, 14) 208 #define LS2K0500_DMA0_CONF 0x1 209 #define LS2K0500_DMA1_CONF 0x2 210 #define LS2K0500_DMA2_CONF 0x3 211 212 enum loongson2_mmc_state { 213 STATE_NONE, 214 STATE_FINALIZE, 215 STATE_CMDSENT, 216 STATE_RSPFIN, 217 STATE_XFERFINISH, 218 STATE_XFERFINISH_RSPFIN, 219 }; 220 221 struct loongson2_dma_desc { 222 u32 ndesc_addr; 223 u32 mem_addr; 224 u32 apb_addr; 225 u32 len; 226 u32 step_len; 227 u32 step_times; 228 u32 cmd; 229 u32 stats; 230 u32 high_ndesc_addr; 231 u32 high_mem_addr; 232 u32 reserved[2]; 233 } __packed; 234 235 struct loongson2_mmc_host { 236 struct device *dev; 237 struct mmc_request *mrq; 238 struct regmap *regmap; 239 struct resource *res; 240 struct clk *clk; 241 u32 current_clk; 242 void *sg_cpu; 243 dma_addr_t sg_dma; 244 int dma_complete; 245 struct dma_chan *chan; 246 int cmd_is_stop; 247 int bus_width; 248 spinlock_t lock; /* Prevent races with irq handler */ 249 enum loongson2_mmc_state state; 250 const struct loongson2_mmc_pdata *pdata; 251 }; 252 253 struct loongson2_mmc_pdata { 254 u32 flags; 255 const struct regmap_config *regmap_config; 256 void (*reorder_cmd_data)(struct loongson2_mmc_host *host, struct mmc_command *cmd); 257 void (*fix_data_timeout)(struct loongson2_mmc_host *host, struct mmc_command *cmd); 258 int (*setting_dma)(struct loongson2_mmc_host *host, struct platform_device *pdev); 259 int (*prepare_dma)(struct loongson2_mmc_host *host, struct mmc_data *data); 260 void (*release_dma)(struct loongson2_mmc_host *host, struct device *dev); 261 }; 262 263 static void loongson2_mmc_send_command(struct loongson2_mmc_host *host, 264 struct mmc_command *cmd) 265 { 266 u32 cctrl; 267 268 if (cmd->data) 269 host->state = STATE_XFERFINISH_RSPFIN; 270 else if (cmd->flags & MMC_RSP_PRESENT) 271 host->state = STATE_RSPFIN; 272 else 273 host->state = STATE_CMDSENT; 274 275 regmap_write(host->regmap, LOONGSON2_MMC_REG_CARG, cmd->arg); 276 277 cctrl = FIELD_PREP(LOONGSON2_MMC_CCTL_INDEX, cmd->opcode); 278 cctrl |= LOONGSON2_MMC_CCTL_HOST | LOONGSON2_MMC_CCTL_START; 279 280 if (cmd->opcode == SD_SWITCH && cmd->data) 281 cctrl |= LOONGSON2_MMC_CCTL_CMD6; 282 283 if (cmd->flags & MMC_RSP_PRESENT) 284 cctrl |= LOONGSON2_MMC_CCTL_WAIT_RSP; 285 286 if (cmd->flags & MMC_RSP_136) 287 cctrl |= LOONGSON2_MMC_CCTL_LONG_RSP; 288 289 regmap_write(host->regmap, LOONGSON2_MMC_REG_CCTL, cctrl); 290 } 291 292 static int loongson2_mmc_setup_data(struct loongson2_mmc_host *host, 293 struct mmc_data *data) 294 { 295 u32 dctrl; 296 297 if ((data->blksz & 3) != 0) 298 return -EINVAL; 299 300 dctrl = FIELD_PREP(LOONGSON2_MMC_DCTL_BNUM, data->blocks); 301 dctrl |= LOONGSON2_MMC_DCTL_START | LOONGSON2_MMC_DCTL_ENDMA; 302 303 if (host->bus_width == MMC_BUS_WIDTH_4) 304 dctrl |= LOONGSON2_MMC_DCTL_WIDE; 305 else if (host->bus_width == MMC_BUS_WIDTH_8) 306 dctrl |= LOONGSON2_MMC_DCTL_8BIT_BUS; 307 308 regmap_write(host->regmap, LOONGSON2_MMC_REG_DCTL, dctrl); 309 regmap_write(host->regmap, LOONGSON2_MMC_REG_BSIZE, data->blksz); 310 regmap_write(host->regmap, LOONGSON2_MMC_REG_TIMER, U32_MAX); 311 312 return 0; 313 } 314 315 static int loongson2_mmc_prepare_dma(struct loongson2_mmc_host *host, 316 struct mmc_data *data) 317 { 318 int ret; 319 320 if (!data) 321 return 0; 322 323 ret = loongson2_mmc_setup_data(host, data); 324 if (ret) 325 return ret; 326 327 host->dma_complete = 0; 328 329 return host->pdata->prepare_dma(host, data); 330 } 331 332 static void loongson2_mmc_send_request(struct mmc_host *mmc) 333 { 334 int ret; 335 struct loongson2_mmc_host *host = mmc_priv(mmc); 336 struct mmc_request *mrq = host->mrq; 337 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; 338 339 ret = loongson2_mmc_prepare_dma(host, cmd->data); 340 if (ret) { 341 dev_err(host->dev, "DMA data prepared failed with %d\n", ret); 342 cmd->error = ret; 343 cmd->data->error = ret; 344 mmc_request_done(mmc, mrq); 345 return; 346 } 347 348 if (host->pdata->fix_data_timeout) 349 host->pdata->fix_data_timeout(host, cmd); 350 351 loongson2_mmc_send_command(host, cmd); 352 353 /* Fix deselect card */ 354 if (cmd->opcode == MMC_SELECT_CARD && cmd->arg == 0) { 355 cmd->error = 0; 356 mmc_request_done(mmc, mrq); 357 } 358 } 359 360 static irqreturn_t loongson2_mmc_irq_worker(int irq, void *devid) 361 { 362 struct loongson2_mmc_host *host = (struct loongson2_mmc_host *)devid; 363 struct mmc_host *mmc = mmc_from_priv(host); 364 struct mmc_request *mrq = host->mrq; 365 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; 366 367 if (cmd->data) 368 dma_unmap_sg(mmc_dev(mmc), cmd->data->sg, cmd->data->sg_len, 369 mmc_get_dma_dir(cmd->data)); 370 371 if (cmd->data && !cmd->error && 372 !cmd->data->error && !host->dma_complete) 373 return IRQ_HANDLED; 374 375 /* Read response from controller. */ 376 regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP0, &cmd->resp[0]); 377 regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP1, &cmd->resp[1]); 378 regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP2, &cmd->resp[2]); 379 regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP3, &cmd->resp[3]); 380 381 /* Cleanup controller */ 382 regmap_write(host->regmap, LOONGSON2_MMC_REG_CARG, 0); 383 regmap_write(host->regmap, LOONGSON2_MMC_REG_CCTL, 0); 384 385 if (cmd->data && cmd->error) 386 cmd->data->error = cmd->error; 387 388 if (cmd->data && cmd->data->stop && !host->cmd_is_stop) { 389 host->cmd_is_stop = 1; 390 loongson2_mmc_send_request(mmc); 391 return IRQ_HANDLED; 392 } 393 394 /* If we have no data transfer we are finished here */ 395 if (!mrq->data) 396 goto request_done; 397 398 /* Calculate the amount of bytes transfer if there was no error */ 399 if (mrq->data->error == 0) { 400 mrq->data->bytes_xfered = 401 (mrq->data->blocks * mrq->data->blksz); 402 } else { 403 mrq->data->bytes_xfered = 0; 404 } 405 406 request_done: 407 host->state = STATE_NONE; 408 host->mrq = NULL; 409 mmc_request_done(mmc, mrq); 410 return IRQ_HANDLED; 411 } 412 413 static irqreturn_t loongson2_mmc_irq(int irq, void *devid) 414 { 415 struct loongson2_mmc_host *host = (struct loongson2_mmc_host *)devid; 416 struct mmc_host *mmc = mmc_from_priv(host); 417 struct mmc_command *cmd; 418 unsigned long iflags; 419 u32 dsts, imsk; 420 421 regmap_read(host->regmap, LOONGSON2_MMC_REG_INT, &imsk); 422 regmap_read(host->regmap, LOONGSON2_MMC_REG_DSTS, &dsts); 423 424 if ((dsts & LOONGSON2_MMC_DSTS_IRQ) && 425 (imsk & LOONGSON2_MMC_INT_SDIOIRQ)) { 426 regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_INT, 427 LOONGSON2_MMC_INT_SDIOIRQ, LOONGSON2_MMC_INT_SDIOIRQ); 428 429 sdio_signal_irq(mmc); 430 return IRQ_HANDLED; 431 } 432 433 spin_lock_irqsave(&host->lock, iflags); 434 435 if (host->state == STATE_NONE || host->state == STATE_FINALIZE || !host->mrq) 436 goto irq_out; 437 438 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd; 439 if (!cmd) 440 goto irq_out; 441 442 cmd->error = 0; 443 444 if (imsk & LOONGSON2_MMC_INT_CTIMEOUT) { 445 cmd->error = -ETIMEDOUT; 446 goto close_transfer; 447 } 448 449 if (imsk & LOONGSON2_MMC_INT_CSENT) { 450 if (host->state == STATE_RSPFIN || host->state == STATE_CMDSENT) 451 goto close_transfer; 452 453 if (host->state == STATE_XFERFINISH_RSPFIN) 454 host->state = STATE_XFERFINISH; 455 } 456 457 if (!cmd->data) 458 goto irq_out; 459 460 if (imsk & (LOONGSON2_MMC_INT_RXCRC | LOONGSON2_MMC_INT_TXCRC)) { 461 cmd->data->error = -EILSEQ; 462 goto close_transfer; 463 } 464 465 if (imsk & LOONGSON2_MMC_INT_DTIMEOUT) { 466 cmd->data->error = -ETIMEDOUT; 467 goto close_transfer; 468 } 469 470 if (imsk & LOONGSON2_MMC_INT_DFIN) { 471 if (host->state == STATE_XFERFINISH) { 472 host->dma_complete = 1; 473 goto close_transfer; 474 } 475 476 if (host->state == STATE_XFERFINISH_RSPFIN) 477 host->state = STATE_RSPFIN; 478 } 479 480 irq_out: 481 regmap_write(host->regmap, LOONGSON2_MMC_REG_INT, imsk); 482 spin_unlock_irqrestore(&host->lock, iflags); 483 return IRQ_HANDLED; 484 485 close_transfer: 486 host->state = STATE_FINALIZE; 487 host->pdata->reorder_cmd_data(host, cmd); 488 regmap_write(host->regmap, LOONGSON2_MMC_REG_INT, imsk); 489 spin_unlock_irqrestore(&host->lock, iflags); 490 return IRQ_WAKE_THREAD; 491 } 492 493 static void loongson2_mmc_dll_mode_init(struct loongson2_mmc_host *host) 494 { 495 u32 val, pad_delay, delay; 496 int ret; 497 498 regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_SEL, 499 LOONGSON2_MMC_SEL_DATA, LOONGSON2_MMC_SEL_DATA); 500 501 val = FIELD_PREP(LOONGSON2_MMC_DLLCTL_TIME, 0xc8) 502 | FIELD_PREP(LOONGSON2_MMC_DLLCTL_INCRE, 0x1) 503 | FIELD_PREP(LOONGSON2_MMC_DLLCTL_START, 0x1) 504 | FIELD_PREP(LOONGSON2_MMC_DLLCTL_CLK_MODE, 0x1) 505 | FIELD_PREP(LOONGSON2_MMC_DLLCTL_START_BIT, 0x1) 506 | FIELD_PREP(LOONGSON2_MMC_DLLCTL_TIME_BPASS, 0xf); 507 508 regmap_write(host->regmap, LOONGSON2_MMC_REG_DLLCTL, val); 509 510 ret = regmap_read_poll_timeout(host->regmap, LOONGSON2_MMC_REG_DLLVAL, val, 511 (val & LOONGSON2_MMC_DLLVAL_DONE), 0, 512 LOONGSON2_MMC_DLLVAL_TIMEOUT_US); 513 if (ret < 0) 514 return; 515 516 regmap_read(host->regmap, LOONGSON2_MMC_REG_DLLVAL, &val); 517 pad_delay = FIELD_GET(GENMASK(7, 1), val); 518 519 delay = FIELD_PREP(LOONGSON2_MMC_DELAY_PAD, pad_delay) 520 | FIELD_PREP(LOONGSON2_MMC_DELAY_RD, pad_delay + 1); 521 522 regmap_write(host->regmap, LOONGSON2_MMC_REG_DELAY, delay); 523 } 524 525 static void loongson2_mmc_set_clk(struct loongson2_mmc_host *host, struct mmc_ios *ios) 526 { 527 u32 pre; 528 529 pre = DIV_ROUND_UP(host->current_clk, ios->clock); 530 if (pre > 255) 531 pre = 255; 532 533 regmap_write(host->regmap, LOONGSON2_MMC_REG_PRE, pre | LOONGSON2_MMC_PRE_EN); 534 535 regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_CTL, 536 LOONGSON2_MMC_CTL_ENCLK, LOONGSON2_MMC_CTL_ENCLK); 537 538 /* EMMC DLL mode setting */ 539 if (ios->timing == MMC_TIMING_UHS_DDR50 || ios->timing == MMC_TIMING_MMC_DDR52) 540 loongson2_mmc_dll_mode_init(host); 541 } 542 543 static void loongson2_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 544 { 545 struct loongson2_mmc_host *host = mmc_priv(mmc); 546 int ret; 547 548 if (ios->power_mode == MMC_POWER_UP) { 549 if (!IS_ERR(mmc->supply.vmmc)) { 550 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 551 if (ret) { 552 dev_err(host->dev, "failed to enable vmmc regulator\n"); 553 return; /* return, if failed turn on vmmc */ 554 } 555 } 556 regmap_write(host->regmap, LOONGSON2_MMC_REG_CTL, LOONGSON2_MMC_CTL_RESET); 557 mdelay(10); 558 regmap_write(host->regmap, LOONGSON2_MMC_REG_CTL, LOONGSON2_MMC_CTL_EXTCLK); 559 regmap_write(host->regmap, LOONGSON2_MMC_REG_INT, LOONGSON2_MMC_IEN_ALL); 560 regmap_write(host->regmap, LOONGSON2_MMC_REG_IEN, LOONGSON2_MMC_INT_CLEAR); 561 } else if (ios->power_mode == MMC_POWER_OFF) { 562 regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_CTL, 563 LOONGSON2_MMC_CTL_RESET, LOONGSON2_MMC_CTL_RESET); 564 if (!IS_ERR(mmc->supply.vmmc)) 565 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 566 return; 567 } 568 569 loongson2_mmc_set_clk(host, ios); 570 571 host->bus_width = ios->bus_width; 572 } 573 574 static void loongson2_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 575 { 576 struct loongson2_mmc_host *host = mmc_priv(mmc); 577 578 if ((host->pdata->flags & LOONGSON2_MMC_CMD48_QUIRK) && 579 mrq->cmd->opcode == SD_READ_EXTR_SINGLE) { 580 mmc_request_done(mmc, mrq); 581 return; 582 } 583 584 host->cmd_is_stop = 0; 585 host->mrq = mrq; 586 loongson2_mmc_send_request(mmc); 587 } 588 589 static void loongson2_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 590 { 591 struct loongson2_mmc_host *host = mmc_priv(mmc); 592 593 regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_IEN, LOONGSON2_MMC_INT_SDIOIRQ, enable); 594 } 595 596 static void loongson2_mmc_ack_sdio_irq(struct mmc_host *mmc) 597 { 598 loongson2_mmc_enable_sdio_irq(mmc, 1); 599 } 600 601 static struct mmc_host_ops loongson2_mmc_ops = { 602 .request = loongson2_mmc_request, 603 .set_ios = loongson2_mmc_set_ios, 604 .get_ro = mmc_gpio_get_ro, 605 .get_cd = mmc_gpio_get_cd, 606 .enable_sdio_irq = loongson2_mmc_enable_sdio_irq, 607 .ack_sdio_irq = loongson2_mmc_ack_sdio_irq, 608 }; 609 610 static const struct regmap_config ls2k0500_mmc_regmap_config = { 611 .reg_bits = 32, 612 .val_bits = 32, 613 .reg_stride = 4, 614 .max_register = LOONGSON2_MMC_REG_IEN, 615 }; 616 617 static int loongson2_reorder_cmd_list[] = { SD_APP_SEND_SCR, SD_APP_SEND_NUM_WR_BLKS, 618 SD_APP_SD_STATUS, MMC_SEND_WRITE_PROT, SD_SWITCH }; 619 620 /* 621 * According to SD spec, ACMD13, ACMD22, ACMD51 and CMD30 622 * response datas has different byte order with usual data packets. 623 * However sdio controller will send these datas in usual data format, 624 * so we need to adjust these datas to a protocol consistent byte order. 625 */ 626 static void ls2k0500_mmc_reorder_cmd_data(struct loongson2_mmc_host *host, 627 struct mmc_command *cmd) 628 { 629 struct scatterlist *sg; 630 u32 *data; 631 int i, j; 632 633 if (mmc_cmd_type(cmd) != MMC_CMD_ADTC) 634 return; 635 636 for (i = 0; i < ARRAY_SIZE(loongson2_reorder_cmd_list); i++) 637 if (cmd->opcode == loongson2_reorder_cmd_list[i]) 638 break; 639 640 if (i == ARRAY_SIZE(loongson2_reorder_cmd_list)) 641 return; 642 643 for_each_sg(cmd->data->sg, sg, cmd->data->sg_len, i) { 644 data = sg_virt(&sg[i]); 645 for (j = 0; j < (sg_dma_len(&sg[i]) / 4); j++) 646 if (cmd->opcode == SD_SWITCH) 647 data[j] = bitrev8x4(data[j]); 648 else 649 data[j] = (__force u32)cpu_to_be32(data[j]); 650 } 651 } 652 653 static int loongson2_mmc_prepare_external_dma(struct loongson2_mmc_host *host, 654 struct mmc_data *data) 655 { 656 struct mmc_host *mmc = mmc_from_priv(host); 657 struct dma_slave_config dma_conf = { }; 658 struct dma_async_tx_descriptor *desc; 659 int ret; 660 661 ret = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 662 mmc_get_dma_dir(data)); 663 if (!ret) 664 return -ENOMEM; 665 666 dma_conf.src_addr = host->res->start + LOONGSON2_MMC_REG_DATA, 667 dma_conf.dst_addr = host->res->start + LOONGSON2_MMC_REG_DATA, 668 dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 669 dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 670 dma_conf.direction = !(data->flags & MMC_DATA_WRITE) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 671 672 dmaengine_slave_config(host->chan, &dma_conf); 673 desc = dmaengine_prep_slave_sg(host->chan, data->sg, data->sg_len, 674 dma_conf.direction, 675 DMA_CTRL_ACK | DMA_PREP_INTERRUPT); 676 if (!desc) 677 goto unmap_exit; 678 679 dmaengine_submit(desc); 680 dma_async_issue_pending(host->chan); 681 682 return 0; 683 684 unmap_exit: 685 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, mmc_get_dma_dir(data)); 686 return -ENOMEM; 687 } 688 689 static void loongson2_mmc_release_external_dma(struct loongson2_mmc_host *host, 690 struct device *dev) 691 { 692 dma_release_channel(host->chan); 693 } 694 695 static int ls2k0500_mmc_set_external_dma(struct loongson2_mmc_host *host, 696 struct platform_device *pdev) 697 { 698 int ret, val; 699 void __iomem *regs; 700 701 regs = devm_platform_ioremap_resource(pdev, 1); 702 if (IS_ERR(regs)) 703 return PTR_ERR(regs); 704 705 val = readl(regs); 706 val |= FIELD_PREP(LS2K0500_SDIO_DMA_MASK, LS2K0500_DMA2_CONF); 707 writel(val, regs); 708 709 host->chan = dma_request_chan(&pdev->dev, "rx-tx"); 710 ret = PTR_ERR_OR_ZERO(host->chan); 711 if (ret) { 712 dev_err(&pdev->dev, "Cannot get DMA channel.\n"); 713 return ret; 714 } 715 716 return 0; 717 } 718 719 static int ls2k1000_mmc_set_external_dma(struct loongson2_mmc_host *host, 720 struct platform_device *pdev) 721 { 722 int ret, val; 723 void __iomem *regs; 724 725 regs = devm_platform_ioremap_resource(pdev, 1); 726 if (IS_ERR(regs)) 727 return PTR_ERR(regs); 728 729 val = readl(regs); 730 val |= FIELD_PREP(LS2K1000_SDIO_DMA_MASK, LS2K1000_DMA1_CONF); 731 writel(val, regs); 732 733 host->chan = dma_request_chan(&pdev->dev, "rx-tx"); 734 ret = PTR_ERR_OR_ZERO(host->chan); 735 if (ret) { 736 dev_err(&pdev->dev, "Cannot get DMA channel.\n"); 737 return ret; 738 } 739 740 return 0; 741 } 742 743 static const struct regmap_config ls2k2000_mmc_regmap_config = { 744 .reg_bits = 32, 745 .val_bits = 32, 746 .reg_stride = 4, 747 .max_register = LOONGSON2_MMC_REG_RDMA_HI, 748 }; 749 750 static void ls2k2000_mmc_reorder_cmd_data(struct loongson2_mmc_host *host, 751 struct mmc_command *cmd) 752 { 753 struct scatterlist *sg; 754 u32 *data; 755 int i, j; 756 757 if (cmd->opcode != SD_SWITCH || mmc_cmd_type(cmd) != MMC_CMD_ADTC) 758 return; 759 760 for_each_sg(cmd->data->sg, sg, cmd->data->sg_len, i) { 761 data = sg_virt(&sg[i]); 762 for (j = 0; j < (sg_dma_len(&sg[i]) / 4); j++) 763 data[j] = bitrev8x4(data[j]); 764 } 765 } 766 767 /* 768 * This is a controller hardware defect. Single/multiple block write commands 769 * must be sent after the TX FULL flag is set, otherwise a data timeout interrupt 770 * will occur. 771 */ 772 static void ls2k2000_mmc_fix_data_timeout(struct loongson2_mmc_host *host, 773 struct mmc_command *cmd) 774 { 775 int val; 776 777 if (cmd->opcode != MMC_WRITE_BLOCK && cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK) 778 return; 779 780 regmap_read_poll_timeout(host->regmap, LOONGSON2_MMC_REG_FSTS, val, 781 (val & LOONGSON2_MMC_FSTS_TXFULL), 0, 782 LOONGSON2_MMC_TXFULL_TIMEOUT_US); 783 } 784 785 static int loongson2_mmc_prepare_internal_dma(struct loongson2_mmc_host *host, 786 struct mmc_data *data) 787 { 788 struct loongson2_dma_desc *pdes = (struct loongson2_dma_desc *)host->sg_cpu; 789 struct mmc_host *mmc = mmc_from_priv(host); 790 dma_addr_t next_desc = host->sg_dma; 791 struct scatterlist *sg; 792 int reg_lo, reg_hi; 793 u64 dma_order; 794 int i, ret; 795 796 ret = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 797 mmc_get_dma_dir(data)); 798 if (!ret) 799 return -ENOMEM; 800 801 for_each_sg(data->sg, sg, data->sg_len, i) { 802 pdes[i].len = sg_dma_len(&sg[i]) / 4; 803 pdes[i].step_len = 0; 804 pdes[i].step_times = 1; 805 pdes[i].mem_addr = lower_32_bits(sg_dma_address(&sg[i])); 806 pdes[i].high_mem_addr = upper_32_bits(sg_dma_address(&sg[i])); 807 pdes[i].apb_addr = host->res->start + LOONGSON2_MMC_REG_DATA; 808 pdes[i].cmd = LOONGSON2_MMC_DMA_INT; 809 810 if (data->flags & MMC_DATA_READ) { 811 reg_lo = LOONGSON2_MMC_REG_RDMA_LO; 812 reg_hi = LOONGSON2_MMC_REG_RDMA_HI; 813 } else { 814 pdes[i].cmd |= LOONGSON2_MMC_DMA_DATA_DIR; 815 reg_lo = LOONGSON2_MMC_REG_WDMA_LO; 816 reg_hi = LOONGSON2_MMC_REG_WDMA_HI; 817 } 818 819 next_desc += sizeof(struct loongson2_dma_desc); 820 pdes[i].ndesc_addr = lower_32_bits(next_desc) | 821 LOONGSON2_MMC_DMA_DESC_EN; 822 pdes[i].high_ndesc_addr = upper_32_bits(next_desc); 823 } 824 825 /* Setting the last descriptor enable bit */ 826 pdes[i - 1].ndesc_addr &= ~LOONGSON2_MMC_DMA_DESC_EN; 827 828 dma_order = (host->sg_dma & ~LOONGSON2_MMC_DMA_CONFIG_MASK) | 829 LOONGSON2_MMC_DMA_64BIT_EN | 830 LOONGSON2_MMC_DMA_START; 831 832 regmap_write(host->regmap, reg_hi, upper_32_bits(dma_order)); 833 regmap_write(host->regmap, reg_lo, lower_32_bits(dma_order)); 834 835 return 0; 836 } 837 838 static int ls2k2000_mmc_set_internal_dma(struct loongson2_mmc_host *host, 839 struct platform_device *pdev) 840 { 841 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 842 &host->sg_dma, GFP_KERNEL); 843 if (!host->sg_cpu) 844 return -ENOMEM; 845 846 return 0; 847 } 848 849 static void loongson2_mmc_release_internal_dma(struct loongson2_mmc_host *host, 850 struct device *dev) 851 { 852 dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 853 } 854 855 static struct loongson2_mmc_pdata ls2k0300_mmc_pdata = { 856 .flags = LOONGSON2_MMC_CMD48_QUIRK, 857 .regmap_config = &ls2k2000_mmc_regmap_config, 858 .reorder_cmd_data = ls2k2000_mmc_reorder_cmd_data, 859 .fix_data_timeout = ls2k2000_mmc_fix_data_timeout, 860 .setting_dma = ls2k2000_mmc_set_internal_dma, 861 .prepare_dma = loongson2_mmc_prepare_internal_dma, 862 .release_dma = loongson2_mmc_release_internal_dma, 863 }; 864 865 static struct loongson2_mmc_pdata ls2k0500_mmc_pdata = { 866 .flags = 0, 867 .regmap_config = &ls2k0500_mmc_regmap_config, 868 .reorder_cmd_data = ls2k0500_mmc_reorder_cmd_data, 869 .setting_dma = ls2k0500_mmc_set_external_dma, 870 .prepare_dma = loongson2_mmc_prepare_external_dma, 871 .release_dma = loongson2_mmc_release_external_dma, 872 }; 873 874 static struct loongson2_mmc_pdata ls2k1000_mmc_pdata = { 875 .flags = 0, 876 .regmap_config = &ls2k0500_mmc_regmap_config, 877 .reorder_cmd_data = ls2k0500_mmc_reorder_cmd_data, 878 .setting_dma = ls2k1000_mmc_set_external_dma, 879 .prepare_dma = loongson2_mmc_prepare_external_dma, 880 .release_dma = loongson2_mmc_release_external_dma, 881 }; 882 883 static struct loongson2_mmc_pdata ls2k2000_mmc_pdata = { 884 .flags = 0, 885 .regmap_config = &ls2k2000_mmc_regmap_config, 886 .reorder_cmd_data = ls2k2000_mmc_reorder_cmd_data, 887 .fix_data_timeout = ls2k2000_mmc_fix_data_timeout, 888 .setting_dma = ls2k2000_mmc_set_internal_dma, 889 .prepare_dma = loongson2_mmc_prepare_internal_dma, 890 .release_dma = loongson2_mmc_release_internal_dma, 891 }; 892 893 static int loongson2_mmc_resource_request(struct platform_device *pdev, 894 struct loongson2_mmc_host *host) 895 { 896 struct device *dev = &pdev->dev; 897 void __iomem *base; 898 int ret, irq; 899 900 base = devm_platform_get_and_ioremap_resource(pdev, 0, &host->res); 901 if (IS_ERR(base)) 902 return PTR_ERR(base); 903 904 host->regmap = devm_regmap_init_mmio(dev, base, host->pdata->regmap_config); 905 if (IS_ERR(host->regmap)) 906 return PTR_ERR(host->regmap); 907 908 host->clk = devm_clk_get_optional_enabled(dev, NULL); 909 if (IS_ERR(host->clk)) 910 return PTR_ERR(host->clk); 911 912 if (host->clk) { 913 ret = devm_clk_rate_exclusive_get(dev, host->clk); 914 if (ret) 915 return ret; 916 917 host->current_clk = clk_get_rate(host->clk); 918 } else { 919 /* For ACPI, the clock is accessed via the clock-frequency attribute. */ 920 device_property_read_u32(dev, "clock-frequency", &host->current_clk); 921 } 922 923 irq = platform_get_irq(pdev, 0); 924 if (irq < 0) 925 return irq; 926 927 ret = devm_request_threaded_irq(dev, irq, loongson2_mmc_irq, 928 loongson2_mmc_irq_worker, 929 IRQF_ONESHOT, "loongson2-mmc", host); 930 if (ret) 931 return ret; 932 933 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 934 if (ret) 935 return ret; 936 937 return host->pdata->setting_dma(host, pdev); 938 } 939 940 static int loongson2_mmc_probe(struct platform_device *pdev) 941 { 942 struct device *dev = &pdev->dev; 943 struct loongson2_mmc_host *host; 944 struct mmc_host *mmc; 945 int ret; 946 947 mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 948 if (!mmc) 949 return -ENOMEM; 950 951 platform_set_drvdata(pdev, mmc); 952 953 host = mmc_priv(mmc); 954 host->state = STATE_NONE; 955 spin_lock_init(&host->lock); 956 957 host->pdata = device_get_match_data(dev); 958 if (!host->pdata) 959 return dev_err_probe(dev, -EINVAL, "Failed to get match data\n"); 960 961 ret = loongson2_mmc_resource_request(pdev, host); 962 if (ret) 963 return dev_err_probe(dev, ret, "Failed to request resource\n"); 964 965 mmc->ops = &loongson2_mmc_ops; 966 mmc->f_min = DIV_ROUND_UP(host->current_clk, 256); 967 mmc->f_max = host->current_clk; 968 mmc->max_blk_count = 4095; 969 mmc->max_blk_size = 4095; 970 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 971 mmc->max_segs = 1; 972 mmc->max_seg_size = mmc->max_req_size; 973 974 /* Process SDIO IRQs through the sdio_irq_work. */ 975 if (mmc->caps & MMC_CAP_SDIO_IRQ) 976 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 977 978 ret = mmc_regulator_get_supply(mmc); 979 if (ret || mmc->ocr_avail == 0) { 980 dev_warn(dev, "Can't get voltage, defaulting to 3.3V\n"); 981 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 982 } 983 984 ret = mmc_of_parse(mmc); 985 if (ret) { 986 dev_err(dev, "Failed to parse device node\n"); 987 goto free_dma; 988 } 989 990 ret = mmc_add_host(mmc); 991 if (ret) { 992 dev_err(dev, "Failed to add mmc host\n"); 993 goto free_dma; 994 } 995 996 return 0; 997 998 free_dma: 999 host->pdata->release_dma(host, dev); 1000 return ret; 1001 } 1002 1003 static void loongson2_mmc_remove(struct platform_device *pdev) 1004 { 1005 struct mmc_host *mmc = platform_get_drvdata(pdev); 1006 struct loongson2_mmc_host *host = mmc_priv(mmc); 1007 1008 mmc_remove_host(mmc); 1009 host->pdata->release_dma(host, &pdev->dev); 1010 } 1011 1012 static const struct of_device_id loongson2_mmc_of_ids[] = { 1013 { .compatible = "loongson,ls2k0300-mmc", .data = &ls2k0300_mmc_pdata }, 1014 { .compatible = "loongson,ls2k0500-mmc", .data = &ls2k0500_mmc_pdata }, 1015 { .compatible = "loongson,ls2k1000-mmc", .data = &ls2k1000_mmc_pdata }, 1016 { .compatible = "loongson,ls2k2000-mmc", .data = &ls2k2000_mmc_pdata }, 1017 { }, 1018 }; 1019 MODULE_DEVICE_TABLE(of, loongson2_mmc_of_ids); 1020 1021 static int loongson2_mmc_suspend(struct device *dev) 1022 { 1023 struct mmc_host *mmc = dev_get_drvdata(dev); 1024 struct loongson2_mmc_host *host = mmc_priv(mmc); 1025 1026 clk_disable_unprepare(host->clk); 1027 1028 return 0; 1029 } 1030 1031 static int loongson2_mmc_resume(struct device *dev) 1032 { 1033 struct mmc_host *mmc = dev_get_drvdata(dev); 1034 struct loongson2_mmc_host *host = mmc_priv(mmc); 1035 1036 return clk_prepare_enable(host->clk); 1037 } 1038 1039 static DEFINE_SIMPLE_DEV_PM_OPS(loongson2_mmc_pm_ops, loongson2_mmc_suspend, loongson2_mmc_resume); 1040 1041 static struct platform_driver loongson2_mmc_driver = { 1042 .driver = { 1043 .name = "loongson2-mmc", 1044 .of_match_table = loongson2_mmc_of_ids, 1045 .pm = pm_ptr(&loongson2_mmc_pm_ops), 1046 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1047 }, 1048 .probe = loongson2_mmc_probe, 1049 .remove = loongson2_mmc_remove, 1050 }; 1051 1052 module_platform_driver(loongson2_mmc_driver); 1053 1054 MODULE_DESCRIPTION("Loongson-2K SD/SDIO/eMMC Interface driver"); 1055 MODULE_AUTHOR("Loongson Technology Corporation Limited"); 1056 MODULE_LICENSE("GPL"); 1057