1 /* 2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 3 * JZ4740 SD/MMC controller driver 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * You should have received a copy of the GNU General Public License along 11 * with this program; if not, write to the Free Software Foundation, Inc., 12 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * 14 */ 15 16 #include <linux/mmc/host.h> 17 #include <linux/mmc/slot-gpio.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/delay.h> 25 #include <linux/scatterlist.h> 26 #include <linux/clk.h> 27 28 #include <linux/bitops.h> 29 #include <linux/gpio.h> 30 #include <asm/mach-jz4740/gpio.h> 31 #include <asm/cacheflush.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/dmaengine.h> 34 35 #include <asm/mach-jz4740/dma.h> 36 #include <asm/mach-jz4740/jz4740_mmc.h> 37 38 #define JZ_REG_MMC_STRPCL 0x00 39 #define JZ_REG_MMC_STATUS 0x04 40 #define JZ_REG_MMC_CLKRT 0x08 41 #define JZ_REG_MMC_CMDAT 0x0C 42 #define JZ_REG_MMC_RESTO 0x10 43 #define JZ_REG_MMC_RDTO 0x14 44 #define JZ_REG_MMC_BLKLEN 0x18 45 #define JZ_REG_MMC_NOB 0x1C 46 #define JZ_REG_MMC_SNOB 0x20 47 #define JZ_REG_MMC_IMASK 0x24 48 #define JZ_REG_MMC_IREG 0x28 49 #define JZ_REG_MMC_CMD 0x2C 50 #define JZ_REG_MMC_ARG 0x30 51 #define JZ_REG_MMC_RESP_FIFO 0x34 52 #define JZ_REG_MMC_RXFIFO 0x38 53 #define JZ_REG_MMC_TXFIFO 0x3C 54 55 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) 56 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) 57 #define JZ_MMC_STRPCL_START_READWAIT BIT(5) 58 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) 59 #define JZ_MMC_STRPCL_RESET BIT(3) 60 #define JZ_MMC_STRPCL_START_OP BIT(2) 61 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) 62 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) 63 #define JZ_MMC_STRPCL_CLOCK_START BIT(1) 64 65 66 #define JZ_MMC_STATUS_IS_RESETTING BIT(15) 67 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) 68 #define JZ_MMC_STATUS_PRG_DONE BIT(13) 69 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) 70 #define JZ_MMC_STATUS_END_CMD_RES BIT(11) 71 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) 72 #define JZ_MMC_STATUS_IS_READWAIT BIT(9) 73 #define JZ_MMC_STATUS_CLK_EN BIT(8) 74 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) 75 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) 76 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) 77 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) 78 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) 79 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) 80 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) 81 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) 82 83 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) 84 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) 85 86 87 #define JZ_MMC_CMDAT_IO_ABORT BIT(11) 88 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) 89 #define JZ_MMC_CMDAT_DMA_EN BIT(8) 90 #define JZ_MMC_CMDAT_INIT BIT(7) 91 #define JZ_MMC_CMDAT_BUSY BIT(6) 92 #define JZ_MMC_CMDAT_STREAM BIT(5) 93 #define JZ_MMC_CMDAT_WRITE BIT(4) 94 #define JZ_MMC_CMDAT_DATA_EN BIT(3) 95 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) 96 #define JZ_MMC_CMDAT_RSP_R1 1 97 #define JZ_MMC_CMDAT_RSP_R2 2 98 #define JZ_MMC_CMDAT_RSP_R3 3 99 100 #define JZ_MMC_IRQ_SDIO BIT(7) 101 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) 102 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) 103 #define JZ_MMC_IRQ_END_CMD_RES BIT(2) 104 #define JZ_MMC_IRQ_PRG_DONE BIT(1) 105 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) 106 107 108 #define JZ_MMC_CLK_RATE 24000000 109 110 enum jz4740_mmc_state { 111 JZ4740_MMC_STATE_READ_RESPONSE, 112 JZ4740_MMC_STATE_TRANSFER_DATA, 113 JZ4740_MMC_STATE_SEND_STOP, 114 JZ4740_MMC_STATE_DONE, 115 }; 116 117 struct jz4740_mmc_host_next { 118 int sg_len; 119 s32 cookie; 120 }; 121 122 struct jz4740_mmc_host { 123 struct mmc_host *mmc; 124 struct platform_device *pdev; 125 struct jz4740_mmc_platform_data *pdata; 126 struct clk *clk; 127 128 int irq; 129 int card_detect_irq; 130 131 void __iomem *base; 132 struct resource *mem_res; 133 struct mmc_request *req; 134 struct mmc_command *cmd; 135 136 unsigned long waiting; 137 138 uint32_t cmdat; 139 140 uint16_t irq_mask; 141 142 spinlock_t lock; 143 144 struct timer_list timeout_timer; 145 struct sg_mapping_iter miter; 146 enum jz4740_mmc_state state; 147 148 /* DMA support */ 149 struct dma_chan *dma_rx; 150 struct dma_chan *dma_tx; 151 struct jz4740_mmc_host_next next_data; 152 bool use_dma; 153 int sg_len; 154 155 /* The DMA trigger level is 8 words, that is to say, the DMA read 156 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write 157 * trigger is when data words in MSC_TXFIFO is < 8. 158 */ 159 #define JZ4740_MMC_FIFO_HALF_SIZE 8 160 }; 161 162 /*----------------------------------------------------------------------------*/ 163 /* DMA infrastructure */ 164 165 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host) 166 { 167 if (!host->use_dma) 168 return; 169 170 dma_release_channel(host->dma_tx); 171 dma_release_channel(host->dma_rx); 172 } 173 174 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host) 175 { 176 dma_cap_mask_t mask; 177 178 dma_cap_zero(mask); 179 dma_cap_set(DMA_SLAVE, mask); 180 181 host->dma_tx = dma_request_channel(mask, NULL, host); 182 if (!host->dma_tx) { 183 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n"); 184 return -ENODEV; 185 } 186 187 host->dma_rx = dma_request_channel(mask, NULL, host); 188 if (!host->dma_rx) { 189 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n"); 190 goto free_master_write; 191 } 192 193 /* Initialize DMA pre request cookie */ 194 host->next_data.cookie = 1; 195 196 return 0; 197 198 free_master_write: 199 dma_release_channel(host->dma_tx); 200 return -ENODEV; 201 } 202 203 static inline int jz4740_mmc_get_dma_dir(struct mmc_data *data) 204 { 205 return (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 206 } 207 208 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host, 209 struct mmc_data *data) 210 { 211 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx; 212 } 213 214 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host, 215 struct mmc_data *data) 216 { 217 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 218 enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data); 219 220 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 221 } 222 223 /* Prepares DMA data for current/next transfer, returns non-zero on failure */ 224 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host, 225 struct mmc_data *data, 226 struct jz4740_mmc_host_next *next, 227 struct dma_chan *chan) 228 { 229 struct jz4740_mmc_host_next *next_data = &host->next_data; 230 enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data); 231 int sg_len; 232 233 if (!next && data->host_cookie && 234 data->host_cookie != host->next_data.cookie) { 235 dev_warn(mmc_dev(host->mmc), 236 "[%s] invalid cookie: data->host_cookie %d host->next_data.cookie %d\n", 237 __func__, 238 data->host_cookie, 239 host->next_data.cookie); 240 data->host_cookie = 0; 241 } 242 243 /* Check if next job is already prepared */ 244 if (next || data->host_cookie != host->next_data.cookie) { 245 sg_len = dma_map_sg(chan->device->dev, 246 data->sg, 247 data->sg_len, 248 dir); 249 250 } else { 251 sg_len = next_data->sg_len; 252 next_data->sg_len = 0; 253 } 254 255 if (sg_len <= 0) { 256 dev_err(mmc_dev(host->mmc), 257 "Failed to map scatterlist for DMA operation\n"); 258 return -EINVAL; 259 } 260 261 if (next) { 262 next->sg_len = sg_len; 263 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 264 } else 265 host->sg_len = sg_len; 266 267 return 0; 268 } 269 270 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host, 271 struct mmc_data *data) 272 { 273 int ret; 274 struct dma_chan *chan; 275 struct dma_async_tx_descriptor *desc; 276 struct dma_slave_config conf = { 277 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 278 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 279 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, 280 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, 281 }; 282 283 if (data->flags & MMC_DATA_WRITE) { 284 conf.direction = DMA_MEM_TO_DEV; 285 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO; 286 conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT; 287 chan = host->dma_tx; 288 } else { 289 conf.direction = DMA_DEV_TO_MEM; 290 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO; 291 conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE; 292 chan = host->dma_rx; 293 } 294 295 ret = jz4740_mmc_prepare_dma_data(host, data, NULL, chan); 296 if (ret) 297 return ret; 298 299 dmaengine_slave_config(chan, &conf); 300 desc = dmaengine_prep_slave_sg(chan, 301 data->sg, 302 host->sg_len, 303 conf.direction, 304 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 305 if (!desc) { 306 dev_err(mmc_dev(host->mmc), 307 "Failed to allocate DMA %s descriptor", 308 conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX"); 309 goto dma_unmap; 310 } 311 312 dmaengine_submit(desc); 313 dma_async_issue_pending(chan); 314 315 return 0; 316 317 dma_unmap: 318 jz4740_mmc_dma_unmap(host, data); 319 return -ENOMEM; 320 } 321 322 static void jz4740_mmc_pre_request(struct mmc_host *mmc, 323 struct mmc_request *mrq, 324 bool is_first_req) 325 { 326 struct jz4740_mmc_host *host = mmc_priv(mmc); 327 struct mmc_data *data = mrq->data; 328 struct jz4740_mmc_host_next *next_data = &host->next_data; 329 330 BUG_ON(data->host_cookie); 331 332 if (host->use_dma) { 333 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 334 335 if (jz4740_mmc_prepare_dma_data(host, data, next_data, chan)) 336 data->host_cookie = 0; 337 } 338 } 339 340 static void jz4740_mmc_post_request(struct mmc_host *mmc, 341 struct mmc_request *mrq, 342 int err) 343 { 344 struct jz4740_mmc_host *host = mmc_priv(mmc); 345 struct mmc_data *data = mrq->data; 346 347 if (host->use_dma && data->host_cookie) { 348 jz4740_mmc_dma_unmap(host, data); 349 data->host_cookie = 0; 350 } 351 352 if (err) { 353 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 354 355 dmaengine_terminate_all(chan); 356 } 357 } 358 359 /*----------------------------------------------------------------------------*/ 360 361 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, 362 unsigned int irq, bool enabled) 363 { 364 unsigned long flags; 365 366 spin_lock_irqsave(&host->lock, flags); 367 if (enabled) 368 host->irq_mask &= ~irq; 369 else 370 host->irq_mask |= irq; 371 spin_unlock_irqrestore(&host->lock, flags); 372 373 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK); 374 } 375 376 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, 377 bool start_transfer) 378 { 379 uint16_t val = JZ_MMC_STRPCL_CLOCK_START; 380 381 if (start_transfer) 382 val |= JZ_MMC_STRPCL_START_OP; 383 384 writew(val, host->base + JZ_REG_MMC_STRPCL); 385 } 386 387 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) 388 { 389 uint32_t status; 390 unsigned int timeout = 1000; 391 392 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); 393 do { 394 status = readl(host->base + JZ_REG_MMC_STATUS); 395 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); 396 } 397 398 static void jz4740_mmc_reset(struct jz4740_mmc_host *host) 399 { 400 uint32_t status; 401 unsigned int timeout = 1000; 402 403 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); 404 udelay(10); 405 do { 406 status = readl(host->base + JZ_REG_MMC_STATUS); 407 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); 408 } 409 410 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) 411 { 412 struct mmc_request *req; 413 414 req = host->req; 415 host->req = NULL; 416 417 mmc_request_done(host->mmc, req); 418 } 419 420 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, 421 unsigned int irq) 422 { 423 unsigned int timeout = 0x800; 424 uint16_t status; 425 426 do { 427 status = readw(host->base + JZ_REG_MMC_IREG); 428 } while (!(status & irq) && --timeout); 429 430 if (timeout == 0) { 431 set_bit(0, &host->waiting); 432 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 433 jz4740_mmc_set_irq_enabled(host, irq, true); 434 return true; 435 } 436 437 return false; 438 } 439 440 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, 441 struct mmc_data *data) 442 { 443 int status; 444 445 status = readl(host->base + JZ_REG_MMC_STATUS); 446 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { 447 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { 448 host->req->cmd->error = -ETIMEDOUT; 449 data->error = -ETIMEDOUT; 450 } else { 451 host->req->cmd->error = -EIO; 452 data->error = -EIO; 453 } 454 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) { 455 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) { 456 host->req->cmd->error = -ETIMEDOUT; 457 data->error = -ETIMEDOUT; 458 } else { 459 host->req->cmd->error = -EIO; 460 data->error = -EIO; 461 } 462 } 463 } 464 465 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, 466 struct mmc_data *data) 467 { 468 struct sg_mapping_iter *miter = &host->miter; 469 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; 470 uint32_t *buf; 471 bool timeout; 472 size_t i, j; 473 474 while (sg_miter_next(miter)) { 475 buf = miter->addr; 476 i = miter->length / 4; 477 j = i / 8; 478 i = i & 0x7; 479 while (j) { 480 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 481 if (unlikely(timeout)) 482 goto poll_timeout; 483 484 writel(buf[0], fifo_addr); 485 writel(buf[1], fifo_addr); 486 writel(buf[2], fifo_addr); 487 writel(buf[3], fifo_addr); 488 writel(buf[4], fifo_addr); 489 writel(buf[5], fifo_addr); 490 writel(buf[6], fifo_addr); 491 writel(buf[7], fifo_addr); 492 buf += 8; 493 --j; 494 } 495 if (unlikely(i)) { 496 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 497 if (unlikely(timeout)) 498 goto poll_timeout; 499 500 while (i) { 501 writel(*buf, fifo_addr); 502 ++buf; 503 --i; 504 } 505 } 506 data->bytes_xfered += miter->length; 507 } 508 sg_miter_stop(miter); 509 510 return false; 511 512 poll_timeout: 513 miter->consumed = (void *)buf - miter->addr; 514 data->bytes_xfered += miter->consumed; 515 sg_miter_stop(miter); 516 517 return true; 518 } 519 520 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, 521 struct mmc_data *data) 522 { 523 struct sg_mapping_iter *miter = &host->miter; 524 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; 525 uint32_t *buf; 526 uint32_t d; 527 uint16_t status; 528 size_t i, j; 529 unsigned int timeout; 530 531 while (sg_miter_next(miter)) { 532 buf = miter->addr; 533 i = miter->length; 534 j = i / 32; 535 i = i & 0x1f; 536 while (j) { 537 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 538 if (unlikely(timeout)) 539 goto poll_timeout; 540 541 buf[0] = readl(fifo_addr); 542 buf[1] = readl(fifo_addr); 543 buf[2] = readl(fifo_addr); 544 buf[3] = readl(fifo_addr); 545 buf[4] = readl(fifo_addr); 546 buf[5] = readl(fifo_addr); 547 buf[6] = readl(fifo_addr); 548 buf[7] = readl(fifo_addr); 549 550 buf += 8; 551 --j; 552 } 553 554 if (unlikely(i)) { 555 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 556 if (unlikely(timeout)) 557 goto poll_timeout; 558 559 while (i >= 4) { 560 *buf++ = readl(fifo_addr); 561 i -= 4; 562 } 563 if (unlikely(i > 0)) { 564 d = readl(fifo_addr); 565 memcpy(buf, &d, i); 566 } 567 } 568 data->bytes_xfered += miter->length; 569 570 /* This can go away once MIPS implements 571 * flush_kernel_dcache_page */ 572 flush_dcache_page(miter->page); 573 } 574 sg_miter_stop(miter); 575 576 /* For whatever reason there is sometime one word more in the fifo then 577 * requested */ 578 timeout = 1000; 579 status = readl(host->base + JZ_REG_MMC_STATUS); 580 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { 581 d = readl(fifo_addr); 582 status = readl(host->base + JZ_REG_MMC_STATUS); 583 } 584 585 return false; 586 587 poll_timeout: 588 miter->consumed = (void *)buf - miter->addr; 589 data->bytes_xfered += miter->consumed; 590 sg_miter_stop(miter); 591 592 return true; 593 } 594 595 static void jz4740_mmc_timeout(unsigned long data) 596 { 597 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data; 598 599 if (!test_and_clear_bit(0, &host->waiting)) 600 return; 601 602 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); 603 604 host->req->cmd->error = -ETIMEDOUT; 605 jz4740_mmc_request_done(host); 606 } 607 608 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, 609 struct mmc_command *cmd) 610 { 611 int i; 612 uint16_t tmp; 613 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; 614 615 if (cmd->flags & MMC_RSP_136) { 616 tmp = readw(fifo_addr); 617 for (i = 0; i < 4; ++i) { 618 cmd->resp[i] = tmp << 24; 619 tmp = readw(fifo_addr); 620 cmd->resp[i] |= tmp << 8; 621 tmp = readw(fifo_addr); 622 cmd->resp[i] |= tmp >> 8; 623 } 624 } else { 625 cmd->resp[0] = readw(fifo_addr) << 24; 626 cmd->resp[0] |= readw(fifo_addr) << 8; 627 cmd->resp[0] |= readw(fifo_addr) & 0xff; 628 } 629 } 630 631 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, 632 struct mmc_command *cmd) 633 { 634 uint32_t cmdat = host->cmdat; 635 636 host->cmdat &= ~JZ_MMC_CMDAT_INIT; 637 jz4740_mmc_clock_disable(host); 638 639 host->cmd = cmd; 640 641 if (cmd->flags & MMC_RSP_BUSY) 642 cmdat |= JZ_MMC_CMDAT_BUSY; 643 644 switch (mmc_resp_type(cmd)) { 645 case MMC_RSP_R1B: 646 case MMC_RSP_R1: 647 cmdat |= JZ_MMC_CMDAT_RSP_R1; 648 break; 649 case MMC_RSP_R2: 650 cmdat |= JZ_MMC_CMDAT_RSP_R2; 651 break; 652 case MMC_RSP_R3: 653 cmdat |= JZ_MMC_CMDAT_RSP_R3; 654 break; 655 default: 656 break; 657 } 658 659 if (cmd->data) { 660 cmdat |= JZ_MMC_CMDAT_DATA_EN; 661 if (cmd->data->flags & MMC_DATA_WRITE) 662 cmdat |= JZ_MMC_CMDAT_WRITE; 663 if (cmd->data->flags & MMC_DATA_STREAM) 664 cmdat |= JZ_MMC_CMDAT_STREAM; 665 if (host->use_dma) 666 cmdat |= JZ_MMC_CMDAT_DMA_EN; 667 668 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); 669 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); 670 } 671 672 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); 673 writel(cmd->arg, host->base + JZ_REG_MMC_ARG); 674 writel(cmdat, host->base + JZ_REG_MMC_CMDAT); 675 676 jz4740_mmc_clock_enable(host, 1); 677 } 678 679 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) 680 { 681 struct mmc_command *cmd = host->req->cmd; 682 struct mmc_data *data = cmd->data; 683 int direction; 684 685 if (data->flags & MMC_DATA_READ) 686 direction = SG_MITER_TO_SG; 687 else 688 direction = SG_MITER_FROM_SG; 689 690 sg_miter_start(&host->miter, data->sg, data->sg_len, direction); 691 } 692 693 694 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) 695 { 696 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; 697 struct mmc_command *cmd = host->req->cmd; 698 struct mmc_request *req = host->req; 699 struct mmc_data *data = cmd->data; 700 bool timeout = false; 701 702 if (cmd->error) 703 host->state = JZ4740_MMC_STATE_DONE; 704 705 switch (host->state) { 706 case JZ4740_MMC_STATE_READ_RESPONSE: 707 if (cmd->flags & MMC_RSP_PRESENT) 708 jz4740_mmc_read_response(host, cmd); 709 710 if (!data) 711 break; 712 713 jz_mmc_prepare_data_transfer(host); 714 715 case JZ4740_MMC_STATE_TRANSFER_DATA: 716 if (host->use_dma) { 717 /* Use DMA if enabled. 718 * Data transfer direction is defined later by 719 * relying on data flags in 720 * jz4740_mmc_prepare_dma_data() and 721 * jz4740_mmc_start_dma_transfer(). 722 */ 723 timeout = jz4740_mmc_start_dma_transfer(host, data); 724 data->bytes_xfered = data->blocks * data->blksz; 725 } else if (data->flags & MMC_DATA_READ) 726 /* Use PIO if DMA is not enabled. 727 * Data transfer direction was defined before 728 * by relying on data flags in 729 * jz_mmc_prepare_data_transfer(). 730 */ 731 timeout = jz4740_mmc_read_data(host, data); 732 else 733 timeout = jz4740_mmc_write_data(host, data); 734 735 if (unlikely(timeout)) { 736 host->state = JZ4740_MMC_STATE_TRANSFER_DATA; 737 break; 738 } 739 740 jz4740_mmc_transfer_check_state(host, data); 741 742 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); 743 if (unlikely(timeout)) { 744 host->state = JZ4740_MMC_STATE_SEND_STOP; 745 break; 746 } 747 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); 748 749 case JZ4740_MMC_STATE_SEND_STOP: 750 if (!req->stop) 751 break; 752 753 jz4740_mmc_send_command(host, req->stop); 754 755 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) { 756 timeout = jz4740_mmc_poll_irq(host, 757 JZ_MMC_IRQ_PRG_DONE); 758 if (timeout) { 759 host->state = JZ4740_MMC_STATE_DONE; 760 break; 761 } 762 } 763 case JZ4740_MMC_STATE_DONE: 764 break; 765 } 766 767 if (!timeout) 768 jz4740_mmc_request_done(host); 769 770 return IRQ_HANDLED; 771 } 772 773 static irqreturn_t jz_mmc_irq(int irq, void *devid) 774 { 775 struct jz4740_mmc_host *host = devid; 776 struct mmc_command *cmd = host->cmd; 777 uint16_t irq_reg, status, tmp; 778 779 irq_reg = readw(host->base + JZ_REG_MMC_IREG); 780 781 tmp = irq_reg; 782 irq_reg &= ~host->irq_mask; 783 784 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | 785 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); 786 787 if (tmp != irq_reg) 788 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); 789 790 if (irq_reg & JZ_MMC_IRQ_SDIO) { 791 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); 792 mmc_signal_sdio_irq(host->mmc); 793 irq_reg &= ~JZ_MMC_IRQ_SDIO; 794 } 795 796 if (host->req && cmd && irq_reg) { 797 if (test_and_clear_bit(0, &host->waiting)) { 798 del_timer(&host->timeout_timer); 799 800 status = readl(host->base + JZ_REG_MMC_STATUS); 801 802 if (status & JZ_MMC_STATUS_TIMEOUT_RES) { 803 cmd->error = -ETIMEDOUT; 804 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { 805 cmd->error = -EIO; 806 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | 807 JZ_MMC_STATUS_CRC_WRITE_ERROR)) { 808 if (cmd->data) 809 cmd->data->error = -EIO; 810 cmd->error = -EIO; 811 } 812 813 jz4740_mmc_set_irq_enabled(host, irq_reg, false); 814 writew(irq_reg, host->base + JZ_REG_MMC_IREG); 815 816 return IRQ_WAKE_THREAD; 817 } 818 } 819 820 return IRQ_HANDLED; 821 } 822 823 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) 824 { 825 int div = 0; 826 int real_rate; 827 828 jz4740_mmc_clock_disable(host); 829 clk_set_rate(host->clk, JZ_MMC_CLK_RATE); 830 831 real_rate = clk_get_rate(host->clk); 832 833 while (real_rate > rate && div < 7) { 834 ++div; 835 real_rate >>= 1; 836 } 837 838 writew(div, host->base + JZ_REG_MMC_CLKRT); 839 return real_rate; 840 } 841 842 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) 843 { 844 struct jz4740_mmc_host *host = mmc_priv(mmc); 845 846 host->req = req; 847 848 writew(0xffff, host->base + JZ_REG_MMC_IREG); 849 850 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG); 851 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); 852 853 host->state = JZ4740_MMC_STATE_READ_RESPONSE; 854 set_bit(0, &host->waiting); 855 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 856 jz4740_mmc_send_command(host, req->cmd); 857 } 858 859 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 860 { 861 struct jz4740_mmc_host *host = mmc_priv(mmc); 862 if (ios->clock) 863 jz4740_mmc_set_clock_rate(host, ios->clock); 864 865 switch (ios->power_mode) { 866 case MMC_POWER_UP: 867 jz4740_mmc_reset(host); 868 if (gpio_is_valid(host->pdata->gpio_power)) 869 gpio_set_value(host->pdata->gpio_power, 870 !host->pdata->power_active_low); 871 host->cmdat |= JZ_MMC_CMDAT_INIT; 872 clk_prepare_enable(host->clk); 873 break; 874 case MMC_POWER_ON: 875 break; 876 default: 877 if (gpio_is_valid(host->pdata->gpio_power)) 878 gpio_set_value(host->pdata->gpio_power, 879 host->pdata->power_active_low); 880 clk_disable_unprepare(host->clk); 881 break; 882 } 883 884 switch (ios->bus_width) { 885 case MMC_BUS_WIDTH_1: 886 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; 887 break; 888 case MMC_BUS_WIDTH_4: 889 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; 890 break; 891 default: 892 break; 893 } 894 } 895 896 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 897 { 898 struct jz4740_mmc_host *host = mmc_priv(mmc); 899 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); 900 } 901 902 static const struct mmc_host_ops jz4740_mmc_ops = { 903 .request = jz4740_mmc_request, 904 .pre_req = jz4740_mmc_pre_request, 905 .post_req = jz4740_mmc_post_request, 906 .set_ios = jz4740_mmc_set_ios, 907 .get_ro = mmc_gpio_get_ro, 908 .get_cd = mmc_gpio_get_cd, 909 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, 910 }; 911 912 static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { 913 JZ_GPIO_BULK_PIN(MSC_CMD), 914 JZ_GPIO_BULK_PIN(MSC_CLK), 915 JZ_GPIO_BULK_PIN(MSC_DATA0), 916 JZ_GPIO_BULK_PIN(MSC_DATA1), 917 JZ_GPIO_BULK_PIN(MSC_DATA2), 918 JZ_GPIO_BULK_PIN(MSC_DATA3), 919 }; 920 921 static int jz4740_mmc_request_gpio(struct device *dev, int gpio, 922 const char *name, bool output, int value) 923 { 924 int ret; 925 926 if (!gpio_is_valid(gpio)) 927 return 0; 928 929 ret = gpio_request(gpio, name); 930 if (ret) { 931 dev_err(dev, "Failed to request %s gpio: %d\n", name, ret); 932 return ret; 933 } 934 935 if (output) 936 gpio_direction_output(gpio, value); 937 else 938 gpio_direction_input(gpio); 939 940 return 0; 941 } 942 943 static int jz4740_mmc_request_gpios(struct mmc_host *mmc, 944 struct platform_device *pdev) 945 { 946 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; 947 int ret = 0; 948 949 if (!pdata) 950 return 0; 951 952 if (!pdata->card_detect_active_low) 953 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 954 if (!pdata->read_only_active_low) 955 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 956 957 if (gpio_is_valid(pdata->gpio_card_detect)) { 958 ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0); 959 if (ret) 960 return ret; 961 } 962 963 if (gpio_is_valid(pdata->gpio_read_only)) { 964 ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only); 965 if (ret) 966 return ret; 967 } 968 969 return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, 970 "MMC read only", true, pdata->power_active_low); 971 } 972 973 static void jz4740_mmc_free_gpios(struct platform_device *pdev) 974 { 975 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; 976 977 if (!pdata) 978 return; 979 980 if (gpio_is_valid(pdata->gpio_power)) 981 gpio_free(pdata->gpio_power); 982 } 983 984 static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) 985 { 986 size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); 987 if (host->pdata && host->pdata->data_1bit) 988 num_pins -= 3; 989 990 return num_pins; 991 } 992 993 static int jz4740_mmc_probe(struct platform_device* pdev) 994 { 995 int ret; 996 struct mmc_host *mmc; 997 struct jz4740_mmc_host *host; 998 struct jz4740_mmc_platform_data *pdata; 999 1000 pdata = pdev->dev.platform_data; 1001 1002 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); 1003 if (!mmc) { 1004 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); 1005 return -ENOMEM; 1006 } 1007 1008 host = mmc_priv(mmc); 1009 host->pdata = pdata; 1010 1011 host->irq = platform_get_irq(pdev, 0); 1012 if (host->irq < 0) { 1013 ret = host->irq; 1014 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); 1015 goto err_free_host; 1016 } 1017 1018 host->clk = devm_clk_get(&pdev->dev, "mmc"); 1019 if (IS_ERR(host->clk)) { 1020 ret = PTR_ERR(host->clk); 1021 dev_err(&pdev->dev, "Failed to get mmc clock\n"); 1022 goto err_free_host; 1023 } 1024 1025 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1026 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res); 1027 if (IS_ERR(host->base)) { 1028 ret = PTR_ERR(host->base); 1029 dev_err(&pdev->dev, "Failed to ioremap base memory\n"); 1030 goto err_free_host; 1031 } 1032 1033 ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 1034 if (ret) { 1035 dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); 1036 goto err_free_host; 1037 } 1038 1039 ret = jz4740_mmc_request_gpios(mmc, pdev); 1040 if (ret) 1041 goto err_gpio_bulk_free; 1042 1043 mmc->ops = &jz4740_mmc_ops; 1044 mmc->f_min = JZ_MMC_CLK_RATE / 128; 1045 mmc->f_max = JZ_MMC_CLK_RATE; 1046 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1047 mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA; 1048 mmc->caps |= MMC_CAP_SDIO_IRQ; 1049 1050 mmc->max_blk_size = (1 << 10) - 1; 1051 mmc->max_blk_count = (1 << 15) - 1; 1052 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1053 1054 mmc->max_segs = 128; 1055 mmc->max_seg_size = mmc->max_req_size; 1056 1057 host->mmc = mmc; 1058 host->pdev = pdev; 1059 spin_lock_init(&host->lock); 1060 host->irq_mask = 0xffff; 1061 1062 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, 1063 dev_name(&pdev->dev), host); 1064 if (ret) { 1065 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); 1066 goto err_free_gpios; 1067 } 1068 1069 jz4740_mmc_reset(host); 1070 jz4740_mmc_clock_disable(host); 1071 setup_timer(&host->timeout_timer, jz4740_mmc_timeout, 1072 (unsigned long)host); 1073 /* It is not important when it times out, it just needs to timeout. */ 1074 set_timer_slack(&host->timeout_timer, HZ); 1075 1076 host->use_dma = true; 1077 if (host->use_dma && jz4740_mmc_acquire_dma_channels(host) != 0) 1078 host->use_dma = false; 1079 1080 platform_set_drvdata(pdev, host); 1081 ret = mmc_add_host(mmc); 1082 1083 if (ret) { 1084 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); 1085 goto err_free_irq; 1086 } 1087 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); 1088 1089 dev_info(&pdev->dev, "Using %s, %d-bit mode\n", 1090 host->use_dma ? "DMA" : "PIO", 1091 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1092 1093 return 0; 1094 1095 err_free_irq: 1096 free_irq(host->irq, host); 1097 err_free_gpios: 1098 jz4740_mmc_free_gpios(pdev); 1099 err_gpio_bulk_free: 1100 if (host->use_dma) 1101 jz4740_mmc_release_dma_channels(host); 1102 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 1103 err_free_host: 1104 mmc_free_host(mmc); 1105 1106 return ret; 1107 } 1108 1109 static int jz4740_mmc_remove(struct platform_device *pdev) 1110 { 1111 struct jz4740_mmc_host *host = platform_get_drvdata(pdev); 1112 1113 del_timer_sync(&host->timeout_timer); 1114 jz4740_mmc_set_irq_enabled(host, 0xff, false); 1115 jz4740_mmc_reset(host); 1116 1117 mmc_remove_host(host->mmc); 1118 1119 free_irq(host->irq, host); 1120 1121 jz4740_mmc_free_gpios(pdev); 1122 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 1123 1124 if (host->use_dma) 1125 jz4740_mmc_release_dma_channels(host); 1126 1127 mmc_free_host(host->mmc); 1128 1129 return 0; 1130 } 1131 1132 #ifdef CONFIG_PM_SLEEP 1133 1134 static int jz4740_mmc_suspend(struct device *dev) 1135 { 1136 struct jz4740_mmc_host *host = dev_get_drvdata(dev); 1137 1138 jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 1139 1140 return 0; 1141 } 1142 1143 static int jz4740_mmc_resume(struct device *dev) 1144 { 1145 struct jz4740_mmc_host *host = dev_get_drvdata(dev); 1146 1147 jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 1148 1149 return 0; 1150 } 1151 1152 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend, 1153 jz4740_mmc_resume); 1154 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) 1155 #else 1156 #define JZ4740_MMC_PM_OPS NULL 1157 #endif 1158 1159 static struct platform_driver jz4740_mmc_driver = { 1160 .probe = jz4740_mmc_probe, 1161 .remove = jz4740_mmc_remove, 1162 .driver = { 1163 .name = "jz4740-mmc", 1164 .pm = JZ4740_MMC_PM_OPS, 1165 }, 1166 }; 1167 1168 module_platform_driver(jz4740_mmc_driver); 1169 1170 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); 1171 MODULE_LICENSE("GPL"); 1172 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1173