1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare Multimedia Card Interface driver 4 * (Based on NXP driver for lpc 31xx) 5 * 6 * Copyright (C) 2009 NXP Semiconductors 7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8 */ 9 10 #ifndef _DW_MMC_H_ 11 #define _DW_MMC_H_ 12 13 #include <linux/scatterlist.h> 14 #include <linux/mmc/core.h> 15 #include <linux/dmaengine.h> 16 #include <linux/reset.h> 17 #include <linux/fault-inject.h> 18 #include <linux/hrtimer.h> 19 #include <linux/interrupt.h> 20 #include <linux/workqueue.h> 21 22 extern const struct dev_pm_ops dw_mci_pmops; 23 24 enum dw_mci_state { 25 STATE_IDLE = 0, 26 STATE_SENDING_CMD, 27 STATE_SENDING_DATA, 28 STATE_DATA_BUSY, 29 STATE_SENDING_STOP, 30 STATE_DATA_ERROR, 31 STATE_SENDING_CMD11, 32 STATE_WAITING_CMD11_DONE, 33 }; 34 35 enum { 36 EVENT_CMD_COMPLETE = 0, 37 EVENT_XFER_COMPLETE, 38 EVENT_DATA_COMPLETE, 39 EVENT_DATA_ERROR, 40 }; 41 42 enum dw_mci_cookie { 43 COOKIE_UNMAPPED, 44 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ 45 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ 46 }; 47 48 enum { 49 TRANS_MODE_PIO = 0, 50 TRANS_MODE_IDMAC, 51 TRANS_MODE_EDMAC 52 }; 53 54 struct dw_mci_dma_slave { 55 struct dma_chan *ch; 56 enum dma_transfer_direction direction; 57 }; 58 59 /** 60 * struct dw_mci - MMC controller state 61 * @lock: Spinlock protecting the queue and associated data. 62 * @irq_lock: Spinlock protecting the INTMASK setting. 63 * @regs: Pointer to MMIO registers. 64 * @fifo_reg: Pointer to MMIO registers for data FIFO 65 * @sg: Scatterlist entry currently being processed by PIO code, if any. 66 * @sg_miter: PIO mapping scatterlist iterator. 67 * @mrq: The request currently being processed on @host, 68 * or NULL if the controller is idle. 69 * @cmd: The command currently being sent to the card, or NULL. 70 * @data: The data currently being transferred, or NULL if no data 71 * transfer is in progress. 72 * @stop_abort: The command currently prepared for stoping transfer. 73 * @prev_blksz: The former transfer blksz record. 74 * @timing: Record of current ios timing. 75 * @use_dma: Which DMA channel is in use for the current transfer, zero 76 * denotes PIO mode. 77 * @using_dma: Whether DMA is in use for the current transfer. 78 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 79 * @sg_dma: Bus address of DMA buffer. 80 * @sg_cpu: Virtual address of DMA buffer. 81 * @dma_ops: Pointer to DMA callbacks. 82 * @cmd_status: Snapshot of SR taken upon completion of the current 83 * command. Only valid when EVENT_CMD_COMPLETE is pending. 84 * @desc_num: Number of idmac descriptors available. 85 * @dms: structure of slave-dma private data. 86 * @phy_regs: physical address of controller's register map 87 * @data_status: Snapshot of SR taken upon completion of the current 88 * data transfer. Only valid when EVENT_DATA_COMPLETE or 89 * EVENT_DATA_ERROR is pending. 90 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 91 * to be sent. 92 * @dir_status: Direction of current transfer. 93 * @bh_work: Work running the request state machine. 94 * @pending_events: Bitmask of events flagged by the interrupt handler 95 * to be processed by bh work. 96 * @completed_events: Bitmask of events which the state machine has 97 * processed. 98 * @state: BH work state. 99 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 100 * rate and timeout calculations. 101 * @current_speed: Configured rate of the controller. 102 * @minimum_speed: Stored minimum rate of the controller. 103 * @fifoth_val: The value of FIFOTH register. 104 * @verid: Denote Version ID. 105 * @dev: Device associated with the MMC controller. 106 * @drv_data: Driver specific data for identified variant of the controller 107 * @priv: Implementation defined private data. 108 * @biu_clk: Pointer to bus interface unit clock instance. 109 * @ciu_clk: Pointer to card interface unit clock instance. 110 * @fifo_depth: depth of FIFO. 111 * @data_addr_override: override fifo reg offset with this value. 112 * @dma_threshold: data threshold value in bytes to carry out a DMA transfer. 113 * @wm_aligned: force fifo watermark equal with data length in PIO mode. 114 * Set as true if alignment is needed. 115 * @data_shift: log2 of FIFO item size. 116 * @part_buf_start: Start index in part_buf. 117 * @part_buf_count: Bytes of partial data in part_buf. 118 * @part_buf: Simple buffer for partial fifo reads/writes. 119 * @push_data: Pointer to FIFO push function. 120 * @pull_data: Pointer to FIFO pull function. 121 * @quirks: Set of quirks that apply to specific versions of the IP. 122 * @irq_flags: The flags to be passed to request_irq. 123 * @irq: The irq value to be passed to request_irq. 124 * @sdio_irq: SDIO interrupt bit in interrupt registers. 125 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. 126 * @cto_timer: Timer for broken command transfer over scheme. 127 * @dto_timer: Timer for broken data transfer over scheme. 128 * @mmc: The mmc_host representing this dw_mci. 129 * @flags: Random state bits associated with the host. 130 * @ctype: Card type for this host. 131 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 132 * @clk_old: The last clock value that was requested from core. 133 * @pdev: platform_device registered 134 * @rstc: Reset controller for this host. 135 * @detect_delay_ms: Delay in mS before detecting cards after interrupt. 136 * @phase_map: The map for recording in and out phases for each timing 137 * 138 * Locking 139 * ======= 140 * 141 * @lock is a softirq-safe spinlock protecting as well as 142 * @mrq and @state. These must always be updated 143 * at the same time while holding @lock. 144 * 145 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 146 * to allow the interrupt handler to modify it directly. Held for only long 147 * enough to read-modify-write INTMASK and no other locks are grabbed when 148 * holding this one. 149 * 150 * @pending_events and @completed_events are accessed using atomic bit 151 * operations, so they don't need any locking. 152 * 153 * None of the fields touched by the interrupt handler need any 154 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 155 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 156 * interrupts must be disabled and @data_status updated with a 157 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 158 * CMDRDY interrupt must be disabled and @cmd_status updated with a 159 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 160 * bytes_xfered field of @data must be written. This is ensured by 161 * using barriers. 162 */ 163 struct dw_mci { 164 spinlock_t lock; 165 spinlock_t irq_lock; 166 void __iomem *regs; 167 void __iomem *fifo_reg; 168 u32 data_addr_override; 169 u32 dma_threshold; 170 bool wm_aligned; 171 172 struct scatterlist *sg; 173 struct sg_mapping_iter sg_miter; 174 175 struct mmc_request *mrq; 176 struct mmc_command *cmd; 177 struct mmc_data *data; 178 struct mmc_command stop_abort; 179 unsigned int prev_blksz; 180 unsigned char timing; 181 182 /* DMA interface members*/ 183 int use_dma; 184 int using_dma; 185 int dma_64bit_address; 186 187 dma_addr_t sg_dma; 188 void *sg_cpu; 189 const struct dw_mci_dma_ops *dma_ops; 190 /* For idmac */ 191 unsigned short desc_num; 192 193 /* For edmac */ 194 struct dw_mci_dma_slave *dms; 195 /* Registers's physical base address */ 196 resource_size_t phy_regs; 197 198 u32 cmd_status; 199 u32 data_status; 200 u32 stop_cmdr; 201 u32 dir_status; 202 struct work_struct bh_work; 203 unsigned long pending_events; 204 unsigned long completed_events; 205 enum dw_mci_state state; 206 207 u32 bus_hz; 208 u32 current_speed; 209 u32 minimum_speed; 210 u32 fifoth_val; 211 u16 verid; 212 struct device *dev; 213 const struct dw_mci_drv_data *drv_data; 214 void *priv; 215 struct clk *biu_clk; 216 struct clk *ciu_clk; 217 struct dw_mci_slot *slot; 218 219 /* FIFO push and pull */ 220 int fifo_depth; 221 int data_shift; 222 u8 part_buf_start; 223 u8 part_buf_count; 224 union { 225 u16 part_buf16; 226 u32 part_buf32; 227 u64 part_buf; 228 }; 229 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 230 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 231 232 u32 quirks; 233 unsigned long irq_flags; /* IRQ flags */ 234 int irq; 235 236 int sdio_irq; 237 238 struct timer_list cmd11_timer; 239 struct timer_list cto_timer; 240 struct timer_list dto_timer; 241 242 #ifdef CONFIG_FAULT_INJECTION 243 struct fault_attr fail_data_crc; 244 struct hrtimer fault_timer; 245 #endif 246 struct mmc_host *mmc; 247 unsigned long flags; 248 #define DW_MMC_CARD_NEED_INIT 0 249 #define DW_MMC_CARD_NO_LOW_PWR 1 250 #define DW_MMC_CARD_NO_USE_HOLD 2 251 #define DW_MMC_CARD_NEEDS_POLL 3 252 u32 ctype; 253 unsigned int clock; 254 unsigned int clk_old; 255 struct platform_device *pdev; 256 struct reset_control *rstc; 257 u32 detect_delay_ms; 258 struct mmc_clk_phase_map phase_map; 259 }; 260 261 /* DMA ops for Internal/External DMAC interface */ 262 struct dw_mci_dma_ops { 263 /* DMA Ops */ 264 int (*init)(struct dw_mci *host); 265 int (*start)(struct dw_mci *host, unsigned int sg_len); 266 void (*complete)(void *host); 267 void (*stop)(struct dw_mci *host); 268 void (*cleanup)(struct dw_mci *host); 269 void (*exit)(struct dw_mci *host); 270 }; 271 272 /* Support for longer data read timeout */ 273 #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) 274 /* Force 32-bit access to the FIFO */ 275 #define DW_MMC_QUIRK_FIFO64_32 BIT(1) 276 277 #define DW_MMC_240A 0x240a 278 #define DW_MMC_280A 0x280a 279 280 #define SDMMC_CTRL 0x000 281 #define SDMMC_PWREN 0x004 282 #define SDMMC_CLKDIV 0x008 283 #define SDMMC_CLKSRC 0x00c 284 #define SDMMC_CLKENA 0x010 285 #define SDMMC_TMOUT 0x014 286 #define SDMMC_CTYPE 0x018 287 #define SDMMC_BLKSIZ 0x01c 288 #define SDMMC_BYTCNT 0x020 289 #define SDMMC_INTMASK 0x024 290 #define SDMMC_CMDARG 0x028 291 #define SDMMC_CMD 0x02c 292 #define SDMMC_RESP0 0x030 293 #define SDMMC_RESP1 0x034 294 #define SDMMC_RESP2 0x038 295 #define SDMMC_RESP3 0x03c 296 #define SDMMC_MINTSTS 0x040 297 #define SDMMC_RINTSTS 0x044 298 #define SDMMC_STATUS 0x048 299 #define SDMMC_FIFOTH 0x04c 300 #define SDMMC_CDETECT 0x050 301 #define SDMMC_WRTPRT 0x054 302 #define SDMMC_GPIO 0x058 303 #define SDMMC_TCBCNT 0x05c 304 #define SDMMC_TBBCNT 0x060 305 #define SDMMC_DEBNCE 0x064 306 #define SDMMC_USRID 0x068 307 #define SDMMC_VERID 0x06c 308 #define SDMMC_HCON 0x070 309 #define SDMMC_UHS_REG 0x074 310 #define SDMMC_RST_N 0x078 311 #define SDMMC_BMOD 0x080 312 #define SDMMC_PLDMND 0x084 313 #define SDMMC_DBADDR 0x088 314 #define SDMMC_IDSTS 0x08c 315 #define SDMMC_IDINTEN 0x090 316 #define SDMMC_DSCADDR 0x094 317 #define SDMMC_BUFADDR 0x098 318 #define SDMMC_CDTHRCTL 0x100 319 #define SDMMC_UHS_REG_EXT 0x108 320 #define SDMMC_DDR_REG 0x10c 321 #define SDMMC_ENABLE_SHIFT 0x110 322 #define SDMMC_DATA(x) (x) 323 /* 324 * Registers to support idmac 64-bit address mode 325 */ 326 #define SDMMC_DBADDRL 0x088 327 #define SDMMC_DBADDRU 0x08c 328 #define SDMMC_IDSTS64 0x090 329 #define SDMMC_IDINTEN64 0x094 330 #define SDMMC_DSCADDRL 0x098 331 #define SDMMC_DSCADDRU 0x09c 332 #define SDMMC_BUFADDRL 0x0A0 333 #define SDMMC_BUFADDRU 0x0A4 334 335 /* 336 * Data offset is difference according to Version 337 * Lower than 2.40a : data register offest is 0x100 338 */ 339 #define DATA_OFFSET 0x100 340 #define DATA_240A_OFFSET 0x200 341 342 /* shift bit field */ 343 #define _SBF(f, v) ((v) << (f)) 344 345 /* Control register defines */ 346 #define SDMMC_CTRL_USE_IDMAC BIT(25) 347 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 348 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 349 #define SDMMC_CTRL_SEND_CCSD BIT(9) 350 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 351 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 352 #define SDMMC_CTRL_READ_WAIT BIT(6) 353 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 354 #define SDMMC_CTRL_INT_ENABLE BIT(4) 355 #define SDMMC_CTRL_DMA_RESET BIT(2) 356 #define SDMMC_CTRL_FIFO_RESET BIT(1) 357 #define SDMMC_CTRL_RESET BIT(0) 358 /* Clock Enable register defines */ 359 #define SDMMC_CLKEN_LOW_PWR BIT(16) 360 #define SDMMC_CLKEN_ENABLE BIT(0) 361 /* time-out register defines */ 362 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 363 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 364 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 365 #define SDMMC_TMOUT_RESP_MSK 0xFF 366 /* card-type register defines */ 367 #define SDMMC_CTYPE_8BIT BIT(16) 368 #define SDMMC_CTYPE_4BIT BIT(0) 369 #define SDMMC_CTYPE_1BIT 0 370 /* Interrupt status & mask register defines */ 371 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 372 #define SDMMC_INT_EBE BIT(15) 373 #define SDMMC_INT_ACD BIT(14) 374 #define SDMMC_INT_SBE BIT(13) 375 #define SDMMC_INT_HLE BIT(12) 376 #define SDMMC_INT_FRUN BIT(11) 377 #define SDMMC_INT_HTO BIT(10) 378 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 379 #define SDMMC_INT_DRTO BIT(9) 380 #define SDMMC_INT_RTO BIT(8) 381 #define SDMMC_INT_DCRC BIT(7) 382 #define SDMMC_INT_RCRC BIT(6) 383 #define SDMMC_INT_RXDR BIT(5) 384 #define SDMMC_INT_TXDR BIT(4) 385 #define SDMMC_INT_DATA_OVER BIT(3) 386 #define SDMMC_INT_CMD_DONE BIT(2) 387 #define SDMMC_INT_RESP_ERR BIT(1) 388 #define SDMMC_INT_CD BIT(0) 389 /* Command register defines */ 390 #define SDMMC_CMD_START BIT(31) 391 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 392 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 393 #define SDMMC_CMD_CCS_EXP BIT(23) 394 #define SDMMC_CMD_CEATA_RD BIT(22) 395 #define SDMMC_CMD_UPD_CLK BIT(21) 396 #define SDMMC_CMD_INIT BIT(15) 397 #define SDMMC_CMD_STOP BIT(14) 398 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 399 #define SDMMC_CMD_SEND_STOP BIT(12) 400 #define SDMMC_CMD_STRM_MODE BIT(11) 401 #define SDMMC_CMD_DAT_WR BIT(10) 402 #define SDMMC_CMD_DAT_EXP BIT(9) 403 #define SDMMC_CMD_RESP_CRC BIT(8) 404 #define SDMMC_CMD_RESP_LONG BIT(7) 405 #define SDMMC_CMD_RESP_EXP BIT(6) 406 #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 407 /* Status register defines */ 408 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 409 #define SDMMC_STATUS_DMA_REQ BIT(31) 410 #define SDMMC_STATUS_BUSY BIT(9) 411 /* FIFOTH register defines */ 412 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 413 ((r) & 0xFFF) << 16 | \ 414 ((t) & 0xFFF)) 415 /* HCON register defines */ 416 #define DMA_INTERFACE_IDMA (0x0) 417 #define DMA_INTERFACE_DWDMA (0x1) 418 #define DMA_INTERFACE_GDMA (0x2) 419 #define DMA_INTERFACE_NODMA (0x3) 420 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 421 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 422 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 423 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 424 /* Internal DMAC interrupt defines */ 425 #define SDMMC_IDMAC_INT_AI BIT(9) 426 #define SDMMC_IDMAC_INT_NI BIT(8) 427 #define SDMMC_IDMAC_INT_CES BIT(5) 428 #define SDMMC_IDMAC_INT_DU BIT(4) 429 #define SDMMC_IDMAC_INT_FBE BIT(2) 430 #define SDMMC_IDMAC_INT_RI BIT(1) 431 #define SDMMC_IDMAC_INT_TI BIT(0) 432 /* Internal DMAC bus mode bits */ 433 #define SDMMC_IDMAC_ENABLE BIT(7) 434 #define SDMMC_IDMAC_FB BIT(1) 435 #define SDMMC_IDMAC_SWRESET BIT(0) 436 /* H/W reset */ 437 #define SDMMC_RST_HWACTIVE 0x1 438 /* Version ID register define */ 439 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 440 /* Card read threshold */ 441 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 442 #define SDMMC_CARD_WR_THR_EN BIT(2) 443 #define SDMMC_CARD_RD_THR_EN BIT(0) 444 /* UHS-1 register defines */ 445 #define SDMMC_UHS_DDR BIT(16) 446 #define SDMMC_UHS_18V BIT(0) 447 /* DDR register defines */ 448 #define SDMMC_DDR_HS400 BIT(31) 449 /* Enable shift register defines */ 450 #define SDMMC_ENABLE_PHASE BIT(0) 451 /* All ctrl reset bits */ 452 #define SDMMC_CTRL_ALL_RESET_FLAGS \ 453 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 454 455 /* FIFO register access macros. These should not change the data endian-ness 456 * as they are written to memory to be dealt with by the upper layers 457 */ 458 #define mci_fifo_readw(__reg) __raw_readw(__reg) 459 #define mci_fifo_readl(__reg) __raw_readl(__reg) 460 #define mci_fifo_readq(__reg) __raw_readq(__reg) 461 462 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 463 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 464 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 465 466 /* 467 * Some dw_mmc devices have 64-bit FIFOs, but expect them to be 468 * accessed using two 32-bit accesses. If such controller is used 469 * with a 64-bit kernel, this has to be done explicitly. 470 */ 471 static inline u64 mci_fifo_l_readq(void __iomem *addr) 472 { 473 u64 ans; 474 u32 proxy[2]; 475 476 proxy[0] = mci_fifo_readl(addr); 477 proxy[1] = mci_fifo_readl(addr + 4); 478 memcpy(&ans, proxy, 8); 479 return ans; 480 } 481 482 static inline void mci_fifo_l_writeq(void __iomem *addr, u64 value) 483 { 484 u32 proxy[2]; 485 486 memcpy(proxy, &value, 8); 487 mci_fifo_writel(addr, proxy[0]); 488 mci_fifo_writel(addr + 4, proxy[1]); 489 } 490 491 /* Register access macros */ 492 #define mci_readl(dev, reg) \ 493 readl_relaxed((dev)->regs + SDMMC_##reg) 494 #define mci_writel(dev, reg, value) \ 495 writel_relaxed((value), (dev)->regs + SDMMC_##reg) 496 497 #ifndef readq 498 #define __raw_writeq(__value, __reg) \ 499 (*(volatile u64 __force *)(__reg) = (__value)) 500 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 501 #endif 502 503 extern struct dw_mci *dw_mci_alloc_host(struct device *device); 504 extern int dw_mci_probe(struct dw_mci *host); 505 extern void dw_mci_remove(struct dw_mci *host); 506 extern int dw_mci_runtime_suspend(struct device *device); 507 extern int dw_mci_runtime_resume(struct device *device); 508 509 /** 510 * dw_mci driver data - dw-mshc implementation specific driver data. 511 * @caps: mmc subsystem specified capabilities of the controller(s). 512 * @num_caps: number of capabilities specified by @caps. 513 * @common_caps: mmc subsystem specified capabilities applicable to all of 514 * the controllers 515 * @init: early implementation specific initialization. 516 * @set_ios: handle bus specific extensions. 517 * @parse_dt: parse implementation specific device tree properties. 518 * @execute_tuning: implementation specific tuning procedure. 519 * @set_data_timeout: implementation specific timeout. 520 * @get_drto_clks: implementation specific cycle count for data read timeout. 521 * @hw_reset: implementation specific HW reset. 522 * 523 * Provide controller implementation specific extensions. The usage of this 524 * data structure is fully optional and usage of each member in this structure 525 * is optional as well. 526 */ 527 struct dw_mci_drv_data { 528 unsigned long *caps; 529 u32 num_caps; 530 u32 common_caps; 531 int (*init)(struct dw_mci *host); 532 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 533 int (*parse_dt)(struct dw_mci *host); 534 int (*execute_tuning)(struct dw_mci *host, u32 opcode); 535 int (*prepare_hs400_tuning)(struct dw_mci *host, 536 struct mmc_ios *ios); 537 int (*switch_voltage)(struct dw_mci *host, 538 struct mmc_ios *ios); 539 void (*set_data_timeout)(struct dw_mci *host, 540 unsigned int timeout_ns); 541 u32 (*get_drto_clks)(struct dw_mci *host); 542 void (*hw_reset)(struct dw_mci *host); 543 }; 544 #endif /* _DW_MMC_H_ */ 545