1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/iopoll.h> 23 #include <linux/ioport.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/seq_file.h> 28 #include <linux/slab.h> 29 #include <linux/stat.h> 30 #include <linux/delay.h> 31 #include <linux/irq.h> 32 #include <linux/mmc/card.h> 33 #include <linux/mmc/host.h> 34 #include <linux/mmc/mmc.h> 35 #include <linux/mmc/sd.h> 36 #include <linux/mmc/sdio.h> 37 #include <linux/bitops.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/of.h> 40 #include <linux/of_gpio.h> 41 #include <linux/mmc/slot-gpio.h> 42 43 #include "dw_mmc.h" 44 45 /* Common flag combinations */ 46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 48 SDMMC_INT_EBE | SDMMC_INT_HLE) 49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 52 DW_MCI_CMD_ERROR_FLAGS) 53 #define DW_MCI_SEND_STATUS 1 54 #define DW_MCI_RECV_STATUS 2 55 #define DW_MCI_DMA_THRESHOLD 16 56 57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 59 60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63 SDMMC_IDMAC_INT_TI) 64 65 #define DESC_RING_BUF_SZ PAGE_SIZE 66 67 struct idmac_desc_64addr { 68 u32 des0; /* Control Descriptor */ 69 #define IDMAC_OWN_CLR64(x) \ 70 !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 71 72 u32 des1; /* Reserved */ 73 74 u32 des2; /*Buffer sizes */ 75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 78 79 u32 des3; /* Reserved */ 80 81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 83 84 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 85 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 86 }; 87 88 struct idmac_desc { 89 __le32 des0; /* Control Descriptor */ 90 #define IDMAC_DES0_DIC BIT(1) 91 #define IDMAC_DES0_LD BIT(2) 92 #define IDMAC_DES0_FD BIT(3) 93 #define IDMAC_DES0_CH BIT(4) 94 #define IDMAC_DES0_ER BIT(5) 95 #define IDMAC_DES0_CES BIT(30) 96 #define IDMAC_DES0_OWN BIT(31) 97 98 __le32 des1; /* Buffer sizes */ 99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101 102 __le32 des2; /* buffer 1 physical address */ 103 104 __le32 des3; /* buffer 2 physical address */ 105 }; 106 107 /* Each descriptor can transfer up to 4KB of data in chained mode */ 108 #define DW_MCI_DESC_DATA_LENGTH 0x1000 109 110 #if defined(CONFIG_DEBUG_FS) 111 static int dw_mci_req_show(struct seq_file *s, void *v) 112 { 113 struct dw_mci_slot *slot = s->private; 114 struct mmc_request *mrq; 115 struct mmc_command *cmd; 116 struct mmc_command *stop; 117 struct mmc_data *data; 118 119 /* Make sure we get a consistent snapshot */ 120 spin_lock_bh(&slot->host->lock); 121 mrq = slot->mrq; 122 123 if (mrq) { 124 cmd = mrq->cmd; 125 data = mrq->data; 126 stop = mrq->stop; 127 128 if (cmd) 129 seq_printf(s, 130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131 cmd->opcode, cmd->arg, cmd->flags, 132 cmd->resp[0], cmd->resp[1], cmd->resp[2], 133 cmd->resp[2], cmd->error); 134 if (data) 135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136 data->bytes_xfered, data->blocks, 137 data->blksz, data->flags, data->error); 138 if (stop) 139 seq_printf(s, 140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141 stop->opcode, stop->arg, stop->flags, 142 stop->resp[0], stop->resp[1], stop->resp[2], 143 stop->resp[2], stop->error); 144 } 145 146 spin_unlock_bh(&slot->host->lock); 147 148 return 0; 149 } 150 151 static int dw_mci_req_open(struct inode *inode, struct file *file) 152 { 153 return single_open(file, dw_mci_req_show, inode->i_private); 154 } 155 156 static const struct file_operations dw_mci_req_fops = { 157 .owner = THIS_MODULE, 158 .open = dw_mci_req_open, 159 .read = seq_read, 160 .llseek = seq_lseek, 161 .release = single_release, 162 }; 163 164 static int dw_mci_regs_show(struct seq_file *s, void *v) 165 { 166 struct dw_mci *host = s->private; 167 168 pm_runtime_get_sync(host->dev); 169 170 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 171 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 172 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 173 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 174 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 175 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 176 177 pm_runtime_put_autosuspend(host->dev); 178 179 return 0; 180 } 181 182 static int dw_mci_regs_open(struct inode *inode, struct file *file) 183 { 184 return single_open(file, dw_mci_regs_show, inode->i_private); 185 } 186 187 static const struct file_operations dw_mci_regs_fops = { 188 .owner = THIS_MODULE, 189 .open = dw_mci_regs_open, 190 .read = seq_read, 191 .llseek = seq_lseek, 192 .release = single_release, 193 }; 194 195 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 196 { 197 struct mmc_host *mmc = slot->mmc; 198 struct dw_mci *host = slot->host; 199 struct dentry *root; 200 struct dentry *node; 201 202 root = mmc->debugfs_root; 203 if (!root) 204 return; 205 206 node = debugfs_create_file("regs", S_IRUSR, root, host, 207 &dw_mci_regs_fops); 208 if (!node) 209 goto err; 210 211 node = debugfs_create_file("req", S_IRUSR, root, slot, 212 &dw_mci_req_fops); 213 if (!node) 214 goto err; 215 216 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 217 if (!node) 218 goto err; 219 220 node = debugfs_create_x32("pending_events", S_IRUSR, root, 221 (u32 *)&host->pending_events); 222 if (!node) 223 goto err; 224 225 node = debugfs_create_x32("completed_events", S_IRUSR, root, 226 (u32 *)&host->completed_events); 227 if (!node) 228 goto err; 229 230 return; 231 232 err: 233 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 234 } 235 #endif /* defined(CONFIG_DEBUG_FS) */ 236 237 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 238 { 239 u32 ctrl; 240 241 ctrl = mci_readl(host, CTRL); 242 ctrl |= reset; 243 mci_writel(host, CTRL, ctrl); 244 245 /* wait till resets clear */ 246 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 247 !(ctrl & reset), 248 1, 500 * USEC_PER_MSEC)) { 249 dev_err(host->dev, 250 "Timeout resetting block (ctrl reset %#x)\n", 251 ctrl & reset); 252 return false; 253 } 254 255 return true; 256 } 257 258 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 259 { 260 u32 status; 261 262 /* 263 * Databook says that before issuing a new data transfer command 264 * we need to check to see if the card is busy. Data transfer commands 265 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 266 * 267 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 268 * expected. 269 */ 270 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 271 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 272 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 273 status, 274 !(status & SDMMC_STATUS_BUSY), 275 10, 500 * USEC_PER_MSEC)) 276 dev_err(host->dev, "Busy; trying anyway\n"); 277 } 278 } 279 280 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 281 { 282 struct dw_mci *host = slot->host; 283 unsigned int cmd_status = 0; 284 285 mci_writel(host, CMDARG, arg); 286 wmb(); /* drain writebuffer */ 287 dw_mci_wait_while_busy(host, cmd); 288 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 289 290 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 291 !(cmd_status & SDMMC_CMD_START), 292 1, 500 * USEC_PER_MSEC)) 293 dev_err(&slot->mmc->class_dev, 294 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 295 cmd, arg, cmd_status); 296 } 297 298 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 299 { 300 struct dw_mci_slot *slot = mmc_priv(mmc); 301 struct dw_mci *host = slot->host; 302 u32 cmdr; 303 304 cmd->error = -EINPROGRESS; 305 cmdr = cmd->opcode; 306 307 if (cmd->opcode == MMC_STOP_TRANSMISSION || 308 cmd->opcode == MMC_GO_IDLE_STATE || 309 cmd->opcode == MMC_GO_INACTIVE_STATE || 310 (cmd->opcode == SD_IO_RW_DIRECT && 311 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 312 cmdr |= SDMMC_CMD_STOP; 313 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 314 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 315 316 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 317 u32 clk_en_a; 318 319 /* Special bit makes CMD11 not die */ 320 cmdr |= SDMMC_CMD_VOLT_SWITCH; 321 322 /* Change state to continue to handle CMD11 weirdness */ 323 WARN_ON(slot->host->state != STATE_SENDING_CMD); 324 slot->host->state = STATE_SENDING_CMD11; 325 326 /* 327 * We need to disable low power mode (automatic clock stop) 328 * while doing voltage switch so we don't confuse the card, 329 * since stopping the clock is a specific part of the UHS 330 * voltage change dance. 331 * 332 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 333 * unconditionally turned back on in dw_mci_setup_bus() if it's 334 * ever called with a non-zero clock. That shouldn't happen 335 * until the voltage change is all done. 336 */ 337 clk_en_a = mci_readl(host, CLKENA); 338 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 339 mci_writel(host, CLKENA, clk_en_a); 340 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 341 SDMMC_CMD_PRV_DAT_WAIT, 0); 342 } 343 344 if (cmd->flags & MMC_RSP_PRESENT) { 345 /* We expect a response, so set this bit */ 346 cmdr |= SDMMC_CMD_RESP_EXP; 347 if (cmd->flags & MMC_RSP_136) 348 cmdr |= SDMMC_CMD_RESP_LONG; 349 } 350 351 if (cmd->flags & MMC_RSP_CRC) 352 cmdr |= SDMMC_CMD_RESP_CRC; 353 354 if (cmd->data) { 355 cmdr |= SDMMC_CMD_DAT_EXP; 356 if (cmd->data->flags & MMC_DATA_WRITE) 357 cmdr |= SDMMC_CMD_DAT_WR; 358 } 359 360 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 361 cmdr |= SDMMC_CMD_USE_HOLD_REG; 362 363 return cmdr; 364 } 365 366 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 367 { 368 struct mmc_command *stop; 369 u32 cmdr; 370 371 if (!cmd->data) 372 return 0; 373 374 stop = &host->stop_abort; 375 cmdr = cmd->opcode; 376 memset(stop, 0, sizeof(struct mmc_command)); 377 378 if (cmdr == MMC_READ_SINGLE_BLOCK || 379 cmdr == MMC_READ_MULTIPLE_BLOCK || 380 cmdr == MMC_WRITE_BLOCK || 381 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 382 cmdr == MMC_SEND_TUNING_BLOCK || 383 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 384 stop->opcode = MMC_STOP_TRANSMISSION; 385 stop->arg = 0; 386 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 387 } else if (cmdr == SD_IO_RW_EXTENDED) { 388 stop->opcode = SD_IO_RW_DIRECT; 389 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 390 ((cmd->arg >> 28) & 0x7); 391 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 392 } else { 393 return 0; 394 } 395 396 cmdr = stop->opcode | SDMMC_CMD_STOP | 397 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 398 399 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 400 cmdr |= SDMMC_CMD_USE_HOLD_REG; 401 402 return cmdr; 403 } 404 405 static inline void dw_mci_set_cto(struct dw_mci *host) 406 { 407 unsigned int cto_clks; 408 unsigned int cto_div; 409 unsigned int cto_ms; 410 unsigned long irqflags; 411 412 cto_clks = mci_readl(host, TMOUT) & 0xff; 413 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 414 if (cto_div == 0) 415 cto_div = 1; 416 417 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 418 host->bus_hz); 419 420 /* add a bit spare time */ 421 cto_ms += 10; 422 423 /* 424 * The durations we're working with are fairly short so we have to be 425 * extra careful about synchronization here. Specifically in hardware a 426 * command timeout is _at most_ 5.1 ms, so that means we expect an 427 * interrupt (either command done or timeout) to come rather quickly 428 * after the mci_writel. ...but just in case we have a long interrupt 429 * latency let's add a bit of paranoia. 430 * 431 * In general we'll assume that at least an interrupt will be asserted 432 * in hardware by the time the cto_timer runs. ...and if it hasn't 433 * been asserted in hardware by that time then we'll assume it'll never 434 * come. 435 */ 436 spin_lock_irqsave(&host->irq_lock, irqflags); 437 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 438 mod_timer(&host->cto_timer, 439 jiffies + msecs_to_jiffies(cto_ms) + 1); 440 spin_unlock_irqrestore(&host->irq_lock, irqflags); 441 } 442 443 static void dw_mci_start_command(struct dw_mci *host, 444 struct mmc_command *cmd, u32 cmd_flags) 445 { 446 host->cmd = cmd; 447 dev_vdbg(host->dev, 448 "start command: ARGR=0x%08x CMDR=0x%08x\n", 449 cmd->arg, cmd_flags); 450 451 mci_writel(host, CMDARG, cmd->arg); 452 wmb(); /* drain writebuffer */ 453 dw_mci_wait_while_busy(host, cmd_flags); 454 455 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 456 457 /* response expected command only */ 458 if (cmd_flags & SDMMC_CMD_RESP_EXP) 459 dw_mci_set_cto(host); 460 } 461 462 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 463 { 464 struct mmc_command *stop = &host->stop_abort; 465 466 dw_mci_start_command(host, stop, host->stop_cmdr); 467 } 468 469 /* DMA interface functions */ 470 static void dw_mci_stop_dma(struct dw_mci *host) 471 { 472 if (host->using_dma) { 473 host->dma_ops->stop(host); 474 host->dma_ops->cleanup(host); 475 } 476 477 /* Data transfer was stopped by the interrupt handler */ 478 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 479 } 480 481 static void dw_mci_dma_cleanup(struct dw_mci *host) 482 { 483 struct mmc_data *data = host->data; 484 485 if (data && data->host_cookie == COOKIE_MAPPED) { 486 dma_unmap_sg(host->dev, 487 data->sg, 488 data->sg_len, 489 mmc_get_dma_dir(data)); 490 data->host_cookie = COOKIE_UNMAPPED; 491 } 492 } 493 494 static void dw_mci_idmac_reset(struct dw_mci *host) 495 { 496 u32 bmod = mci_readl(host, BMOD); 497 /* Software reset of DMA */ 498 bmod |= SDMMC_IDMAC_SWRESET; 499 mci_writel(host, BMOD, bmod); 500 } 501 502 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 503 { 504 u32 temp; 505 506 /* Disable and reset the IDMAC interface */ 507 temp = mci_readl(host, CTRL); 508 temp &= ~SDMMC_CTRL_USE_IDMAC; 509 temp |= SDMMC_CTRL_DMA_RESET; 510 mci_writel(host, CTRL, temp); 511 512 /* Stop the IDMAC running */ 513 temp = mci_readl(host, BMOD); 514 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 515 temp |= SDMMC_IDMAC_SWRESET; 516 mci_writel(host, BMOD, temp); 517 } 518 519 static void dw_mci_dmac_complete_dma(void *arg) 520 { 521 struct dw_mci *host = arg; 522 struct mmc_data *data = host->data; 523 524 dev_vdbg(host->dev, "DMA complete\n"); 525 526 if ((host->use_dma == TRANS_MODE_EDMAC) && 527 data && (data->flags & MMC_DATA_READ)) 528 /* Invalidate cache after read */ 529 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 530 data->sg, 531 data->sg_len, 532 DMA_FROM_DEVICE); 533 534 host->dma_ops->cleanup(host); 535 536 /* 537 * If the card was removed, data will be NULL. No point in trying to 538 * send the stop command or waiting for NBUSY in this case. 539 */ 540 if (data) { 541 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 542 tasklet_schedule(&host->tasklet); 543 } 544 } 545 546 static int dw_mci_idmac_init(struct dw_mci *host) 547 { 548 int i; 549 550 if (host->dma_64bit_address == 1) { 551 struct idmac_desc_64addr *p; 552 /* Number of descriptors in the ring buffer */ 553 host->ring_size = 554 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 555 556 /* Forward link the descriptor list */ 557 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 558 i++, p++) { 559 p->des6 = (host->sg_dma + 560 (sizeof(struct idmac_desc_64addr) * 561 (i + 1))) & 0xffffffff; 562 563 p->des7 = (u64)(host->sg_dma + 564 (sizeof(struct idmac_desc_64addr) * 565 (i + 1))) >> 32; 566 /* Initialize reserved and buffer size fields to "0" */ 567 p->des0 = 0; 568 p->des1 = 0; 569 p->des2 = 0; 570 p->des3 = 0; 571 } 572 573 /* Set the last descriptor as the end-of-ring descriptor */ 574 p->des6 = host->sg_dma & 0xffffffff; 575 p->des7 = (u64)host->sg_dma >> 32; 576 p->des0 = IDMAC_DES0_ER; 577 578 } else { 579 struct idmac_desc *p; 580 /* Number of descriptors in the ring buffer */ 581 host->ring_size = 582 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 583 584 /* Forward link the descriptor list */ 585 for (i = 0, p = host->sg_cpu; 586 i < host->ring_size - 1; 587 i++, p++) { 588 p->des3 = cpu_to_le32(host->sg_dma + 589 (sizeof(struct idmac_desc) * (i + 1))); 590 p->des0 = 0; 591 p->des1 = 0; 592 } 593 594 /* Set the last descriptor as the end-of-ring descriptor */ 595 p->des3 = cpu_to_le32(host->sg_dma); 596 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 597 } 598 599 dw_mci_idmac_reset(host); 600 601 if (host->dma_64bit_address == 1) { 602 /* Mask out interrupts - get Tx & Rx complete only */ 603 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 604 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 605 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 606 607 /* Set the descriptor base address */ 608 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 609 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 610 611 } else { 612 /* Mask out interrupts - get Tx & Rx complete only */ 613 mci_writel(host, IDSTS, IDMAC_INT_CLR); 614 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 615 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 616 617 /* Set the descriptor base address */ 618 mci_writel(host, DBADDR, host->sg_dma); 619 } 620 621 return 0; 622 } 623 624 static inline int dw_mci_prepare_desc64(struct dw_mci *host, 625 struct mmc_data *data, 626 unsigned int sg_len) 627 { 628 unsigned int desc_len; 629 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 630 u32 val; 631 int i; 632 633 desc_first = desc_last = desc = host->sg_cpu; 634 635 for (i = 0; i < sg_len; i++) { 636 unsigned int length = sg_dma_len(&data->sg[i]); 637 638 u64 mem_addr = sg_dma_address(&data->sg[i]); 639 640 for ( ; length ; desc++) { 641 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 642 length : DW_MCI_DESC_DATA_LENGTH; 643 644 length -= desc_len; 645 646 /* 647 * Wait for the former clear OWN bit operation 648 * of IDMAC to make sure that this descriptor 649 * isn't still owned by IDMAC as IDMAC's write 650 * ops and CPU's read ops are asynchronous. 651 */ 652 if (readl_poll_timeout_atomic(&desc->des0, val, 653 !(val & IDMAC_DES0_OWN), 654 10, 100 * USEC_PER_MSEC)) 655 goto err_own_bit; 656 657 /* 658 * Set the OWN bit and disable interrupts 659 * for this descriptor 660 */ 661 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 662 IDMAC_DES0_CH; 663 664 /* Buffer length */ 665 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 666 667 /* Physical address to DMA to/from */ 668 desc->des4 = mem_addr & 0xffffffff; 669 desc->des5 = mem_addr >> 32; 670 671 /* Update physical address for the next desc */ 672 mem_addr += desc_len; 673 674 /* Save pointer to the last descriptor */ 675 desc_last = desc; 676 } 677 } 678 679 /* Set first descriptor */ 680 desc_first->des0 |= IDMAC_DES0_FD; 681 682 /* Set last descriptor */ 683 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 684 desc_last->des0 |= IDMAC_DES0_LD; 685 686 return 0; 687 err_own_bit: 688 /* restore the descriptor chain as it's polluted */ 689 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 690 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 691 dw_mci_idmac_init(host); 692 return -EINVAL; 693 } 694 695 696 static inline int dw_mci_prepare_desc32(struct dw_mci *host, 697 struct mmc_data *data, 698 unsigned int sg_len) 699 { 700 unsigned int desc_len; 701 struct idmac_desc *desc_first, *desc_last, *desc; 702 u32 val; 703 int i; 704 705 desc_first = desc_last = desc = host->sg_cpu; 706 707 for (i = 0; i < sg_len; i++) { 708 unsigned int length = sg_dma_len(&data->sg[i]); 709 710 u32 mem_addr = sg_dma_address(&data->sg[i]); 711 712 for ( ; length ; desc++) { 713 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 714 length : DW_MCI_DESC_DATA_LENGTH; 715 716 length -= desc_len; 717 718 /* 719 * Wait for the former clear OWN bit operation 720 * of IDMAC to make sure that this descriptor 721 * isn't still owned by IDMAC as IDMAC's write 722 * ops and CPU's read ops are asynchronous. 723 */ 724 if (readl_poll_timeout_atomic(&desc->des0, val, 725 IDMAC_OWN_CLR64(val), 726 10, 727 100 * USEC_PER_MSEC)) 728 goto err_own_bit; 729 730 /* 731 * Set the OWN bit and disable interrupts 732 * for this descriptor 733 */ 734 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 735 IDMAC_DES0_DIC | 736 IDMAC_DES0_CH); 737 738 /* Buffer length */ 739 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 740 741 /* Physical address to DMA to/from */ 742 desc->des2 = cpu_to_le32(mem_addr); 743 744 /* Update physical address for the next desc */ 745 mem_addr += desc_len; 746 747 /* Save pointer to the last descriptor */ 748 desc_last = desc; 749 } 750 } 751 752 /* Set first descriptor */ 753 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 754 755 /* Set last descriptor */ 756 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 757 IDMAC_DES0_DIC)); 758 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 759 760 return 0; 761 err_own_bit: 762 /* restore the descriptor chain as it's polluted */ 763 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 764 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 765 dw_mci_idmac_init(host); 766 return -EINVAL; 767 } 768 769 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 770 { 771 u32 temp; 772 int ret; 773 774 if (host->dma_64bit_address == 1) 775 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 776 else 777 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 778 779 if (ret) 780 goto out; 781 782 /* drain writebuffer */ 783 wmb(); 784 785 /* Make sure to reset DMA in case we did PIO before this */ 786 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 787 dw_mci_idmac_reset(host); 788 789 /* Select IDMAC interface */ 790 temp = mci_readl(host, CTRL); 791 temp |= SDMMC_CTRL_USE_IDMAC; 792 mci_writel(host, CTRL, temp); 793 794 /* drain writebuffer */ 795 wmb(); 796 797 /* Enable the IDMAC */ 798 temp = mci_readl(host, BMOD); 799 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 800 mci_writel(host, BMOD, temp); 801 802 /* Start it running */ 803 mci_writel(host, PLDMND, 1); 804 805 out: 806 return ret; 807 } 808 809 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 810 .init = dw_mci_idmac_init, 811 .start = dw_mci_idmac_start_dma, 812 .stop = dw_mci_idmac_stop_dma, 813 .complete = dw_mci_dmac_complete_dma, 814 .cleanup = dw_mci_dma_cleanup, 815 }; 816 817 static void dw_mci_edmac_stop_dma(struct dw_mci *host) 818 { 819 dmaengine_terminate_async(host->dms->ch); 820 } 821 822 static int dw_mci_edmac_start_dma(struct dw_mci *host, 823 unsigned int sg_len) 824 { 825 struct dma_slave_config cfg; 826 struct dma_async_tx_descriptor *desc = NULL; 827 struct scatterlist *sgl = host->data->sg; 828 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 829 u32 sg_elems = host->data->sg_len; 830 u32 fifoth_val; 831 u32 fifo_offset = host->fifo_reg - host->regs; 832 int ret = 0; 833 834 /* Set external dma config: burst size, burst width */ 835 cfg.dst_addr = host->phy_regs + fifo_offset; 836 cfg.src_addr = cfg.dst_addr; 837 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 838 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 839 840 /* Match burst msize with external dma config */ 841 fifoth_val = mci_readl(host, FIFOTH); 842 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 843 cfg.src_maxburst = cfg.dst_maxburst; 844 845 if (host->data->flags & MMC_DATA_WRITE) 846 cfg.direction = DMA_MEM_TO_DEV; 847 else 848 cfg.direction = DMA_DEV_TO_MEM; 849 850 ret = dmaengine_slave_config(host->dms->ch, &cfg); 851 if (ret) { 852 dev_err(host->dev, "Failed to config edmac.\n"); 853 return -EBUSY; 854 } 855 856 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 857 sg_len, cfg.direction, 858 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 859 if (!desc) { 860 dev_err(host->dev, "Can't prepare slave sg.\n"); 861 return -EBUSY; 862 } 863 864 /* Set dw_mci_dmac_complete_dma as callback */ 865 desc->callback = dw_mci_dmac_complete_dma; 866 desc->callback_param = (void *)host; 867 dmaengine_submit(desc); 868 869 /* Flush cache before write */ 870 if (host->data->flags & MMC_DATA_WRITE) 871 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 872 sg_elems, DMA_TO_DEVICE); 873 874 dma_async_issue_pending(host->dms->ch); 875 876 return 0; 877 } 878 879 static int dw_mci_edmac_init(struct dw_mci *host) 880 { 881 /* Request external dma channel */ 882 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 883 if (!host->dms) 884 return -ENOMEM; 885 886 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 887 if (!host->dms->ch) { 888 dev_err(host->dev, "Failed to get external DMA channel.\n"); 889 kfree(host->dms); 890 host->dms = NULL; 891 return -ENXIO; 892 } 893 894 return 0; 895 } 896 897 static void dw_mci_edmac_exit(struct dw_mci *host) 898 { 899 if (host->dms) { 900 if (host->dms->ch) { 901 dma_release_channel(host->dms->ch); 902 host->dms->ch = NULL; 903 } 904 kfree(host->dms); 905 host->dms = NULL; 906 } 907 } 908 909 static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 910 .init = dw_mci_edmac_init, 911 .exit = dw_mci_edmac_exit, 912 .start = dw_mci_edmac_start_dma, 913 .stop = dw_mci_edmac_stop_dma, 914 .complete = dw_mci_dmac_complete_dma, 915 .cleanup = dw_mci_dma_cleanup, 916 }; 917 918 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 919 struct mmc_data *data, 920 int cookie) 921 { 922 struct scatterlist *sg; 923 unsigned int i, sg_len; 924 925 if (data->host_cookie == COOKIE_PRE_MAPPED) 926 return data->sg_len; 927 928 /* 929 * We don't do DMA on "complex" transfers, i.e. with 930 * non-word-aligned buffers or lengths. Also, we don't bother 931 * with all the DMA setup overhead for short transfers. 932 */ 933 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 934 return -EINVAL; 935 936 if (data->blksz & 3) 937 return -EINVAL; 938 939 for_each_sg(data->sg, sg, data->sg_len, i) { 940 if (sg->offset & 3 || sg->length & 3) 941 return -EINVAL; 942 } 943 944 sg_len = dma_map_sg(host->dev, 945 data->sg, 946 data->sg_len, 947 mmc_get_dma_dir(data)); 948 if (sg_len == 0) 949 return -EINVAL; 950 951 data->host_cookie = cookie; 952 953 return sg_len; 954 } 955 956 static void dw_mci_pre_req(struct mmc_host *mmc, 957 struct mmc_request *mrq) 958 { 959 struct dw_mci_slot *slot = mmc_priv(mmc); 960 struct mmc_data *data = mrq->data; 961 962 if (!slot->host->use_dma || !data) 963 return; 964 965 /* This data might be unmapped at this time */ 966 data->host_cookie = COOKIE_UNMAPPED; 967 968 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 969 COOKIE_PRE_MAPPED) < 0) 970 data->host_cookie = COOKIE_UNMAPPED; 971 } 972 973 static void dw_mci_post_req(struct mmc_host *mmc, 974 struct mmc_request *mrq, 975 int err) 976 { 977 struct dw_mci_slot *slot = mmc_priv(mmc); 978 struct mmc_data *data = mrq->data; 979 980 if (!slot->host->use_dma || !data) 981 return; 982 983 if (data->host_cookie != COOKIE_UNMAPPED) 984 dma_unmap_sg(slot->host->dev, 985 data->sg, 986 data->sg_len, 987 mmc_get_dma_dir(data)); 988 data->host_cookie = COOKIE_UNMAPPED; 989 } 990 991 static int dw_mci_get_cd(struct mmc_host *mmc) 992 { 993 int present; 994 struct dw_mci_slot *slot = mmc_priv(mmc); 995 struct dw_mci *host = slot->host; 996 int gpio_cd = mmc_gpio_get_cd(mmc); 997 998 /* Use platform get_cd function, else try onboard card detect */ 999 if (((mmc->caps & MMC_CAP_NEEDS_POLL) 1000 || !mmc_card_is_removable(mmc))) { 1001 present = 1; 1002 1003 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 1004 if (mmc->caps & MMC_CAP_NEEDS_POLL) { 1005 dev_info(&mmc->class_dev, 1006 "card is polling.\n"); 1007 } else { 1008 dev_info(&mmc->class_dev, 1009 "card is non-removable.\n"); 1010 } 1011 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1012 } 1013 1014 return present; 1015 } else if (gpio_cd >= 0) 1016 present = gpio_cd; 1017 else 1018 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1019 == 0 ? 1 : 0; 1020 1021 spin_lock_bh(&host->lock); 1022 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 1023 dev_dbg(&mmc->class_dev, "card is present\n"); 1024 else if (!present && 1025 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 1026 dev_dbg(&mmc->class_dev, "card is not present\n"); 1027 spin_unlock_bh(&host->lock); 1028 1029 return present; 1030 } 1031 1032 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 1033 { 1034 unsigned int blksz = data->blksz; 1035 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 1036 u32 fifo_width = 1 << host->data_shift; 1037 u32 blksz_depth = blksz / fifo_width, fifoth_val; 1038 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 1039 int idx = ARRAY_SIZE(mszs) - 1; 1040 1041 /* pio should ship this scenario */ 1042 if (!host->use_dma) 1043 return; 1044 1045 tx_wmark = (host->fifo_depth) / 2; 1046 tx_wmark_invers = host->fifo_depth - tx_wmark; 1047 1048 /* 1049 * MSIZE is '1', 1050 * if blksz is not a multiple of the FIFO width 1051 */ 1052 if (blksz % fifo_width) 1053 goto done; 1054 1055 do { 1056 if (!((blksz_depth % mszs[idx]) || 1057 (tx_wmark_invers % mszs[idx]))) { 1058 msize = idx; 1059 rx_wmark = mszs[idx] - 1; 1060 break; 1061 } 1062 } while (--idx > 0); 1063 /* 1064 * If idx is '0', it won't be tried 1065 * Thus, initial values are uesed 1066 */ 1067 done: 1068 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 1069 mci_writel(host, FIFOTH, fifoth_val); 1070 } 1071 1072 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1073 { 1074 unsigned int blksz = data->blksz; 1075 u32 blksz_depth, fifo_depth; 1076 u16 thld_size; 1077 u8 enable; 1078 1079 /* 1080 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 1081 * in the FIFO region, so we really shouldn't access it). 1082 */ 1083 if (host->verid < DW_MMC_240A || 1084 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 1085 return; 1086 1087 /* 1088 * Card write Threshold is introduced since 2.80a 1089 * It's used when HS400 mode is enabled. 1090 */ 1091 if (data->flags & MMC_DATA_WRITE && 1092 !(host->timing != MMC_TIMING_MMC_HS400)) 1093 return; 1094 1095 if (data->flags & MMC_DATA_WRITE) 1096 enable = SDMMC_CARD_WR_THR_EN; 1097 else 1098 enable = SDMMC_CARD_RD_THR_EN; 1099 1100 if (host->timing != MMC_TIMING_MMC_HS200 && 1101 host->timing != MMC_TIMING_UHS_SDR104) 1102 goto disable; 1103 1104 blksz_depth = blksz / (1 << host->data_shift); 1105 fifo_depth = host->fifo_depth; 1106 1107 if (blksz_depth > fifo_depth) 1108 goto disable; 1109 1110 /* 1111 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1112 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1113 * Currently just choose blksz. 1114 */ 1115 thld_size = blksz; 1116 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1117 return; 1118 1119 disable: 1120 mci_writel(host, CDTHRCTL, 0); 1121 } 1122 1123 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1124 { 1125 unsigned long irqflags; 1126 int sg_len; 1127 u32 temp; 1128 1129 host->using_dma = 0; 1130 1131 /* If we don't have a channel, we can't do DMA */ 1132 if (!host->use_dma) 1133 return -ENODEV; 1134 1135 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1136 if (sg_len < 0) { 1137 host->dma_ops->stop(host); 1138 return sg_len; 1139 } 1140 1141 host->using_dma = 1; 1142 1143 if (host->use_dma == TRANS_MODE_IDMAC) 1144 dev_vdbg(host->dev, 1145 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1146 (unsigned long)host->sg_cpu, 1147 (unsigned long)host->sg_dma, 1148 sg_len); 1149 1150 /* 1151 * Decide the MSIZE and RX/TX Watermark. 1152 * If current block size is same with previous size, 1153 * no need to update fifoth. 1154 */ 1155 if (host->prev_blksz != data->blksz) 1156 dw_mci_adjust_fifoth(host, data); 1157 1158 /* Enable the DMA interface */ 1159 temp = mci_readl(host, CTRL); 1160 temp |= SDMMC_CTRL_DMA_ENABLE; 1161 mci_writel(host, CTRL, temp); 1162 1163 /* Disable RX/TX IRQs, let DMA handle it */ 1164 spin_lock_irqsave(&host->irq_lock, irqflags); 1165 temp = mci_readl(host, INTMASK); 1166 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1167 mci_writel(host, INTMASK, temp); 1168 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1169 1170 if (host->dma_ops->start(host, sg_len)) { 1171 host->dma_ops->stop(host); 1172 /* We can't do DMA, try PIO for this one */ 1173 dev_dbg(host->dev, 1174 "%s: fall back to PIO mode for current transfer\n", 1175 __func__); 1176 return -ENODEV; 1177 } 1178 1179 return 0; 1180 } 1181 1182 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1183 { 1184 unsigned long irqflags; 1185 int flags = SG_MITER_ATOMIC; 1186 u32 temp; 1187 1188 data->error = -EINPROGRESS; 1189 1190 WARN_ON(host->data); 1191 host->sg = NULL; 1192 host->data = data; 1193 1194 if (data->flags & MMC_DATA_READ) 1195 host->dir_status = DW_MCI_RECV_STATUS; 1196 else 1197 host->dir_status = DW_MCI_SEND_STATUS; 1198 1199 dw_mci_ctrl_thld(host, data); 1200 1201 if (dw_mci_submit_data_dma(host, data)) { 1202 if (host->data->flags & MMC_DATA_READ) 1203 flags |= SG_MITER_TO_SG; 1204 else 1205 flags |= SG_MITER_FROM_SG; 1206 1207 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1208 host->sg = data->sg; 1209 host->part_buf_start = 0; 1210 host->part_buf_count = 0; 1211 1212 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1213 1214 spin_lock_irqsave(&host->irq_lock, irqflags); 1215 temp = mci_readl(host, INTMASK); 1216 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1217 mci_writel(host, INTMASK, temp); 1218 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1219 1220 temp = mci_readl(host, CTRL); 1221 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1222 mci_writel(host, CTRL, temp); 1223 1224 /* 1225 * Use the initial fifoth_val for PIO mode. If wm_algined 1226 * is set, we set watermark same as data size. 1227 * If next issued data may be transfered by DMA mode, 1228 * prev_blksz should be invalidated. 1229 */ 1230 if (host->wm_aligned) 1231 dw_mci_adjust_fifoth(host, data); 1232 else 1233 mci_writel(host, FIFOTH, host->fifoth_val); 1234 host->prev_blksz = 0; 1235 } else { 1236 /* 1237 * Keep the current block size. 1238 * It will be used to decide whether to update 1239 * fifoth register next time. 1240 */ 1241 host->prev_blksz = data->blksz; 1242 } 1243 } 1244 1245 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1246 { 1247 struct dw_mci *host = slot->host; 1248 unsigned int clock = slot->clock; 1249 u32 div; 1250 u32 clk_en_a; 1251 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1252 1253 /* We must continue to set bit 28 in CMD until the change is complete */ 1254 if (host->state == STATE_WAITING_CMD11_DONE) 1255 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1256 1257 if (!clock) { 1258 mci_writel(host, CLKENA, 0); 1259 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1260 } else if (clock != host->current_speed || force_clkinit) { 1261 div = host->bus_hz / clock; 1262 if (host->bus_hz % clock && host->bus_hz > clock) 1263 /* 1264 * move the + 1 after the divide to prevent 1265 * over-clocking the card. 1266 */ 1267 div += 1; 1268 1269 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1270 1271 if ((clock != slot->__clk_old && 1272 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1273 force_clkinit) { 1274 /* Silent the verbose log if calling from PM context */ 1275 if (!force_clkinit) 1276 dev_info(&slot->mmc->class_dev, 1277 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1278 slot->id, host->bus_hz, clock, 1279 div ? ((host->bus_hz / div) >> 1) : 1280 host->bus_hz, div); 1281 1282 /* 1283 * If card is polling, display the message only 1284 * one time at boot time. 1285 */ 1286 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1287 slot->mmc->f_min == clock) 1288 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1289 } 1290 1291 /* disable clock */ 1292 mci_writel(host, CLKENA, 0); 1293 mci_writel(host, CLKSRC, 0); 1294 1295 /* inform CIU */ 1296 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1297 1298 /* set clock to desired speed */ 1299 mci_writel(host, CLKDIV, div); 1300 1301 /* inform CIU */ 1302 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1303 1304 /* enable clock; only low power if no SDIO */ 1305 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1306 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1307 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1308 mci_writel(host, CLKENA, clk_en_a); 1309 1310 /* inform CIU */ 1311 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1312 1313 /* keep the last clock value that was requested from core */ 1314 slot->__clk_old = clock; 1315 } 1316 1317 host->current_speed = clock; 1318 1319 /* Set the current slot bus width */ 1320 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1321 } 1322 1323 static void __dw_mci_start_request(struct dw_mci *host, 1324 struct dw_mci_slot *slot, 1325 struct mmc_command *cmd) 1326 { 1327 struct mmc_request *mrq; 1328 struct mmc_data *data; 1329 u32 cmdflags; 1330 1331 mrq = slot->mrq; 1332 1333 host->mrq = mrq; 1334 1335 host->pending_events = 0; 1336 host->completed_events = 0; 1337 host->cmd_status = 0; 1338 host->data_status = 0; 1339 host->dir_status = 0; 1340 1341 data = cmd->data; 1342 if (data) { 1343 mci_writel(host, TMOUT, 0xFFFFFFFF); 1344 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1345 mci_writel(host, BLKSIZ, data->blksz); 1346 } 1347 1348 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1349 1350 /* this is the first command, send the initialization clock */ 1351 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1352 cmdflags |= SDMMC_CMD_INIT; 1353 1354 if (data) { 1355 dw_mci_submit_data(host, data); 1356 wmb(); /* drain writebuffer */ 1357 } 1358 1359 dw_mci_start_command(host, cmd, cmdflags); 1360 1361 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1362 unsigned long irqflags; 1363 1364 /* 1365 * Databook says to fail after 2ms w/ no response, but evidence 1366 * shows that sometimes the cmd11 interrupt takes over 130ms. 1367 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1368 * is just about to roll over. 1369 * 1370 * We do this whole thing under spinlock and only if the 1371 * command hasn't already completed (indicating the the irq 1372 * already ran so we don't want the timeout). 1373 */ 1374 spin_lock_irqsave(&host->irq_lock, irqflags); 1375 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1376 mod_timer(&host->cmd11_timer, 1377 jiffies + msecs_to_jiffies(500) + 1); 1378 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1379 } 1380 1381 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1382 } 1383 1384 static void dw_mci_start_request(struct dw_mci *host, 1385 struct dw_mci_slot *slot) 1386 { 1387 struct mmc_request *mrq = slot->mrq; 1388 struct mmc_command *cmd; 1389 1390 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1391 __dw_mci_start_request(host, slot, cmd); 1392 } 1393 1394 /* must be called with host->lock held */ 1395 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1396 struct mmc_request *mrq) 1397 { 1398 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1399 host->state); 1400 1401 slot->mrq = mrq; 1402 1403 if (host->state == STATE_WAITING_CMD11_DONE) { 1404 dev_warn(&slot->mmc->class_dev, 1405 "Voltage change didn't complete\n"); 1406 /* 1407 * this case isn't expected to happen, so we can 1408 * either crash here or just try to continue on 1409 * in the closest possible state 1410 */ 1411 host->state = STATE_IDLE; 1412 } 1413 1414 if (host->state == STATE_IDLE) { 1415 host->state = STATE_SENDING_CMD; 1416 dw_mci_start_request(host, slot); 1417 } else { 1418 list_add_tail(&slot->queue_node, &host->queue); 1419 } 1420 } 1421 1422 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1423 { 1424 struct dw_mci_slot *slot = mmc_priv(mmc); 1425 struct dw_mci *host = slot->host; 1426 1427 WARN_ON(slot->mrq); 1428 1429 /* 1430 * The check for card presence and queueing of the request must be 1431 * atomic, otherwise the card could be removed in between and the 1432 * request wouldn't fail until another card was inserted. 1433 */ 1434 1435 if (!dw_mci_get_cd(mmc)) { 1436 mrq->cmd->error = -ENOMEDIUM; 1437 mmc_request_done(mmc, mrq); 1438 return; 1439 } 1440 1441 spin_lock_bh(&host->lock); 1442 1443 dw_mci_queue_request(host, slot, mrq); 1444 1445 spin_unlock_bh(&host->lock); 1446 } 1447 1448 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1449 { 1450 struct dw_mci_slot *slot = mmc_priv(mmc); 1451 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1452 u32 regs; 1453 int ret; 1454 1455 switch (ios->bus_width) { 1456 case MMC_BUS_WIDTH_4: 1457 slot->ctype = SDMMC_CTYPE_4BIT; 1458 break; 1459 case MMC_BUS_WIDTH_8: 1460 slot->ctype = SDMMC_CTYPE_8BIT; 1461 break; 1462 default: 1463 /* set default 1 bit mode */ 1464 slot->ctype = SDMMC_CTYPE_1BIT; 1465 } 1466 1467 regs = mci_readl(slot->host, UHS_REG); 1468 1469 /* DDR mode set */ 1470 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1471 ios->timing == MMC_TIMING_UHS_DDR50 || 1472 ios->timing == MMC_TIMING_MMC_HS400) 1473 regs |= ((0x1 << slot->id) << 16); 1474 else 1475 regs &= ~((0x1 << slot->id) << 16); 1476 1477 mci_writel(slot->host, UHS_REG, regs); 1478 slot->host->timing = ios->timing; 1479 1480 /* 1481 * Use mirror of ios->clock to prevent race with mmc 1482 * core ios update when finding the minimum. 1483 */ 1484 slot->clock = ios->clock; 1485 1486 if (drv_data && drv_data->set_ios) 1487 drv_data->set_ios(slot->host, ios); 1488 1489 switch (ios->power_mode) { 1490 case MMC_POWER_UP: 1491 if (!IS_ERR(mmc->supply.vmmc)) { 1492 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1493 ios->vdd); 1494 if (ret) { 1495 dev_err(slot->host->dev, 1496 "failed to enable vmmc regulator\n"); 1497 /*return, if failed turn on vmmc*/ 1498 return; 1499 } 1500 } 1501 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1502 regs = mci_readl(slot->host, PWREN); 1503 regs |= (1 << slot->id); 1504 mci_writel(slot->host, PWREN, regs); 1505 break; 1506 case MMC_POWER_ON: 1507 if (!slot->host->vqmmc_enabled) { 1508 if (!IS_ERR(mmc->supply.vqmmc)) { 1509 ret = regulator_enable(mmc->supply.vqmmc); 1510 if (ret < 0) 1511 dev_err(slot->host->dev, 1512 "failed to enable vqmmc\n"); 1513 else 1514 slot->host->vqmmc_enabled = true; 1515 1516 } else { 1517 /* Keep track so we don't reset again */ 1518 slot->host->vqmmc_enabled = true; 1519 } 1520 1521 /* Reset our state machine after powering on */ 1522 dw_mci_ctrl_reset(slot->host, 1523 SDMMC_CTRL_ALL_RESET_FLAGS); 1524 } 1525 1526 /* Adjust clock / bus width after power is up */ 1527 dw_mci_setup_bus(slot, false); 1528 1529 break; 1530 case MMC_POWER_OFF: 1531 /* Turn clock off before power goes down */ 1532 dw_mci_setup_bus(slot, false); 1533 1534 if (!IS_ERR(mmc->supply.vmmc)) 1535 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1536 1537 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1538 regulator_disable(mmc->supply.vqmmc); 1539 slot->host->vqmmc_enabled = false; 1540 1541 regs = mci_readl(slot->host, PWREN); 1542 regs &= ~(1 << slot->id); 1543 mci_writel(slot->host, PWREN, regs); 1544 break; 1545 default: 1546 break; 1547 } 1548 1549 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1550 slot->host->state = STATE_IDLE; 1551 } 1552 1553 static int dw_mci_card_busy(struct mmc_host *mmc) 1554 { 1555 struct dw_mci_slot *slot = mmc_priv(mmc); 1556 u32 status; 1557 1558 /* 1559 * Check the busy bit which is low when DAT[3:0] 1560 * (the data lines) are 0000 1561 */ 1562 status = mci_readl(slot->host, STATUS); 1563 1564 return !!(status & SDMMC_STATUS_BUSY); 1565 } 1566 1567 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1568 { 1569 struct dw_mci_slot *slot = mmc_priv(mmc); 1570 struct dw_mci *host = slot->host; 1571 const struct dw_mci_drv_data *drv_data = host->drv_data; 1572 u32 uhs; 1573 u32 v18 = SDMMC_UHS_18V << slot->id; 1574 int ret; 1575 1576 if (drv_data && drv_data->switch_voltage) 1577 return drv_data->switch_voltage(mmc, ios); 1578 1579 /* 1580 * Program the voltage. Note that some instances of dw_mmc may use 1581 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1582 * does no harm but you need to set the regulator directly. Try both. 1583 */ 1584 uhs = mci_readl(host, UHS_REG); 1585 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1586 uhs &= ~v18; 1587 else 1588 uhs |= v18; 1589 1590 if (!IS_ERR(mmc->supply.vqmmc)) { 1591 ret = mmc_regulator_set_vqmmc(mmc, ios); 1592 1593 if (ret) { 1594 dev_dbg(&mmc->class_dev, 1595 "Regulator set error %d - %s V\n", 1596 ret, uhs & v18 ? "1.8" : "3.3"); 1597 return ret; 1598 } 1599 } 1600 mci_writel(host, UHS_REG, uhs); 1601 1602 return 0; 1603 } 1604 1605 static int dw_mci_get_ro(struct mmc_host *mmc) 1606 { 1607 int read_only; 1608 struct dw_mci_slot *slot = mmc_priv(mmc); 1609 int gpio_ro = mmc_gpio_get_ro(mmc); 1610 1611 /* Use platform get_ro function, else try on board write protect */ 1612 if (gpio_ro >= 0) 1613 read_only = gpio_ro; 1614 else 1615 read_only = 1616 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1617 1618 dev_dbg(&mmc->class_dev, "card is %s\n", 1619 read_only ? "read-only" : "read-write"); 1620 1621 return read_only; 1622 } 1623 1624 static void dw_mci_hw_reset(struct mmc_host *mmc) 1625 { 1626 struct dw_mci_slot *slot = mmc_priv(mmc); 1627 struct dw_mci *host = slot->host; 1628 int reset; 1629 1630 if (host->use_dma == TRANS_MODE_IDMAC) 1631 dw_mci_idmac_reset(host); 1632 1633 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1634 SDMMC_CTRL_FIFO_RESET)) 1635 return; 1636 1637 /* 1638 * According to eMMC spec, card reset procedure: 1639 * tRstW >= 1us: RST_n pulse width 1640 * tRSCA >= 200us: RST_n to Command time 1641 * tRSTH >= 1us: RST_n high period 1642 */ 1643 reset = mci_readl(host, RST_N); 1644 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1645 mci_writel(host, RST_N, reset); 1646 usleep_range(1, 2); 1647 reset |= SDMMC_RST_HWACTIVE << slot->id; 1648 mci_writel(host, RST_N, reset); 1649 usleep_range(200, 300); 1650 } 1651 1652 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1653 { 1654 struct dw_mci_slot *slot = mmc_priv(mmc); 1655 struct dw_mci *host = slot->host; 1656 1657 /* 1658 * Low power mode will stop the card clock when idle. According to the 1659 * description of the CLKENA register we should disable low power mode 1660 * for SDIO cards if we need SDIO interrupts to work. 1661 */ 1662 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1663 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1664 u32 clk_en_a_old; 1665 u32 clk_en_a; 1666 1667 clk_en_a_old = mci_readl(host, CLKENA); 1668 1669 if (card->type == MMC_TYPE_SDIO || 1670 card->type == MMC_TYPE_SD_COMBO) { 1671 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1672 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1673 } else { 1674 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1675 clk_en_a = clk_en_a_old | clken_low_pwr; 1676 } 1677 1678 if (clk_en_a != clk_en_a_old) { 1679 mci_writel(host, CLKENA, clk_en_a); 1680 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1681 SDMMC_CMD_PRV_DAT_WAIT, 0); 1682 } 1683 } 1684 } 1685 1686 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 1687 { 1688 struct dw_mci *host = slot->host; 1689 unsigned long irqflags; 1690 u32 int_mask; 1691 1692 spin_lock_irqsave(&host->irq_lock, irqflags); 1693 1694 /* Enable/disable Slot Specific SDIO interrupt */ 1695 int_mask = mci_readl(host, INTMASK); 1696 if (enb) 1697 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1698 else 1699 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1700 mci_writel(host, INTMASK, int_mask); 1701 1702 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1703 } 1704 1705 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1706 { 1707 struct dw_mci_slot *slot = mmc_priv(mmc); 1708 struct dw_mci *host = slot->host; 1709 1710 __dw_mci_enable_sdio_irq(slot, enb); 1711 1712 /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1713 if (enb) 1714 pm_runtime_get_noresume(host->dev); 1715 else 1716 pm_runtime_put_noidle(host->dev); 1717 } 1718 1719 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 1720 { 1721 struct dw_mci_slot *slot = mmc_priv(mmc); 1722 1723 __dw_mci_enable_sdio_irq(slot, 1); 1724 } 1725 1726 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1727 { 1728 struct dw_mci_slot *slot = mmc_priv(mmc); 1729 struct dw_mci *host = slot->host; 1730 const struct dw_mci_drv_data *drv_data = host->drv_data; 1731 int err = -EINVAL; 1732 1733 if (drv_data && drv_data->execute_tuning) 1734 err = drv_data->execute_tuning(slot, opcode); 1735 return err; 1736 } 1737 1738 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1739 struct mmc_ios *ios) 1740 { 1741 struct dw_mci_slot *slot = mmc_priv(mmc); 1742 struct dw_mci *host = slot->host; 1743 const struct dw_mci_drv_data *drv_data = host->drv_data; 1744 1745 if (drv_data && drv_data->prepare_hs400_tuning) 1746 return drv_data->prepare_hs400_tuning(host, ios); 1747 1748 return 0; 1749 } 1750 1751 static bool dw_mci_reset(struct dw_mci *host) 1752 { 1753 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 1754 bool ret = false; 1755 u32 status = 0; 1756 1757 /* 1758 * Resetting generates a block interrupt, hence setting 1759 * the scatter-gather pointer to NULL. 1760 */ 1761 if (host->sg) { 1762 sg_miter_stop(&host->sg_miter); 1763 host->sg = NULL; 1764 } 1765 1766 if (host->use_dma) 1767 flags |= SDMMC_CTRL_DMA_RESET; 1768 1769 if (dw_mci_ctrl_reset(host, flags)) { 1770 /* 1771 * In all cases we clear the RAWINTS 1772 * register to clear any interrupts. 1773 */ 1774 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1775 1776 if (!host->use_dma) { 1777 ret = true; 1778 goto ciu_out; 1779 } 1780 1781 /* Wait for dma_req to be cleared */ 1782 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 1783 status, 1784 !(status & SDMMC_STATUS_DMA_REQ), 1785 1, 500 * USEC_PER_MSEC)) { 1786 dev_err(host->dev, 1787 "%s: Timeout waiting for dma_req to be cleared\n", 1788 __func__); 1789 goto ciu_out; 1790 } 1791 1792 /* when using DMA next we reset the fifo again */ 1793 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 1794 goto ciu_out; 1795 } else { 1796 /* if the controller reset bit did clear, then set clock regs */ 1797 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 1798 dev_err(host->dev, 1799 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 1800 __func__); 1801 goto ciu_out; 1802 } 1803 } 1804 1805 if (host->use_dma == TRANS_MODE_IDMAC) 1806 /* It is also required that we reinit idmac */ 1807 dw_mci_idmac_init(host); 1808 1809 ret = true; 1810 1811 ciu_out: 1812 /* After a CTRL reset we need to have CIU set clock registers */ 1813 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 1814 1815 return ret; 1816 } 1817 1818 static const struct mmc_host_ops dw_mci_ops = { 1819 .request = dw_mci_request, 1820 .pre_req = dw_mci_pre_req, 1821 .post_req = dw_mci_post_req, 1822 .set_ios = dw_mci_set_ios, 1823 .get_ro = dw_mci_get_ro, 1824 .get_cd = dw_mci_get_cd, 1825 .hw_reset = dw_mci_hw_reset, 1826 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1827 .ack_sdio_irq = dw_mci_ack_sdio_irq, 1828 .execute_tuning = dw_mci_execute_tuning, 1829 .card_busy = dw_mci_card_busy, 1830 .start_signal_voltage_switch = dw_mci_switch_voltage, 1831 .init_card = dw_mci_init_card, 1832 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1833 }; 1834 1835 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1836 __releases(&host->lock) 1837 __acquires(&host->lock) 1838 { 1839 struct dw_mci_slot *slot; 1840 struct mmc_host *prev_mmc = host->slot->mmc; 1841 1842 WARN_ON(host->cmd || host->data); 1843 1844 host->slot->mrq = NULL; 1845 host->mrq = NULL; 1846 if (!list_empty(&host->queue)) { 1847 slot = list_entry(host->queue.next, 1848 struct dw_mci_slot, queue_node); 1849 list_del(&slot->queue_node); 1850 dev_vdbg(host->dev, "list not empty: %s is next\n", 1851 mmc_hostname(slot->mmc)); 1852 host->state = STATE_SENDING_CMD; 1853 dw_mci_start_request(host, slot); 1854 } else { 1855 dev_vdbg(host->dev, "list empty\n"); 1856 1857 if (host->state == STATE_SENDING_CMD11) 1858 host->state = STATE_WAITING_CMD11_DONE; 1859 else 1860 host->state = STATE_IDLE; 1861 } 1862 1863 spin_unlock(&host->lock); 1864 mmc_request_done(prev_mmc, mrq); 1865 spin_lock(&host->lock); 1866 } 1867 1868 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1869 { 1870 u32 status = host->cmd_status; 1871 1872 host->cmd_status = 0; 1873 1874 /* Read the response from the card (up to 16 bytes) */ 1875 if (cmd->flags & MMC_RSP_PRESENT) { 1876 if (cmd->flags & MMC_RSP_136) { 1877 cmd->resp[3] = mci_readl(host, RESP0); 1878 cmd->resp[2] = mci_readl(host, RESP1); 1879 cmd->resp[1] = mci_readl(host, RESP2); 1880 cmd->resp[0] = mci_readl(host, RESP3); 1881 } else { 1882 cmd->resp[0] = mci_readl(host, RESP0); 1883 cmd->resp[1] = 0; 1884 cmd->resp[2] = 0; 1885 cmd->resp[3] = 0; 1886 } 1887 } 1888 1889 if (status & SDMMC_INT_RTO) 1890 cmd->error = -ETIMEDOUT; 1891 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1892 cmd->error = -EILSEQ; 1893 else if (status & SDMMC_INT_RESP_ERR) 1894 cmd->error = -EIO; 1895 else 1896 cmd->error = 0; 1897 1898 return cmd->error; 1899 } 1900 1901 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1902 { 1903 u32 status = host->data_status; 1904 1905 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1906 if (status & SDMMC_INT_DRTO) { 1907 data->error = -ETIMEDOUT; 1908 } else if (status & SDMMC_INT_DCRC) { 1909 data->error = -EILSEQ; 1910 } else if (status & SDMMC_INT_EBE) { 1911 if (host->dir_status == 1912 DW_MCI_SEND_STATUS) { 1913 /* 1914 * No data CRC status was returned. 1915 * The number of bytes transferred 1916 * will be exaggerated in PIO mode. 1917 */ 1918 data->bytes_xfered = 0; 1919 data->error = -ETIMEDOUT; 1920 } else if (host->dir_status == 1921 DW_MCI_RECV_STATUS) { 1922 data->error = -EILSEQ; 1923 } 1924 } else { 1925 /* SDMMC_INT_SBE is included */ 1926 data->error = -EILSEQ; 1927 } 1928 1929 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1930 1931 /* 1932 * After an error, there may be data lingering 1933 * in the FIFO 1934 */ 1935 dw_mci_reset(host); 1936 } else { 1937 data->bytes_xfered = data->blocks * data->blksz; 1938 data->error = 0; 1939 } 1940 1941 return data->error; 1942 } 1943 1944 static void dw_mci_set_drto(struct dw_mci *host) 1945 { 1946 unsigned int drto_clks; 1947 unsigned int drto_div; 1948 unsigned int drto_ms; 1949 unsigned long irqflags; 1950 1951 drto_clks = mci_readl(host, TMOUT) >> 8; 1952 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 1953 if (drto_div == 0) 1954 drto_div = 1; 1955 1956 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 1957 host->bus_hz); 1958 1959 /* add a bit spare time */ 1960 drto_ms += 10; 1961 1962 spin_lock_irqsave(&host->irq_lock, irqflags); 1963 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1964 mod_timer(&host->dto_timer, 1965 jiffies + msecs_to_jiffies(drto_ms)); 1966 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1967 } 1968 1969 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 1970 { 1971 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1972 return false; 1973 1974 /* 1975 * Really be certain that the timer has stopped. This is a bit of 1976 * paranoia and could only really happen if we had really bad 1977 * interrupt latency and the interrupt routine and timeout were 1978 * running concurrently so that the del_timer() in the interrupt 1979 * handler couldn't run. 1980 */ 1981 WARN_ON(del_timer_sync(&host->cto_timer)); 1982 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1983 1984 return true; 1985 } 1986 1987 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 1988 { 1989 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1990 return false; 1991 1992 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 1993 WARN_ON(del_timer_sync(&host->dto_timer)); 1994 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1995 1996 return true; 1997 } 1998 1999 static void dw_mci_tasklet_func(unsigned long priv) 2000 { 2001 struct dw_mci *host = (struct dw_mci *)priv; 2002 struct mmc_data *data; 2003 struct mmc_command *cmd; 2004 struct mmc_request *mrq; 2005 enum dw_mci_state state; 2006 enum dw_mci_state prev_state; 2007 unsigned int err; 2008 2009 spin_lock(&host->lock); 2010 2011 state = host->state; 2012 data = host->data; 2013 mrq = host->mrq; 2014 2015 do { 2016 prev_state = state; 2017 2018 switch (state) { 2019 case STATE_IDLE: 2020 case STATE_WAITING_CMD11_DONE: 2021 break; 2022 2023 case STATE_SENDING_CMD11: 2024 case STATE_SENDING_CMD: 2025 if (!dw_mci_clear_pending_cmd_complete(host)) 2026 break; 2027 2028 cmd = host->cmd; 2029 host->cmd = NULL; 2030 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 2031 err = dw_mci_command_complete(host, cmd); 2032 if (cmd == mrq->sbc && !err) { 2033 prev_state = state = STATE_SENDING_CMD; 2034 __dw_mci_start_request(host, host->slot, 2035 mrq->cmd); 2036 goto unlock; 2037 } 2038 2039 if (cmd->data && err) { 2040 /* 2041 * During UHS tuning sequence, sending the stop 2042 * command after the response CRC error would 2043 * throw the system into a confused state 2044 * causing all future tuning phases to report 2045 * failure. 2046 * 2047 * In such case controller will move into a data 2048 * transfer state after a response error or 2049 * response CRC error. Let's let that finish 2050 * before trying to send a stop, so we'll go to 2051 * STATE_SENDING_DATA. 2052 * 2053 * Although letting the data transfer take place 2054 * will waste a bit of time (we already know 2055 * the command was bad), it can't cause any 2056 * errors since it's possible it would have 2057 * taken place anyway if this tasklet got 2058 * delayed. Allowing the transfer to take place 2059 * avoids races and keeps things simple. 2060 */ 2061 if ((err != -ETIMEDOUT) && 2062 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 2063 state = STATE_SENDING_DATA; 2064 continue; 2065 } 2066 2067 dw_mci_stop_dma(host); 2068 send_stop_abort(host, data); 2069 state = STATE_SENDING_STOP; 2070 break; 2071 } 2072 2073 if (!cmd->data || err) { 2074 dw_mci_request_end(host, mrq); 2075 goto unlock; 2076 } 2077 2078 prev_state = state = STATE_SENDING_DATA; 2079 /* fall through */ 2080 2081 case STATE_SENDING_DATA: 2082 /* 2083 * We could get a data error and never a transfer 2084 * complete so we'd better check for it here. 2085 * 2086 * Note that we don't really care if we also got a 2087 * transfer complete; stopping the DMA and sending an 2088 * abort won't hurt. 2089 */ 2090 if (test_and_clear_bit(EVENT_DATA_ERROR, 2091 &host->pending_events)) { 2092 dw_mci_stop_dma(host); 2093 if (!(host->data_status & (SDMMC_INT_DRTO | 2094 SDMMC_INT_EBE))) 2095 send_stop_abort(host, data); 2096 state = STATE_DATA_ERROR; 2097 break; 2098 } 2099 2100 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2101 &host->pending_events)) { 2102 /* 2103 * If all data-related interrupts don't come 2104 * within the given time in reading data state. 2105 */ 2106 if (host->dir_status == DW_MCI_RECV_STATUS) 2107 dw_mci_set_drto(host); 2108 break; 2109 } 2110 2111 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 2112 2113 /* 2114 * Handle an EVENT_DATA_ERROR that might have shown up 2115 * before the transfer completed. This might not have 2116 * been caught by the check above because the interrupt 2117 * could have gone off between the previous check and 2118 * the check for transfer complete. 2119 * 2120 * Technically this ought not be needed assuming we 2121 * get a DATA_COMPLETE eventually (we'll notice the 2122 * error and end the request), but it shouldn't hurt. 2123 * 2124 * This has the advantage of sending the stop command. 2125 */ 2126 if (test_and_clear_bit(EVENT_DATA_ERROR, 2127 &host->pending_events)) { 2128 dw_mci_stop_dma(host); 2129 if (!(host->data_status & (SDMMC_INT_DRTO | 2130 SDMMC_INT_EBE))) 2131 send_stop_abort(host, data); 2132 state = STATE_DATA_ERROR; 2133 break; 2134 } 2135 prev_state = state = STATE_DATA_BUSY; 2136 2137 /* fall through */ 2138 2139 case STATE_DATA_BUSY: 2140 if (!dw_mci_clear_pending_data_complete(host)) { 2141 /* 2142 * If data error interrupt comes but data over 2143 * interrupt doesn't come within the given time. 2144 * in reading data state. 2145 */ 2146 if (host->dir_status == DW_MCI_RECV_STATUS) 2147 dw_mci_set_drto(host); 2148 break; 2149 } 2150 2151 host->data = NULL; 2152 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2153 err = dw_mci_data_complete(host, data); 2154 2155 if (!err) { 2156 if (!data->stop || mrq->sbc) { 2157 if (mrq->sbc && data->stop) 2158 data->stop->error = 0; 2159 dw_mci_request_end(host, mrq); 2160 goto unlock; 2161 } 2162 2163 /* stop command for open-ended transfer*/ 2164 if (data->stop) 2165 send_stop_abort(host, data); 2166 } else { 2167 /* 2168 * If we don't have a command complete now we'll 2169 * never get one since we just reset everything; 2170 * better end the request. 2171 * 2172 * If we do have a command complete we'll fall 2173 * through to the SENDING_STOP command and 2174 * everything will be peachy keen. 2175 */ 2176 if (!test_bit(EVENT_CMD_COMPLETE, 2177 &host->pending_events)) { 2178 host->cmd = NULL; 2179 dw_mci_request_end(host, mrq); 2180 goto unlock; 2181 } 2182 } 2183 2184 /* 2185 * If err has non-zero, 2186 * stop-abort command has been already issued. 2187 */ 2188 prev_state = state = STATE_SENDING_STOP; 2189 2190 /* fall through */ 2191 2192 case STATE_SENDING_STOP: 2193 if (!dw_mci_clear_pending_cmd_complete(host)) 2194 break; 2195 2196 /* CMD error in data command */ 2197 if (mrq->cmd->error && mrq->data) 2198 dw_mci_reset(host); 2199 2200 host->cmd = NULL; 2201 host->data = NULL; 2202 2203 if (!mrq->sbc && mrq->stop) 2204 dw_mci_command_complete(host, mrq->stop); 2205 else 2206 host->cmd_status = 0; 2207 2208 dw_mci_request_end(host, mrq); 2209 goto unlock; 2210 2211 case STATE_DATA_ERROR: 2212 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2213 &host->pending_events)) 2214 break; 2215 2216 state = STATE_DATA_BUSY; 2217 break; 2218 } 2219 } while (state != prev_state); 2220 2221 host->state = state; 2222 unlock: 2223 spin_unlock(&host->lock); 2224 2225 } 2226 2227 /* push final bytes to part_buf, only use during push */ 2228 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2229 { 2230 memcpy((void *)&host->part_buf, buf, cnt); 2231 host->part_buf_count = cnt; 2232 } 2233 2234 /* append bytes to part_buf, only use during push */ 2235 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2236 { 2237 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2238 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2239 host->part_buf_count += cnt; 2240 return cnt; 2241 } 2242 2243 /* pull first bytes from part_buf, only use during pull */ 2244 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2245 { 2246 cnt = min_t(int, cnt, host->part_buf_count); 2247 if (cnt) { 2248 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2249 cnt); 2250 host->part_buf_count -= cnt; 2251 host->part_buf_start += cnt; 2252 } 2253 return cnt; 2254 } 2255 2256 /* pull final bytes from the part_buf, assuming it's just been filled */ 2257 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2258 { 2259 memcpy(buf, &host->part_buf, cnt); 2260 host->part_buf_start = cnt; 2261 host->part_buf_count = (1 << host->data_shift) - cnt; 2262 } 2263 2264 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2265 { 2266 struct mmc_data *data = host->data; 2267 int init_cnt = cnt; 2268 2269 /* try and push anything in the part_buf */ 2270 if (unlikely(host->part_buf_count)) { 2271 int len = dw_mci_push_part_bytes(host, buf, cnt); 2272 2273 buf += len; 2274 cnt -= len; 2275 if (host->part_buf_count == 2) { 2276 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2277 host->part_buf_count = 0; 2278 } 2279 } 2280 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2281 if (unlikely((unsigned long)buf & 0x1)) { 2282 while (cnt >= 2) { 2283 u16 aligned_buf[64]; 2284 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2285 int items = len >> 1; 2286 int i; 2287 /* memcpy from input buffer into aligned buffer */ 2288 memcpy(aligned_buf, buf, len); 2289 buf += len; 2290 cnt -= len; 2291 /* push data from aligned buffer into fifo */ 2292 for (i = 0; i < items; ++i) 2293 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2294 } 2295 } else 2296 #endif 2297 { 2298 u16 *pdata = buf; 2299 2300 for (; cnt >= 2; cnt -= 2) 2301 mci_fifo_writew(host->fifo_reg, *pdata++); 2302 buf = pdata; 2303 } 2304 /* put anything remaining in the part_buf */ 2305 if (cnt) { 2306 dw_mci_set_part_bytes(host, buf, cnt); 2307 /* Push data if we have reached the expected data length */ 2308 if ((data->bytes_xfered + init_cnt) == 2309 (data->blksz * data->blocks)) 2310 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2311 } 2312 } 2313 2314 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2315 { 2316 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2317 if (unlikely((unsigned long)buf & 0x1)) { 2318 while (cnt >= 2) { 2319 /* pull data from fifo into aligned buffer */ 2320 u16 aligned_buf[64]; 2321 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2322 int items = len >> 1; 2323 int i; 2324 2325 for (i = 0; i < items; ++i) 2326 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2327 /* memcpy from aligned buffer into output buffer */ 2328 memcpy(buf, aligned_buf, len); 2329 buf += len; 2330 cnt -= len; 2331 } 2332 } else 2333 #endif 2334 { 2335 u16 *pdata = buf; 2336 2337 for (; cnt >= 2; cnt -= 2) 2338 *pdata++ = mci_fifo_readw(host->fifo_reg); 2339 buf = pdata; 2340 } 2341 if (cnt) { 2342 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2343 dw_mci_pull_final_bytes(host, buf, cnt); 2344 } 2345 } 2346 2347 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2348 { 2349 struct mmc_data *data = host->data; 2350 int init_cnt = cnt; 2351 2352 /* try and push anything in the part_buf */ 2353 if (unlikely(host->part_buf_count)) { 2354 int len = dw_mci_push_part_bytes(host, buf, cnt); 2355 2356 buf += len; 2357 cnt -= len; 2358 if (host->part_buf_count == 4) { 2359 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2360 host->part_buf_count = 0; 2361 } 2362 } 2363 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2364 if (unlikely((unsigned long)buf & 0x3)) { 2365 while (cnt >= 4) { 2366 u32 aligned_buf[32]; 2367 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2368 int items = len >> 2; 2369 int i; 2370 /* memcpy from input buffer into aligned buffer */ 2371 memcpy(aligned_buf, buf, len); 2372 buf += len; 2373 cnt -= len; 2374 /* push data from aligned buffer into fifo */ 2375 for (i = 0; i < items; ++i) 2376 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2377 } 2378 } else 2379 #endif 2380 { 2381 u32 *pdata = buf; 2382 2383 for (; cnt >= 4; cnt -= 4) 2384 mci_fifo_writel(host->fifo_reg, *pdata++); 2385 buf = pdata; 2386 } 2387 /* put anything remaining in the part_buf */ 2388 if (cnt) { 2389 dw_mci_set_part_bytes(host, buf, cnt); 2390 /* Push data if we have reached the expected data length */ 2391 if ((data->bytes_xfered + init_cnt) == 2392 (data->blksz * data->blocks)) 2393 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2394 } 2395 } 2396 2397 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2398 { 2399 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2400 if (unlikely((unsigned long)buf & 0x3)) { 2401 while (cnt >= 4) { 2402 /* pull data from fifo into aligned buffer */ 2403 u32 aligned_buf[32]; 2404 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2405 int items = len >> 2; 2406 int i; 2407 2408 for (i = 0; i < items; ++i) 2409 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2410 /* memcpy from aligned buffer into output buffer */ 2411 memcpy(buf, aligned_buf, len); 2412 buf += len; 2413 cnt -= len; 2414 } 2415 } else 2416 #endif 2417 { 2418 u32 *pdata = buf; 2419 2420 for (; cnt >= 4; cnt -= 4) 2421 *pdata++ = mci_fifo_readl(host->fifo_reg); 2422 buf = pdata; 2423 } 2424 if (cnt) { 2425 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2426 dw_mci_pull_final_bytes(host, buf, cnt); 2427 } 2428 } 2429 2430 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2431 { 2432 struct mmc_data *data = host->data; 2433 int init_cnt = cnt; 2434 2435 /* try and push anything in the part_buf */ 2436 if (unlikely(host->part_buf_count)) { 2437 int len = dw_mci_push_part_bytes(host, buf, cnt); 2438 2439 buf += len; 2440 cnt -= len; 2441 2442 if (host->part_buf_count == 8) { 2443 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2444 host->part_buf_count = 0; 2445 } 2446 } 2447 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2448 if (unlikely((unsigned long)buf & 0x7)) { 2449 while (cnt >= 8) { 2450 u64 aligned_buf[16]; 2451 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2452 int items = len >> 3; 2453 int i; 2454 /* memcpy from input buffer into aligned buffer */ 2455 memcpy(aligned_buf, buf, len); 2456 buf += len; 2457 cnt -= len; 2458 /* push data from aligned buffer into fifo */ 2459 for (i = 0; i < items; ++i) 2460 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2461 } 2462 } else 2463 #endif 2464 { 2465 u64 *pdata = buf; 2466 2467 for (; cnt >= 8; cnt -= 8) 2468 mci_fifo_writeq(host->fifo_reg, *pdata++); 2469 buf = pdata; 2470 } 2471 /* put anything remaining in the part_buf */ 2472 if (cnt) { 2473 dw_mci_set_part_bytes(host, buf, cnt); 2474 /* Push data if we have reached the expected data length */ 2475 if ((data->bytes_xfered + init_cnt) == 2476 (data->blksz * data->blocks)) 2477 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2478 } 2479 } 2480 2481 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2482 { 2483 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2484 if (unlikely((unsigned long)buf & 0x7)) { 2485 while (cnt >= 8) { 2486 /* pull data from fifo into aligned buffer */ 2487 u64 aligned_buf[16]; 2488 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2489 int items = len >> 3; 2490 int i; 2491 2492 for (i = 0; i < items; ++i) 2493 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2494 2495 /* memcpy from aligned buffer into output buffer */ 2496 memcpy(buf, aligned_buf, len); 2497 buf += len; 2498 cnt -= len; 2499 } 2500 } else 2501 #endif 2502 { 2503 u64 *pdata = buf; 2504 2505 for (; cnt >= 8; cnt -= 8) 2506 *pdata++ = mci_fifo_readq(host->fifo_reg); 2507 buf = pdata; 2508 } 2509 if (cnt) { 2510 host->part_buf = mci_fifo_readq(host->fifo_reg); 2511 dw_mci_pull_final_bytes(host, buf, cnt); 2512 } 2513 } 2514 2515 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2516 { 2517 int len; 2518 2519 /* get remaining partial bytes */ 2520 len = dw_mci_pull_part_bytes(host, buf, cnt); 2521 if (unlikely(len == cnt)) 2522 return; 2523 buf += len; 2524 cnt -= len; 2525 2526 /* get the rest of the data */ 2527 host->pull_data(host, buf, cnt); 2528 } 2529 2530 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2531 { 2532 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2533 void *buf; 2534 unsigned int offset; 2535 struct mmc_data *data = host->data; 2536 int shift = host->data_shift; 2537 u32 status; 2538 unsigned int len; 2539 unsigned int remain, fcnt; 2540 2541 do { 2542 if (!sg_miter_next(sg_miter)) 2543 goto done; 2544 2545 host->sg = sg_miter->piter.sg; 2546 buf = sg_miter->addr; 2547 remain = sg_miter->length; 2548 offset = 0; 2549 2550 do { 2551 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2552 << shift) + host->part_buf_count; 2553 len = min(remain, fcnt); 2554 if (!len) 2555 break; 2556 dw_mci_pull_data(host, (void *)(buf + offset), len); 2557 data->bytes_xfered += len; 2558 offset += len; 2559 remain -= len; 2560 } while (remain); 2561 2562 sg_miter->consumed = offset; 2563 status = mci_readl(host, MINTSTS); 2564 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2565 /* if the RXDR is ready read again */ 2566 } while ((status & SDMMC_INT_RXDR) || 2567 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2568 2569 if (!remain) { 2570 if (!sg_miter_next(sg_miter)) 2571 goto done; 2572 sg_miter->consumed = 0; 2573 } 2574 sg_miter_stop(sg_miter); 2575 return; 2576 2577 done: 2578 sg_miter_stop(sg_miter); 2579 host->sg = NULL; 2580 smp_wmb(); /* drain writebuffer */ 2581 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2582 } 2583 2584 static void dw_mci_write_data_pio(struct dw_mci *host) 2585 { 2586 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2587 void *buf; 2588 unsigned int offset; 2589 struct mmc_data *data = host->data; 2590 int shift = host->data_shift; 2591 u32 status; 2592 unsigned int len; 2593 unsigned int fifo_depth = host->fifo_depth; 2594 unsigned int remain, fcnt; 2595 2596 do { 2597 if (!sg_miter_next(sg_miter)) 2598 goto done; 2599 2600 host->sg = sg_miter->piter.sg; 2601 buf = sg_miter->addr; 2602 remain = sg_miter->length; 2603 offset = 0; 2604 2605 do { 2606 fcnt = ((fifo_depth - 2607 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2608 << shift) - host->part_buf_count; 2609 len = min(remain, fcnt); 2610 if (!len) 2611 break; 2612 host->push_data(host, (void *)(buf + offset), len); 2613 data->bytes_xfered += len; 2614 offset += len; 2615 remain -= len; 2616 } while (remain); 2617 2618 sg_miter->consumed = offset; 2619 status = mci_readl(host, MINTSTS); 2620 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2621 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2622 2623 if (!remain) { 2624 if (!sg_miter_next(sg_miter)) 2625 goto done; 2626 sg_miter->consumed = 0; 2627 } 2628 sg_miter_stop(sg_miter); 2629 return; 2630 2631 done: 2632 sg_miter_stop(sg_miter); 2633 host->sg = NULL; 2634 smp_wmb(); /* drain writebuffer */ 2635 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2636 } 2637 2638 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2639 { 2640 del_timer(&host->cto_timer); 2641 2642 if (!host->cmd_status) 2643 host->cmd_status = status; 2644 2645 smp_wmb(); /* drain writebuffer */ 2646 2647 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2648 tasklet_schedule(&host->tasklet); 2649 } 2650 2651 static void dw_mci_handle_cd(struct dw_mci *host) 2652 { 2653 struct dw_mci_slot *slot = host->slot; 2654 2655 if (slot->mmc->ops->card_event) 2656 slot->mmc->ops->card_event(slot->mmc); 2657 mmc_detect_change(slot->mmc, 2658 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2659 } 2660 2661 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2662 { 2663 struct dw_mci *host = dev_id; 2664 u32 pending; 2665 struct dw_mci_slot *slot = host->slot; 2666 unsigned long irqflags; 2667 2668 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2669 2670 if (pending) { 2671 /* Check volt switch first, since it can look like an error */ 2672 if ((host->state == STATE_SENDING_CMD11) && 2673 (pending & SDMMC_INT_VOLT_SWITCH)) { 2674 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2675 pending &= ~SDMMC_INT_VOLT_SWITCH; 2676 2677 /* 2678 * Hold the lock; we know cmd11_timer can't be kicked 2679 * off after the lock is released, so safe to delete. 2680 */ 2681 spin_lock_irqsave(&host->irq_lock, irqflags); 2682 dw_mci_cmd_interrupt(host, pending); 2683 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2684 2685 del_timer(&host->cmd11_timer); 2686 } 2687 2688 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2689 spin_lock_irqsave(&host->irq_lock, irqflags); 2690 2691 del_timer(&host->cto_timer); 2692 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2693 host->cmd_status = pending; 2694 smp_wmb(); /* drain writebuffer */ 2695 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2696 2697 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2698 } 2699 2700 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2701 /* if there is an error report DATA_ERROR */ 2702 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2703 host->data_status = pending; 2704 smp_wmb(); /* drain writebuffer */ 2705 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2706 tasklet_schedule(&host->tasklet); 2707 } 2708 2709 if (pending & SDMMC_INT_DATA_OVER) { 2710 spin_lock_irqsave(&host->irq_lock, irqflags); 2711 2712 del_timer(&host->dto_timer); 2713 2714 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2715 if (!host->data_status) 2716 host->data_status = pending; 2717 smp_wmb(); /* drain writebuffer */ 2718 if (host->dir_status == DW_MCI_RECV_STATUS) { 2719 if (host->sg != NULL) 2720 dw_mci_read_data_pio(host, true); 2721 } 2722 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2723 tasklet_schedule(&host->tasklet); 2724 2725 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2726 } 2727 2728 if (pending & SDMMC_INT_RXDR) { 2729 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2730 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2731 dw_mci_read_data_pio(host, false); 2732 } 2733 2734 if (pending & SDMMC_INT_TXDR) { 2735 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2736 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2737 dw_mci_write_data_pio(host); 2738 } 2739 2740 if (pending & SDMMC_INT_CMD_DONE) { 2741 spin_lock_irqsave(&host->irq_lock, irqflags); 2742 2743 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2744 dw_mci_cmd_interrupt(host, pending); 2745 2746 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2747 } 2748 2749 if (pending & SDMMC_INT_CD) { 2750 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2751 dw_mci_handle_cd(host); 2752 } 2753 2754 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2755 mci_writel(host, RINTSTS, 2756 SDMMC_INT_SDIO(slot->sdio_id)); 2757 __dw_mci_enable_sdio_irq(slot, 0); 2758 sdio_signal_irq(slot->mmc); 2759 } 2760 2761 } 2762 2763 if (host->use_dma != TRANS_MODE_IDMAC) 2764 return IRQ_HANDLED; 2765 2766 /* Handle IDMA interrupts */ 2767 if (host->dma_64bit_address == 1) { 2768 pending = mci_readl(host, IDSTS64); 2769 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2770 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2771 SDMMC_IDMAC_INT_RI); 2772 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2773 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2774 host->dma_ops->complete((void *)host); 2775 } 2776 } else { 2777 pending = mci_readl(host, IDSTS); 2778 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2779 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2780 SDMMC_IDMAC_INT_RI); 2781 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2782 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2783 host->dma_ops->complete((void *)host); 2784 } 2785 } 2786 2787 return IRQ_HANDLED; 2788 } 2789 2790 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) 2791 { 2792 struct dw_mci *host = slot->host; 2793 const struct dw_mci_drv_data *drv_data = host->drv_data; 2794 struct mmc_host *mmc = slot->mmc; 2795 int ctrl_id; 2796 2797 if (host->pdata->caps) 2798 mmc->caps = host->pdata->caps; 2799 2800 /* 2801 * Support MMC_CAP_ERASE by default. 2802 * It needs to use trim/discard/erase commands. 2803 */ 2804 mmc->caps |= MMC_CAP_ERASE; 2805 2806 if (host->pdata->pm_caps) 2807 mmc->pm_caps = host->pdata->pm_caps; 2808 2809 if (host->dev->of_node) { 2810 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2811 if (ctrl_id < 0) 2812 ctrl_id = 0; 2813 } else { 2814 ctrl_id = to_platform_device(host->dev)->id; 2815 } 2816 2817 if (drv_data && drv_data->caps) { 2818 if (ctrl_id >= drv_data->num_caps) { 2819 dev_err(host->dev, "invalid controller id %d\n", 2820 ctrl_id); 2821 return -EINVAL; 2822 } 2823 mmc->caps |= drv_data->caps[ctrl_id]; 2824 } 2825 2826 if (host->pdata->caps2) 2827 mmc->caps2 = host->pdata->caps2; 2828 2829 /* Process SDIO IRQs through the sdio_irq_work. */ 2830 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2831 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2832 2833 return 0; 2834 } 2835 2836 static int dw_mci_init_slot(struct dw_mci *host) 2837 { 2838 struct mmc_host *mmc; 2839 struct dw_mci_slot *slot; 2840 int ret; 2841 u32 freq[2]; 2842 2843 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2844 if (!mmc) 2845 return -ENOMEM; 2846 2847 slot = mmc_priv(mmc); 2848 slot->id = 0; 2849 slot->sdio_id = host->sdio_id0 + slot->id; 2850 slot->mmc = mmc; 2851 slot->host = host; 2852 host->slot = slot; 2853 2854 mmc->ops = &dw_mci_ops; 2855 if (device_property_read_u32_array(host->dev, "clock-freq-min-max", 2856 freq, 2)) { 2857 mmc->f_min = DW_MCI_FREQ_MIN; 2858 mmc->f_max = DW_MCI_FREQ_MAX; 2859 } else { 2860 dev_info(host->dev, 2861 "'clock-freq-min-max' property was deprecated.\n"); 2862 mmc->f_min = freq[0]; 2863 mmc->f_max = freq[1]; 2864 } 2865 2866 /*if there are external regulators, get them*/ 2867 ret = mmc_regulator_get_supply(mmc); 2868 if (ret) 2869 goto err_host_allocated; 2870 2871 if (!mmc->ocr_avail) 2872 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2873 2874 ret = mmc_of_parse(mmc); 2875 if (ret) 2876 goto err_host_allocated; 2877 2878 ret = dw_mci_init_slot_caps(slot); 2879 if (ret) 2880 goto err_host_allocated; 2881 2882 /* Useful defaults if platform data is unset. */ 2883 if (host->use_dma == TRANS_MODE_IDMAC) { 2884 mmc->max_segs = host->ring_size; 2885 mmc->max_blk_size = 65535; 2886 mmc->max_seg_size = 0x1000; 2887 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2888 mmc->max_blk_count = mmc->max_req_size / 512; 2889 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2890 mmc->max_segs = 64; 2891 mmc->max_blk_size = 65535; 2892 mmc->max_blk_count = 65535; 2893 mmc->max_req_size = 2894 mmc->max_blk_size * mmc->max_blk_count; 2895 mmc->max_seg_size = mmc->max_req_size; 2896 } else { 2897 /* TRANS_MODE_PIO */ 2898 mmc->max_segs = 64; 2899 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2900 mmc->max_blk_count = 512; 2901 mmc->max_req_size = mmc->max_blk_size * 2902 mmc->max_blk_count; 2903 mmc->max_seg_size = mmc->max_req_size; 2904 } 2905 2906 dw_mci_get_cd(mmc); 2907 2908 ret = mmc_add_host(mmc); 2909 if (ret) 2910 goto err_host_allocated; 2911 2912 #if defined(CONFIG_DEBUG_FS) 2913 dw_mci_init_debugfs(slot); 2914 #endif 2915 2916 return 0; 2917 2918 err_host_allocated: 2919 mmc_free_host(mmc); 2920 return ret; 2921 } 2922 2923 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2924 { 2925 /* Debugfs stuff is cleaned up by mmc core */ 2926 mmc_remove_host(slot->mmc); 2927 slot->host->slot = NULL; 2928 mmc_free_host(slot->mmc); 2929 } 2930 2931 static void dw_mci_init_dma(struct dw_mci *host) 2932 { 2933 int addr_config; 2934 struct device *dev = host->dev; 2935 2936 /* 2937 * Check tansfer mode from HCON[17:16] 2938 * Clear the ambiguous description of dw_mmc databook: 2939 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2940 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2941 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2942 * 2b'11: Non DW DMA Interface -> pio only 2943 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2944 * simpler request/acknowledge handshake mechanism and both of them 2945 * are regarded as external dma master for dw_mmc. 2946 */ 2947 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2948 if (host->use_dma == DMA_INTERFACE_IDMA) { 2949 host->use_dma = TRANS_MODE_IDMAC; 2950 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2951 host->use_dma == DMA_INTERFACE_GDMA) { 2952 host->use_dma = TRANS_MODE_EDMAC; 2953 } else { 2954 goto no_dma; 2955 } 2956 2957 /* Determine which DMA interface to use */ 2958 if (host->use_dma == TRANS_MODE_IDMAC) { 2959 /* 2960 * Check ADDR_CONFIG bit in HCON to find 2961 * IDMAC address bus width 2962 */ 2963 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2964 2965 if (addr_config == 1) { 2966 /* host supports IDMAC in 64-bit address mode */ 2967 host->dma_64bit_address = 1; 2968 dev_info(host->dev, 2969 "IDMAC supports 64-bit address mode.\n"); 2970 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2971 dma_set_coherent_mask(host->dev, 2972 DMA_BIT_MASK(64)); 2973 } else { 2974 /* host supports IDMAC in 32-bit address mode */ 2975 host->dma_64bit_address = 0; 2976 dev_info(host->dev, 2977 "IDMAC supports 32-bit address mode.\n"); 2978 } 2979 2980 /* Alloc memory for sg translation */ 2981 host->sg_cpu = dmam_alloc_coherent(host->dev, 2982 DESC_RING_BUF_SZ, 2983 &host->sg_dma, GFP_KERNEL); 2984 if (!host->sg_cpu) { 2985 dev_err(host->dev, 2986 "%s: could not alloc DMA memory\n", 2987 __func__); 2988 goto no_dma; 2989 } 2990 2991 host->dma_ops = &dw_mci_idmac_ops; 2992 dev_info(host->dev, "Using internal DMA controller.\n"); 2993 } else { 2994 /* TRANS_MODE_EDMAC: check dma bindings again */ 2995 if ((device_property_read_string_array(dev, "dma-names", 2996 NULL, 0) < 0) || 2997 !device_property_present(dev, "dmas")) { 2998 goto no_dma; 2999 } 3000 host->dma_ops = &dw_mci_edmac_ops; 3001 dev_info(host->dev, "Using external DMA controller.\n"); 3002 } 3003 3004 if (host->dma_ops->init && host->dma_ops->start && 3005 host->dma_ops->stop && host->dma_ops->cleanup) { 3006 if (host->dma_ops->init(host)) { 3007 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 3008 __func__); 3009 goto no_dma; 3010 } 3011 } else { 3012 dev_err(host->dev, "DMA initialization not found.\n"); 3013 goto no_dma; 3014 } 3015 3016 return; 3017 3018 no_dma: 3019 dev_info(host->dev, "Using PIO mode.\n"); 3020 host->use_dma = TRANS_MODE_PIO; 3021 } 3022 3023 static void dw_mci_cmd11_timer(struct timer_list *t) 3024 { 3025 struct dw_mci *host = from_timer(host, t, cmd11_timer); 3026 3027 if (host->state != STATE_SENDING_CMD11) { 3028 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 3029 return; 3030 } 3031 3032 host->cmd_status = SDMMC_INT_RTO; 3033 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3034 tasklet_schedule(&host->tasklet); 3035 } 3036 3037 static void dw_mci_cto_timer(struct timer_list *t) 3038 { 3039 struct dw_mci *host = from_timer(host, t, cto_timer); 3040 unsigned long irqflags; 3041 u32 pending; 3042 3043 spin_lock_irqsave(&host->irq_lock, irqflags); 3044 3045 /* 3046 * If somehow we have very bad interrupt latency it's remotely possible 3047 * that the timer could fire while the interrupt is still pending or 3048 * while the interrupt is midway through running. Let's be paranoid 3049 * and detect those two cases. Note that this is paranoia is somewhat 3050 * justified because in this function we don't actually cancel the 3051 * pending command in the controller--we just assume it will never come. 3052 */ 3053 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3054 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 3055 /* The interrupt should fire; no need to act but we can warn */ 3056 dev_warn(host->dev, "Unexpected interrupt latency\n"); 3057 goto exit; 3058 } 3059 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 3060 /* Presumably interrupt handler couldn't delete the timer */ 3061 dev_warn(host->dev, "CTO timeout when already completed\n"); 3062 goto exit; 3063 } 3064 3065 /* 3066 * Continued paranoia to make sure we're in the state we expect. 3067 * This paranoia isn't really justified but it seems good to be safe. 3068 */ 3069 switch (host->state) { 3070 case STATE_SENDING_CMD11: 3071 case STATE_SENDING_CMD: 3072 case STATE_SENDING_STOP: 3073 /* 3074 * If CMD_DONE interrupt does NOT come in sending command 3075 * state, we should notify the driver to terminate current 3076 * transfer and report a command timeout to the core. 3077 */ 3078 host->cmd_status = SDMMC_INT_RTO; 3079 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3080 tasklet_schedule(&host->tasklet); 3081 break; 3082 default: 3083 dev_warn(host->dev, "Unexpected command timeout, state %d\n", 3084 host->state); 3085 break; 3086 } 3087 3088 exit: 3089 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3090 } 3091 3092 static void dw_mci_dto_timer(struct timer_list *t) 3093 { 3094 struct dw_mci *host = from_timer(host, t, dto_timer); 3095 unsigned long irqflags; 3096 u32 pending; 3097 3098 spin_lock_irqsave(&host->irq_lock, irqflags); 3099 3100 /* 3101 * The DTO timer is much longer than the CTO timer, so it's even less 3102 * likely that we'll these cases, but it pays to be paranoid. 3103 */ 3104 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3105 if (pending & SDMMC_INT_DATA_OVER) { 3106 /* The interrupt should fire; no need to act but we can warn */ 3107 dev_warn(host->dev, "Unexpected data interrupt latency\n"); 3108 goto exit; 3109 } 3110 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 3111 /* Presumably interrupt handler couldn't delete the timer */ 3112 dev_warn(host->dev, "DTO timeout when already completed\n"); 3113 goto exit; 3114 } 3115 3116 /* 3117 * Continued paranoia to make sure we're in the state we expect. 3118 * This paranoia isn't really justified but it seems good to be safe. 3119 */ 3120 switch (host->state) { 3121 case STATE_SENDING_DATA: 3122 case STATE_DATA_BUSY: 3123 /* 3124 * If DTO interrupt does NOT come in sending data state, 3125 * we should notify the driver to terminate current transfer 3126 * and report a data timeout to the core. 3127 */ 3128 host->data_status = SDMMC_INT_DRTO; 3129 set_bit(EVENT_DATA_ERROR, &host->pending_events); 3130 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 3131 tasklet_schedule(&host->tasklet); 3132 break; 3133 default: 3134 dev_warn(host->dev, "Unexpected data timeout, state %d\n", 3135 host->state); 3136 break; 3137 } 3138 3139 exit: 3140 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3141 } 3142 3143 #ifdef CONFIG_OF 3144 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3145 { 3146 struct dw_mci_board *pdata; 3147 struct device *dev = host->dev; 3148 const struct dw_mci_drv_data *drv_data = host->drv_data; 3149 int ret; 3150 u32 clock_frequency; 3151 3152 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3153 if (!pdata) 3154 return ERR_PTR(-ENOMEM); 3155 3156 /* find reset controller when exist */ 3157 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3158 if (IS_ERR(pdata->rstc)) { 3159 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3160 return ERR_PTR(-EPROBE_DEFER); 3161 } 3162 3163 /* find out number of slots supported */ 3164 if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots)) 3165 dev_info(dev, "'num-slots' was deprecated.\n"); 3166 3167 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 3168 dev_info(dev, 3169 "fifo-depth property not found, using value of FIFOTH register as default\n"); 3170 3171 device_property_read_u32(dev, "card-detect-delay", 3172 &pdata->detect_delay_ms); 3173 3174 device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3175 3176 if (device_property_present(dev, "fifo-watermark-aligned")) 3177 host->wm_aligned = true; 3178 3179 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 3180 pdata->bus_hz = clock_frequency; 3181 3182 if (drv_data && drv_data->parse_dt) { 3183 ret = drv_data->parse_dt(host); 3184 if (ret) 3185 return ERR_PTR(ret); 3186 } 3187 3188 return pdata; 3189 } 3190 3191 #else /* CONFIG_OF */ 3192 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3193 { 3194 return ERR_PTR(-EINVAL); 3195 } 3196 #endif /* CONFIG_OF */ 3197 3198 static void dw_mci_enable_cd(struct dw_mci *host) 3199 { 3200 unsigned long irqflags; 3201 u32 temp; 3202 3203 /* 3204 * No need for CD if all slots have a non-error GPIO 3205 * as well as broken card detection is found. 3206 */ 3207 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3208 return; 3209 3210 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3211 spin_lock_irqsave(&host->irq_lock, irqflags); 3212 temp = mci_readl(host, INTMASK); 3213 temp |= SDMMC_INT_CD; 3214 mci_writel(host, INTMASK, temp); 3215 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3216 } 3217 } 3218 3219 int dw_mci_probe(struct dw_mci *host) 3220 { 3221 const struct dw_mci_drv_data *drv_data = host->drv_data; 3222 int width, i, ret = 0; 3223 u32 fifo_size; 3224 3225 if (!host->pdata) { 3226 host->pdata = dw_mci_parse_dt(host); 3227 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3228 return -EPROBE_DEFER; 3229 } else if (IS_ERR(host->pdata)) { 3230 dev_err(host->dev, "platform data not available\n"); 3231 return -EINVAL; 3232 } 3233 } 3234 3235 host->biu_clk = devm_clk_get(host->dev, "biu"); 3236 if (IS_ERR(host->biu_clk)) { 3237 dev_dbg(host->dev, "biu clock not available\n"); 3238 } else { 3239 ret = clk_prepare_enable(host->biu_clk); 3240 if (ret) { 3241 dev_err(host->dev, "failed to enable biu clock\n"); 3242 return ret; 3243 } 3244 } 3245 3246 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3247 if (IS_ERR(host->ciu_clk)) { 3248 dev_dbg(host->dev, "ciu clock not available\n"); 3249 host->bus_hz = host->pdata->bus_hz; 3250 } else { 3251 ret = clk_prepare_enable(host->ciu_clk); 3252 if (ret) { 3253 dev_err(host->dev, "failed to enable ciu clock\n"); 3254 goto err_clk_biu; 3255 } 3256 3257 if (host->pdata->bus_hz) { 3258 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3259 if (ret) 3260 dev_warn(host->dev, 3261 "Unable to set bus rate to %uHz\n", 3262 host->pdata->bus_hz); 3263 } 3264 host->bus_hz = clk_get_rate(host->ciu_clk); 3265 } 3266 3267 if (!host->bus_hz) { 3268 dev_err(host->dev, 3269 "Platform data must supply bus speed\n"); 3270 ret = -ENODEV; 3271 goto err_clk_ciu; 3272 } 3273 3274 if (!IS_ERR(host->pdata->rstc)) { 3275 reset_control_assert(host->pdata->rstc); 3276 usleep_range(10, 50); 3277 reset_control_deassert(host->pdata->rstc); 3278 } 3279 3280 if (drv_data && drv_data->init) { 3281 ret = drv_data->init(host); 3282 if (ret) { 3283 dev_err(host->dev, 3284 "implementation specific init failed\n"); 3285 goto err_clk_ciu; 3286 } 3287 } 3288 3289 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 3290 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 3291 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 3292 3293 spin_lock_init(&host->lock); 3294 spin_lock_init(&host->irq_lock); 3295 INIT_LIST_HEAD(&host->queue); 3296 3297 /* 3298 * Get the host data width - this assumes that HCON has been set with 3299 * the correct values. 3300 */ 3301 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3302 if (!i) { 3303 host->push_data = dw_mci_push_data16; 3304 host->pull_data = dw_mci_pull_data16; 3305 width = 16; 3306 host->data_shift = 1; 3307 } else if (i == 2) { 3308 host->push_data = dw_mci_push_data64; 3309 host->pull_data = dw_mci_pull_data64; 3310 width = 64; 3311 host->data_shift = 3; 3312 } else { 3313 /* Check for a reserved value, and warn if it is */ 3314 WARN((i != 1), 3315 "HCON reports a reserved host data width!\n" 3316 "Defaulting to 32-bit access.\n"); 3317 host->push_data = dw_mci_push_data32; 3318 host->pull_data = dw_mci_pull_data32; 3319 width = 32; 3320 host->data_shift = 2; 3321 } 3322 3323 /* Reset all blocks */ 3324 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3325 ret = -ENODEV; 3326 goto err_clk_ciu; 3327 } 3328 3329 host->dma_ops = host->pdata->dma_ops; 3330 dw_mci_init_dma(host); 3331 3332 /* Clear the interrupts for the host controller */ 3333 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3334 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3335 3336 /* Put in max timeout */ 3337 mci_writel(host, TMOUT, 0xFFFFFFFF); 3338 3339 /* 3340 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3341 * Tx Mark = fifo_size / 2 DMA Size = 8 3342 */ 3343 if (!host->pdata->fifo_depth) { 3344 /* 3345 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3346 * have been overwritten by the bootloader, just like we're 3347 * about to do, so if you know the value for your hardware, you 3348 * should put it in the platform data. 3349 */ 3350 fifo_size = mci_readl(host, FIFOTH); 3351 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3352 } else { 3353 fifo_size = host->pdata->fifo_depth; 3354 } 3355 host->fifo_depth = fifo_size; 3356 host->fifoth_val = 3357 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3358 mci_writel(host, FIFOTH, host->fifoth_val); 3359 3360 /* disable clock to CIU */ 3361 mci_writel(host, CLKENA, 0); 3362 mci_writel(host, CLKSRC, 0); 3363 3364 /* 3365 * In 2.40a spec, Data offset is changed. 3366 * Need to check the version-id and set data-offset for DATA register. 3367 */ 3368 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3369 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3370 3371 if (host->data_addr_override) 3372 host->fifo_reg = host->regs + host->data_addr_override; 3373 else if (host->verid < DW_MMC_240A) 3374 host->fifo_reg = host->regs + DATA_OFFSET; 3375 else 3376 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3377 3378 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3379 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3380 host->irq_flags, "dw-mci", host); 3381 if (ret) 3382 goto err_dmaunmap; 3383 3384 /* 3385 * Enable interrupts for command done, data over, data empty, 3386 * receive ready and error such as transmit, receive timeout, crc error 3387 */ 3388 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3389 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3390 DW_MCI_ERROR_FLAGS); 3391 /* Enable mci interrupt */ 3392 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3393 3394 dev_info(host->dev, 3395 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3396 host->irq, width, fifo_size); 3397 3398 /* We need at least one slot to succeed */ 3399 ret = dw_mci_init_slot(host); 3400 if (ret) { 3401 dev_dbg(host->dev, "slot %d init failed\n", i); 3402 goto err_dmaunmap; 3403 } 3404 3405 /* Now that slots are all setup, we can enable card detect */ 3406 dw_mci_enable_cd(host); 3407 3408 return 0; 3409 3410 err_dmaunmap: 3411 if (host->use_dma && host->dma_ops->exit) 3412 host->dma_ops->exit(host); 3413 3414 if (!IS_ERR(host->pdata->rstc)) 3415 reset_control_assert(host->pdata->rstc); 3416 3417 err_clk_ciu: 3418 clk_disable_unprepare(host->ciu_clk); 3419 3420 err_clk_biu: 3421 clk_disable_unprepare(host->biu_clk); 3422 3423 return ret; 3424 } 3425 EXPORT_SYMBOL(dw_mci_probe); 3426 3427 void dw_mci_remove(struct dw_mci *host) 3428 { 3429 dev_dbg(host->dev, "remove slot\n"); 3430 if (host->slot) 3431 dw_mci_cleanup_slot(host->slot); 3432 3433 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3434 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3435 3436 /* disable clock to CIU */ 3437 mci_writel(host, CLKENA, 0); 3438 mci_writel(host, CLKSRC, 0); 3439 3440 if (host->use_dma && host->dma_ops->exit) 3441 host->dma_ops->exit(host); 3442 3443 if (!IS_ERR(host->pdata->rstc)) 3444 reset_control_assert(host->pdata->rstc); 3445 3446 clk_disable_unprepare(host->ciu_clk); 3447 clk_disable_unprepare(host->biu_clk); 3448 } 3449 EXPORT_SYMBOL(dw_mci_remove); 3450 3451 3452 3453 #ifdef CONFIG_PM 3454 int dw_mci_runtime_suspend(struct device *dev) 3455 { 3456 struct dw_mci *host = dev_get_drvdata(dev); 3457 3458 if (host->use_dma && host->dma_ops->exit) 3459 host->dma_ops->exit(host); 3460 3461 clk_disable_unprepare(host->ciu_clk); 3462 3463 if (host->slot && 3464 (mmc_can_gpio_cd(host->slot->mmc) || 3465 !mmc_card_is_removable(host->slot->mmc))) 3466 clk_disable_unprepare(host->biu_clk); 3467 3468 return 0; 3469 } 3470 EXPORT_SYMBOL(dw_mci_runtime_suspend); 3471 3472 int dw_mci_runtime_resume(struct device *dev) 3473 { 3474 int ret = 0; 3475 struct dw_mci *host = dev_get_drvdata(dev); 3476 3477 if (host->slot && 3478 (mmc_can_gpio_cd(host->slot->mmc) || 3479 !mmc_card_is_removable(host->slot->mmc))) { 3480 ret = clk_prepare_enable(host->biu_clk); 3481 if (ret) 3482 return ret; 3483 } 3484 3485 ret = clk_prepare_enable(host->ciu_clk); 3486 if (ret) 3487 goto err; 3488 3489 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3490 clk_disable_unprepare(host->ciu_clk); 3491 ret = -ENODEV; 3492 goto err; 3493 } 3494 3495 if (host->use_dma && host->dma_ops->init) 3496 host->dma_ops->init(host); 3497 3498 /* 3499 * Restore the initial value at FIFOTH register 3500 * And Invalidate the prev_blksz with zero 3501 */ 3502 mci_writel(host, FIFOTH, host->fifoth_val); 3503 host->prev_blksz = 0; 3504 3505 /* Put in max timeout */ 3506 mci_writel(host, TMOUT, 0xFFFFFFFF); 3507 3508 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3509 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3510 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3511 DW_MCI_ERROR_FLAGS); 3512 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3513 3514 3515 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3516 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3517 3518 /* Force setup bus to guarantee available clock output */ 3519 dw_mci_setup_bus(host->slot, true); 3520 3521 /* Now that slots are all setup, we can enable card detect */ 3522 dw_mci_enable_cd(host); 3523 3524 return 0; 3525 3526 err: 3527 if (host->slot && 3528 (mmc_can_gpio_cd(host->slot->mmc) || 3529 !mmc_card_is_removable(host->slot->mmc))) 3530 clk_disable_unprepare(host->biu_clk); 3531 3532 return ret; 3533 } 3534 EXPORT_SYMBOL(dw_mci_runtime_resume); 3535 #endif /* CONFIG_PM */ 3536 3537 static int __init dw_mci_init(void) 3538 { 3539 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3540 return 0; 3541 } 3542 3543 static void __exit dw_mci_exit(void) 3544 { 3545 } 3546 3547 module_init(dw_mci_init); 3548 module_exit(dw_mci_exit); 3549 3550 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3551 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3552 MODULE_AUTHOR("Imagination Technologies Ltd"); 3553 MODULE_LICENSE("GPL v2"); 3554