1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47f95f3850SWill Newton SDMMC_INT_EBE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49f95f3850SWill Newton SDMMC_INT_RESP_ERR) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51f95f3850SWill Newton DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 6569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6669d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6769d99fdcSPrabu Thangamuthu 6869d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6969d99fdcSPrabu Thangamuthu 7069d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7169d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 7269d99fdcSPrabu Thangamuthu ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff)) 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7769d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8069d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu }; 8269d99fdcSPrabu Thangamuthu 83f95f3850SWill Newton struct idmac_desc { 84f95f3850SWill Newton u32 des0; /* Control Descriptor */ 85f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 86f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 87f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 88f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 89f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 90f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 91f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 92f95f3850SWill Newton 93f95f3850SWill Newton u32 des1; /* Buffer sizes */ 94f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 959b7bbe10SShashidhar Hiremath ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 96f95f3850SWill Newton 97f95f3850SWill Newton u32 des2; /* buffer 1 physical address */ 98f95f3850SWill Newton 99f95f3850SWill Newton u32 des3; /* buffer 2 physical address */ 100f95f3850SWill Newton }; 101f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 102f95f3850SWill Newton 1033a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 104536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 1050bdbd0e8SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc); 10631bff450SSeungwon Jeon 107f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 108f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 109f95f3850SWill Newton { 110f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 111f95f3850SWill Newton struct mmc_request *mrq; 112f95f3850SWill Newton struct mmc_command *cmd; 113f95f3850SWill Newton struct mmc_command *stop; 114f95f3850SWill Newton struct mmc_data *data; 115f95f3850SWill Newton 116f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 117f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 118f95f3850SWill Newton mrq = slot->mrq; 119f95f3850SWill Newton 120f95f3850SWill Newton if (mrq) { 121f95f3850SWill Newton cmd = mrq->cmd; 122f95f3850SWill Newton data = mrq->data; 123f95f3850SWill Newton stop = mrq->stop; 124f95f3850SWill Newton 125f95f3850SWill Newton if (cmd) 126f95f3850SWill Newton seq_printf(s, 127f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 128f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 129f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 130f95f3850SWill Newton cmd->resp[2], cmd->error); 131f95f3850SWill Newton if (data) 132f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 133f95f3850SWill Newton data->bytes_xfered, data->blocks, 134f95f3850SWill Newton data->blksz, data->flags, data->error); 135f95f3850SWill Newton if (stop) 136f95f3850SWill Newton seq_printf(s, 137f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 138f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 139f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 140f95f3850SWill Newton stop->resp[2], stop->error); 141f95f3850SWill Newton } 142f95f3850SWill Newton 143f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 144f95f3850SWill Newton 145f95f3850SWill Newton return 0; 146f95f3850SWill Newton } 147f95f3850SWill Newton 148f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 149f95f3850SWill Newton { 150f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 151f95f3850SWill Newton } 152f95f3850SWill Newton 153f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 154f95f3850SWill Newton .owner = THIS_MODULE, 155f95f3850SWill Newton .open = dw_mci_req_open, 156f95f3850SWill Newton .read = seq_read, 157f95f3850SWill Newton .llseek = seq_lseek, 158f95f3850SWill Newton .release = single_release, 159f95f3850SWill Newton }; 160f95f3850SWill Newton 161f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 162f95f3850SWill Newton { 163f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 164f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 165f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 166f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 167f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 168f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 169f95f3850SWill Newton 170f95f3850SWill Newton return 0; 171f95f3850SWill Newton } 172f95f3850SWill Newton 173f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 174f95f3850SWill Newton { 175f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 176f95f3850SWill Newton } 177f95f3850SWill Newton 178f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 179f95f3850SWill Newton .owner = THIS_MODULE, 180f95f3850SWill Newton .open = dw_mci_regs_open, 181f95f3850SWill Newton .read = seq_read, 182f95f3850SWill Newton .llseek = seq_lseek, 183f95f3850SWill Newton .release = single_release, 184f95f3850SWill Newton }; 185f95f3850SWill Newton 186f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 187f95f3850SWill Newton { 188f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 189f95f3850SWill Newton struct dw_mci *host = slot->host; 190f95f3850SWill Newton struct dentry *root; 191f95f3850SWill Newton struct dentry *node; 192f95f3850SWill Newton 193f95f3850SWill Newton root = mmc->debugfs_root; 194f95f3850SWill Newton if (!root) 195f95f3850SWill Newton return; 196f95f3850SWill Newton 197f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 198f95f3850SWill Newton &dw_mci_regs_fops); 199f95f3850SWill Newton if (!node) 200f95f3850SWill Newton goto err; 201f95f3850SWill Newton 202f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 203f95f3850SWill Newton &dw_mci_req_fops); 204f95f3850SWill Newton if (!node) 205f95f3850SWill Newton goto err; 206f95f3850SWill Newton 207f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 208f95f3850SWill Newton if (!node) 209f95f3850SWill Newton goto err; 210f95f3850SWill Newton 211f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 212f95f3850SWill Newton (u32 *)&host->pending_events); 213f95f3850SWill Newton if (!node) 214f95f3850SWill Newton goto err; 215f95f3850SWill Newton 216f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 217f95f3850SWill Newton (u32 *)&host->completed_events); 218f95f3850SWill Newton if (!node) 219f95f3850SWill Newton goto err; 220f95f3850SWill Newton 221f95f3850SWill Newton return; 222f95f3850SWill Newton 223f95f3850SWill Newton err: 224f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 225f95f3850SWill Newton } 226f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 227f95f3850SWill Newton 22801730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 22901730558SDoug Anderson 230f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 231f95f3850SWill Newton { 232f95f3850SWill Newton struct mmc_data *data; 233800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23401730558SDoug Anderson struct dw_mci *host = slot->host; 235e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 236f95f3850SWill Newton u32 cmdr; 237f95f3850SWill Newton cmd->error = -EINPROGRESS; 238f95f3850SWill Newton 239f95f3850SWill Newton cmdr = cmd->opcode; 240f95f3850SWill Newton 24190c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24290c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24390c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24490c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24590c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 246f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2474a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 248f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 249f95f3850SWill Newton 25001730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25101730558SDoug Anderson u32 clk_en_a; 25201730558SDoug Anderson 25301730558SDoug Anderson /* Special bit makes CMD11 not die */ 25401730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25501730558SDoug Anderson 25601730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25701730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 25801730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 25901730558SDoug Anderson 26001730558SDoug Anderson /* 26101730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26201730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26301730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26401730558SDoug Anderson * voltage change dance. 26501730558SDoug Anderson * 26601730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26701730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 26801730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 26901730558SDoug Anderson * until the voltage change is all done. 27001730558SDoug Anderson */ 27101730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27201730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27301730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27401730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27501730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27601730558SDoug Anderson } 27701730558SDoug Anderson 278f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 279f95f3850SWill Newton /* We expect a response, so set this bit */ 280f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 281f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 282f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 283f95f3850SWill Newton } 284f95f3850SWill Newton 285f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 286f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 287f95f3850SWill Newton 288f95f3850SWill Newton data = cmd->data; 289f95f3850SWill Newton if (data) { 290f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 291f95f3850SWill Newton if (data->flags & MMC_DATA_STREAM) 292f95f3850SWill Newton cmdr |= SDMMC_CMD_STRM_MODE; 293f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 294f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 295f95f3850SWill Newton } 296f95f3850SWill Newton 297cb27a843SJames Hogan if (drv_data && drv_data->prepare_command) 298cb27a843SJames Hogan drv_data->prepare_command(slot->host, &cmdr); 299800d78bfSThomas Abraham 300f95f3850SWill Newton return cmdr; 301f95f3850SWill Newton } 302f95f3850SWill Newton 30390c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30490c2143aSSeungwon Jeon { 30590c2143aSSeungwon Jeon struct mmc_command *stop; 30690c2143aSSeungwon Jeon u32 cmdr; 30790c2143aSSeungwon Jeon 30890c2143aSSeungwon Jeon if (!cmd->data) 30990c2143aSSeungwon Jeon return 0; 31090c2143aSSeungwon Jeon 31190c2143aSSeungwon Jeon stop = &host->stop_abort; 31290c2143aSSeungwon Jeon cmdr = cmd->opcode; 31390c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31490c2143aSSeungwon Jeon 31590c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31690c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31790c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3186c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3196c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3206c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 32190c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 32290c2143aSSeungwon Jeon stop->arg = 0; 32390c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32490c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32590c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32690c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32790c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 32890c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 32990c2143aSSeungwon Jeon } else { 33090c2143aSSeungwon Jeon return 0; 33190c2143aSSeungwon Jeon } 33290c2143aSSeungwon Jeon 33390c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33490c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33590c2143aSSeungwon Jeon 33690c2143aSSeungwon Jeon return cmdr; 33790c2143aSSeungwon Jeon } 33890c2143aSSeungwon Jeon 3390bdbd0e8SDoug Anderson static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 3400bdbd0e8SDoug Anderson { 3410bdbd0e8SDoug Anderson unsigned long timeout = jiffies + msecs_to_jiffies(500); 3420bdbd0e8SDoug Anderson 3430bdbd0e8SDoug Anderson /* 3440bdbd0e8SDoug Anderson * Databook says that before issuing a new data transfer command 3450bdbd0e8SDoug Anderson * we need to check to see if the card is busy. Data transfer commands 3460bdbd0e8SDoug Anderson * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 3470bdbd0e8SDoug Anderson * 3480bdbd0e8SDoug Anderson * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 3490bdbd0e8SDoug Anderson * expected. 3500bdbd0e8SDoug Anderson */ 3510bdbd0e8SDoug Anderson if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 3520bdbd0e8SDoug Anderson !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 3530bdbd0e8SDoug Anderson while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 3540bdbd0e8SDoug Anderson if (time_after(jiffies, timeout)) { 3550bdbd0e8SDoug Anderson /* Command will fail; we'll pass error then */ 3560bdbd0e8SDoug Anderson dev_err(host->dev, "Busy; trying anyway\n"); 3570bdbd0e8SDoug Anderson break; 3580bdbd0e8SDoug Anderson } 3590bdbd0e8SDoug Anderson udelay(10); 3600bdbd0e8SDoug Anderson } 3610bdbd0e8SDoug Anderson } 3620bdbd0e8SDoug Anderson } 3630bdbd0e8SDoug Anderson 364f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 365f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 366f95f3850SWill Newton { 367f95f3850SWill Newton host->cmd = cmd; 3684a90920cSThomas Abraham dev_vdbg(host->dev, 369f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 370f95f3850SWill Newton cmd->arg, cmd_flags); 371f95f3850SWill Newton 372f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 373f95f3850SWill Newton wmb(); 3740bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 375f95f3850SWill Newton 376f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 377f95f3850SWill Newton } 378f95f3850SWill Newton 37990c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 380f95f3850SWill Newton { 38190c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 38290c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 383f95f3850SWill Newton } 384f95f3850SWill Newton 385f95f3850SWill Newton /* DMA interface functions */ 386f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 387f95f3850SWill Newton { 38803e8cb53SJames Hogan if (host->using_dma) { 389f95f3850SWill Newton host->dma_ops->stop(host); 390f95f3850SWill Newton host->dma_ops->cleanup(host); 391aa50f259SSeungwon Jeon } 392aa50f259SSeungwon Jeon 393f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 394f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 395f95f3850SWill Newton } 396f95f3850SWill Newton 3979aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 3989aa51408SSeungwon Jeon { 3999aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4009aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4019aa51408SSeungwon Jeon else 4029aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4039aa51408SSeungwon Jeon } 4049aa51408SSeungwon Jeon 4059beee912SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 406f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 407f95f3850SWill Newton { 408f95f3850SWill Newton struct mmc_data *data = host->data; 409f95f3850SWill Newton 410f95f3850SWill Newton if (data) 4119aa51408SSeungwon Jeon if (!data->host_cookie) 4124a90920cSThomas Abraham dma_unmap_sg(host->dev, 4139aa51408SSeungwon Jeon data->sg, 4149aa51408SSeungwon Jeon data->sg_len, 4159aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 416f95f3850SWill Newton } 417f95f3850SWill Newton 4185ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4195ce9d961SSeungwon Jeon { 4205ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4215ce9d961SSeungwon Jeon /* Software reset of DMA */ 4225ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4235ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4245ce9d961SSeungwon Jeon } 4255ce9d961SSeungwon Jeon 426f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 427f95f3850SWill Newton { 428f95f3850SWill Newton u32 temp; 429f95f3850SWill Newton 430f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 431f95f3850SWill Newton temp = mci_readl(host, CTRL); 432f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 433f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 434f95f3850SWill Newton mci_writel(host, CTRL, temp); 435f95f3850SWill Newton 436f95f3850SWill Newton /* Stop the IDMAC running */ 437f95f3850SWill Newton temp = mci_readl(host, BMOD); 438a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4395ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 440f95f3850SWill Newton mci_writel(host, BMOD, temp); 441f95f3850SWill Newton } 442f95f3850SWill Newton 443f95f3850SWill Newton static void dw_mci_idmac_complete_dma(struct dw_mci *host) 444f95f3850SWill Newton { 445f95f3850SWill Newton struct mmc_data *data = host->data; 446f95f3850SWill Newton 4474a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 448f95f3850SWill Newton 449f95f3850SWill Newton host->dma_ops->cleanup(host); 450f95f3850SWill Newton 451f95f3850SWill Newton /* 452f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 453f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 454f95f3850SWill Newton */ 455f95f3850SWill Newton if (data) { 456f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 457f95f3850SWill Newton tasklet_schedule(&host->tasklet); 458f95f3850SWill Newton } 459f95f3850SWill Newton } 460f95f3850SWill Newton 461f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 462f95f3850SWill Newton unsigned int sg_len) 463f95f3850SWill Newton { 464f95f3850SWill Newton int i; 46569d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 46669d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *desc = host->sg_cpu; 46769d99fdcSPrabu Thangamuthu 46869d99fdcSPrabu Thangamuthu for (i = 0; i < sg_len; i++, desc++) { 46969d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 47069d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 47169d99fdcSPrabu Thangamuthu 47269d99fdcSPrabu Thangamuthu /* 47369d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 47469d99fdcSPrabu Thangamuthu * descriptor 47569d99fdcSPrabu Thangamuthu */ 47669d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 47769d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 47869d99fdcSPrabu Thangamuthu /* Buffer length */ 47969d99fdcSPrabu Thangamuthu IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length); 48069d99fdcSPrabu Thangamuthu 48169d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 48269d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 48369d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 48469d99fdcSPrabu Thangamuthu } 48569d99fdcSPrabu Thangamuthu 48669d99fdcSPrabu Thangamuthu /* Set first descriptor */ 48769d99fdcSPrabu Thangamuthu desc = host->sg_cpu; 48869d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_FD; 48969d99fdcSPrabu Thangamuthu 49069d99fdcSPrabu Thangamuthu /* Set last descriptor */ 49169d99fdcSPrabu Thangamuthu desc = host->sg_cpu + (i - 1) * 49269d99fdcSPrabu Thangamuthu sizeof(struct idmac_desc_64addr); 49369d99fdcSPrabu Thangamuthu desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 49469d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_LD; 49569d99fdcSPrabu Thangamuthu 49669d99fdcSPrabu Thangamuthu } else { 497f95f3850SWill Newton struct idmac_desc *desc = host->sg_cpu; 498f95f3850SWill Newton 499f95f3850SWill Newton for (i = 0; i < sg_len; i++, desc++) { 500f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 501f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 502f95f3850SWill Newton 50369d99fdcSPrabu Thangamuthu /* 50469d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 50569d99fdcSPrabu Thangamuthu * descriptor 50669d99fdcSPrabu Thangamuthu */ 50769d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 50869d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 509f95f3850SWill Newton /* Buffer length */ 510f95f3850SWill Newton IDMAC_SET_BUFFER1_SIZE(desc, length); 511f95f3850SWill Newton 512f95f3850SWill Newton /* Physical address to DMA to/from */ 513f95f3850SWill Newton desc->des2 = mem_addr; 514f95f3850SWill Newton } 515f95f3850SWill Newton 516f95f3850SWill Newton /* Set first descriptor */ 517f95f3850SWill Newton desc = host->sg_cpu; 518f95f3850SWill Newton desc->des0 |= IDMAC_DES0_FD; 519f95f3850SWill Newton 520f95f3850SWill Newton /* Set last descriptor */ 521f95f3850SWill Newton desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 522f95f3850SWill Newton desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 523f95f3850SWill Newton desc->des0 |= IDMAC_DES0_LD; 52469d99fdcSPrabu Thangamuthu } 525f95f3850SWill Newton 526f95f3850SWill Newton wmb(); 527f95f3850SWill Newton } 528f95f3850SWill Newton 529f95f3850SWill Newton static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 530f95f3850SWill Newton { 531f95f3850SWill Newton u32 temp; 532f95f3850SWill Newton 533f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 534f95f3850SWill Newton 535536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 536536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 537536f6b91SSonny Rao dw_mci_idmac_reset(host); 538536f6b91SSonny Rao 539f95f3850SWill Newton /* Select IDMAC interface */ 540f95f3850SWill Newton temp = mci_readl(host, CTRL); 541f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 542f95f3850SWill Newton mci_writel(host, CTRL, temp); 543f95f3850SWill Newton 544f95f3850SWill Newton wmb(); 545f95f3850SWill Newton 546f95f3850SWill Newton /* Enable the IDMAC */ 547f95f3850SWill Newton temp = mci_readl(host, BMOD); 548a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 549f95f3850SWill Newton mci_writel(host, BMOD, temp); 550f95f3850SWill Newton 551f95f3850SWill Newton /* Start it running */ 552f95f3850SWill Newton mci_writel(host, PLDMND, 1); 553f95f3850SWill Newton } 554f95f3850SWill Newton 555f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 556f95f3850SWill Newton { 557897b69e7SSeungwon Jeon int i; 558f95f3850SWill Newton 55969d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 56069d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 56169d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 56269d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 56369d99fdcSPrabu Thangamuthu 56469d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 56569d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 56669d99fdcSPrabu Thangamuthu i++, p++) { 56769d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 56869d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 56969d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 57069d99fdcSPrabu Thangamuthu 57169d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 57269d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 57369d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 57469d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 57569d99fdcSPrabu Thangamuthu p->des1 = 0; 57669d99fdcSPrabu Thangamuthu p->des2 = 0; 57769d99fdcSPrabu Thangamuthu p->des3 = 0; 57869d99fdcSPrabu Thangamuthu } 57969d99fdcSPrabu Thangamuthu 58069d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 58169d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 58269d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 58369d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 58469d99fdcSPrabu Thangamuthu 58569d99fdcSPrabu Thangamuthu } else { 58669d99fdcSPrabu Thangamuthu struct idmac_desc *p; 587f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 588f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 589f95f3850SWill Newton 590f95f3850SWill Newton /* Forward link the descriptor list */ 591f95f3850SWill Newton for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 59269d99fdcSPrabu Thangamuthu p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * 59369d99fdcSPrabu Thangamuthu (i + 1)); 594f95f3850SWill Newton 595f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 596f95f3850SWill Newton p->des3 = host->sg_dma; 597f95f3850SWill Newton p->des0 = IDMAC_DES0_ER; 59869d99fdcSPrabu Thangamuthu } 599f95f3850SWill Newton 6005ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 601141a712aSSeungwon Jeon 60269d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 60369d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 60469d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 60569d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 60669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 60769d99fdcSPrabu Thangamuthu 60869d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 60969d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 61069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 61169d99fdcSPrabu Thangamuthu 61269d99fdcSPrabu Thangamuthu } else { 613f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 614fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 61569d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 61669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 617f95f3850SWill Newton 618f95f3850SWill Newton /* Set the descriptor base address */ 619f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 62069d99fdcSPrabu Thangamuthu } 62169d99fdcSPrabu Thangamuthu 622f95f3850SWill Newton return 0; 623f95f3850SWill Newton } 624f95f3850SWill Newton 6258e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 626885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 627885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 628885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 629885c3e80SSeungwon Jeon .complete = dw_mci_idmac_complete_dma, 630885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 631885c3e80SSeungwon Jeon }; 632885c3e80SSeungwon Jeon #endif /* CONFIG_MMC_DW_IDMAC */ 633885c3e80SSeungwon Jeon 6349aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 6359aa51408SSeungwon Jeon struct mmc_data *data, 6369aa51408SSeungwon Jeon bool next) 637f95f3850SWill Newton { 638f95f3850SWill Newton struct scatterlist *sg; 6399aa51408SSeungwon Jeon unsigned int i, sg_len; 640f95f3850SWill Newton 6419aa51408SSeungwon Jeon if (!next && data->host_cookie) 6429aa51408SSeungwon Jeon return data->host_cookie; 643f95f3850SWill Newton 644f95f3850SWill Newton /* 645f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 646f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 647f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 648f95f3850SWill Newton */ 649f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 650f95f3850SWill Newton return -EINVAL; 6519aa51408SSeungwon Jeon 652f95f3850SWill Newton if (data->blksz & 3) 653f95f3850SWill Newton return -EINVAL; 654f95f3850SWill Newton 655f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 656f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 657f95f3850SWill Newton return -EINVAL; 658f95f3850SWill Newton } 659f95f3850SWill Newton 6604a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 6619aa51408SSeungwon Jeon data->sg, 6629aa51408SSeungwon Jeon data->sg_len, 6639aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 6649aa51408SSeungwon Jeon if (sg_len == 0) 6659aa51408SSeungwon Jeon return -EINVAL; 6669aa51408SSeungwon Jeon 6679aa51408SSeungwon Jeon if (next) 6689aa51408SSeungwon Jeon data->host_cookie = sg_len; 6699aa51408SSeungwon Jeon 6709aa51408SSeungwon Jeon return sg_len; 6719aa51408SSeungwon Jeon } 6729aa51408SSeungwon Jeon 6739aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 6749aa51408SSeungwon Jeon struct mmc_request *mrq, 6759aa51408SSeungwon Jeon bool is_first_req) 6769aa51408SSeungwon Jeon { 6779aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6789aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6799aa51408SSeungwon Jeon 6809aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 6819aa51408SSeungwon Jeon return; 6829aa51408SSeungwon Jeon 6839aa51408SSeungwon Jeon if (data->host_cookie) { 6849aa51408SSeungwon Jeon data->host_cookie = 0; 6859aa51408SSeungwon Jeon return; 6869aa51408SSeungwon Jeon } 6879aa51408SSeungwon Jeon 6889aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 6899aa51408SSeungwon Jeon data->host_cookie = 0; 6909aa51408SSeungwon Jeon } 6919aa51408SSeungwon Jeon 6929aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 6939aa51408SSeungwon Jeon struct mmc_request *mrq, 6949aa51408SSeungwon Jeon int err) 6959aa51408SSeungwon Jeon { 6969aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6979aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6989aa51408SSeungwon Jeon 6999aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 7009aa51408SSeungwon Jeon return; 7019aa51408SSeungwon Jeon 7029aa51408SSeungwon Jeon if (data->host_cookie) 7034a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 7049aa51408SSeungwon Jeon data->sg, 7059aa51408SSeungwon Jeon data->sg_len, 7069aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 7079aa51408SSeungwon Jeon data->host_cookie = 0; 7089aa51408SSeungwon Jeon } 7099aa51408SSeungwon Jeon 71052426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 71152426899SSeungwon Jeon { 71252426899SSeungwon Jeon #ifdef CONFIG_MMC_DW_IDMAC 71352426899SSeungwon Jeon unsigned int blksz = data->blksz; 71452426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 71552426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 71652426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 71752426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 71852426899SSeungwon Jeon int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; 71952426899SSeungwon Jeon 72052426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 72152426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 72252426899SSeungwon Jeon 72352426899SSeungwon Jeon /* 72452426899SSeungwon Jeon * MSIZE is '1', 72552426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 72652426899SSeungwon Jeon */ 72752426899SSeungwon Jeon if (blksz % fifo_width) { 72852426899SSeungwon Jeon msize = 0; 72952426899SSeungwon Jeon rx_wmark = 1; 73052426899SSeungwon Jeon goto done; 73152426899SSeungwon Jeon } 73252426899SSeungwon Jeon 73352426899SSeungwon Jeon do { 73452426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 73552426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 73652426899SSeungwon Jeon msize = idx; 73752426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 73852426899SSeungwon Jeon break; 73952426899SSeungwon Jeon } 74052426899SSeungwon Jeon } while (--idx > 0); 74152426899SSeungwon Jeon /* 74252426899SSeungwon Jeon * If idx is '0', it won't be tried 74352426899SSeungwon Jeon * Thus, initial values are uesed 74452426899SSeungwon Jeon */ 74552426899SSeungwon Jeon done: 74652426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 74752426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 74852426899SSeungwon Jeon #endif 74952426899SSeungwon Jeon } 75052426899SSeungwon Jeon 751f1d2736cSSeungwon Jeon static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 752f1d2736cSSeungwon Jeon { 753f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 754f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 755f1d2736cSSeungwon Jeon u16 thld_size; 756f1d2736cSSeungwon Jeon 757f1d2736cSSeungwon Jeon WARN_ON(!(data->flags & MMC_DATA_READ)); 758f1d2736cSSeungwon Jeon 75966dfd101SJames Hogan /* 76066dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 76166dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 76266dfd101SJames Hogan */ 76366dfd101SJames Hogan if (host->verid < DW_MMC_240A) 76466dfd101SJames Hogan return; 76566dfd101SJames Hogan 766f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 767f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 768f1d2736cSSeungwon Jeon goto disable; 769f1d2736cSSeungwon Jeon 770f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 771f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 772f1d2736cSSeungwon Jeon 773f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 774f1d2736cSSeungwon Jeon goto disable; 775f1d2736cSSeungwon Jeon 776f1d2736cSSeungwon Jeon /* 777f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 778f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 779f1d2736cSSeungwon Jeon * Currently just choose blksz. 780f1d2736cSSeungwon Jeon */ 781f1d2736cSSeungwon Jeon thld_size = blksz; 782f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 783f1d2736cSSeungwon Jeon return; 784f1d2736cSSeungwon Jeon 785f1d2736cSSeungwon Jeon disable: 786f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 787f1d2736cSSeungwon Jeon } 788f1d2736cSSeungwon Jeon 7899aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 7909aa51408SSeungwon Jeon { 791f8c58c11SDoug Anderson unsigned long irqflags; 7929aa51408SSeungwon Jeon int sg_len; 7939aa51408SSeungwon Jeon u32 temp; 7949aa51408SSeungwon Jeon 7959aa51408SSeungwon Jeon host->using_dma = 0; 7969aa51408SSeungwon Jeon 7979aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 7989aa51408SSeungwon Jeon if (!host->use_dma) 7999aa51408SSeungwon Jeon return -ENODEV; 8009aa51408SSeungwon Jeon 8019aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 802a99aa9b9SSeungwon Jeon if (sg_len < 0) { 803a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 8049aa51408SSeungwon Jeon return sg_len; 805a99aa9b9SSeungwon Jeon } 8069aa51408SSeungwon Jeon 80703e8cb53SJames Hogan host->using_dma = 1; 80803e8cb53SJames Hogan 8094a90920cSThomas Abraham dev_vdbg(host->dev, 810f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 811f95f3850SWill Newton (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 812f95f3850SWill Newton sg_len); 813f95f3850SWill Newton 81452426899SSeungwon Jeon /* 81552426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 81652426899SSeungwon Jeon * If current block size is same with previous size, 81752426899SSeungwon Jeon * no need to update fifoth. 81852426899SSeungwon Jeon */ 81952426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 82052426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 82152426899SSeungwon Jeon 822f95f3850SWill Newton /* Enable the DMA interface */ 823f95f3850SWill Newton temp = mci_readl(host, CTRL); 824f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 825f95f3850SWill Newton mci_writel(host, CTRL, temp); 826f95f3850SWill Newton 827f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 828f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 829f95f3850SWill Newton temp = mci_readl(host, INTMASK); 830f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 831f95f3850SWill Newton mci_writel(host, INTMASK, temp); 832f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 833f95f3850SWill Newton 834f95f3850SWill Newton host->dma_ops->start(host, sg_len); 835f95f3850SWill Newton 836f95f3850SWill Newton return 0; 837f95f3850SWill Newton } 838f95f3850SWill Newton 839f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 840f95f3850SWill Newton { 841f8c58c11SDoug Anderson unsigned long irqflags; 842f95f3850SWill Newton u32 temp; 843f95f3850SWill Newton 844f95f3850SWill Newton data->error = -EINPROGRESS; 845f95f3850SWill Newton 846f95f3850SWill Newton WARN_ON(host->data); 847f95f3850SWill Newton host->sg = NULL; 848f95f3850SWill Newton host->data = data; 849f95f3850SWill Newton 850f1d2736cSSeungwon Jeon if (data->flags & MMC_DATA_READ) { 85155c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 852f1d2736cSSeungwon Jeon dw_mci_ctrl_rd_thld(host, data); 853f1d2736cSSeungwon Jeon } else { 85455c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 855f1d2736cSSeungwon Jeon } 85655c5efbcSJames Hogan 857f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 858f9c2a0dcSSeungwon Jeon int flags = SG_MITER_ATOMIC; 859f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 860f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 861f9c2a0dcSSeungwon Jeon else 862f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 863f9c2a0dcSSeungwon Jeon 864f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 865f95f3850SWill Newton host->sg = data->sg; 86634b664a2SJames Hogan host->part_buf_start = 0; 86734b664a2SJames Hogan host->part_buf_count = 0; 868f95f3850SWill Newton 869b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 870f8c58c11SDoug Anderson 871f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 872f95f3850SWill Newton temp = mci_readl(host, INTMASK); 873f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 874f95f3850SWill Newton mci_writel(host, INTMASK, temp); 875f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 876f95f3850SWill Newton 877f95f3850SWill Newton temp = mci_readl(host, CTRL); 878f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 879f95f3850SWill Newton mci_writel(host, CTRL, temp); 88052426899SSeungwon Jeon 88152426899SSeungwon Jeon /* 88252426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 88352426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 88452426899SSeungwon Jeon * prev_blksz should be invalidated. 88552426899SSeungwon Jeon */ 88652426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 88752426899SSeungwon Jeon host->prev_blksz = 0; 88852426899SSeungwon Jeon } else { 88952426899SSeungwon Jeon /* 89052426899SSeungwon Jeon * Keep the current block size. 89152426899SSeungwon Jeon * It will be used to decide whether to update 89252426899SSeungwon Jeon * fifoth register next time. 89352426899SSeungwon Jeon */ 89452426899SSeungwon Jeon host->prev_blksz = data->blksz; 895f95f3850SWill Newton } 896f95f3850SWill Newton } 897f95f3850SWill Newton 898f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 899f95f3850SWill Newton { 900f95f3850SWill Newton struct dw_mci *host = slot->host; 901f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 902f95f3850SWill Newton unsigned int cmd_status = 0; 903f95f3850SWill Newton 904f95f3850SWill Newton mci_writel(host, CMDARG, arg); 905f95f3850SWill Newton wmb(); 9060bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd); 907f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 908f95f3850SWill Newton 909f95f3850SWill Newton while (time_before(jiffies, timeout)) { 910f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 911f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 912f95f3850SWill Newton return; 913f95f3850SWill Newton } 914f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 915f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 916f95f3850SWill Newton cmd, arg, cmd_status); 917f95f3850SWill Newton } 918f95f3850SWill Newton 919ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 920f95f3850SWill Newton { 921f95f3850SWill Newton struct dw_mci *host = slot->host; 922fdf492a1SDoug Anderson unsigned int clock = slot->clock; 923f95f3850SWill Newton u32 div; 9249623b5b9SDoug Anderson u32 clk_en_a; 92501730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 92601730558SDoug Anderson 92701730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 92801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 92901730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 930f95f3850SWill Newton 931fdf492a1SDoug Anderson if (!clock) { 932fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 93301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 934fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 935fdf492a1SDoug Anderson div = host->bus_hz / clock; 936fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 937f95f3850SWill Newton /* 938f95f3850SWill Newton * move the + 1 after the divide to prevent 939f95f3850SWill Newton * over-clocking the card. 940f95f3850SWill Newton */ 941e419990bSSeungwon Jeon div += 1; 942e419990bSSeungwon Jeon 943fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 944f95f3850SWill Newton 945fdf492a1SDoug Anderson if ((clock << div) != slot->__clk_old || force_clkinit) 946f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 947fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 948fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 949fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 950fdf492a1SDoug Anderson host->bus_hz, div); 951f95f3850SWill Newton 952f95f3850SWill Newton /* disable clock */ 953f95f3850SWill Newton mci_writel(host, CLKENA, 0); 954f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 955f95f3850SWill Newton 956f95f3850SWill Newton /* inform CIU */ 95701730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 958f95f3850SWill Newton 959f95f3850SWill Newton /* set clock to desired speed */ 960f95f3850SWill Newton mci_writel(host, CLKDIV, div); 961f95f3850SWill Newton 962f95f3850SWill Newton /* inform CIU */ 96301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 964f95f3850SWill Newton 9659623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 9669623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 967b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 9689623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 9699623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 970f95f3850SWill Newton 971f95f3850SWill Newton /* inform CIU */ 97201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 973f95f3850SWill Newton 974fdf492a1SDoug Anderson /* keep the clock with reflecting clock dividor */ 975fdf492a1SDoug Anderson slot->__clk_old = clock << div; 976f95f3850SWill Newton } 977f95f3850SWill Newton 978fdf492a1SDoug Anderson host->current_speed = clock; 979fdf492a1SDoug Anderson 980f95f3850SWill Newton /* Set the current slot bus width */ 9811d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 982f95f3850SWill Newton } 983f95f3850SWill Newton 984053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 985053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 986053b3ce6SSeungwon Jeon struct mmc_command *cmd) 987f95f3850SWill Newton { 988f95f3850SWill Newton struct mmc_request *mrq; 989f95f3850SWill Newton struct mmc_data *data; 990f95f3850SWill Newton u32 cmdflags; 991f95f3850SWill Newton 992f95f3850SWill Newton mrq = slot->mrq; 993f95f3850SWill Newton 994f95f3850SWill Newton host->cur_slot = slot; 995f95f3850SWill Newton host->mrq = mrq; 996f95f3850SWill Newton 997f95f3850SWill Newton host->pending_events = 0; 998f95f3850SWill Newton host->completed_events = 0; 999e352c813SSeungwon Jeon host->cmd_status = 0; 1000f95f3850SWill Newton host->data_status = 0; 1001e352c813SSeungwon Jeon host->dir_status = 0; 1002f95f3850SWill Newton 1003053b3ce6SSeungwon Jeon data = cmd->data; 1004f95f3850SWill Newton if (data) { 1005f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1006f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1007f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1008f95f3850SWill Newton } 1009f95f3850SWill Newton 1010f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1011f95f3850SWill Newton 1012f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1013f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1014f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1015f95f3850SWill Newton 1016f95f3850SWill Newton if (data) { 1017f95f3850SWill Newton dw_mci_submit_data(host, data); 1018f95f3850SWill Newton wmb(); 1019f95f3850SWill Newton } 1020f95f3850SWill Newton 1021f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1022f95f3850SWill Newton 1023f95f3850SWill Newton if (mrq->stop) 1024f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 102590c2143aSSeungwon Jeon else 102690c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1027f95f3850SWill Newton } 1028f95f3850SWill Newton 1029053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1030053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1031053b3ce6SSeungwon Jeon { 1032053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1033053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1034053b3ce6SSeungwon Jeon 1035053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1036053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1037053b3ce6SSeungwon Jeon } 1038053b3ce6SSeungwon Jeon 10397456caaeSJames Hogan /* must be called with host->lock held */ 1040f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1041f95f3850SWill Newton struct mmc_request *mrq) 1042f95f3850SWill Newton { 1043f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1044f95f3850SWill Newton host->state); 1045f95f3850SWill Newton 1046f95f3850SWill Newton slot->mrq = mrq; 1047f95f3850SWill Newton 104801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 104901730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 105001730558SDoug Anderson "Voltage change didn't complete\n"); 105101730558SDoug Anderson /* 105201730558SDoug Anderson * this case isn't expected to happen, so we can 105301730558SDoug Anderson * either crash here or just try to continue on 105401730558SDoug Anderson * in the closest possible state 105501730558SDoug Anderson */ 105601730558SDoug Anderson host->state = STATE_IDLE; 105701730558SDoug Anderson } 105801730558SDoug Anderson 1059f95f3850SWill Newton if (host->state == STATE_IDLE) { 1060f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1061f95f3850SWill Newton dw_mci_start_request(host, slot); 1062f95f3850SWill Newton } else { 1063f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1064f95f3850SWill Newton } 1065f95f3850SWill Newton } 1066f95f3850SWill Newton 1067f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1068f95f3850SWill Newton { 1069f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1070f95f3850SWill Newton struct dw_mci *host = slot->host; 1071f95f3850SWill Newton 1072f95f3850SWill Newton WARN_ON(slot->mrq); 1073f95f3850SWill Newton 10747456caaeSJames Hogan /* 10757456caaeSJames Hogan * The check for card presence and queueing of the request must be 10767456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 10777456caaeSJames Hogan * request wouldn't fail until another card was inserted. 10787456caaeSJames Hogan */ 10797456caaeSJames Hogan spin_lock_bh(&host->lock); 10807456caaeSJames Hogan 1081f95f3850SWill Newton if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 10827456caaeSJames Hogan spin_unlock_bh(&host->lock); 1083f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1084f95f3850SWill Newton mmc_request_done(mmc, mrq); 1085f95f3850SWill Newton return; 1086f95f3850SWill Newton } 1087f95f3850SWill Newton 1088f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 10897456caaeSJames Hogan 10907456caaeSJames Hogan spin_unlock_bh(&host->lock); 1091f95f3850SWill Newton } 1092f95f3850SWill Newton 1093f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1094f95f3850SWill Newton { 1095f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1096e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 109741babf75SJaehoon Chung u32 regs; 109851da2240SYuvaraj CD int ret; 1099f95f3850SWill Newton 1100f95f3850SWill Newton switch (ios->bus_width) { 1101f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1102f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1103f95f3850SWill Newton break; 1104c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1105c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1106c9b2a06fSJaehoon Chung break; 1107b2f7cb45SJaehoon Chung default: 1108b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1109b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1110f95f3850SWill Newton } 1111f95f3850SWill Newton 111241babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 11133f514291SSeungwon Jeon 11143f514291SSeungwon Jeon /* DDR mode set */ 111580113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 111680113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1117c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 11183f514291SSeungwon Jeon else 1119c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 11203f514291SSeungwon Jeon 112141babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1122f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 112341babf75SJaehoon Chung 1124f95f3850SWill Newton /* 1125f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1126f95f3850SWill Newton * core ios update when finding the minimum. 1127f95f3850SWill Newton */ 1128f95f3850SWill Newton slot->clock = ios->clock; 1129f95f3850SWill Newton 1130cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1131cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1132800d78bfSThomas Abraham 1133f95f3850SWill Newton switch (ios->power_mode) { 1134f95f3850SWill Newton case MMC_POWER_UP: 113551da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 113651da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 113751da2240SYuvaraj CD ios->vdd); 113851da2240SYuvaraj CD if (ret) { 113951da2240SYuvaraj CD dev_err(slot->host->dev, 114051da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 114151da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 114251da2240SYuvaraj CD return; 114351da2240SYuvaraj CD } 114451da2240SYuvaraj CD } 114529d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 114629d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 114729d0d161SDoug Anderson regs |= (1 << slot->id); 114829d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 114929d0d161SDoug Anderson break; 115029d0d161SDoug Anderson case MMC_POWER_ON: 1151d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1152d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 115351da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 115451da2240SYuvaraj CD if (ret < 0) 115551da2240SYuvaraj CD dev_err(slot->host->dev, 1156d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 115751da2240SYuvaraj CD else 115851da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1159d1f1dd86SDoug Anderson 1160d1f1dd86SDoug Anderson } else { 1161d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1162d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1163d1f1dd86SDoug Anderson } 1164d1f1dd86SDoug Anderson 1165d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1166d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1167d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 116851da2240SYuvaraj CD } 1169655babbdSDoug Anderson 1170655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1171655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1172655babbdSDoug Anderson 1173e6f34e2fSJames Hogan break; 1174e6f34e2fSJames Hogan case MMC_POWER_OFF: 1175655babbdSDoug Anderson /* Turn clock off before power goes down */ 1176655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1177655babbdSDoug Anderson 117851da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 117951da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 118051da2240SYuvaraj CD 1181d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 118251da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 118351da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 118451da2240SYuvaraj CD 11854366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 11864366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 11874366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1188f95f3850SWill Newton break; 1189f95f3850SWill Newton default: 1190f95f3850SWill Newton break; 1191f95f3850SWill Newton } 1192655babbdSDoug Anderson 1193655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1194655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1195f95f3850SWill Newton } 1196f95f3850SWill Newton 119701730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 119801730558SDoug Anderson { 119901730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 120001730558SDoug Anderson u32 status; 120101730558SDoug Anderson 120201730558SDoug Anderson /* 120301730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 120401730558SDoug Anderson * (the data lines) are 0000 120501730558SDoug Anderson */ 120601730558SDoug Anderson status = mci_readl(slot->host, STATUS); 120701730558SDoug Anderson 120801730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 120901730558SDoug Anderson } 121001730558SDoug Anderson 121101730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 121201730558SDoug Anderson { 121301730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 121401730558SDoug Anderson struct dw_mci *host = slot->host; 121501730558SDoug Anderson u32 uhs; 121601730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 121701730558SDoug Anderson int min_uv, max_uv; 121801730558SDoug Anderson int ret; 121901730558SDoug Anderson 122001730558SDoug Anderson /* 122101730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 122201730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 122301730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 122401730558SDoug Anderson */ 122501730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 122601730558SDoug Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 122701730558SDoug Anderson min_uv = 2700000; 122801730558SDoug Anderson max_uv = 3600000; 122901730558SDoug Anderson uhs &= ~v18; 123001730558SDoug Anderson } else { 123101730558SDoug Anderson min_uv = 1700000; 123201730558SDoug Anderson max_uv = 1950000; 123301730558SDoug Anderson uhs |= v18; 123401730558SDoug Anderson } 123501730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 123601730558SDoug Anderson ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 123701730558SDoug Anderson 123801730558SDoug Anderson if (ret) { 1239b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 124001730558SDoug Anderson "Regulator set error %d: %d - %d\n", 124101730558SDoug Anderson ret, min_uv, max_uv); 124201730558SDoug Anderson return ret; 124301730558SDoug Anderson } 124401730558SDoug Anderson } 124501730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 124601730558SDoug Anderson 124701730558SDoug Anderson return 0; 124801730558SDoug Anderson } 124901730558SDoug Anderson 1250f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1251f95f3850SWill Newton { 1252f95f3850SWill Newton int read_only; 1253f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 12549795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1255f95f3850SWill Newton 1256f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 125726375b5cSJaehoon Chung if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) || 125826375b5cSJaehoon Chung (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)) 1259b4967aa5SThomas Abraham read_only = 0; 12609795a846SJaehoon Chung else if (!IS_ERR_VALUE(gpio_ro)) 12619795a846SJaehoon Chung read_only = gpio_ro; 1262f95f3850SWill Newton else 1263f95f3850SWill Newton read_only = 1264f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1265f95f3850SWill Newton 1266f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1267f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1268f95f3850SWill Newton 1269f95f3850SWill Newton return read_only; 1270f95f3850SWill Newton } 1271f95f3850SWill Newton 1272f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1273f95f3850SWill Newton { 1274f95f3850SWill Newton int present; 1275f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1276f95f3850SWill Newton struct dw_mci_board *brd = slot->host->pdata; 12777cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 12787cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1279f95f3850SWill Newton 1280f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1281fc3d7720SJaehoon Chung if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 1282fc3d7720SJaehoon Chung present = 1; 1283bf626e55SZhangfei Gao else if (!IS_ERR_VALUE(gpio_cd)) 12847cf347bdSZhangfei Gao present = gpio_cd; 1285f95f3850SWill Newton else 1286f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1287f95f3850SWill Newton == 0 ? 1 : 0; 1288f95f3850SWill Newton 12897cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1290bf626e55SZhangfei Gao if (present) { 1291bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1292f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1293bf626e55SZhangfei Gao } else { 1294bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1295f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1296bf626e55SZhangfei Gao } 12977cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1298f95f3850SWill Newton 1299f95f3850SWill Newton return present; 1300f95f3850SWill Newton } 1301f95f3850SWill Newton 1302b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1303b24c8b26SDoug Anderson { 1304b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1305b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1306b24c8b26SDoug Anderson 13079623b5b9SDoug Anderson /* 13089623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 13099623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 13109623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 13119623b5b9SDoug Anderson */ 1312b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 13139623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1314b24c8b26SDoug Anderson u32 clk_en_a_old; 1315b24c8b26SDoug Anderson u32 clk_en_a; 13169623b5b9SDoug Anderson 1317b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 13189623b5b9SDoug Anderson 1319b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1320b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1321b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1322b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1323b24c8b26SDoug Anderson } else { 1324b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1325b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1326b24c8b26SDoug Anderson } 1327b24c8b26SDoug Anderson 1328b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1329b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 13309623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 13319623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 13329623b5b9SDoug Anderson } 13339623b5b9SDoug Anderson } 1334b24c8b26SDoug Anderson } 13359623b5b9SDoug Anderson 13361a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 13371a5c8e1fSShashidhar Hiremath { 13381a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 13391a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1340f8c58c11SDoug Anderson unsigned long irqflags; 13411a5c8e1fSShashidhar Hiremath u32 int_mask; 13421a5c8e1fSShashidhar Hiremath 1343f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1344f8c58c11SDoug Anderson 13451a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 13461a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1347b24c8b26SDoug Anderson if (enb) 1348b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1349b24c8b26SDoug Anderson else 1350b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1351b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1352f8c58c11SDoug Anderson 1353f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13541a5c8e1fSShashidhar Hiremath } 13551a5c8e1fSShashidhar Hiremath 13560976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 13570976f16dSSeungwon Jeon { 13580976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 13590976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 13600976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 13610976f16dSSeungwon Jeon int err = -ENOSYS; 13620976f16dSSeungwon Jeon 13630976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 13646c2c6506SUlf Hansson err = drv_data->execute_tuning(slot); 13650976f16dSSeungwon Jeon return err; 13660976f16dSSeungwon Jeon } 13670976f16dSSeungwon Jeon 136880113132SSeungwon Jeon int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 136980113132SSeungwon Jeon { 137080113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 137180113132SSeungwon Jeon struct dw_mci *host = slot->host; 137280113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 137380113132SSeungwon Jeon 137480113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 137580113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 137680113132SSeungwon Jeon 137780113132SSeungwon Jeon return 0; 137880113132SSeungwon Jeon } 137980113132SSeungwon Jeon 1380f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1381f95f3850SWill Newton .request = dw_mci_request, 13829aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 13839aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1384f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1385f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1386f95f3850SWill Newton .get_cd = dw_mci_get_cd, 13871a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 13880976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 138901730558SDoug Anderson .card_busy = dw_mci_card_busy, 139001730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1391b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 139280113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1393f95f3850SWill Newton }; 1394f95f3850SWill Newton 1395f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1396f95f3850SWill Newton __releases(&host->lock) 1397f95f3850SWill Newton __acquires(&host->lock) 1398f95f3850SWill Newton { 1399f95f3850SWill Newton struct dw_mci_slot *slot; 1400f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1401f95f3850SWill Newton 1402f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1403f95f3850SWill Newton 1404f95f3850SWill Newton host->cur_slot->mrq = NULL; 1405f95f3850SWill Newton host->mrq = NULL; 1406f95f3850SWill Newton if (!list_empty(&host->queue)) { 1407f95f3850SWill Newton slot = list_entry(host->queue.next, 1408f95f3850SWill Newton struct dw_mci_slot, queue_node); 1409f95f3850SWill Newton list_del(&slot->queue_node); 14104a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1411f95f3850SWill Newton mmc_hostname(slot->mmc)); 1412f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1413f95f3850SWill Newton dw_mci_start_request(host, slot); 1414f95f3850SWill Newton } else { 14154a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 141601730558SDoug Anderson 141701730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 141801730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 141901730558SDoug Anderson else 1420f95f3850SWill Newton host->state = STATE_IDLE; 1421f95f3850SWill Newton } 1422f95f3850SWill Newton 1423f95f3850SWill Newton spin_unlock(&host->lock); 1424f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1425f95f3850SWill Newton spin_lock(&host->lock); 1426f95f3850SWill Newton } 1427f95f3850SWill Newton 1428e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1429f95f3850SWill Newton { 1430f95f3850SWill Newton u32 status = host->cmd_status; 1431f95f3850SWill Newton 1432f95f3850SWill Newton host->cmd_status = 0; 1433f95f3850SWill Newton 1434f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1435f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1436f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1437f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1438f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1439f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1440f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1441f95f3850SWill Newton } else { 1442f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1443f95f3850SWill Newton cmd->resp[1] = 0; 1444f95f3850SWill Newton cmd->resp[2] = 0; 1445f95f3850SWill Newton cmd->resp[3] = 0; 1446f95f3850SWill Newton } 1447f95f3850SWill Newton } 1448f95f3850SWill Newton 1449f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1450f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1451f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1452f95f3850SWill Newton cmd->error = -EILSEQ; 1453f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1454f95f3850SWill Newton cmd->error = -EIO; 1455f95f3850SWill Newton else 1456f95f3850SWill Newton cmd->error = 0; 1457f95f3850SWill Newton 1458f95f3850SWill Newton if (cmd->error) { 1459f95f3850SWill Newton /* newer ip versions need a delay between retries */ 1460f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1461f95f3850SWill Newton mdelay(20); 1462f95f3850SWill Newton } 1463e352c813SSeungwon Jeon 1464e352c813SSeungwon Jeon return cmd->error; 1465e352c813SSeungwon Jeon } 1466e352c813SSeungwon Jeon 1467e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1468e352c813SSeungwon Jeon { 146931bff450SSeungwon Jeon u32 status = host->data_status; 1470e352c813SSeungwon Jeon 1471e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1472e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1473e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1474e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1475e352c813SSeungwon Jeon data->error = -EILSEQ; 1476e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1477e352c813SSeungwon Jeon if (host->dir_status == 1478e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1479e352c813SSeungwon Jeon /* 1480e352c813SSeungwon Jeon * No data CRC status was returned. 1481e352c813SSeungwon Jeon * The number of bytes transferred 1482e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1483e352c813SSeungwon Jeon */ 1484e352c813SSeungwon Jeon data->bytes_xfered = 0; 1485e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1486e352c813SSeungwon Jeon } else if (host->dir_status == 1487e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1488e352c813SSeungwon Jeon data->error = -EIO; 1489e352c813SSeungwon Jeon } 1490e352c813SSeungwon Jeon } else { 1491e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1492e352c813SSeungwon Jeon data->error = -EIO; 1493e352c813SSeungwon Jeon } 1494e352c813SSeungwon Jeon 1495e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1496e352c813SSeungwon Jeon 1497e352c813SSeungwon Jeon /* 1498e352c813SSeungwon Jeon * After an error, there may be data lingering 149931bff450SSeungwon Jeon * in the FIFO 1500e352c813SSeungwon Jeon */ 15013a33a94cSSonny Rao dw_mci_reset(host); 1502e352c813SSeungwon Jeon } else { 1503e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1504e352c813SSeungwon Jeon data->error = 0; 1505e352c813SSeungwon Jeon } 1506e352c813SSeungwon Jeon 1507e352c813SSeungwon Jeon return data->error; 1508f95f3850SWill Newton } 1509f95f3850SWill Newton 1510f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1511f95f3850SWill Newton { 1512f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1513f95f3850SWill Newton struct mmc_data *data; 1514f95f3850SWill Newton struct mmc_command *cmd; 1515e352c813SSeungwon Jeon struct mmc_request *mrq; 1516f95f3850SWill Newton enum dw_mci_state state; 1517f95f3850SWill Newton enum dw_mci_state prev_state; 1518e352c813SSeungwon Jeon unsigned int err; 1519f95f3850SWill Newton 1520f95f3850SWill Newton spin_lock(&host->lock); 1521f95f3850SWill Newton 1522f95f3850SWill Newton state = host->state; 1523f95f3850SWill Newton data = host->data; 1524e352c813SSeungwon Jeon mrq = host->mrq; 1525f95f3850SWill Newton 1526f95f3850SWill Newton do { 1527f95f3850SWill Newton prev_state = state; 1528f95f3850SWill Newton 1529f95f3850SWill Newton switch (state) { 1530f95f3850SWill Newton case STATE_IDLE: 153101730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1532f95f3850SWill Newton break; 1533f95f3850SWill Newton 153401730558SDoug Anderson case STATE_SENDING_CMD11: 1535f95f3850SWill Newton case STATE_SENDING_CMD: 1536f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1537f95f3850SWill Newton &host->pending_events)) 1538f95f3850SWill Newton break; 1539f95f3850SWill Newton 1540f95f3850SWill Newton cmd = host->cmd; 1541f95f3850SWill Newton host->cmd = NULL; 1542f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1543e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1544e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1545053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1546053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1547e352c813SSeungwon Jeon mrq->cmd); 1548053b3ce6SSeungwon Jeon goto unlock; 1549053b3ce6SSeungwon Jeon } 1550053b3ce6SSeungwon Jeon 1551e352c813SSeungwon Jeon if (cmd->data && err) { 155271abb133SSeungwon Jeon dw_mci_stop_dma(host); 155390c2143aSSeungwon Jeon send_stop_abort(host, data); 155471abb133SSeungwon Jeon state = STATE_SENDING_STOP; 155571abb133SSeungwon Jeon break; 155671abb133SSeungwon Jeon } 155771abb133SSeungwon Jeon 1558e352c813SSeungwon Jeon if (!cmd->data || err) { 1559e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1560f95f3850SWill Newton goto unlock; 1561f95f3850SWill Newton } 1562f95f3850SWill Newton 1563f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1564f95f3850SWill Newton /* fall through */ 1565f95f3850SWill Newton 1566f95f3850SWill Newton case STATE_SENDING_DATA: 15672aa35465SDoug Anderson /* 15682aa35465SDoug Anderson * We could get a data error and never a transfer 15692aa35465SDoug Anderson * complete so we'd better check for it here. 15702aa35465SDoug Anderson * 15712aa35465SDoug Anderson * Note that we don't really care if we also got a 15722aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 15732aa35465SDoug Anderson * abort won't hurt. 15742aa35465SDoug Anderson */ 1575f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1576f95f3850SWill Newton &host->pending_events)) { 1577f95f3850SWill Newton dw_mci_stop_dma(host); 1578bdb9a90bSaddy ke if (data->stop || 1579bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1580bdb9a90bSaddy ke SDMMC_INT_EBE))) 158190c2143aSSeungwon Jeon send_stop_abort(host, data); 1582f95f3850SWill Newton state = STATE_DATA_ERROR; 1583f95f3850SWill Newton break; 1584f95f3850SWill Newton } 1585f95f3850SWill Newton 1586f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1587f95f3850SWill Newton &host->pending_events)) 1588f95f3850SWill Newton break; 1589f95f3850SWill Newton 1590f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 15912aa35465SDoug Anderson 15922aa35465SDoug Anderson /* 15932aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 15942aa35465SDoug Anderson * before the transfer completed. This might not have 15952aa35465SDoug Anderson * been caught by the check above because the interrupt 15962aa35465SDoug Anderson * could have gone off between the previous check and 15972aa35465SDoug Anderson * the check for transfer complete. 15982aa35465SDoug Anderson * 15992aa35465SDoug Anderson * Technically this ought not be needed assuming we 16002aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 16012aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 16022aa35465SDoug Anderson * 16032aa35465SDoug Anderson * This has the advantage of sending the stop command. 16042aa35465SDoug Anderson */ 16052aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 16062aa35465SDoug Anderson &host->pending_events)) { 16072aa35465SDoug Anderson dw_mci_stop_dma(host); 1608bdb9a90bSaddy ke if (data->stop || 1609bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1610bdb9a90bSaddy ke SDMMC_INT_EBE))) 16112aa35465SDoug Anderson send_stop_abort(host, data); 16122aa35465SDoug Anderson state = STATE_DATA_ERROR; 16132aa35465SDoug Anderson break; 16142aa35465SDoug Anderson } 1615f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 16162aa35465SDoug Anderson 1617f95f3850SWill Newton /* fall through */ 1618f95f3850SWill Newton 1619f95f3850SWill Newton case STATE_DATA_BUSY: 1620f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1621f95f3850SWill Newton &host->pending_events)) 1622f95f3850SWill Newton break; 1623f95f3850SWill Newton 1624f95f3850SWill Newton host->data = NULL; 1625f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1626e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1627f95f3850SWill Newton 1628e352c813SSeungwon Jeon if (!err) { 1629e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 163017c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1631053b3ce6SSeungwon Jeon data->stop->error = 0; 1632e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1633053b3ce6SSeungwon Jeon goto unlock; 1634053b3ce6SSeungwon Jeon } 1635053b3ce6SSeungwon Jeon 163690c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1637e352c813SSeungwon Jeon if (data->stop) 163890c2143aSSeungwon Jeon send_stop_abort(host, data); 16392aa35465SDoug Anderson } else { 16402aa35465SDoug Anderson /* 16412aa35465SDoug Anderson * If we don't have a command complete now we'll 16422aa35465SDoug Anderson * never get one since we just reset everything; 16432aa35465SDoug Anderson * better end the request. 16442aa35465SDoug Anderson * 16452aa35465SDoug Anderson * If we do have a command complete we'll fall 16462aa35465SDoug Anderson * through to the SENDING_STOP command and 16472aa35465SDoug Anderson * everything will be peachy keen. 16482aa35465SDoug Anderson */ 16492aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 16502aa35465SDoug Anderson &host->pending_events)) { 16512aa35465SDoug Anderson host->cmd = NULL; 16522aa35465SDoug Anderson dw_mci_request_end(host, mrq); 16532aa35465SDoug Anderson goto unlock; 16542aa35465SDoug Anderson } 165590c2143aSSeungwon Jeon } 1656e352c813SSeungwon Jeon 1657e352c813SSeungwon Jeon /* 1658e352c813SSeungwon Jeon * If err has non-zero, 1659e352c813SSeungwon Jeon * stop-abort command has been already issued. 1660e352c813SSeungwon Jeon */ 1661e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1662e352c813SSeungwon Jeon 1663f95f3850SWill Newton /* fall through */ 1664f95f3850SWill Newton 1665f95f3850SWill Newton case STATE_SENDING_STOP: 1666f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1667f95f3850SWill Newton &host->pending_events)) 1668f95f3850SWill Newton break; 1669f95f3850SWill Newton 167071abb133SSeungwon Jeon /* CMD error in data command */ 167131bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 16723a33a94cSSonny Rao dw_mci_reset(host); 167371abb133SSeungwon Jeon 1674f95f3850SWill Newton host->cmd = NULL; 167571abb133SSeungwon Jeon host->data = NULL; 167690c2143aSSeungwon Jeon 1677e352c813SSeungwon Jeon if (mrq->stop) 1678e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 167990c2143aSSeungwon Jeon else 168090c2143aSSeungwon Jeon host->cmd_status = 0; 168190c2143aSSeungwon Jeon 1682e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1683f95f3850SWill Newton goto unlock; 1684f95f3850SWill Newton 1685f95f3850SWill Newton case STATE_DATA_ERROR: 1686f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1687f95f3850SWill Newton &host->pending_events)) 1688f95f3850SWill Newton break; 1689f95f3850SWill Newton 1690f95f3850SWill Newton state = STATE_DATA_BUSY; 1691f95f3850SWill Newton break; 1692f95f3850SWill Newton } 1693f95f3850SWill Newton } while (state != prev_state); 1694f95f3850SWill Newton 1695f95f3850SWill Newton host->state = state; 1696f95f3850SWill Newton unlock: 1697f95f3850SWill Newton spin_unlock(&host->lock); 1698f95f3850SWill Newton 1699f95f3850SWill Newton } 1700f95f3850SWill Newton 170134b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 170234b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 170334b664a2SJames Hogan { 170434b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 170534b664a2SJames Hogan host->part_buf_count = cnt; 170634b664a2SJames Hogan } 170734b664a2SJames Hogan 170834b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 170934b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 171034b664a2SJames Hogan { 171134b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 171234b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 171334b664a2SJames Hogan host->part_buf_count += cnt; 171434b664a2SJames Hogan return cnt; 171534b664a2SJames Hogan } 171634b664a2SJames Hogan 171734b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 171834b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 171934b664a2SJames Hogan { 172034b664a2SJames Hogan cnt = min(cnt, (int)host->part_buf_count); 172134b664a2SJames Hogan if (cnt) { 172234b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 172334b664a2SJames Hogan cnt); 172434b664a2SJames Hogan host->part_buf_count -= cnt; 172534b664a2SJames Hogan host->part_buf_start += cnt; 172634b664a2SJames Hogan } 172734b664a2SJames Hogan return cnt; 172834b664a2SJames Hogan } 172934b664a2SJames Hogan 173034b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 173134b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 173234b664a2SJames Hogan { 173334b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 173434b664a2SJames Hogan host->part_buf_start = cnt; 173534b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 173634b664a2SJames Hogan } 173734b664a2SJames Hogan 1738f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1739f95f3850SWill Newton { 1740cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1741cfbeb59cSMarkos Chandras int init_cnt = cnt; 1742cfbeb59cSMarkos Chandras 174334b664a2SJames Hogan /* try and push anything in the part_buf */ 174434b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 174534b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 174634b664a2SJames Hogan buf += len; 174734b664a2SJames Hogan cnt -= len; 1748cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 17494e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17504e0a5adfSJaehoon Chung host->part_buf16); 175134b664a2SJames Hogan host->part_buf_count = 0; 175234b664a2SJames Hogan } 175334b664a2SJames Hogan } 175434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 175534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 175634b664a2SJames Hogan while (cnt >= 2) { 175734b664a2SJames Hogan u16 aligned_buf[64]; 175834b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 175934b664a2SJames Hogan int items = len >> 1; 176034b664a2SJames Hogan int i; 176134b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 176234b664a2SJames Hogan memcpy(aligned_buf, buf, len); 176334b664a2SJames Hogan buf += len; 176434b664a2SJames Hogan cnt -= len; 176534b664a2SJames Hogan /* push data from aligned buffer into fifo */ 176634b664a2SJames Hogan for (i = 0; i < items; ++i) 17674e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17684e0a5adfSJaehoon Chung aligned_buf[i]); 176934b664a2SJames Hogan } 177034b664a2SJames Hogan } else 177134b664a2SJames Hogan #endif 177234b664a2SJames Hogan { 177334b664a2SJames Hogan u16 *pdata = buf; 177434b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 17754e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), *pdata++); 177634b664a2SJames Hogan buf = pdata; 177734b664a2SJames Hogan } 177834b664a2SJames Hogan /* put anything remaining in the part_buf */ 177934b664a2SJames Hogan if (cnt) { 178034b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1781cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1782cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1783cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 17844e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17854e0a5adfSJaehoon Chung host->part_buf16); 1786f95f3850SWill Newton } 1787f95f3850SWill Newton } 1788f95f3850SWill Newton 1789f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1790f95f3850SWill Newton { 179134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 179234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 179334b664a2SJames Hogan while (cnt >= 2) { 179434b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 179534b664a2SJames Hogan u16 aligned_buf[64]; 179634b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 179734b664a2SJames Hogan int items = len >> 1; 179834b664a2SJames Hogan int i; 179934b664a2SJames Hogan for (i = 0; i < items; ++i) 18004e0a5adfSJaehoon Chung aligned_buf[i] = mci_readw(host, 18014e0a5adfSJaehoon Chung DATA(host->data_offset)); 180234b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 180334b664a2SJames Hogan memcpy(buf, aligned_buf, len); 180434b664a2SJames Hogan buf += len; 180534b664a2SJames Hogan cnt -= len; 180634b664a2SJames Hogan } 180734b664a2SJames Hogan } else 180834b664a2SJames Hogan #endif 180934b664a2SJames Hogan { 181034b664a2SJames Hogan u16 *pdata = buf; 181134b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 18124e0a5adfSJaehoon Chung *pdata++ = mci_readw(host, DATA(host->data_offset)); 181334b664a2SJames Hogan buf = pdata; 181434b664a2SJames Hogan } 181534b664a2SJames Hogan if (cnt) { 18164e0a5adfSJaehoon Chung host->part_buf16 = mci_readw(host, DATA(host->data_offset)); 181734b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1818f95f3850SWill Newton } 1819f95f3850SWill Newton } 1820f95f3850SWill Newton 1821f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1822f95f3850SWill Newton { 1823cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1824cfbeb59cSMarkos Chandras int init_cnt = cnt; 1825cfbeb59cSMarkos Chandras 182634b664a2SJames Hogan /* try and push anything in the part_buf */ 182734b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 182834b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 182934b664a2SJames Hogan buf += len; 183034b664a2SJames Hogan cnt -= len; 1831cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 18324e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18334e0a5adfSJaehoon Chung host->part_buf32); 183434b664a2SJames Hogan host->part_buf_count = 0; 183534b664a2SJames Hogan } 183634b664a2SJames Hogan } 183734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 183834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 183934b664a2SJames Hogan while (cnt >= 4) { 184034b664a2SJames Hogan u32 aligned_buf[32]; 184134b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 184234b664a2SJames Hogan int items = len >> 2; 184334b664a2SJames Hogan int i; 184434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 184534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 184634b664a2SJames Hogan buf += len; 184734b664a2SJames Hogan cnt -= len; 184834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 184934b664a2SJames Hogan for (i = 0; i < items; ++i) 18504e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18514e0a5adfSJaehoon Chung aligned_buf[i]); 185234b664a2SJames Hogan } 185334b664a2SJames Hogan } else 185434b664a2SJames Hogan #endif 185534b664a2SJames Hogan { 185634b664a2SJames Hogan u32 *pdata = buf; 185734b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 18584e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), *pdata++); 185934b664a2SJames Hogan buf = pdata; 186034b664a2SJames Hogan } 186134b664a2SJames Hogan /* put anything remaining in the part_buf */ 186234b664a2SJames Hogan if (cnt) { 186334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1864cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1865cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1866cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 18674e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18684e0a5adfSJaehoon Chung host->part_buf32); 1869f95f3850SWill Newton } 1870f95f3850SWill Newton } 1871f95f3850SWill Newton 1872f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1873f95f3850SWill Newton { 187434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 187534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 187634b664a2SJames Hogan while (cnt >= 4) { 187734b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 187834b664a2SJames Hogan u32 aligned_buf[32]; 187934b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 188034b664a2SJames Hogan int items = len >> 2; 188134b664a2SJames Hogan int i; 188234b664a2SJames Hogan for (i = 0; i < items; ++i) 18834e0a5adfSJaehoon Chung aligned_buf[i] = mci_readl(host, 18844e0a5adfSJaehoon Chung DATA(host->data_offset)); 188534b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 188634b664a2SJames Hogan memcpy(buf, aligned_buf, len); 188734b664a2SJames Hogan buf += len; 188834b664a2SJames Hogan cnt -= len; 188934b664a2SJames Hogan } 189034b664a2SJames Hogan } else 189134b664a2SJames Hogan #endif 189234b664a2SJames Hogan { 189334b664a2SJames Hogan u32 *pdata = buf; 189434b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 18954e0a5adfSJaehoon Chung *pdata++ = mci_readl(host, DATA(host->data_offset)); 189634b664a2SJames Hogan buf = pdata; 189734b664a2SJames Hogan } 189834b664a2SJames Hogan if (cnt) { 18994e0a5adfSJaehoon Chung host->part_buf32 = mci_readl(host, DATA(host->data_offset)); 190034b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1901f95f3850SWill Newton } 1902f95f3850SWill Newton } 1903f95f3850SWill Newton 1904f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1905f95f3850SWill Newton { 1906cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1907cfbeb59cSMarkos Chandras int init_cnt = cnt; 1908cfbeb59cSMarkos Chandras 190934b664a2SJames Hogan /* try and push anything in the part_buf */ 191034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 191134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 191234b664a2SJames Hogan buf += len; 191334b664a2SJames Hogan cnt -= len; 1914c09fbd74SSeungwon Jeon 1915cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 1916c09fbd74SSeungwon Jeon mci_writeq(host, DATA(host->data_offset), 19174e0a5adfSJaehoon Chung host->part_buf); 191834b664a2SJames Hogan host->part_buf_count = 0; 191934b664a2SJames Hogan } 192034b664a2SJames Hogan } 192134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 192234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 192334b664a2SJames Hogan while (cnt >= 8) { 192434b664a2SJames Hogan u64 aligned_buf[16]; 192534b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 192634b664a2SJames Hogan int items = len >> 3; 192734b664a2SJames Hogan int i; 192834b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 192934b664a2SJames Hogan memcpy(aligned_buf, buf, len); 193034b664a2SJames Hogan buf += len; 193134b664a2SJames Hogan cnt -= len; 193234b664a2SJames Hogan /* push data from aligned buffer into fifo */ 193334b664a2SJames Hogan for (i = 0; i < items; ++i) 19344e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 19354e0a5adfSJaehoon Chung aligned_buf[i]); 193634b664a2SJames Hogan } 193734b664a2SJames Hogan } else 193834b664a2SJames Hogan #endif 193934b664a2SJames Hogan { 194034b664a2SJames Hogan u64 *pdata = buf; 194134b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 19424e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), *pdata++); 194334b664a2SJames Hogan buf = pdata; 194434b664a2SJames Hogan } 194534b664a2SJames Hogan /* put anything remaining in the part_buf */ 194634b664a2SJames Hogan if (cnt) { 194734b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1948cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1949cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1950cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 19514e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 19524e0a5adfSJaehoon Chung host->part_buf); 1953f95f3850SWill Newton } 1954f95f3850SWill Newton } 1955f95f3850SWill Newton 1956f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1957f95f3850SWill Newton { 195834b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 195934b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 196034b664a2SJames Hogan while (cnt >= 8) { 196134b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 196234b664a2SJames Hogan u64 aligned_buf[16]; 196334b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 196434b664a2SJames Hogan int items = len >> 3; 196534b664a2SJames Hogan int i; 196634b664a2SJames Hogan for (i = 0; i < items; ++i) 19674e0a5adfSJaehoon Chung aligned_buf[i] = mci_readq(host, 19684e0a5adfSJaehoon Chung DATA(host->data_offset)); 196934b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 197034b664a2SJames Hogan memcpy(buf, aligned_buf, len); 197134b664a2SJames Hogan buf += len; 197234b664a2SJames Hogan cnt -= len; 1973f95f3850SWill Newton } 197434b664a2SJames Hogan } else 197534b664a2SJames Hogan #endif 197634b664a2SJames Hogan { 197734b664a2SJames Hogan u64 *pdata = buf; 197834b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 19794e0a5adfSJaehoon Chung *pdata++ = mci_readq(host, DATA(host->data_offset)); 198034b664a2SJames Hogan buf = pdata; 198134b664a2SJames Hogan } 198234b664a2SJames Hogan if (cnt) { 19834e0a5adfSJaehoon Chung host->part_buf = mci_readq(host, DATA(host->data_offset)); 198434b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 198534b664a2SJames Hogan } 198634b664a2SJames Hogan } 198734b664a2SJames Hogan 198834b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 198934b664a2SJames Hogan { 199034b664a2SJames Hogan int len; 199134b664a2SJames Hogan 199234b664a2SJames Hogan /* get remaining partial bytes */ 199334b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 199434b664a2SJames Hogan if (unlikely(len == cnt)) 199534b664a2SJames Hogan return; 199634b664a2SJames Hogan buf += len; 199734b664a2SJames Hogan cnt -= len; 199834b664a2SJames Hogan 199934b664a2SJames Hogan /* get the rest of the data */ 200034b664a2SJames Hogan host->pull_data(host, buf, cnt); 2001f95f3850SWill Newton } 2002f95f3850SWill Newton 200387a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2004f95f3850SWill Newton { 2005f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2006f9c2a0dcSSeungwon Jeon void *buf; 2007f9c2a0dcSSeungwon Jeon unsigned int offset; 2008f95f3850SWill Newton struct mmc_data *data = host->data; 2009f95f3850SWill Newton int shift = host->data_shift; 2010f95f3850SWill Newton u32 status; 20113e4b0d8bSMarkos Chandras unsigned int len; 2012f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2013f95f3850SWill Newton 2014f95f3850SWill Newton do { 2015f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2016f9c2a0dcSSeungwon Jeon goto done; 2017f95f3850SWill Newton 20184225fc85SImre Deak host->sg = sg_miter->piter.sg; 2019f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2020f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2021f9c2a0dcSSeungwon Jeon offset = 0; 2022f9c2a0dcSSeungwon Jeon 2023f9c2a0dcSSeungwon Jeon do { 2024f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2025f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2026f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2027f9c2a0dcSSeungwon Jeon if (!len) 2028f9c2a0dcSSeungwon Jeon break; 2029f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 20303e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2031f95f3850SWill Newton offset += len; 2032f9c2a0dcSSeungwon Jeon remain -= len; 2033f9c2a0dcSSeungwon Jeon } while (remain); 2034f95f3850SWill Newton 2035e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2036f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2037f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 203887a74d39SKyoungil Kim /* if the RXDR is ready read again */ 203987a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 204087a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2041f9c2a0dcSSeungwon Jeon 2042f9c2a0dcSSeungwon Jeon if (!remain) { 2043f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2044f9c2a0dcSSeungwon Jeon goto done; 2045f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2046f9c2a0dcSSeungwon Jeon } 2047f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2048f95f3850SWill Newton return; 2049f95f3850SWill Newton 2050f95f3850SWill Newton done: 2051f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2052f9c2a0dcSSeungwon Jeon host->sg = NULL; 2053f95f3850SWill Newton smp_wmb(); 2054f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2055f95f3850SWill Newton } 2056f95f3850SWill Newton 2057f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2058f95f3850SWill Newton { 2059f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2060f9c2a0dcSSeungwon Jeon void *buf; 2061f9c2a0dcSSeungwon Jeon unsigned int offset; 2062f95f3850SWill Newton struct mmc_data *data = host->data; 2063f95f3850SWill Newton int shift = host->data_shift; 2064f95f3850SWill Newton u32 status; 20653e4b0d8bSMarkos Chandras unsigned int len; 2066f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2067f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2068f95f3850SWill Newton 2069f95f3850SWill Newton do { 2070f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2071f9c2a0dcSSeungwon Jeon goto done; 2072f95f3850SWill Newton 20734225fc85SImre Deak host->sg = sg_miter->piter.sg; 2074f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2075f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2076f9c2a0dcSSeungwon Jeon offset = 0; 2077f9c2a0dcSSeungwon Jeon 2078f9c2a0dcSSeungwon Jeon do { 2079f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2080f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2081f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2082f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2083f9c2a0dcSSeungwon Jeon if (!len) 2084f9c2a0dcSSeungwon Jeon break; 2085f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 20863e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2087f95f3850SWill Newton offset += len; 2088f9c2a0dcSSeungwon Jeon remain -= len; 2089f9c2a0dcSSeungwon Jeon } while (remain); 2090f95f3850SWill Newton 2091e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2092f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2093f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2094f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2095f9c2a0dcSSeungwon Jeon 2096f9c2a0dcSSeungwon Jeon if (!remain) { 2097f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2098f9c2a0dcSSeungwon Jeon goto done; 2099f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2100f9c2a0dcSSeungwon Jeon } 2101f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2102f95f3850SWill Newton return; 2103f95f3850SWill Newton 2104f95f3850SWill Newton done: 2105f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2106f9c2a0dcSSeungwon Jeon host->sg = NULL; 2107f95f3850SWill Newton smp_wmb(); 2108f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2109f95f3850SWill Newton } 2110f95f3850SWill Newton 2111f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2112f95f3850SWill Newton { 2113f95f3850SWill Newton if (!host->cmd_status) 2114f95f3850SWill Newton host->cmd_status = status; 2115f95f3850SWill Newton 2116f95f3850SWill Newton smp_wmb(); 2117f95f3850SWill Newton 2118f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2119f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2120f95f3850SWill Newton } 2121f95f3850SWill Newton 21226130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 21236130e7a9SDoug Anderson { 21246130e7a9SDoug Anderson int i; 21256130e7a9SDoug Anderson 21266130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 21276130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 21286130e7a9SDoug Anderson 21296130e7a9SDoug Anderson if (!slot) 21306130e7a9SDoug Anderson continue; 21316130e7a9SDoug Anderson 21326130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 21336130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 21346130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 21356130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 21366130e7a9SDoug Anderson } 21376130e7a9SDoug Anderson } 21386130e7a9SDoug Anderson 2139f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2140f95f3850SWill Newton { 2141f95f3850SWill Newton struct dw_mci *host = dev_id; 2142182c9081SSeungwon Jeon u32 pending; 21431a5c8e1fSShashidhar Hiremath int i; 2144f95f3850SWill Newton 2145f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2146f95f3850SWill Newton 2147f95f3850SWill Newton /* 2148f95f3850SWill Newton * DTO fix - version 2.10a and below, and only if internal DMA 2149f95f3850SWill Newton * is configured. 2150f95f3850SWill Newton */ 2151f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2152f95f3850SWill Newton if (!pending && 2153f95f3850SWill Newton ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2154f95f3850SWill Newton pending |= SDMMC_INT_DATA_OVER; 2155f95f3850SWill Newton } 2156f95f3850SWill Newton 2157476d79f1SDoug Anderson if (pending) { 215801730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 215901730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 216001730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 216101730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 216201730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 216301730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 216401730558SDoug Anderson } 216501730558SDoug Anderson 2166f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2167f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2168182c9081SSeungwon Jeon host->cmd_status = pending; 2169f95f3850SWill Newton smp_wmb(); 2170f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2171f95f3850SWill Newton } 2172f95f3850SWill Newton 2173f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2174f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2175f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2176182c9081SSeungwon Jeon host->data_status = pending; 2177f95f3850SWill Newton smp_wmb(); 2178f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2179f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2180f95f3850SWill Newton } 2181f95f3850SWill Newton 2182f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 2183f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2184f95f3850SWill Newton if (!host->data_status) 2185182c9081SSeungwon Jeon host->data_status = pending; 2186f95f3850SWill Newton smp_wmb(); 2187f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2188f95f3850SWill Newton if (host->sg != NULL) 218987a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2190f95f3850SWill Newton } 2191f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2192f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2193f95f3850SWill Newton } 2194f95f3850SWill Newton 2195f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2196f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2197b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 219887a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2199f95f3850SWill Newton } 2200f95f3850SWill Newton 2201f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2202f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2203b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2204f95f3850SWill Newton dw_mci_write_data_pio(host); 2205f95f3850SWill Newton } 2206f95f3850SWill Newton 2207f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2208f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2209182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2210f95f3850SWill Newton } 2211f95f3850SWill Newton 2212f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2213f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 22146130e7a9SDoug Anderson dw_mci_handle_cd(host); 2215f95f3850SWill Newton } 2216f95f3850SWill Newton 22171a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 22181a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 22191a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 222076756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 222176756234SAddy Ke mci_writel(host, RINTSTS, 222276756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 22231a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 22241a5c8e1fSShashidhar Hiremath } 22251a5c8e1fSShashidhar Hiremath } 22261a5c8e1fSShashidhar Hiremath 22271fb5f68aSMarkos Chandras } 2228f95f3850SWill Newton 2229f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2230f95f3850SWill Newton /* Handle DMA interrupts */ 223169d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 223269d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 223369d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 223469d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 223569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 223669d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 223769d99fdcSPrabu Thangamuthu host->dma_ops->complete(host); 223869d99fdcSPrabu Thangamuthu } 223969d99fdcSPrabu Thangamuthu } else { 2240f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2241f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 224269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 224369d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2244f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2245f95f3850SWill Newton host->dma_ops->complete(host); 2246f95f3850SWill Newton } 224769d99fdcSPrabu Thangamuthu } 2248f95f3850SWill Newton #endif 2249f95f3850SWill Newton 2250f95f3850SWill Newton return IRQ_HANDLED; 2251f95f3850SWill Newton } 2252f95f3850SWill Newton 2253c91eab4bSThomas Abraham #ifdef CONFIG_OF 2254c91eab4bSThomas Abraham /* given a slot id, find out the device node representing that slot */ 2255c91eab4bSThomas Abraham static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 2256c91eab4bSThomas Abraham { 2257c91eab4bSThomas Abraham struct device_node *np; 2258c91eab4bSThomas Abraham const __be32 *addr; 2259c91eab4bSThomas Abraham int len; 2260c91eab4bSThomas Abraham 2261c91eab4bSThomas Abraham if (!dev || !dev->of_node) 2262c91eab4bSThomas Abraham return NULL; 2263c91eab4bSThomas Abraham 2264c91eab4bSThomas Abraham for_each_child_of_node(dev->of_node, np) { 2265c91eab4bSThomas Abraham addr = of_get_property(np, "reg", &len); 2266c91eab4bSThomas Abraham if (!addr || (len < sizeof(int))) 2267c91eab4bSThomas Abraham continue; 2268c91eab4bSThomas Abraham if (be32_to_cpup(addr) == slot) 2269c91eab4bSThomas Abraham return np; 2270c91eab4bSThomas Abraham } 2271c91eab4bSThomas Abraham return NULL; 2272c91eab4bSThomas Abraham } 2273c91eab4bSThomas Abraham 2274a70aaa64SDoug Anderson static struct dw_mci_of_slot_quirks { 2275a70aaa64SDoug Anderson char *quirk; 2276a70aaa64SDoug Anderson int id; 2277a70aaa64SDoug Anderson } of_slot_quirks[] = { 2278a70aaa64SDoug Anderson { 2279a70aaa64SDoug Anderson .quirk = "disable-wp", 2280a70aaa64SDoug Anderson .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, 2281a70aaa64SDoug Anderson }, 2282a70aaa64SDoug Anderson }; 2283a70aaa64SDoug Anderson 2284a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2285a70aaa64SDoug Anderson { 2286a70aaa64SDoug Anderson struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 2287a70aaa64SDoug Anderson int quirks = 0; 2288a70aaa64SDoug Anderson int idx; 2289a70aaa64SDoug Anderson 2290a70aaa64SDoug Anderson /* get quirks */ 2291a70aaa64SDoug Anderson for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) 229226375b5cSJaehoon Chung if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) { 229326375b5cSJaehoon Chung dev_warn(dev, "Slot quirk %s is deprecated\n", 229426375b5cSJaehoon Chung of_slot_quirks[idx].quirk); 2295a70aaa64SDoug Anderson quirks |= of_slot_quirks[idx].id; 229626375b5cSJaehoon Chung } 2297a70aaa64SDoug Anderson 2298a70aaa64SDoug Anderson return quirks; 2299a70aaa64SDoug Anderson } 2300c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2301a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2302a70aaa64SDoug Anderson { 2303a70aaa64SDoug Anderson return 0; 2304a70aaa64SDoug Anderson } 2305c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2306c91eab4bSThomas Abraham 230736c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2308f95f3850SWill Newton { 2309f95f3850SWill Newton struct mmc_host *mmc; 2310f95f3850SWill Newton struct dw_mci_slot *slot; 2311e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2312800d78bfSThomas Abraham int ctrl_id, ret; 23131f44a2a5SSeungwon Jeon u32 freq[2]; 2314f95f3850SWill Newton 23154a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2316f95f3850SWill Newton if (!mmc) 2317f95f3850SWill Newton return -ENOMEM; 2318f95f3850SWill Newton 2319f95f3850SWill Newton slot = mmc_priv(mmc); 2320f95f3850SWill Newton slot->id = id; 232176756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2322f95f3850SWill Newton slot->mmc = mmc; 2323f95f3850SWill Newton slot->host = host; 2324c91eab4bSThomas Abraham host->slot[id] = slot; 2325f95f3850SWill Newton 2326a70aaa64SDoug Anderson slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 2327a70aaa64SDoug Anderson 2328f95f3850SWill Newton mmc->ops = &dw_mci_ops; 23291f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 23301f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 23311f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 23321f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 23331f44a2a5SSeungwon Jeon } else { 23341f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 23351f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 23361f44a2a5SSeungwon Jeon } 2337f95f3850SWill Newton 233851da2240SYuvaraj CD /*if there are external regulators, get them*/ 233951da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 234051da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 23413cf890fcSDoug Anderson goto err_host_allocated; 234251da2240SYuvaraj CD 234351da2240SYuvaraj CD if (!mmc->ocr_avail) 2344f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2345f95f3850SWill Newton 2346fc3d7720SJaehoon Chung if (host->pdata->caps) 2347fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2348fc3d7720SJaehoon Chung 2349ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2350ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2351ab269128SAbhilash Kesavan 2352800d78bfSThomas Abraham if (host->dev->of_node) { 2353800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2354800d78bfSThomas Abraham if (ctrl_id < 0) 2355800d78bfSThomas Abraham ctrl_id = 0; 2356800d78bfSThomas Abraham } else { 2357800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2358800d78bfSThomas Abraham } 2359cb27a843SJames Hogan if (drv_data && drv_data->caps) 2360cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2361800d78bfSThomas Abraham 23624f408cc6SSeungwon Jeon if (host->pdata->caps2) 23634f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 23644f408cc6SSeungwon Jeon 23653cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 23663cf890fcSDoug Anderson if (ret) 23673cf890fcSDoug Anderson goto err_host_allocated; 2368f95f3850SWill Newton 2369f95f3850SWill Newton if (host->pdata->blk_settings) { 2370f95f3850SWill Newton mmc->max_segs = host->pdata->blk_settings->max_segs; 2371f95f3850SWill Newton mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 2372f95f3850SWill Newton mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 2373f95f3850SWill Newton mmc->max_req_size = host->pdata->blk_settings->max_req_size; 2374f95f3850SWill Newton mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 2375f95f3850SWill Newton } else { 2376f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 2377a39e5746SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 2378a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2379a39e5746SJaehoon Chung mmc->max_blk_size = 65536; 2380a39e5746SJaehoon Chung mmc->max_seg_size = 0x1000; 23811a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 23821a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 2383a39e5746SJaehoon Chung #else 2384f95f3850SWill Newton mmc->max_segs = 64; 2385f95f3850SWill Newton mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2386f95f3850SWill Newton mmc->max_blk_count = 512; 2387f95f3850SWill Newton mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2388f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2389f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 2390a39e5746SJaehoon Chung } 2391f95f3850SWill Newton 2392ae0eb348SJaehoon Chung if (dw_mci_get_cd(mmc)) 2393ae0eb348SJaehoon Chung set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2394ae0eb348SJaehoon Chung else 2395ae0eb348SJaehoon Chung clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2396ae0eb348SJaehoon Chung 23970cea529dSJaehoon Chung ret = mmc_add_host(mmc); 23980cea529dSJaehoon Chung if (ret) 23993cf890fcSDoug Anderson goto err_host_allocated; 2400f95f3850SWill Newton 2401f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2402f95f3850SWill Newton dw_mci_init_debugfs(slot); 2403f95f3850SWill Newton #endif 2404f95f3850SWill Newton 2405f95f3850SWill Newton return 0; 2406800d78bfSThomas Abraham 24073cf890fcSDoug Anderson err_host_allocated: 2408800d78bfSThomas Abraham mmc_free_host(mmc); 240951da2240SYuvaraj CD return ret; 2410f95f3850SWill Newton } 2411f95f3850SWill Newton 2412f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2413f95f3850SWill Newton { 2414f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2415f95f3850SWill Newton mmc_remove_host(slot->mmc); 2416f95f3850SWill Newton slot->host->slot[id] = NULL; 2417f95f3850SWill Newton mmc_free_host(slot->mmc); 2418f95f3850SWill Newton } 2419f95f3850SWill Newton 2420f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2421f95f3850SWill Newton { 242269d99fdcSPrabu Thangamuthu int addr_config; 242369d99fdcSPrabu Thangamuthu /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ 242469d99fdcSPrabu Thangamuthu addr_config = (mci_readl(host, HCON) >> 27) & 0x01; 242569d99fdcSPrabu Thangamuthu 242669d99fdcSPrabu Thangamuthu if (addr_config == 1) { 242769d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 242869d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 242969d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); 243069d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 243169d99fdcSPrabu Thangamuthu dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); 243269d99fdcSPrabu Thangamuthu } else { 243369d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 243469d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 243569d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); 243669d99fdcSPrabu Thangamuthu } 243769d99fdcSPrabu Thangamuthu 2438f95f3850SWill Newton /* Alloc memory for sg translation */ 2439780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2440f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2441f95f3850SWill Newton if (!host->sg_cpu) { 24424a90920cSThomas Abraham dev_err(host->dev, "%s: could not alloc DMA memory\n", 2443f95f3850SWill Newton __func__); 2444f95f3850SWill Newton goto no_dma; 2445f95f3850SWill Newton } 2446f95f3850SWill Newton 2447f95f3850SWill Newton /* Determine which DMA interface to use */ 2448f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2449f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 245000956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 2451f95f3850SWill Newton #endif 2452f95f3850SWill Newton 2453f95f3850SWill Newton if (!host->dma_ops) 2454f95f3850SWill Newton goto no_dma; 2455f95f3850SWill Newton 2456e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2457e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2458f95f3850SWill Newton if (host->dma_ops->init(host)) { 24594a90920cSThomas Abraham dev_err(host->dev, "%s: Unable to initialize " 2460f95f3850SWill Newton "DMA Controller.\n", __func__); 2461f95f3850SWill Newton goto no_dma; 2462f95f3850SWill Newton } 2463f95f3850SWill Newton } else { 24644a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2465f95f3850SWill Newton goto no_dma; 2466f95f3850SWill Newton } 2467f95f3850SWill Newton 2468f95f3850SWill Newton host->use_dma = 1; 2469f95f3850SWill Newton return; 2470f95f3850SWill Newton 2471f95f3850SWill Newton no_dma: 24724a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 2473f95f3850SWill Newton host->use_dma = 0; 2474f95f3850SWill Newton return; 2475f95f3850SWill Newton } 2476f95f3850SWill Newton 247731bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2478f95f3850SWill Newton { 2479f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 248031bff450SSeungwon Jeon u32 ctrl; 2481f95f3850SWill Newton 248231bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 248331bff450SSeungwon Jeon ctrl |= reset; 248431bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2485f95f3850SWill Newton 2486f95f3850SWill Newton /* wait till resets clear */ 2487f95f3850SWill Newton do { 2488f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 248931bff450SSeungwon Jeon if (!(ctrl & reset)) 2490f95f3850SWill Newton return true; 2491f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2492f95f3850SWill Newton 249331bff450SSeungwon Jeon dev_err(host->dev, 249431bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 249531bff450SSeungwon Jeon ctrl & reset); 2496f95f3850SWill Newton 2497f95f3850SWill Newton return false; 2498f95f3850SWill Newton } 2499f95f3850SWill Newton 25003a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 250131bff450SSeungwon Jeon { 25023a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 25033a33a94cSSonny Rao bool ret = false; 25043a33a94cSSonny Rao 250531bff450SSeungwon Jeon /* 250631bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 250731bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 250831bff450SSeungwon Jeon */ 250931bff450SSeungwon Jeon if (host->sg) { 251031bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 251131bff450SSeungwon Jeon host->sg = NULL; 251231bff450SSeungwon Jeon } 251331bff450SSeungwon Jeon 25143a33a94cSSonny Rao if (host->use_dma) 25153a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 25163a33a94cSSonny Rao 25173a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 25183a33a94cSSonny Rao /* 25193a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 25203a33a94cSSonny Rao * interrupts. 25213a33a94cSSonny Rao */ 25223a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 25233a33a94cSSonny Rao 25243a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 25253a33a94cSSonny Rao if (host->use_dma) { 25263a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 25273a33a94cSSonny Rao u32 status; 25283a33a94cSSonny Rao do { 25293a33a94cSSonny Rao status = mci_readl(host, STATUS); 25303a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 25313a33a94cSSonny Rao break; 25323a33a94cSSonny Rao cpu_relax(); 25333a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 25343a33a94cSSonny Rao 25353a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 25363a33a94cSSonny Rao dev_err(host->dev, 25373a33a94cSSonny Rao "%s: Timeout waiting for dma_req to " 25383a33a94cSSonny Rao "clear during reset\n", __func__); 25393a33a94cSSonny Rao goto ciu_out; 254031bff450SSeungwon Jeon } 254131bff450SSeungwon Jeon 25423a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 25433a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 25443a33a94cSSonny Rao goto ciu_out; 25453a33a94cSSonny Rao } 25463a33a94cSSonny Rao } else { 25473a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 25483a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 25493a33a94cSSonny Rao dev_err(host->dev, "%s: fifo/dma reset bits didn't " 25503a33a94cSSonny Rao "clear but ciu was reset, doing clock update\n", 25513a33a94cSSonny Rao __func__); 25523a33a94cSSonny Rao goto ciu_out; 25533a33a94cSSonny Rao } 25543a33a94cSSonny Rao } 25553a33a94cSSonny Rao 25563a33a94cSSonny Rao #if IS_ENABLED(CONFIG_MMC_DW_IDMAC) 25573a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 25583a33a94cSSonny Rao dw_mci_idmac_reset(host); 25593a33a94cSSonny Rao #endif 25603a33a94cSSonny Rao 25613a33a94cSSonny Rao ret = true; 25623a33a94cSSonny Rao 25633a33a94cSSonny Rao ciu_out: 25643a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 25653a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 25663a33a94cSSonny Rao 25673a33a94cSSonny Rao return ret; 256831bff450SSeungwon Jeon } 256931bff450SSeungwon Jeon 2570c91eab4bSThomas Abraham #ifdef CONFIG_OF 2571c91eab4bSThomas Abraham static struct dw_mci_of_quirks { 2572c91eab4bSThomas Abraham char *quirk; 2573c91eab4bSThomas Abraham int id; 2574c91eab4bSThomas Abraham } of_quirks[] = { 2575c91eab4bSThomas Abraham { 2576c91eab4bSThomas Abraham .quirk = "broken-cd", 2577c91eab4bSThomas Abraham .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 257826375b5cSJaehoon Chung }, { 257926375b5cSJaehoon Chung .quirk = "disable-wp", 258026375b5cSJaehoon Chung .id = DW_MCI_QUIRK_NO_WRITE_PROTECT, 2581c91eab4bSThomas Abraham }, 2582c91eab4bSThomas Abraham }; 2583c91eab4bSThomas Abraham 2584c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2585c91eab4bSThomas Abraham { 2586c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2587c91eab4bSThomas Abraham struct device *dev = host->dev; 2588c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2589e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2590800d78bfSThomas Abraham int idx, ret; 25913c6d89eaSDoug Anderson u32 clock_frequency; 2592c91eab4bSThomas Abraham 2593c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2594bf3707eaSBeomho Seo if (!pdata) 2595c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2596c91eab4bSThomas Abraham 2597c91eab4bSThomas Abraham /* find out number of slots supported */ 2598c91eab4bSThomas Abraham if (of_property_read_u32(dev->of_node, "num-slots", 2599c91eab4bSThomas Abraham &pdata->num_slots)) { 2600c91eab4bSThomas Abraham dev_info(dev, "num-slots property not found, " 2601c91eab4bSThomas Abraham "assuming 1 slot is available\n"); 2602c91eab4bSThomas Abraham pdata->num_slots = 1; 2603c91eab4bSThomas Abraham } 2604c91eab4bSThomas Abraham 2605c91eab4bSThomas Abraham /* get quirks */ 2606c91eab4bSThomas Abraham for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2607c91eab4bSThomas Abraham if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2608c91eab4bSThomas Abraham pdata->quirks |= of_quirks[idx].id; 2609c91eab4bSThomas Abraham 2610c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2611c91eab4bSThomas Abraham dev_info(dev, "fifo-depth property not found, using " 2612c91eab4bSThomas Abraham "value of FIFOTH register as default\n"); 2613c91eab4bSThomas Abraham 2614c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2615c91eab4bSThomas Abraham 26163c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 26173c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 26183c6d89eaSDoug Anderson 2619cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2620cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2621800d78bfSThomas Abraham if (ret) 2622800d78bfSThomas Abraham return ERR_PTR(ret); 2623800d78bfSThomas Abraham } 2624800d78bfSThomas Abraham 262510b49841SSeungwon Jeon if (of_find_property(np, "supports-highspeed", NULL)) 262610b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 262710b49841SSeungwon Jeon 2628c91eab4bSThomas Abraham return pdata; 2629c91eab4bSThomas Abraham } 2630c91eab4bSThomas Abraham 2631c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2632c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2633c91eab4bSThomas Abraham { 2634c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2635c91eab4bSThomas Abraham } 2636c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2637c91eab4bSThomas Abraham 2638*fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2639*fa0c3283SDoug Anderson { 2640*fa0c3283SDoug Anderson struct dw_mci_board *brd = host->pdata; 2641*fa0c3283SDoug Anderson unsigned long irqflags; 2642*fa0c3283SDoug Anderson u32 temp; 2643*fa0c3283SDoug Anderson int i; 2644*fa0c3283SDoug Anderson 2645*fa0c3283SDoug Anderson /* No need for CD if broken card detection */ 2646*fa0c3283SDoug Anderson if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 2647*fa0c3283SDoug Anderson return; 2648*fa0c3283SDoug Anderson 2649*fa0c3283SDoug Anderson /* No need for CD if all slots have a non-error GPIO */ 2650*fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 2651*fa0c3283SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 2652*fa0c3283SDoug Anderson 2653*fa0c3283SDoug Anderson if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) 2654*fa0c3283SDoug Anderson break; 2655*fa0c3283SDoug Anderson } 2656*fa0c3283SDoug Anderson if (i == host->num_slots) 2657*fa0c3283SDoug Anderson return; 2658*fa0c3283SDoug Anderson 2659*fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 2660*fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 2661*fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 2662*fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 2663*fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2664*fa0c3283SDoug Anderson } 2665*fa0c3283SDoug Anderson 266662ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2667f95f3850SWill Newton { 2668e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 266962ca8034SShashidhar Hiremath int width, i, ret = 0; 2670f95f3850SWill Newton u32 fifo_size; 26711c2215b7SThomas Abraham int init_slots = 0; 2672f95f3850SWill Newton 2673c91eab4bSThomas Abraham if (!host->pdata) { 2674c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2675c91eab4bSThomas Abraham if (IS_ERR(host->pdata)) { 2676c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2677c91eab4bSThomas Abraham return -EINVAL; 2678c91eab4bSThomas Abraham } 2679f95f3850SWill Newton } 2680f95f3850SWill Newton 2681907abd51SJaehoon Chung if (host->pdata->num_slots > 1) { 26824a90920cSThomas Abraham dev_err(host->dev, 2683907abd51SJaehoon Chung "Platform data must supply num_slots.\n"); 268462ca8034SShashidhar Hiremath return -ENODEV; 2685f95f3850SWill Newton } 2686f95f3850SWill Newton 2687780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2688f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2689f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2690f90a0612SThomas Abraham } else { 2691f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2692f90a0612SThomas Abraham if (ret) { 2693f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2694f90a0612SThomas Abraham return ret; 2695f90a0612SThomas Abraham } 2696f95f3850SWill Newton } 2697f95f3850SWill Newton 2698780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2699f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2700f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 27013c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2702f90a0612SThomas Abraham } else { 2703f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2704f90a0612SThomas Abraham if (ret) { 2705f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2706f90a0612SThomas Abraham goto err_clk_biu; 2707f90a0612SThomas Abraham } 2708f90a0612SThomas Abraham 27093c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 27103c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 27113c6d89eaSDoug Anderson if (ret) 27123c6d89eaSDoug Anderson dev_warn(host->dev, 2713612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 27143c6d89eaSDoug Anderson host->pdata->bus_hz); 27153c6d89eaSDoug Anderson } 2716f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 27173c6d89eaSDoug Anderson } 2718f90a0612SThomas Abraham 2719612de4c1SJaehoon Chung if (!host->bus_hz) { 2720612de4c1SJaehoon Chung dev_err(host->dev, 2721612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 2722612de4c1SJaehoon Chung ret = -ENODEV; 2723612de4c1SJaehoon Chung goto err_clk_ciu; 2724612de4c1SJaehoon Chung } 2725612de4c1SJaehoon Chung 2726002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 2727002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 2728002f0d5cSYuvaraj Kumar C D if (ret) { 2729002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 2730002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 2731002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 2732002f0d5cSYuvaraj Kumar C D } 2733002f0d5cSYuvaraj Kumar C D } 2734002f0d5cSYuvaraj Kumar C D 2735cb27a843SJames Hogan if (drv_data && drv_data->setup_clock) { 2736cb27a843SJames Hogan ret = drv_data->setup_clock(host); 2737800d78bfSThomas Abraham if (ret) { 2738800d78bfSThomas Abraham dev_err(host->dev, 2739800d78bfSThomas Abraham "implementation specific clock setup failed\n"); 2740800d78bfSThomas Abraham goto err_clk_ciu; 2741800d78bfSThomas Abraham } 2742800d78bfSThomas Abraham } 2743800d78bfSThomas Abraham 274462ca8034SShashidhar Hiremath host->quirks = host->pdata->quirks; 2745f95f3850SWill Newton 2746f95f3850SWill Newton spin_lock_init(&host->lock); 2747f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 2748f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 2749f95f3850SWill Newton 2750f95f3850SWill Newton /* 2751f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 2752f95f3850SWill Newton * the correct values. 2753f95f3850SWill Newton */ 2754f95f3850SWill Newton i = (mci_readl(host, HCON) >> 7) & 0x7; 2755f95f3850SWill Newton if (!i) { 2756f95f3850SWill Newton host->push_data = dw_mci_push_data16; 2757f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 2758f95f3850SWill Newton width = 16; 2759f95f3850SWill Newton host->data_shift = 1; 2760f95f3850SWill Newton } else if (i == 2) { 2761f95f3850SWill Newton host->push_data = dw_mci_push_data64; 2762f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 2763f95f3850SWill Newton width = 64; 2764f95f3850SWill Newton host->data_shift = 3; 2765f95f3850SWill Newton } else { 2766f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 2767f95f3850SWill Newton WARN((i != 1), 2768f95f3850SWill Newton "HCON reports a reserved host data width!\n" 2769f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 2770f95f3850SWill Newton host->push_data = dw_mci_push_data32; 2771f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 2772f95f3850SWill Newton width = 32; 2773f95f3850SWill Newton host->data_shift = 2; 2774f95f3850SWill Newton } 2775f95f3850SWill Newton 2776f95f3850SWill Newton /* Reset all blocks */ 27773a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 2778141a712aSSeungwon Jeon return -ENODEV; 2779141a712aSSeungwon Jeon 2780141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 2781141a712aSSeungwon Jeon dw_mci_init_dma(host); 2782f95f3850SWill Newton 2783f95f3850SWill Newton /* Clear the interrupts for the host controller */ 2784f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2785f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2786f95f3850SWill Newton 2787f95f3850SWill Newton /* Put in max timeout */ 2788f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 2789f95f3850SWill Newton 2790f95f3850SWill Newton /* 2791f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2792f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 2793f95f3850SWill Newton */ 2794b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 2795b86d8253SJames Hogan /* 2796b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2797b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 2798b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 2799b86d8253SJames Hogan * should put it in the platform data. 2800b86d8253SJames Hogan */ 2801f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 28028234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2803b86d8253SJames Hogan } else { 2804b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 2805b86d8253SJames Hogan } 2806b86d8253SJames Hogan host->fifo_depth = fifo_size; 280752426899SSeungwon Jeon host->fifoth_val = 280852426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 2809e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 2810f95f3850SWill Newton 2811f95f3850SWill Newton /* disable clock to CIU */ 2812f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2813f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2814f95f3850SWill Newton 281563008768SJames Hogan /* 281663008768SJames Hogan * In 2.40a spec, Data offset is changed. 281763008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 281863008768SJames Hogan */ 281963008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 282063008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 282163008768SJames Hogan 282263008768SJames Hogan if (host->verid < DW_MMC_240A) 282363008768SJames Hogan host->data_offset = DATA_OFFSET; 282463008768SJames Hogan else 282563008768SJames Hogan host->data_offset = DATA_240A_OFFSET; 282663008768SJames Hogan 2827f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2828780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2829780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 2830f95f3850SWill Newton if (ret) 28316130e7a9SDoug Anderson goto err_dmaunmap; 2832f95f3850SWill Newton 2833f95f3850SWill Newton if (host->pdata->num_slots) 2834f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 2835f95f3850SWill Newton else 2836f95f3850SWill Newton host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2837f95f3850SWill Newton 28382da1d7f2SYuvaraj CD /* 2839*fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 28402da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 28412da1d7f2SYuvaraj CD */ 28422da1d7f2SYuvaraj CD mci_writel(host, RINTSTS, 0xFFFFFFFF); 28432da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 28442da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2845*fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 28462da1d7f2SYuvaraj CD mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 28472da1d7f2SYuvaraj CD 28482da1d7f2SYuvaraj CD dev_info(host->dev, "DW MMC controller at irq %d, " 28492da1d7f2SYuvaraj CD "%d bit host data width, " 28502da1d7f2SYuvaraj CD "%u deep fifo\n", 28512da1d7f2SYuvaraj CD host->irq, width, fifo_size); 28522da1d7f2SYuvaraj CD 2853f95f3850SWill Newton /* We need at least one slot to succeed */ 2854f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2855f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 28561c2215b7SThomas Abraham if (ret) 28571c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 28581c2215b7SThomas Abraham else 28591c2215b7SThomas Abraham init_slots++; 2860f95f3850SWill Newton } 28611c2215b7SThomas Abraham 2862*fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 2863*fa0c3283SDoug Anderson dw_mci_enable_cd(host); 2864*fa0c3283SDoug Anderson 28651c2215b7SThomas Abraham if (init_slots) { 28661c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 28671c2215b7SThomas Abraham } else { 28681c2215b7SThomas Abraham dev_dbg(host->dev, "attempted to initialize %d slots, " 28691c2215b7SThomas Abraham "but failed on all\n", host->num_slots); 28706130e7a9SDoug Anderson goto err_dmaunmap; 2871f95f3850SWill Newton } 2872f95f3850SWill Newton 2873f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 28744a90920cSThomas Abraham dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2875f95f3850SWill Newton 2876f95f3850SWill Newton return 0; 2877f95f3850SWill Newton 2878f95f3850SWill Newton err_dmaunmap: 2879f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2880f95f3850SWill Newton host->dma_ops->exit(host); 2881f90a0612SThomas Abraham 2882f90a0612SThomas Abraham err_clk_ciu: 2883780f22afSSeungwon Jeon if (!IS_ERR(host->ciu_clk)) 2884f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2885780f22afSSeungwon Jeon 2886f90a0612SThomas Abraham err_clk_biu: 2887780f22afSSeungwon Jeon if (!IS_ERR(host->biu_clk)) 2888f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2889780f22afSSeungwon Jeon 2890f95f3850SWill Newton return ret; 2891f95f3850SWill Newton } 289262ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 2893f95f3850SWill Newton 289462ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 2895f95f3850SWill Newton { 2896f95f3850SWill Newton int i; 2897f95f3850SWill Newton 2898f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2899f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2900f95f3850SWill Newton 2901f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 29024a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 2903f95f3850SWill Newton if (host->slot[i]) 2904f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 2905f95f3850SWill Newton } 2906f95f3850SWill Newton 2907f95f3850SWill Newton /* disable clock to CIU */ 2908f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2909f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2910f95f3850SWill Newton 2911f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2912f95f3850SWill Newton host->dma_ops->exit(host); 2913f95f3850SWill Newton 2914f90a0612SThomas Abraham if (!IS_ERR(host->ciu_clk)) 2915f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2916780f22afSSeungwon Jeon 2917f90a0612SThomas Abraham if (!IS_ERR(host->biu_clk)) 2918f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2919f95f3850SWill Newton } 292062ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 292162ca8034SShashidhar Hiremath 292262ca8034SShashidhar Hiremath 2923f95f3850SWill Newton 29246fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 2925f95f3850SWill Newton /* 2926f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 2927f95f3850SWill Newton */ 292862ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 2929f95f3850SWill Newton { 2930f95f3850SWill Newton return 0; 2931f95f3850SWill Newton } 293262ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 2933f95f3850SWill Newton 293462ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 2935f95f3850SWill Newton { 2936f95f3850SWill Newton int i, ret; 2937f95f3850SWill Newton 29383a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 2939e61cf118SJaehoon Chung ret = -ENODEV; 2940e61cf118SJaehoon Chung return ret; 2941e61cf118SJaehoon Chung } 2942e61cf118SJaehoon Chung 29433bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 2944141a712aSSeungwon Jeon host->dma_ops->init(host); 2945141a712aSSeungwon Jeon 294652426899SSeungwon Jeon /* 294752426899SSeungwon Jeon * Restore the initial value at FIFOTH register 294852426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 294952426899SSeungwon Jeon */ 2950e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 295152426899SSeungwon Jeon host->prev_blksz = 0; 2952e61cf118SJaehoon Chung 29532eb2944fSDoug Anderson /* Put in max timeout */ 29542eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 29552eb2944fSDoug Anderson 2956e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 2957e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2958e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2959*fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 2960e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2961e61cf118SJaehoon Chung 2962f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2963f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 2964f95f3850SWill Newton if (!slot) 2965f95f3850SWill Newton continue; 2966ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 2967ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 2968ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 2969ab269128SAbhilash Kesavan } 2970f95f3850SWill Newton } 2971*fa0c3283SDoug Anderson 2972*fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 2973*fa0c3283SDoug Anderson dw_mci_enable_cd(host); 2974*fa0c3283SDoug Anderson 2975f95f3850SWill Newton return 0; 2976f95f3850SWill Newton } 297762ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 29786fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 29796fe8890dSJaehoon Chung 2980f95f3850SWill Newton static int __init dw_mci_init(void) 2981f95f3850SWill Newton { 29828e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 298362ca8034SShashidhar Hiremath return 0; 2984f95f3850SWill Newton } 2985f95f3850SWill Newton 2986f95f3850SWill Newton static void __exit dw_mci_exit(void) 2987f95f3850SWill Newton { 2988f95f3850SWill Newton } 2989f95f3850SWill Newton 2990f95f3850SWill Newton module_init(dw_mci_init); 2991f95f3850SWill Newton module_exit(dw_mci_exit); 2992f95f3850SWill Newton 2993f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 2994f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 2995f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 2996f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 2997