1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47f95f3850SWill Newton SDMMC_INT_EBE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49f95f3850SWill Newton SDMMC_INT_RESP_ERR) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51f95f3850SWill Newton DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 6569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6669d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6769d99fdcSPrabu Thangamuthu 6869d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6969d99fdcSPrabu Thangamuthu 7069d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7169d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 7269d99fdcSPrabu Thangamuthu ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff)) 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7769d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8069d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu }; 8269d99fdcSPrabu Thangamuthu 83f95f3850SWill Newton struct idmac_desc { 84f95f3850SWill Newton u32 des0; /* Control Descriptor */ 85f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 86f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 87f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 88f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 89f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 90f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 91f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 92f95f3850SWill Newton 93f95f3850SWill Newton u32 des1; /* Buffer sizes */ 94f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 959b7bbe10SShashidhar Hiremath ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 96f95f3850SWill Newton 97f95f3850SWill Newton u32 des2; /* buffer 1 physical address */ 98f95f3850SWill Newton 99f95f3850SWill Newton u32 des3; /* buffer 2 physical address */ 100f95f3850SWill Newton }; 101f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 102f95f3850SWill Newton 1033a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 104536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 10531bff450SSeungwon Jeon 106f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 107f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 108f95f3850SWill Newton { 109f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 110f95f3850SWill Newton struct mmc_request *mrq; 111f95f3850SWill Newton struct mmc_command *cmd; 112f95f3850SWill Newton struct mmc_command *stop; 113f95f3850SWill Newton struct mmc_data *data; 114f95f3850SWill Newton 115f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 116f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 117f95f3850SWill Newton mrq = slot->mrq; 118f95f3850SWill Newton 119f95f3850SWill Newton if (mrq) { 120f95f3850SWill Newton cmd = mrq->cmd; 121f95f3850SWill Newton data = mrq->data; 122f95f3850SWill Newton stop = mrq->stop; 123f95f3850SWill Newton 124f95f3850SWill Newton if (cmd) 125f95f3850SWill Newton seq_printf(s, 126f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 127f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 128f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 129f95f3850SWill Newton cmd->resp[2], cmd->error); 130f95f3850SWill Newton if (data) 131f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 132f95f3850SWill Newton data->bytes_xfered, data->blocks, 133f95f3850SWill Newton data->blksz, data->flags, data->error); 134f95f3850SWill Newton if (stop) 135f95f3850SWill Newton seq_printf(s, 136f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 137f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 138f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 139f95f3850SWill Newton stop->resp[2], stop->error); 140f95f3850SWill Newton } 141f95f3850SWill Newton 142f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 143f95f3850SWill Newton 144f95f3850SWill Newton return 0; 145f95f3850SWill Newton } 146f95f3850SWill Newton 147f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 148f95f3850SWill Newton { 149f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 150f95f3850SWill Newton } 151f95f3850SWill Newton 152f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 153f95f3850SWill Newton .owner = THIS_MODULE, 154f95f3850SWill Newton .open = dw_mci_req_open, 155f95f3850SWill Newton .read = seq_read, 156f95f3850SWill Newton .llseek = seq_lseek, 157f95f3850SWill Newton .release = single_release, 158f95f3850SWill Newton }; 159f95f3850SWill Newton 160f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 161f95f3850SWill Newton { 162f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 163f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 164f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 165f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 166f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 167f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 168f95f3850SWill Newton 169f95f3850SWill Newton return 0; 170f95f3850SWill Newton } 171f95f3850SWill Newton 172f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 173f95f3850SWill Newton { 174f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 175f95f3850SWill Newton } 176f95f3850SWill Newton 177f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 178f95f3850SWill Newton .owner = THIS_MODULE, 179f95f3850SWill Newton .open = dw_mci_regs_open, 180f95f3850SWill Newton .read = seq_read, 181f95f3850SWill Newton .llseek = seq_lseek, 182f95f3850SWill Newton .release = single_release, 183f95f3850SWill Newton }; 184f95f3850SWill Newton 185f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 186f95f3850SWill Newton { 187f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 188f95f3850SWill Newton struct dw_mci *host = slot->host; 189f95f3850SWill Newton struct dentry *root; 190f95f3850SWill Newton struct dentry *node; 191f95f3850SWill Newton 192f95f3850SWill Newton root = mmc->debugfs_root; 193f95f3850SWill Newton if (!root) 194f95f3850SWill Newton return; 195f95f3850SWill Newton 196f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 197f95f3850SWill Newton &dw_mci_regs_fops); 198f95f3850SWill Newton if (!node) 199f95f3850SWill Newton goto err; 200f95f3850SWill Newton 201f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 202f95f3850SWill Newton &dw_mci_req_fops); 203f95f3850SWill Newton if (!node) 204f95f3850SWill Newton goto err; 205f95f3850SWill Newton 206f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 207f95f3850SWill Newton if (!node) 208f95f3850SWill Newton goto err; 209f95f3850SWill Newton 210f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 211f95f3850SWill Newton (u32 *)&host->pending_events); 212f95f3850SWill Newton if (!node) 213f95f3850SWill Newton goto err; 214f95f3850SWill Newton 215f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 216f95f3850SWill Newton (u32 *)&host->completed_events); 217f95f3850SWill Newton if (!node) 218f95f3850SWill Newton goto err; 219f95f3850SWill Newton 220f95f3850SWill Newton return; 221f95f3850SWill Newton 222f95f3850SWill Newton err: 223f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 224f95f3850SWill Newton } 225f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 226f95f3850SWill Newton 22701730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 22801730558SDoug Anderson 229f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 230f95f3850SWill Newton { 231f95f3850SWill Newton struct mmc_data *data; 232800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23301730558SDoug Anderson struct dw_mci *host = slot->host; 234e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 235f95f3850SWill Newton u32 cmdr; 236f95f3850SWill Newton cmd->error = -EINPROGRESS; 237f95f3850SWill Newton 238f95f3850SWill Newton cmdr = cmd->opcode; 239f95f3850SWill Newton 24090c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24190c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24290c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24390c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24490c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 245f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2464a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 247f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 248f95f3850SWill Newton 24901730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25001730558SDoug Anderson u32 clk_en_a; 25101730558SDoug Anderson 25201730558SDoug Anderson /* Special bit makes CMD11 not die */ 25301730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25401730558SDoug Anderson 25501730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25601730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 25701730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 25801730558SDoug Anderson 25901730558SDoug Anderson /* 26001730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26101730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26201730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26301730558SDoug Anderson * voltage change dance. 26401730558SDoug Anderson * 26501730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26601730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 26701730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 26801730558SDoug Anderson * until the voltage change is all done. 26901730558SDoug Anderson */ 27001730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27101730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27201730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27301730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27401730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27501730558SDoug Anderson } 27601730558SDoug Anderson 277f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 278f95f3850SWill Newton /* We expect a response, so set this bit */ 279f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 280f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 281f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 282f95f3850SWill Newton } 283f95f3850SWill Newton 284f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 285f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 286f95f3850SWill Newton 287f95f3850SWill Newton data = cmd->data; 288f95f3850SWill Newton if (data) { 289f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 290f95f3850SWill Newton if (data->flags & MMC_DATA_STREAM) 291f95f3850SWill Newton cmdr |= SDMMC_CMD_STRM_MODE; 292f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 293f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 294f95f3850SWill Newton } 295f95f3850SWill Newton 296cb27a843SJames Hogan if (drv_data && drv_data->prepare_command) 297cb27a843SJames Hogan drv_data->prepare_command(slot->host, &cmdr); 298800d78bfSThomas Abraham 299f95f3850SWill Newton return cmdr; 300f95f3850SWill Newton } 301f95f3850SWill Newton 30290c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30390c2143aSSeungwon Jeon { 30490c2143aSSeungwon Jeon struct mmc_command *stop; 30590c2143aSSeungwon Jeon u32 cmdr; 30690c2143aSSeungwon Jeon 30790c2143aSSeungwon Jeon if (!cmd->data) 30890c2143aSSeungwon Jeon return 0; 30990c2143aSSeungwon Jeon 31090c2143aSSeungwon Jeon stop = &host->stop_abort; 31190c2143aSSeungwon Jeon cmdr = cmd->opcode; 31290c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31390c2143aSSeungwon Jeon 31490c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31590c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31690c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 31790c2143aSSeungwon Jeon cmdr == MMC_WRITE_MULTIPLE_BLOCK) { 31890c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 31990c2143aSSeungwon Jeon stop->arg = 0; 32090c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32190c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32290c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32390c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32490c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 32590c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 32690c2143aSSeungwon Jeon } else { 32790c2143aSSeungwon Jeon return 0; 32890c2143aSSeungwon Jeon } 32990c2143aSSeungwon Jeon 33090c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33190c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33290c2143aSSeungwon Jeon 33390c2143aSSeungwon Jeon return cmdr; 33490c2143aSSeungwon Jeon } 33590c2143aSSeungwon Jeon 336f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 337f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 338f95f3850SWill Newton { 339f95f3850SWill Newton host->cmd = cmd; 3404a90920cSThomas Abraham dev_vdbg(host->dev, 341f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 342f95f3850SWill Newton cmd->arg, cmd_flags); 343f95f3850SWill Newton 344f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 345f95f3850SWill Newton wmb(); 346f95f3850SWill Newton 347f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 348f95f3850SWill Newton } 349f95f3850SWill Newton 35090c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 351f95f3850SWill Newton { 35290c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 35390c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 354f95f3850SWill Newton } 355f95f3850SWill Newton 356f95f3850SWill Newton /* DMA interface functions */ 357f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 358f95f3850SWill Newton { 35903e8cb53SJames Hogan if (host->using_dma) { 360f95f3850SWill Newton host->dma_ops->stop(host); 361f95f3850SWill Newton host->dma_ops->cleanup(host); 362aa50f259SSeungwon Jeon } 363aa50f259SSeungwon Jeon 364f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 365f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 366f95f3850SWill Newton } 367f95f3850SWill Newton 3689aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 3699aa51408SSeungwon Jeon { 3709aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 3719aa51408SSeungwon Jeon return DMA_TO_DEVICE; 3729aa51408SSeungwon Jeon else 3739aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 3749aa51408SSeungwon Jeon } 3759aa51408SSeungwon Jeon 3769beee912SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 377f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 378f95f3850SWill Newton { 379f95f3850SWill Newton struct mmc_data *data = host->data; 380f95f3850SWill Newton 381f95f3850SWill Newton if (data) 3829aa51408SSeungwon Jeon if (!data->host_cookie) 3834a90920cSThomas Abraham dma_unmap_sg(host->dev, 3849aa51408SSeungwon Jeon data->sg, 3859aa51408SSeungwon Jeon data->sg_len, 3869aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 387f95f3850SWill Newton } 388f95f3850SWill Newton 3895ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 3905ce9d961SSeungwon Jeon { 3915ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 3925ce9d961SSeungwon Jeon /* Software reset of DMA */ 3935ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 3945ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 3955ce9d961SSeungwon Jeon } 3965ce9d961SSeungwon Jeon 397f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 398f95f3850SWill Newton { 399f95f3850SWill Newton u32 temp; 400f95f3850SWill Newton 401f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 402f95f3850SWill Newton temp = mci_readl(host, CTRL); 403f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 404f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 405f95f3850SWill Newton mci_writel(host, CTRL, temp); 406f95f3850SWill Newton 407f95f3850SWill Newton /* Stop the IDMAC running */ 408f95f3850SWill Newton temp = mci_readl(host, BMOD); 409a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4105ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 411f95f3850SWill Newton mci_writel(host, BMOD, temp); 412f95f3850SWill Newton } 413f95f3850SWill Newton 414f95f3850SWill Newton static void dw_mci_idmac_complete_dma(struct dw_mci *host) 415f95f3850SWill Newton { 416f95f3850SWill Newton struct mmc_data *data = host->data; 417f95f3850SWill Newton 4184a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 419f95f3850SWill Newton 420f95f3850SWill Newton host->dma_ops->cleanup(host); 421f95f3850SWill Newton 422f95f3850SWill Newton /* 423f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 424f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 425f95f3850SWill Newton */ 426f95f3850SWill Newton if (data) { 427f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 428f95f3850SWill Newton tasklet_schedule(&host->tasklet); 429f95f3850SWill Newton } 430f95f3850SWill Newton } 431f95f3850SWill Newton 432f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 433f95f3850SWill Newton unsigned int sg_len) 434f95f3850SWill Newton { 435f95f3850SWill Newton int i; 43669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 43769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *desc = host->sg_cpu; 43869d99fdcSPrabu Thangamuthu 43969d99fdcSPrabu Thangamuthu for (i = 0; i < sg_len; i++, desc++) { 44069d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 44169d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 44269d99fdcSPrabu Thangamuthu 44369d99fdcSPrabu Thangamuthu /* 44469d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 44569d99fdcSPrabu Thangamuthu * descriptor 44669d99fdcSPrabu Thangamuthu */ 44769d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 44869d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 44969d99fdcSPrabu Thangamuthu /* Buffer length */ 45069d99fdcSPrabu Thangamuthu IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length); 45169d99fdcSPrabu Thangamuthu 45269d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 45369d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 45469d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 45569d99fdcSPrabu Thangamuthu } 45669d99fdcSPrabu Thangamuthu 45769d99fdcSPrabu Thangamuthu /* Set first descriptor */ 45869d99fdcSPrabu Thangamuthu desc = host->sg_cpu; 45969d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_FD; 46069d99fdcSPrabu Thangamuthu 46169d99fdcSPrabu Thangamuthu /* Set last descriptor */ 46269d99fdcSPrabu Thangamuthu desc = host->sg_cpu + (i - 1) * 46369d99fdcSPrabu Thangamuthu sizeof(struct idmac_desc_64addr); 46469d99fdcSPrabu Thangamuthu desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 46569d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_LD; 46669d99fdcSPrabu Thangamuthu 46769d99fdcSPrabu Thangamuthu } else { 468f95f3850SWill Newton struct idmac_desc *desc = host->sg_cpu; 469f95f3850SWill Newton 470f95f3850SWill Newton for (i = 0; i < sg_len; i++, desc++) { 471f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 472f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 473f95f3850SWill Newton 47469d99fdcSPrabu Thangamuthu /* 47569d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 47669d99fdcSPrabu Thangamuthu * descriptor 47769d99fdcSPrabu Thangamuthu */ 47869d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 47969d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 480f95f3850SWill Newton /* Buffer length */ 481f95f3850SWill Newton IDMAC_SET_BUFFER1_SIZE(desc, length); 482f95f3850SWill Newton 483f95f3850SWill Newton /* Physical address to DMA to/from */ 484f95f3850SWill Newton desc->des2 = mem_addr; 485f95f3850SWill Newton } 486f95f3850SWill Newton 487f95f3850SWill Newton /* Set first descriptor */ 488f95f3850SWill Newton desc = host->sg_cpu; 489f95f3850SWill Newton desc->des0 |= IDMAC_DES0_FD; 490f95f3850SWill Newton 491f95f3850SWill Newton /* Set last descriptor */ 492f95f3850SWill Newton desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 493f95f3850SWill Newton desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 494f95f3850SWill Newton desc->des0 |= IDMAC_DES0_LD; 49569d99fdcSPrabu Thangamuthu } 496f95f3850SWill Newton 497f95f3850SWill Newton wmb(); 498f95f3850SWill Newton } 499f95f3850SWill Newton 500f95f3850SWill Newton static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 501f95f3850SWill Newton { 502f95f3850SWill Newton u32 temp; 503f95f3850SWill Newton 504f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 505f95f3850SWill Newton 506536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 507536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 508536f6b91SSonny Rao dw_mci_idmac_reset(host); 509536f6b91SSonny Rao 510f95f3850SWill Newton /* Select IDMAC interface */ 511f95f3850SWill Newton temp = mci_readl(host, CTRL); 512f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 513f95f3850SWill Newton mci_writel(host, CTRL, temp); 514f95f3850SWill Newton 515f95f3850SWill Newton wmb(); 516f95f3850SWill Newton 517f95f3850SWill Newton /* Enable the IDMAC */ 518f95f3850SWill Newton temp = mci_readl(host, BMOD); 519a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 520f95f3850SWill Newton mci_writel(host, BMOD, temp); 521f95f3850SWill Newton 522f95f3850SWill Newton /* Start it running */ 523f95f3850SWill Newton mci_writel(host, PLDMND, 1); 524f95f3850SWill Newton } 525f95f3850SWill Newton 526f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 527f95f3850SWill Newton { 528897b69e7SSeungwon Jeon int i; 529f95f3850SWill Newton 53069d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 53169d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 53269d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 53369d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 53469d99fdcSPrabu Thangamuthu 53569d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 53669d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 53769d99fdcSPrabu Thangamuthu i++, p++) { 53869d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 53969d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 54069d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 54169d99fdcSPrabu Thangamuthu 54269d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 54369d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 54469d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 54569d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 54669d99fdcSPrabu Thangamuthu p->des1 = 0; 54769d99fdcSPrabu Thangamuthu p->des2 = 0; 54869d99fdcSPrabu Thangamuthu p->des3 = 0; 54969d99fdcSPrabu Thangamuthu } 55069d99fdcSPrabu Thangamuthu 55169d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 55269d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 55369d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 55469d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 55569d99fdcSPrabu Thangamuthu 55669d99fdcSPrabu Thangamuthu } else { 55769d99fdcSPrabu Thangamuthu struct idmac_desc *p; 558f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 559f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 560f95f3850SWill Newton 561f95f3850SWill Newton /* Forward link the descriptor list */ 562f95f3850SWill Newton for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 56369d99fdcSPrabu Thangamuthu p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * 56469d99fdcSPrabu Thangamuthu (i + 1)); 565f95f3850SWill Newton 566f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 567f95f3850SWill Newton p->des3 = host->sg_dma; 568f95f3850SWill Newton p->des0 = IDMAC_DES0_ER; 56969d99fdcSPrabu Thangamuthu } 570f95f3850SWill Newton 5715ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 572141a712aSSeungwon Jeon 57369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 57469d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 57569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 57669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 57769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 57869d99fdcSPrabu Thangamuthu 57969d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 58069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 58169d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 58269d99fdcSPrabu Thangamuthu 58369d99fdcSPrabu Thangamuthu } else { 584f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 585fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 58669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 58769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 588f95f3850SWill Newton 589f95f3850SWill Newton /* Set the descriptor base address */ 590f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 59169d99fdcSPrabu Thangamuthu } 59269d99fdcSPrabu Thangamuthu 593f95f3850SWill Newton return 0; 594f95f3850SWill Newton } 595f95f3850SWill Newton 5968e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 597885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 598885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 599885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 600885c3e80SSeungwon Jeon .complete = dw_mci_idmac_complete_dma, 601885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 602885c3e80SSeungwon Jeon }; 603885c3e80SSeungwon Jeon #endif /* CONFIG_MMC_DW_IDMAC */ 604885c3e80SSeungwon Jeon 6059aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 6069aa51408SSeungwon Jeon struct mmc_data *data, 6079aa51408SSeungwon Jeon bool next) 608f95f3850SWill Newton { 609f95f3850SWill Newton struct scatterlist *sg; 6109aa51408SSeungwon Jeon unsigned int i, sg_len; 611f95f3850SWill Newton 6129aa51408SSeungwon Jeon if (!next && data->host_cookie) 6139aa51408SSeungwon Jeon return data->host_cookie; 614f95f3850SWill Newton 615f95f3850SWill Newton /* 616f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 617f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 618f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 619f95f3850SWill Newton */ 620f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 621f95f3850SWill Newton return -EINVAL; 6229aa51408SSeungwon Jeon 623f95f3850SWill Newton if (data->blksz & 3) 624f95f3850SWill Newton return -EINVAL; 625f95f3850SWill Newton 626f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 627f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 628f95f3850SWill Newton return -EINVAL; 629f95f3850SWill Newton } 630f95f3850SWill Newton 6314a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 6329aa51408SSeungwon Jeon data->sg, 6339aa51408SSeungwon Jeon data->sg_len, 6349aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 6359aa51408SSeungwon Jeon if (sg_len == 0) 6369aa51408SSeungwon Jeon return -EINVAL; 6379aa51408SSeungwon Jeon 6389aa51408SSeungwon Jeon if (next) 6399aa51408SSeungwon Jeon data->host_cookie = sg_len; 6409aa51408SSeungwon Jeon 6419aa51408SSeungwon Jeon return sg_len; 6429aa51408SSeungwon Jeon } 6439aa51408SSeungwon Jeon 6449aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 6459aa51408SSeungwon Jeon struct mmc_request *mrq, 6469aa51408SSeungwon Jeon bool is_first_req) 6479aa51408SSeungwon Jeon { 6489aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6499aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6509aa51408SSeungwon Jeon 6519aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 6529aa51408SSeungwon Jeon return; 6539aa51408SSeungwon Jeon 6549aa51408SSeungwon Jeon if (data->host_cookie) { 6559aa51408SSeungwon Jeon data->host_cookie = 0; 6569aa51408SSeungwon Jeon return; 6579aa51408SSeungwon Jeon } 6589aa51408SSeungwon Jeon 6599aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 6609aa51408SSeungwon Jeon data->host_cookie = 0; 6619aa51408SSeungwon Jeon } 6629aa51408SSeungwon Jeon 6639aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 6649aa51408SSeungwon Jeon struct mmc_request *mrq, 6659aa51408SSeungwon Jeon int err) 6669aa51408SSeungwon Jeon { 6679aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6689aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6699aa51408SSeungwon Jeon 6709aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 6719aa51408SSeungwon Jeon return; 6729aa51408SSeungwon Jeon 6739aa51408SSeungwon Jeon if (data->host_cookie) 6744a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 6759aa51408SSeungwon Jeon data->sg, 6769aa51408SSeungwon Jeon data->sg_len, 6779aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 6789aa51408SSeungwon Jeon data->host_cookie = 0; 6799aa51408SSeungwon Jeon } 6809aa51408SSeungwon Jeon 68152426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 68252426899SSeungwon Jeon { 68352426899SSeungwon Jeon #ifdef CONFIG_MMC_DW_IDMAC 68452426899SSeungwon Jeon unsigned int blksz = data->blksz; 68552426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 68652426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 68752426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 68852426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 68952426899SSeungwon Jeon int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; 69052426899SSeungwon Jeon 69152426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 69252426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 69352426899SSeungwon Jeon 69452426899SSeungwon Jeon /* 69552426899SSeungwon Jeon * MSIZE is '1', 69652426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 69752426899SSeungwon Jeon */ 69852426899SSeungwon Jeon if (blksz % fifo_width) { 69952426899SSeungwon Jeon msize = 0; 70052426899SSeungwon Jeon rx_wmark = 1; 70152426899SSeungwon Jeon goto done; 70252426899SSeungwon Jeon } 70352426899SSeungwon Jeon 70452426899SSeungwon Jeon do { 70552426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 70652426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 70752426899SSeungwon Jeon msize = idx; 70852426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 70952426899SSeungwon Jeon break; 71052426899SSeungwon Jeon } 71152426899SSeungwon Jeon } while (--idx > 0); 71252426899SSeungwon Jeon /* 71352426899SSeungwon Jeon * If idx is '0', it won't be tried 71452426899SSeungwon Jeon * Thus, initial values are uesed 71552426899SSeungwon Jeon */ 71652426899SSeungwon Jeon done: 71752426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 71852426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 71952426899SSeungwon Jeon #endif 72052426899SSeungwon Jeon } 72152426899SSeungwon Jeon 722f1d2736cSSeungwon Jeon static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 723f1d2736cSSeungwon Jeon { 724f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 725f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 726f1d2736cSSeungwon Jeon u16 thld_size; 727f1d2736cSSeungwon Jeon 728f1d2736cSSeungwon Jeon WARN_ON(!(data->flags & MMC_DATA_READ)); 729f1d2736cSSeungwon Jeon 73066dfd101SJames Hogan /* 73166dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 73266dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 73366dfd101SJames Hogan */ 73466dfd101SJames Hogan if (host->verid < DW_MMC_240A) 73566dfd101SJames Hogan return; 73666dfd101SJames Hogan 737f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 738f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 739f1d2736cSSeungwon Jeon goto disable; 740f1d2736cSSeungwon Jeon 741f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 742f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 743f1d2736cSSeungwon Jeon 744f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 745f1d2736cSSeungwon Jeon goto disable; 746f1d2736cSSeungwon Jeon 747f1d2736cSSeungwon Jeon /* 748f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 749f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 750f1d2736cSSeungwon Jeon * Currently just choose blksz. 751f1d2736cSSeungwon Jeon */ 752f1d2736cSSeungwon Jeon thld_size = blksz; 753f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 754f1d2736cSSeungwon Jeon return; 755f1d2736cSSeungwon Jeon 756f1d2736cSSeungwon Jeon disable: 757f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 758f1d2736cSSeungwon Jeon } 759f1d2736cSSeungwon Jeon 7609aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 7619aa51408SSeungwon Jeon { 762*f8c58c11SDoug Anderson unsigned long irqflags; 7639aa51408SSeungwon Jeon int sg_len; 7649aa51408SSeungwon Jeon u32 temp; 7659aa51408SSeungwon Jeon 7669aa51408SSeungwon Jeon host->using_dma = 0; 7679aa51408SSeungwon Jeon 7689aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 7699aa51408SSeungwon Jeon if (!host->use_dma) 7709aa51408SSeungwon Jeon return -ENODEV; 7719aa51408SSeungwon Jeon 7729aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 773a99aa9b9SSeungwon Jeon if (sg_len < 0) { 774a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 7759aa51408SSeungwon Jeon return sg_len; 776a99aa9b9SSeungwon Jeon } 7779aa51408SSeungwon Jeon 77803e8cb53SJames Hogan host->using_dma = 1; 77903e8cb53SJames Hogan 7804a90920cSThomas Abraham dev_vdbg(host->dev, 781f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 782f95f3850SWill Newton (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 783f95f3850SWill Newton sg_len); 784f95f3850SWill Newton 78552426899SSeungwon Jeon /* 78652426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 78752426899SSeungwon Jeon * If current block size is same with previous size, 78852426899SSeungwon Jeon * no need to update fifoth. 78952426899SSeungwon Jeon */ 79052426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 79152426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 79252426899SSeungwon Jeon 793f95f3850SWill Newton /* Enable the DMA interface */ 794f95f3850SWill Newton temp = mci_readl(host, CTRL); 795f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 796f95f3850SWill Newton mci_writel(host, CTRL, temp); 797f95f3850SWill Newton 798f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 799*f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 800f95f3850SWill Newton temp = mci_readl(host, INTMASK); 801f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 802f95f3850SWill Newton mci_writel(host, INTMASK, temp); 803*f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 804f95f3850SWill Newton 805f95f3850SWill Newton host->dma_ops->start(host, sg_len); 806f95f3850SWill Newton 807f95f3850SWill Newton return 0; 808f95f3850SWill Newton } 809f95f3850SWill Newton 810f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 811f95f3850SWill Newton { 812*f8c58c11SDoug Anderson unsigned long irqflags; 813f95f3850SWill Newton u32 temp; 814f95f3850SWill Newton 815f95f3850SWill Newton data->error = -EINPROGRESS; 816f95f3850SWill Newton 817f95f3850SWill Newton WARN_ON(host->data); 818f95f3850SWill Newton host->sg = NULL; 819f95f3850SWill Newton host->data = data; 820f95f3850SWill Newton 821f1d2736cSSeungwon Jeon if (data->flags & MMC_DATA_READ) { 82255c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 823f1d2736cSSeungwon Jeon dw_mci_ctrl_rd_thld(host, data); 824f1d2736cSSeungwon Jeon } else { 82555c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 826f1d2736cSSeungwon Jeon } 82755c5efbcSJames Hogan 828f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 829f9c2a0dcSSeungwon Jeon int flags = SG_MITER_ATOMIC; 830f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 831f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 832f9c2a0dcSSeungwon Jeon else 833f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 834f9c2a0dcSSeungwon Jeon 835f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 836f95f3850SWill Newton host->sg = data->sg; 83734b664a2SJames Hogan host->part_buf_start = 0; 83834b664a2SJames Hogan host->part_buf_count = 0; 839f95f3850SWill Newton 840b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 841*f8c58c11SDoug Anderson 842*f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 843f95f3850SWill Newton temp = mci_readl(host, INTMASK); 844f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 845f95f3850SWill Newton mci_writel(host, INTMASK, temp); 846*f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 847f95f3850SWill Newton 848f95f3850SWill Newton temp = mci_readl(host, CTRL); 849f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 850f95f3850SWill Newton mci_writel(host, CTRL, temp); 85152426899SSeungwon Jeon 85252426899SSeungwon Jeon /* 85352426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 85452426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 85552426899SSeungwon Jeon * prev_blksz should be invalidated. 85652426899SSeungwon Jeon */ 85752426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 85852426899SSeungwon Jeon host->prev_blksz = 0; 85952426899SSeungwon Jeon } else { 86052426899SSeungwon Jeon /* 86152426899SSeungwon Jeon * Keep the current block size. 86252426899SSeungwon Jeon * It will be used to decide whether to update 86352426899SSeungwon Jeon * fifoth register next time. 86452426899SSeungwon Jeon */ 86552426899SSeungwon Jeon host->prev_blksz = data->blksz; 866f95f3850SWill Newton } 867f95f3850SWill Newton } 868f95f3850SWill Newton 869f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 870f95f3850SWill Newton { 871f95f3850SWill Newton struct dw_mci *host = slot->host; 872f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 873f95f3850SWill Newton unsigned int cmd_status = 0; 874f95f3850SWill Newton 875f95f3850SWill Newton mci_writel(host, CMDARG, arg); 876f95f3850SWill Newton wmb(); 877f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 878f95f3850SWill Newton 879f95f3850SWill Newton while (time_before(jiffies, timeout)) { 880f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 881f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 882f95f3850SWill Newton return; 883f95f3850SWill Newton } 884f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 885f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 886f95f3850SWill Newton cmd, arg, cmd_status); 887f95f3850SWill Newton } 888f95f3850SWill Newton 889ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 890f95f3850SWill Newton { 891f95f3850SWill Newton struct dw_mci *host = slot->host; 892fdf492a1SDoug Anderson unsigned int clock = slot->clock; 893f95f3850SWill Newton u32 div; 8949623b5b9SDoug Anderson u32 clk_en_a; 89501730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 89601730558SDoug Anderson 89701730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 89801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 89901730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 900f95f3850SWill Newton 901fdf492a1SDoug Anderson if (!clock) { 902fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 90301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 904fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 905fdf492a1SDoug Anderson div = host->bus_hz / clock; 906fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 907f95f3850SWill Newton /* 908f95f3850SWill Newton * move the + 1 after the divide to prevent 909f95f3850SWill Newton * over-clocking the card. 910f95f3850SWill Newton */ 911e419990bSSeungwon Jeon div += 1; 912e419990bSSeungwon Jeon 913fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 914f95f3850SWill Newton 915fdf492a1SDoug Anderson if ((clock << div) != slot->__clk_old || force_clkinit) 916f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 917fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 918fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 919fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 920fdf492a1SDoug Anderson host->bus_hz, div); 921f95f3850SWill Newton 922f95f3850SWill Newton /* disable clock */ 923f95f3850SWill Newton mci_writel(host, CLKENA, 0); 924f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 925f95f3850SWill Newton 926f95f3850SWill Newton /* inform CIU */ 92701730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 928f95f3850SWill Newton 929f95f3850SWill Newton /* set clock to desired speed */ 930f95f3850SWill Newton mci_writel(host, CLKDIV, div); 931f95f3850SWill Newton 932f95f3850SWill Newton /* inform CIU */ 93301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 934f95f3850SWill Newton 9359623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 9369623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 937b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 9389623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 9399623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 940f95f3850SWill Newton 941f95f3850SWill Newton /* inform CIU */ 94201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 943f95f3850SWill Newton 944fdf492a1SDoug Anderson /* keep the clock with reflecting clock dividor */ 945fdf492a1SDoug Anderson slot->__clk_old = clock << div; 946f95f3850SWill Newton } 947f95f3850SWill Newton 948fdf492a1SDoug Anderson host->current_speed = clock; 949fdf492a1SDoug Anderson 950f95f3850SWill Newton /* Set the current slot bus width */ 9511d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 952f95f3850SWill Newton } 953f95f3850SWill Newton 954053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 955053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 956053b3ce6SSeungwon Jeon struct mmc_command *cmd) 957f95f3850SWill Newton { 958f95f3850SWill Newton struct mmc_request *mrq; 959f95f3850SWill Newton struct mmc_data *data; 960f95f3850SWill Newton u32 cmdflags; 961f95f3850SWill Newton 962f95f3850SWill Newton mrq = slot->mrq; 963f95f3850SWill Newton 964f95f3850SWill Newton host->cur_slot = slot; 965f95f3850SWill Newton host->mrq = mrq; 966f95f3850SWill Newton 967f95f3850SWill Newton host->pending_events = 0; 968f95f3850SWill Newton host->completed_events = 0; 969e352c813SSeungwon Jeon host->cmd_status = 0; 970f95f3850SWill Newton host->data_status = 0; 971e352c813SSeungwon Jeon host->dir_status = 0; 972f95f3850SWill Newton 973053b3ce6SSeungwon Jeon data = cmd->data; 974f95f3850SWill Newton if (data) { 975f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 976f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 977f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 978f95f3850SWill Newton } 979f95f3850SWill Newton 980f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 981f95f3850SWill Newton 982f95f3850SWill Newton /* this is the first command, send the initialization clock */ 983f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 984f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 985f95f3850SWill Newton 986f95f3850SWill Newton if (data) { 987f95f3850SWill Newton dw_mci_submit_data(host, data); 988f95f3850SWill Newton wmb(); 989f95f3850SWill Newton } 990f95f3850SWill Newton 991f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 992f95f3850SWill Newton 993f95f3850SWill Newton if (mrq->stop) 994f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 99590c2143aSSeungwon Jeon else 99690c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 997f95f3850SWill Newton } 998f95f3850SWill Newton 999053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1000053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1001053b3ce6SSeungwon Jeon { 1002053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1003053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1004053b3ce6SSeungwon Jeon 1005053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1006053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1007053b3ce6SSeungwon Jeon } 1008053b3ce6SSeungwon Jeon 10097456caaeSJames Hogan /* must be called with host->lock held */ 1010f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1011f95f3850SWill Newton struct mmc_request *mrq) 1012f95f3850SWill Newton { 1013f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1014f95f3850SWill Newton host->state); 1015f95f3850SWill Newton 1016f95f3850SWill Newton slot->mrq = mrq; 1017f95f3850SWill Newton 101801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 101901730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 102001730558SDoug Anderson "Voltage change didn't complete\n"); 102101730558SDoug Anderson /* 102201730558SDoug Anderson * this case isn't expected to happen, so we can 102301730558SDoug Anderson * either crash here or just try to continue on 102401730558SDoug Anderson * in the closest possible state 102501730558SDoug Anderson */ 102601730558SDoug Anderson host->state = STATE_IDLE; 102701730558SDoug Anderson } 102801730558SDoug Anderson 1029f95f3850SWill Newton if (host->state == STATE_IDLE) { 1030f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1031f95f3850SWill Newton dw_mci_start_request(host, slot); 1032f95f3850SWill Newton } else { 1033f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1034f95f3850SWill Newton } 1035f95f3850SWill Newton } 1036f95f3850SWill Newton 1037f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1038f95f3850SWill Newton { 1039f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1040f95f3850SWill Newton struct dw_mci *host = slot->host; 1041f95f3850SWill Newton 1042f95f3850SWill Newton WARN_ON(slot->mrq); 1043f95f3850SWill Newton 10447456caaeSJames Hogan /* 10457456caaeSJames Hogan * The check for card presence and queueing of the request must be 10467456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 10477456caaeSJames Hogan * request wouldn't fail until another card was inserted. 10487456caaeSJames Hogan */ 10497456caaeSJames Hogan spin_lock_bh(&host->lock); 10507456caaeSJames Hogan 1051f95f3850SWill Newton if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 10527456caaeSJames Hogan spin_unlock_bh(&host->lock); 1053f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1054f95f3850SWill Newton mmc_request_done(mmc, mrq); 1055f95f3850SWill Newton return; 1056f95f3850SWill Newton } 1057f95f3850SWill Newton 1058f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 10597456caaeSJames Hogan 10607456caaeSJames Hogan spin_unlock_bh(&host->lock); 1061f95f3850SWill Newton } 1062f95f3850SWill Newton 1063f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1064f95f3850SWill Newton { 1065f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1066e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 106741babf75SJaehoon Chung u32 regs; 106851da2240SYuvaraj CD int ret; 1069f95f3850SWill Newton 1070f95f3850SWill Newton switch (ios->bus_width) { 1071f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1072f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1073f95f3850SWill Newton break; 1074c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1075c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1076c9b2a06fSJaehoon Chung break; 1077b2f7cb45SJaehoon Chung default: 1078b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1079b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1080f95f3850SWill Newton } 1081f95f3850SWill Newton 108241babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 10833f514291SSeungwon Jeon 10843f514291SSeungwon Jeon /* DDR mode set */ 1085cab3a802SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52) 1086c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 10873f514291SSeungwon Jeon else 1088c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 10893f514291SSeungwon Jeon 109041babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1091f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 109241babf75SJaehoon Chung 1093f95f3850SWill Newton /* 1094f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1095f95f3850SWill Newton * core ios update when finding the minimum. 1096f95f3850SWill Newton */ 1097f95f3850SWill Newton slot->clock = ios->clock; 1098f95f3850SWill Newton 1099cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1100cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1101800d78bfSThomas Abraham 1102bf7cb224SJaehoon Chung /* Slot specific timing and width adjustment */ 1103bf7cb224SJaehoon Chung dw_mci_setup_bus(slot, false); 1104bf7cb224SJaehoon Chung 110501730558SDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 110601730558SDoug Anderson slot->host->state = STATE_IDLE; 110701730558SDoug Anderson 1108f95f3850SWill Newton switch (ios->power_mode) { 1109f95f3850SWill Newton case MMC_POWER_UP: 111051da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 111151da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 111251da2240SYuvaraj CD ios->vdd); 111351da2240SYuvaraj CD if (ret) { 111451da2240SYuvaraj CD dev_err(slot->host->dev, 111551da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 111651da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 111751da2240SYuvaraj CD return; 111851da2240SYuvaraj CD } 111951da2240SYuvaraj CD } 112051da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) { 112151da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 112251da2240SYuvaraj CD if (ret < 0) 112351da2240SYuvaraj CD dev_err(slot->host->dev, 112451da2240SYuvaraj CD "failed to enable vqmmc regulator\n"); 112551da2240SYuvaraj CD else 112651da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 112751da2240SYuvaraj CD } 1128f95f3850SWill Newton set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 11294366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 11304366dcc5SJaehoon Chung regs |= (1 << slot->id); 11314366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1132e6f34e2fSJames Hogan break; 1133e6f34e2fSJames Hogan case MMC_POWER_OFF: 113451da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 113551da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 113651da2240SYuvaraj CD 113751da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) { 113851da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 113951da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 114051da2240SYuvaraj CD } 114151da2240SYuvaraj CD 11424366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 11434366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 11444366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1145f95f3850SWill Newton break; 1146f95f3850SWill Newton default: 1147f95f3850SWill Newton break; 1148f95f3850SWill Newton } 1149f95f3850SWill Newton } 1150f95f3850SWill Newton 115101730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 115201730558SDoug Anderson { 115301730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 115401730558SDoug Anderson u32 status; 115501730558SDoug Anderson 115601730558SDoug Anderson /* 115701730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 115801730558SDoug Anderson * (the data lines) are 0000 115901730558SDoug Anderson */ 116001730558SDoug Anderson status = mci_readl(slot->host, STATUS); 116101730558SDoug Anderson 116201730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 116301730558SDoug Anderson } 116401730558SDoug Anderson 116501730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 116601730558SDoug Anderson { 116701730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 116801730558SDoug Anderson struct dw_mci *host = slot->host; 116901730558SDoug Anderson u32 uhs; 117001730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 117101730558SDoug Anderson int min_uv, max_uv; 117201730558SDoug Anderson int ret; 117301730558SDoug Anderson 117401730558SDoug Anderson /* 117501730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 117601730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 117701730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 117801730558SDoug Anderson */ 117901730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 118001730558SDoug Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 118101730558SDoug Anderson min_uv = 2700000; 118201730558SDoug Anderson max_uv = 3600000; 118301730558SDoug Anderson uhs &= ~v18; 118401730558SDoug Anderson } else { 118501730558SDoug Anderson min_uv = 1700000; 118601730558SDoug Anderson max_uv = 1950000; 118701730558SDoug Anderson uhs |= v18; 118801730558SDoug Anderson } 118901730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 119001730558SDoug Anderson ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 119101730558SDoug Anderson 119201730558SDoug Anderson if (ret) { 1193b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 119401730558SDoug Anderson "Regulator set error %d: %d - %d\n", 119501730558SDoug Anderson ret, min_uv, max_uv); 119601730558SDoug Anderson return ret; 119701730558SDoug Anderson } 119801730558SDoug Anderson } 119901730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 120001730558SDoug Anderson 120101730558SDoug Anderson return 0; 120201730558SDoug Anderson } 120301730558SDoug Anderson 1204f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1205f95f3850SWill Newton { 1206f95f3850SWill Newton int read_only; 1207f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 12089795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1209f95f3850SWill Newton 1210f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 121126375b5cSJaehoon Chung if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) || 121226375b5cSJaehoon Chung (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)) 1213b4967aa5SThomas Abraham read_only = 0; 12149795a846SJaehoon Chung else if (!IS_ERR_VALUE(gpio_ro)) 12159795a846SJaehoon Chung read_only = gpio_ro; 1216f95f3850SWill Newton else 1217f95f3850SWill Newton read_only = 1218f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1219f95f3850SWill Newton 1220f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1221f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1222f95f3850SWill Newton 1223f95f3850SWill Newton return read_only; 1224f95f3850SWill Newton } 1225f95f3850SWill Newton 1226f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1227f95f3850SWill Newton { 1228f95f3850SWill Newton int present; 1229f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1230f95f3850SWill Newton struct dw_mci_board *brd = slot->host->pdata; 12317cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 12327cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1233f95f3850SWill Newton 1234f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1235fc3d7720SJaehoon Chung if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 1236fc3d7720SJaehoon Chung present = 1; 1237bf626e55SZhangfei Gao else if (!IS_ERR_VALUE(gpio_cd)) 12387cf347bdSZhangfei Gao present = gpio_cd; 1239f95f3850SWill Newton else 1240f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1241f95f3850SWill Newton == 0 ? 1 : 0; 1242f95f3850SWill Newton 12437cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1244bf626e55SZhangfei Gao if (present) { 1245bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1246f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1247bf626e55SZhangfei Gao } else { 1248bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1249f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1250bf626e55SZhangfei Gao } 12517cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1252f95f3850SWill Newton 1253f95f3850SWill Newton return present; 1254f95f3850SWill Newton } 1255f95f3850SWill Newton 1256b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1257b24c8b26SDoug Anderson { 1258b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1259b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1260b24c8b26SDoug Anderson 12619623b5b9SDoug Anderson /* 12629623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 12639623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 12649623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 12659623b5b9SDoug Anderson */ 1266b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 12679623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1268b24c8b26SDoug Anderson u32 clk_en_a_old; 1269b24c8b26SDoug Anderson u32 clk_en_a; 12709623b5b9SDoug Anderson 1271b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 12729623b5b9SDoug Anderson 1273b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1274b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1275b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1276b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1277b24c8b26SDoug Anderson } else { 1278b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1279b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1280b24c8b26SDoug Anderson } 1281b24c8b26SDoug Anderson 1282b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1283b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 12849623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 12859623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 12869623b5b9SDoug Anderson } 12879623b5b9SDoug Anderson } 1288b24c8b26SDoug Anderson } 12899623b5b9SDoug Anderson 12901a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 12911a5c8e1fSShashidhar Hiremath { 12921a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 12931a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1294*f8c58c11SDoug Anderson unsigned long irqflags; 12951a5c8e1fSShashidhar Hiremath u32 int_mask; 12961a5c8e1fSShashidhar Hiremath 1297*f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1298*f8c58c11SDoug Anderson 12991a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 13001a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1301b24c8b26SDoug Anderson if (enb) 1302b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1303b24c8b26SDoug Anderson else 1304b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1305b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1306*f8c58c11SDoug Anderson 1307*f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13081a5c8e1fSShashidhar Hiremath } 13091a5c8e1fSShashidhar Hiremath 13100976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 13110976f16dSSeungwon Jeon { 13120976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 13130976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 13140976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 13150976f16dSSeungwon Jeon struct dw_mci_tuning_data tuning_data; 13160976f16dSSeungwon Jeon int err = -ENOSYS; 13170976f16dSSeungwon Jeon 13180976f16dSSeungwon Jeon if (opcode == MMC_SEND_TUNING_BLOCK_HS200) { 13190976f16dSSeungwon Jeon if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 13200976f16dSSeungwon Jeon tuning_data.blk_pattern = tuning_blk_pattern_8bit; 13210976f16dSSeungwon Jeon tuning_data.blksz = sizeof(tuning_blk_pattern_8bit); 13220976f16dSSeungwon Jeon } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) { 13230976f16dSSeungwon Jeon tuning_data.blk_pattern = tuning_blk_pattern_4bit; 13240976f16dSSeungwon Jeon tuning_data.blksz = sizeof(tuning_blk_pattern_4bit); 13250976f16dSSeungwon Jeon } else { 13260976f16dSSeungwon Jeon return -EINVAL; 13270976f16dSSeungwon Jeon } 13280976f16dSSeungwon Jeon } else if (opcode == MMC_SEND_TUNING_BLOCK) { 13290976f16dSSeungwon Jeon tuning_data.blk_pattern = tuning_blk_pattern_4bit; 13300976f16dSSeungwon Jeon tuning_data.blksz = sizeof(tuning_blk_pattern_4bit); 13310976f16dSSeungwon Jeon } else { 13320976f16dSSeungwon Jeon dev_err(host->dev, 13330976f16dSSeungwon Jeon "Undefined command(%d) for tuning\n", opcode); 13340976f16dSSeungwon Jeon return -EINVAL; 13350976f16dSSeungwon Jeon } 13360976f16dSSeungwon Jeon 13370976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 13380976f16dSSeungwon Jeon err = drv_data->execute_tuning(slot, opcode, &tuning_data); 13390976f16dSSeungwon Jeon return err; 13400976f16dSSeungwon Jeon } 13410976f16dSSeungwon Jeon 1342f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1343f95f3850SWill Newton .request = dw_mci_request, 13449aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 13459aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1346f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1347f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1348f95f3850SWill Newton .get_cd = dw_mci_get_cd, 13491a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 13500976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 135101730558SDoug Anderson .card_busy = dw_mci_card_busy, 135201730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1353b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 1354f95f3850SWill Newton }; 1355f95f3850SWill Newton 1356f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1357f95f3850SWill Newton __releases(&host->lock) 1358f95f3850SWill Newton __acquires(&host->lock) 1359f95f3850SWill Newton { 1360f95f3850SWill Newton struct dw_mci_slot *slot; 1361f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1362f95f3850SWill Newton 1363f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1364f95f3850SWill Newton 1365f95f3850SWill Newton host->cur_slot->mrq = NULL; 1366f95f3850SWill Newton host->mrq = NULL; 1367f95f3850SWill Newton if (!list_empty(&host->queue)) { 1368f95f3850SWill Newton slot = list_entry(host->queue.next, 1369f95f3850SWill Newton struct dw_mci_slot, queue_node); 1370f95f3850SWill Newton list_del(&slot->queue_node); 13714a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1372f95f3850SWill Newton mmc_hostname(slot->mmc)); 1373f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1374f95f3850SWill Newton dw_mci_start_request(host, slot); 1375f95f3850SWill Newton } else { 13764a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 137701730558SDoug Anderson 137801730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 137901730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 138001730558SDoug Anderson else 1381f95f3850SWill Newton host->state = STATE_IDLE; 1382f95f3850SWill Newton } 1383f95f3850SWill Newton 1384f95f3850SWill Newton spin_unlock(&host->lock); 1385f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1386f95f3850SWill Newton spin_lock(&host->lock); 1387f95f3850SWill Newton } 1388f95f3850SWill Newton 1389e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1390f95f3850SWill Newton { 1391f95f3850SWill Newton u32 status = host->cmd_status; 1392f95f3850SWill Newton 1393f95f3850SWill Newton host->cmd_status = 0; 1394f95f3850SWill Newton 1395f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1396f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1397f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1398f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1399f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1400f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1401f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1402f95f3850SWill Newton } else { 1403f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1404f95f3850SWill Newton cmd->resp[1] = 0; 1405f95f3850SWill Newton cmd->resp[2] = 0; 1406f95f3850SWill Newton cmd->resp[3] = 0; 1407f95f3850SWill Newton } 1408f95f3850SWill Newton } 1409f95f3850SWill Newton 1410f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1411f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1412f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1413f95f3850SWill Newton cmd->error = -EILSEQ; 1414f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1415f95f3850SWill Newton cmd->error = -EIO; 1416f95f3850SWill Newton else 1417f95f3850SWill Newton cmd->error = 0; 1418f95f3850SWill Newton 1419f95f3850SWill Newton if (cmd->error) { 1420f95f3850SWill Newton /* newer ip versions need a delay between retries */ 1421f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1422f95f3850SWill Newton mdelay(20); 1423f95f3850SWill Newton } 1424e352c813SSeungwon Jeon 1425e352c813SSeungwon Jeon return cmd->error; 1426e352c813SSeungwon Jeon } 1427e352c813SSeungwon Jeon 1428e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1429e352c813SSeungwon Jeon { 143031bff450SSeungwon Jeon u32 status = host->data_status; 1431e352c813SSeungwon Jeon 1432e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1433e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1434e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1435e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1436e352c813SSeungwon Jeon data->error = -EILSEQ; 1437e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1438e352c813SSeungwon Jeon if (host->dir_status == 1439e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1440e352c813SSeungwon Jeon /* 1441e352c813SSeungwon Jeon * No data CRC status was returned. 1442e352c813SSeungwon Jeon * The number of bytes transferred 1443e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1444e352c813SSeungwon Jeon */ 1445e352c813SSeungwon Jeon data->bytes_xfered = 0; 1446e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1447e352c813SSeungwon Jeon } else if (host->dir_status == 1448e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1449e352c813SSeungwon Jeon data->error = -EIO; 1450e352c813SSeungwon Jeon } 1451e352c813SSeungwon Jeon } else { 1452e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1453e352c813SSeungwon Jeon data->error = -EIO; 1454e352c813SSeungwon Jeon } 1455e352c813SSeungwon Jeon 1456e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1457e352c813SSeungwon Jeon 1458e352c813SSeungwon Jeon /* 1459e352c813SSeungwon Jeon * After an error, there may be data lingering 146031bff450SSeungwon Jeon * in the FIFO 1461e352c813SSeungwon Jeon */ 14623a33a94cSSonny Rao dw_mci_reset(host); 1463e352c813SSeungwon Jeon } else { 1464e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1465e352c813SSeungwon Jeon data->error = 0; 1466e352c813SSeungwon Jeon } 1467e352c813SSeungwon Jeon 1468e352c813SSeungwon Jeon return data->error; 1469f95f3850SWill Newton } 1470f95f3850SWill Newton 1471f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1472f95f3850SWill Newton { 1473f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1474f95f3850SWill Newton struct mmc_data *data; 1475f95f3850SWill Newton struct mmc_command *cmd; 1476e352c813SSeungwon Jeon struct mmc_request *mrq; 1477f95f3850SWill Newton enum dw_mci_state state; 1478f95f3850SWill Newton enum dw_mci_state prev_state; 1479e352c813SSeungwon Jeon unsigned int err; 1480f95f3850SWill Newton 1481f95f3850SWill Newton spin_lock(&host->lock); 1482f95f3850SWill Newton 1483f95f3850SWill Newton state = host->state; 1484f95f3850SWill Newton data = host->data; 1485e352c813SSeungwon Jeon mrq = host->mrq; 1486f95f3850SWill Newton 1487f95f3850SWill Newton do { 1488f95f3850SWill Newton prev_state = state; 1489f95f3850SWill Newton 1490f95f3850SWill Newton switch (state) { 1491f95f3850SWill Newton case STATE_IDLE: 149201730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1493f95f3850SWill Newton break; 1494f95f3850SWill Newton 149501730558SDoug Anderson case STATE_SENDING_CMD11: 1496f95f3850SWill Newton case STATE_SENDING_CMD: 1497f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1498f95f3850SWill Newton &host->pending_events)) 1499f95f3850SWill Newton break; 1500f95f3850SWill Newton 1501f95f3850SWill Newton cmd = host->cmd; 1502f95f3850SWill Newton host->cmd = NULL; 1503f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1504e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1505e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1506053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1507053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1508e352c813SSeungwon Jeon mrq->cmd); 1509053b3ce6SSeungwon Jeon goto unlock; 1510053b3ce6SSeungwon Jeon } 1511053b3ce6SSeungwon Jeon 1512e352c813SSeungwon Jeon if (cmd->data && err) { 151371abb133SSeungwon Jeon dw_mci_stop_dma(host); 151490c2143aSSeungwon Jeon send_stop_abort(host, data); 151571abb133SSeungwon Jeon state = STATE_SENDING_STOP; 151671abb133SSeungwon Jeon break; 151771abb133SSeungwon Jeon } 151871abb133SSeungwon Jeon 1519e352c813SSeungwon Jeon if (!cmd->data || err) { 1520e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1521f95f3850SWill Newton goto unlock; 1522f95f3850SWill Newton } 1523f95f3850SWill Newton 1524f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1525f95f3850SWill Newton /* fall through */ 1526f95f3850SWill Newton 1527f95f3850SWill Newton case STATE_SENDING_DATA: 15282aa35465SDoug Anderson /* 15292aa35465SDoug Anderson * We could get a data error and never a transfer 15302aa35465SDoug Anderson * complete so we'd better check for it here. 15312aa35465SDoug Anderson * 15322aa35465SDoug Anderson * Note that we don't really care if we also got a 15332aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 15342aa35465SDoug Anderson * abort won't hurt. 15352aa35465SDoug Anderson */ 1536f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1537f95f3850SWill Newton &host->pending_events)) { 1538f95f3850SWill Newton dw_mci_stop_dma(host); 153990c2143aSSeungwon Jeon send_stop_abort(host, data); 1540f95f3850SWill Newton state = STATE_DATA_ERROR; 1541f95f3850SWill Newton break; 1542f95f3850SWill Newton } 1543f95f3850SWill Newton 1544f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1545f95f3850SWill Newton &host->pending_events)) 1546f95f3850SWill Newton break; 1547f95f3850SWill Newton 1548f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 15492aa35465SDoug Anderson 15502aa35465SDoug Anderson /* 15512aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 15522aa35465SDoug Anderson * before the transfer completed. This might not have 15532aa35465SDoug Anderson * been caught by the check above because the interrupt 15542aa35465SDoug Anderson * could have gone off between the previous check and 15552aa35465SDoug Anderson * the check for transfer complete. 15562aa35465SDoug Anderson * 15572aa35465SDoug Anderson * Technically this ought not be needed assuming we 15582aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 15592aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 15602aa35465SDoug Anderson * 15612aa35465SDoug Anderson * This has the advantage of sending the stop command. 15622aa35465SDoug Anderson */ 15632aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 15642aa35465SDoug Anderson &host->pending_events)) { 15652aa35465SDoug Anderson dw_mci_stop_dma(host); 15662aa35465SDoug Anderson send_stop_abort(host, data); 15672aa35465SDoug Anderson state = STATE_DATA_ERROR; 15682aa35465SDoug Anderson break; 15692aa35465SDoug Anderson } 1570f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 15712aa35465SDoug Anderson 1572f95f3850SWill Newton /* fall through */ 1573f95f3850SWill Newton 1574f95f3850SWill Newton case STATE_DATA_BUSY: 1575f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1576f95f3850SWill Newton &host->pending_events)) 1577f95f3850SWill Newton break; 1578f95f3850SWill Newton 1579f95f3850SWill Newton host->data = NULL; 1580f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1581e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1582f95f3850SWill Newton 1583e352c813SSeungwon Jeon if (!err) { 1584e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 158517c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1586053b3ce6SSeungwon Jeon data->stop->error = 0; 1587e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1588053b3ce6SSeungwon Jeon goto unlock; 1589053b3ce6SSeungwon Jeon } 1590053b3ce6SSeungwon Jeon 159190c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1592e352c813SSeungwon Jeon if (data->stop) 159390c2143aSSeungwon Jeon send_stop_abort(host, data); 15942aa35465SDoug Anderson } else { 15952aa35465SDoug Anderson /* 15962aa35465SDoug Anderson * If we don't have a command complete now we'll 15972aa35465SDoug Anderson * never get one since we just reset everything; 15982aa35465SDoug Anderson * better end the request. 15992aa35465SDoug Anderson * 16002aa35465SDoug Anderson * If we do have a command complete we'll fall 16012aa35465SDoug Anderson * through to the SENDING_STOP command and 16022aa35465SDoug Anderson * everything will be peachy keen. 16032aa35465SDoug Anderson */ 16042aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 16052aa35465SDoug Anderson &host->pending_events)) { 16062aa35465SDoug Anderson host->cmd = NULL; 16072aa35465SDoug Anderson dw_mci_request_end(host, mrq); 16082aa35465SDoug Anderson goto unlock; 16092aa35465SDoug Anderson } 161090c2143aSSeungwon Jeon } 1611e352c813SSeungwon Jeon 1612e352c813SSeungwon Jeon /* 1613e352c813SSeungwon Jeon * If err has non-zero, 1614e352c813SSeungwon Jeon * stop-abort command has been already issued. 1615e352c813SSeungwon Jeon */ 1616e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1617e352c813SSeungwon Jeon 1618f95f3850SWill Newton /* fall through */ 1619f95f3850SWill Newton 1620f95f3850SWill Newton case STATE_SENDING_STOP: 1621f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1622f95f3850SWill Newton &host->pending_events)) 1623f95f3850SWill Newton break; 1624f95f3850SWill Newton 162571abb133SSeungwon Jeon /* CMD error in data command */ 162631bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 16273a33a94cSSonny Rao dw_mci_reset(host); 162871abb133SSeungwon Jeon 1629f95f3850SWill Newton host->cmd = NULL; 163071abb133SSeungwon Jeon host->data = NULL; 163190c2143aSSeungwon Jeon 1632e352c813SSeungwon Jeon if (mrq->stop) 1633e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 163490c2143aSSeungwon Jeon else 163590c2143aSSeungwon Jeon host->cmd_status = 0; 163690c2143aSSeungwon Jeon 1637e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1638f95f3850SWill Newton goto unlock; 1639f95f3850SWill Newton 1640f95f3850SWill Newton case STATE_DATA_ERROR: 1641f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1642f95f3850SWill Newton &host->pending_events)) 1643f95f3850SWill Newton break; 1644f95f3850SWill Newton 1645f95f3850SWill Newton state = STATE_DATA_BUSY; 1646f95f3850SWill Newton break; 1647f95f3850SWill Newton } 1648f95f3850SWill Newton } while (state != prev_state); 1649f95f3850SWill Newton 1650f95f3850SWill Newton host->state = state; 1651f95f3850SWill Newton unlock: 1652f95f3850SWill Newton spin_unlock(&host->lock); 1653f95f3850SWill Newton 1654f95f3850SWill Newton } 1655f95f3850SWill Newton 165634b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 165734b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 165834b664a2SJames Hogan { 165934b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 166034b664a2SJames Hogan host->part_buf_count = cnt; 166134b664a2SJames Hogan } 166234b664a2SJames Hogan 166334b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 166434b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 166534b664a2SJames Hogan { 166634b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 166734b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 166834b664a2SJames Hogan host->part_buf_count += cnt; 166934b664a2SJames Hogan return cnt; 167034b664a2SJames Hogan } 167134b664a2SJames Hogan 167234b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 167334b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 167434b664a2SJames Hogan { 167534b664a2SJames Hogan cnt = min(cnt, (int)host->part_buf_count); 167634b664a2SJames Hogan if (cnt) { 167734b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 167834b664a2SJames Hogan cnt); 167934b664a2SJames Hogan host->part_buf_count -= cnt; 168034b664a2SJames Hogan host->part_buf_start += cnt; 168134b664a2SJames Hogan } 168234b664a2SJames Hogan return cnt; 168334b664a2SJames Hogan } 168434b664a2SJames Hogan 168534b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 168634b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 168734b664a2SJames Hogan { 168834b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 168934b664a2SJames Hogan host->part_buf_start = cnt; 169034b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 169134b664a2SJames Hogan } 169234b664a2SJames Hogan 1693f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1694f95f3850SWill Newton { 1695cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1696cfbeb59cSMarkos Chandras int init_cnt = cnt; 1697cfbeb59cSMarkos Chandras 169834b664a2SJames Hogan /* try and push anything in the part_buf */ 169934b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 170034b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 170134b664a2SJames Hogan buf += len; 170234b664a2SJames Hogan cnt -= len; 1703cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 17044e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17054e0a5adfSJaehoon Chung host->part_buf16); 170634b664a2SJames Hogan host->part_buf_count = 0; 170734b664a2SJames Hogan } 170834b664a2SJames Hogan } 170934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 171034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 171134b664a2SJames Hogan while (cnt >= 2) { 171234b664a2SJames Hogan u16 aligned_buf[64]; 171334b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 171434b664a2SJames Hogan int items = len >> 1; 171534b664a2SJames Hogan int i; 171634b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 171734b664a2SJames Hogan memcpy(aligned_buf, buf, len); 171834b664a2SJames Hogan buf += len; 171934b664a2SJames Hogan cnt -= len; 172034b664a2SJames Hogan /* push data from aligned buffer into fifo */ 172134b664a2SJames Hogan for (i = 0; i < items; ++i) 17224e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17234e0a5adfSJaehoon Chung aligned_buf[i]); 172434b664a2SJames Hogan } 172534b664a2SJames Hogan } else 172634b664a2SJames Hogan #endif 172734b664a2SJames Hogan { 172834b664a2SJames Hogan u16 *pdata = buf; 172934b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 17304e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), *pdata++); 173134b664a2SJames Hogan buf = pdata; 173234b664a2SJames Hogan } 173334b664a2SJames Hogan /* put anything remaining in the part_buf */ 173434b664a2SJames Hogan if (cnt) { 173534b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1736cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1737cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1738cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 17394e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17404e0a5adfSJaehoon Chung host->part_buf16); 1741f95f3850SWill Newton } 1742f95f3850SWill Newton } 1743f95f3850SWill Newton 1744f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1745f95f3850SWill Newton { 174634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 174734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 174834b664a2SJames Hogan while (cnt >= 2) { 174934b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 175034b664a2SJames Hogan u16 aligned_buf[64]; 175134b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 175234b664a2SJames Hogan int items = len >> 1; 175334b664a2SJames Hogan int i; 175434b664a2SJames Hogan for (i = 0; i < items; ++i) 17554e0a5adfSJaehoon Chung aligned_buf[i] = mci_readw(host, 17564e0a5adfSJaehoon Chung DATA(host->data_offset)); 175734b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 175834b664a2SJames Hogan memcpy(buf, aligned_buf, len); 175934b664a2SJames Hogan buf += len; 176034b664a2SJames Hogan cnt -= len; 176134b664a2SJames Hogan } 176234b664a2SJames Hogan } else 176334b664a2SJames Hogan #endif 176434b664a2SJames Hogan { 176534b664a2SJames Hogan u16 *pdata = buf; 176634b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 17674e0a5adfSJaehoon Chung *pdata++ = mci_readw(host, DATA(host->data_offset)); 176834b664a2SJames Hogan buf = pdata; 176934b664a2SJames Hogan } 177034b664a2SJames Hogan if (cnt) { 17714e0a5adfSJaehoon Chung host->part_buf16 = mci_readw(host, DATA(host->data_offset)); 177234b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1773f95f3850SWill Newton } 1774f95f3850SWill Newton } 1775f95f3850SWill Newton 1776f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1777f95f3850SWill Newton { 1778cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1779cfbeb59cSMarkos Chandras int init_cnt = cnt; 1780cfbeb59cSMarkos Chandras 178134b664a2SJames Hogan /* try and push anything in the part_buf */ 178234b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 178334b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 178434b664a2SJames Hogan buf += len; 178534b664a2SJames Hogan cnt -= len; 1786cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 17874e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 17884e0a5adfSJaehoon Chung host->part_buf32); 178934b664a2SJames Hogan host->part_buf_count = 0; 179034b664a2SJames Hogan } 179134b664a2SJames Hogan } 179234b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 179334b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 179434b664a2SJames Hogan while (cnt >= 4) { 179534b664a2SJames Hogan u32 aligned_buf[32]; 179634b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 179734b664a2SJames Hogan int items = len >> 2; 179834b664a2SJames Hogan int i; 179934b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 180034b664a2SJames Hogan memcpy(aligned_buf, buf, len); 180134b664a2SJames Hogan buf += len; 180234b664a2SJames Hogan cnt -= len; 180334b664a2SJames Hogan /* push data from aligned buffer into fifo */ 180434b664a2SJames Hogan for (i = 0; i < items; ++i) 18054e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18064e0a5adfSJaehoon Chung aligned_buf[i]); 180734b664a2SJames Hogan } 180834b664a2SJames Hogan } else 180934b664a2SJames Hogan #endif 181034b664a2SJames Hogan { 181134b664a2SJames Hogan u32 *pdata = buf; 181234b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 18134e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), *pdata++); 181434b664a2SJames Hogan buf = pdata; 181534b664a2SJames Hogan } 181634b664a2SJames Hogan /* put anything remaining in the part_buf */ 181734b664a2SJames Hogan if (cnt) { 181834b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1819cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1820cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1821cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 18224e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18234e0a5adfSJaehoon Chung host->part_buf32); 1824f95f3850SWill Newton } 1825f95f3850SWill Newton } 1826f95f3850SWill Newton 1827f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1828f95f3850SWill Newton { 182934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 183034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 183134b664a2SJames Hogan while (cnt >= 4) { 183234b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 183334b664a2SJames Hogan u32 aligned_buf[32]; 183434b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 183534b664a2SJames Hogan int items = len >> 2; 183634b664a2SJames Hogan int i; 183734b664a2SJames Hogan for (i = 0; i < items; ++i) 18384e0a5adfSJaehoon Chung aligned_buf[i] = mci_readl(host, 18394e0a5adfSJaehoon Chung DATA(host->data_offset)); 184034b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 184134b664a2SJames Hogan memcpy(buf, aligned_buf, len); 184234b664a2SJames Hogan buf += len; 184334b664a2SJames Hogan cnt -= len; 184434b664a2SJames Hogan } 184534b664a2SJames Hogan } else 184634b664a2SJames Hogan #endif 184734b664a2SJames Hogan { 184834b664a2SJames Hogan u32 *pdata = buf; 184934b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 18504e0a5adfSJaehoon Chung *pdata++ = mci_readl(host, DATA(host->data_offset)); 185134b664a2SJames Hogan buf = pdata; 185234b664a2SJames Hogan } 185334b664a2SJames Hogan if (cnt) { 18544e0a5adfSJaehoon Chung host->part_buf32 = mci_readl(host, DATA(host->data_offset)); 185534b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1856f95f3850SWill Newton } 1857f95f3850SWill Newton } 1858f95f3850SWill Newton 1859f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1860f95f3850SWill Newton { 1861cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1862cfbeb59cSMarkos Chandras int init_cnt = cnt; 1863cfbeb59cSMarkos Chandras 186434b664a2SJames Hogan /* try and push anything in the part_buf */ 186534b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 186634b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 186734b664a2SJames Hogan buf += len; 186834b664a2SJames Hogan cnt -= len; 1869c09fbd74SSeungwon Jeon 1870cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 1871c09fbd74SSeungwon Jeon mci_writeq(host, DATA(host->data_offset), 18724e0a5adfSJaehoon Chung host->part_buf); 187334b664a2SJames Hogan host->part_buf_count = 0; 187434b664a2SJames Hogan } 187534b664a2SJames Hogan } 187634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 187734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 187834b664a2SJames Hogan while (cnt >= 8) { 187934b664a2SJames Hogan u64 aligned_buf[16]; 188034b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 188134b664a2SJames Hogan int items = len >> 3; 188234b664a2SJames Hogan int i; 188334b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 188434b664a2SJames Hogan memcpy(aligned_buf, buf, len); 188534b664a2SJames Hogan buf += len; 188634b664a2SJames Hogan cnt -= len; 188734b664a2SJames Hogan /* push data from aligned buffer into fifo */ 188834b664a2SJames Hogan for (i = 0; i < items; ++i) 18894e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 18904e0a5adfSJaehoon Chung aligned_buf[i]); 189134b664a2SJames Hogan } 189234b664a2SJames Hogan } else 189334b664a2SJames Hogan #endif 189434b664a2SJames Hogan { 189534b664a2SJames Hogan u64 *pdata = buf; 189634b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 18974e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), *pdata++); 189834b664a2SJames Hogan buf = pdata; 189934b664a2SJames Hogan } 190034b664a2SJames Hogan /* put anything remaining in the part_buf */ 190134b664a2SJames Hogan if (cnt) { 190234b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1903cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1904cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1905cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 19064e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 19074e0a5adfSJaehoon Chung host->part_buf); 1908f95f3850SWill Newton } 1909f95f3850SWill Newton } 1910f95f3850SWill Newton 1911f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1912f95f3850SWill Newton { 191334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 191434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 191534b664a2SJames Hogan while (cnt >= 8) { 191634b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 191734b664a2SJames Hogan u64 aligned_buf[16]; 191834b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 191934b664a2SJames Hogan int items = len >> 3; 192034b664a2SJames Hogan int i; 192134b664a2SJames Hogan for (i = 0; i < items; ++i) 19224e0a5adfSJaehoon Chung aligned_buf[i] = mci_readq(host, 19234e0a5adfSJaehoon Chung DATA(host->data_offset)); 192434b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 192534b664a2SJames Hogan memcpy(buf, aligned_buf, len); 192634b664a2SJames Hogan buf += len; 192734b664a2SJames Hogan cnt -= len; 1928f95f3850SWill Newton } 192934b664a2SJames Hogan } else 193034b664a2SJames Hogan #endif 193134b664a2SJames Hogan { 193234b664a2SJames Hogan u64 *pdata = buf; 193334b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 19344e0a5adfSJaehoon Chung *pdata++ = mci_readq(host, DATA(host->data_offset)); 193534b664a2SJames Hogan buf = pdata; 193634b664a2SJames Hogan } 193734b664a2SJames Hogan if (cnt) { 19384e0a5adfSJaehoon Chung host->part_buf = mci_readq(host, DATA(host->data_offset)); 193934b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 194034b664a2SJames Hogan } 194134b664a2SJames Hogan } 194234b664a2SJames Hogan 194334b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 194434b664a2SJames Hogan { 194534b664a2SJames Hogan int len; 194634b664a2SJames Hogan 194734b664a2SJames Hogan /* get remaining partial bytes */ 194834b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 194934b664a2SJames Hogan if (unlikely(len == cnt)) 195034b664a2SJames Hogan return; 195134b664a2SJames Hogan buf += len; 195234b664a2SJames Hogan cnt -= len; 195334b664a2SJames Hogan 195434b664a2SJames Hogan /* get the rest of the data */ 195534b664a2SJames Hogan host->pull_data(host, buf, cnt); 1956f95f3850SWill Newton } 1957f95f3850SWill Newton 195887a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 1959f95f3850SWill Newton { 1960f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 1961f9c2a0dcSSeungwon Jeon void *buf; 1962f9c2a0dcSSeungwon Jeon unsigned int offset; 1963f95f3850SWill Newton struct mmc_data *data = host->data; 1964f95f3850SWill Newton int shift = host->data_shift; 1965f95f3850SWill Newton u32 status; 19663e4b0d8bSMarkos Chandras unsigned int len; 1967f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 1968f95f3850SWill Newton 1969f95f3850SWill Newton do { 1970f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 1971f9c2a0dcSSeungwon Jeon goto done; 1972f95f3850SWill Newton 19734225fc85SImre Deak host->sg = sg_miter->piter.sg; 1974f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 1975f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 1976f9c2a0dcSSeungwon Jeon offset = 0; 1977f9c2a0dcSSeungwon Jeon 1978f9c2a0dcSSeungwon Jeon do { 1979f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 1980f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 1981f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 1982f9c2a0dcSSeungwon Jeon if (!len) 1983f9c2a0dcSSeungwon Jeon break; 1984f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 19853e4b0d8bSMarkos Chandras data->bytes_xfered += len; 1986f95f3850SWill Newton offset += len; 1987f9c2a0dcSSeungwon Jeon remain -= len; 1988f9c2a0dcSSeungwon Jeon } while (remain); 1989f95f3850SWill Newton 1990e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 1991f95f3850SWill Newton status = mci_readl(host, MINTSTS); 1992f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 199387a74d39SKyoungil Kim /* if the RXDR is ready read again */ 199487a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 199587a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 1996f9c2a0dcSSeungwon Jeon 1997f9c2a0dcSSeungwon Jeon if (!remain) { 1998f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 1999f9c2a0dcSSeungwon Jeon goto done; 2000f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2001f9c2a0dcSSeungwon Jeon } 2002f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2003f95f3850SWill Newton return; 2004f95f3850SWill Newton 2005f95f3850SWill Newton done: 2006f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2007f9c2a0dcSSeungwon Jeon host->sg = NULL; 2008f95f3850SWill Newton smp_wmb(); 2009f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2010f95f3850SWill Newton } 2011f95f3850SWill Newton 2012f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2013f95f3850SWill Newton { 2014f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2015f9c2a0dcSSeungwon Jeon void *buf; 2016f9c2a0dcSSeungwon Jeon unsigned int offset; 2017f95f3850SWill Newton struct mmc_data *data = host->data; 2018f95f3850SWill Newton int shift = host->data_shift; 2019f95f3850SWill Newton u32 status; 20203e4b0d8bSMarkos Chandras unsigned int len; 2021f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2022f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2023f95f3850SWill Newton 2024f95f3850SWill Newton do { 2025f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2026f9c2a0dcSSeungwon Jeon goto done; 2027f95f3850SWill Newton 20284225fc85SImre Deak host->sg = sg_miter->piter.sg; 2029f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2030f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2031f9c2a0dcSSeungwon Jeon offset = 0; 2032f9c2a0dcSSeungwon Jeon 2033f9c2a0dcSSeungwon Jeon do { 2034f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2035f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2036f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2037f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2038f9c2a0dcSSeungwon Jeon if (!len) 2039f9c2a0dcSSeungwon Jeon break; 2040f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 20413e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2042f95f3850SWill Newton offset += len; 2043f9c2a0dcSSeungwon Jeon remain -= len; 2044f9c2a0dcSSeungwon Jeon } while (remain); 2045f95f3850SWill Newton 2046e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2047f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2048f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2049f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2050f9c2a0dcSSeungwon Jeon 2051f9c2a0dcSSeungwon Jeon if (!remain) { 2052f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2053f9c2a0dcSSeungwon Jeon goto done; 2054f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2055f9c2a0dcSSeungwon Jeon } 2056f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2057f95f3850SWill Newton return; 2058f95f3850SWill Newton 2059f95f3850SWill Newton done: 2060f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2061f9c2a0dcSSeungwon Jeon host->sg = NULL; 2062f95f3850SWill Newton smp_wmb(); 2063f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2064f95f3850SWill Newton } 2065f95f3850SWill Newton 2066f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2067f95f3850SWill Newton { 2068f95f3850SWill Newton if (!host->cmd_status) 2069f95f3850SWill Newton host->cmd_status = status; 2070f95f3850SWill Newton 2071f95f3850SWill Newton smp_wmb(); 2072f95f3850SWill Newton 2073f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2074f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2075f95f3850SWill Newton } 2076f95f3850SWill Newton 20776130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 20786130e7a9SDoug Anderson { 20796130e7a9SDoug Anderson int i; 20806130e7a9SDoug Anderson 20816130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 20826130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 20836130e7a9SDoug Anderson 20846130e7a9SDoug Anderson if (!slot) 20856130e7a9SDoug Anderson continue; 20866130e7a9SDoug Anderson 20876130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 20886130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 20896130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 20906130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 20916130e7a9SDoug Anderson } 20926130e7a9SDoug Anderson } 20936130e7a9SDoug Anderson 2094f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2095f95f3850SWill Newton { 2096f95f3850SWill Newton struct dw_mci *host = dev_id; 2097182c9081SSeungwon Jeon u32 pending; 20981a5c8e1fSShashidhar Hiremath int i; 2099f95f3850SWill Newton 2100f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2101f95f3850SWill Newton 2102f95f3850SWill Newton /* 2103f95f3850SWill Newton * DTO fix - version 2.10a and below, and only if internal DMA 2104f95f3850SWill Newton * is configured. 2105f95f3850SWill Newton */ 2106f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2107f95f3850SWill Newton if (!pending && 2108f95f3850SWill Newton ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2109f95f3850SWill Newton pending |= SDMMC_INT_DATA_OVER; 2110f95f3850SWill Newton } 2111f95f3850SWill Newton 2112476d79f1SDoug Anderson if (pending) { 211301730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 211401730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 211501730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 211601730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 211701730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 211801730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 211901730558SDoug Anderson } 212001730558SDoug Anderson 2121f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2122f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2123182c9081SSeungwon Jeon host->cmd_status = pending; 2124f95f3850SWill Newton smp_wmb(); 2125f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2126f95f3850SWill Newton } 2127f95f3850SWill Newton 2128f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2129f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2130f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2131182c9081SSeungwon Jeon host->data_status = pending; 2132f95f3850SWill Newton smp_wmb(); 2133f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2134f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2135f95f3850SWill Newton } 2136f95f3850SWill Newton 2137f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 2138f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2139f95f3850SWill Newton if (!host->data_status) 2140182c9081SSeungwon Jeon host->data_status = pending; 2141f95f3850SWill Newton smp_wmb(); 2142f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2143f95f3850SWill Newton if (host->sg != NULL) 214487a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2145f95f3850SWill Newton } 2146f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2147f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2148f95f3850SWill Newton } 2149f95f3850SWill Newton 2150f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2151f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2152b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 215387a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2154f95f3850SWill Newton } 2155f95f3850SWill Newton 2156f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2157f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2158b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2159f95f3850SWill Newton dw_mci_write_data_pio(host); 2160f95f3850SWill Newton } 2161f95f3850SWill Newton 2162f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2163f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2164182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2165f95f3850SWill Newton } 2166f95f3850SWill Newton 2167f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2168f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 21696130e7a9SDoug Anderson dw_mci_handle_cd(host); 2170f95f3850SWill Newton } 2171f95f3850SWill Newton 21721a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 21731a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 21741a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 217576756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 217676756234SAddy Ke mci_writel(host, RINTSTS, 217776756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 21781a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 21791a5c8e1fSShashidhar Hiremath } 21801a5c8e1fSShashidhar Hiremath } 21811a5c8e1fSShashidhar Hiremath 21821fb5f68aSMarkos Chandras } 2183f95f3850SWill Newton 2184f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2185f95f3850SWill Newton /* Handle DMA interrupts */ 218669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 218769d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 218869d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 218969d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 219069d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 219169d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 219269d99fdcSPrabu Thangamuthu host->dma_ops->complete(host); 219369d99fdcSPrabu Thangamuthu } 219469d99fdcSPrabu Thangamuthu } else { 2195f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2196f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 219769d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 219869d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2199f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2200f95f3850SWill Newton host->dma_ops->complete(host); 2201f95f3850SWill Newton } 220269d99fdcSPrabu Thangamuthu } 2203f95f3850SWill Newton #endif 2204f95f3850SWill Newton 2205f95f3850SWill Newton return IRQ_HANDLED; 2206f95f3850SWill Newton } 2207f95f3850SWill Newton 2208c91eab4bSThomas Abraham #ifdef CONFIG_OF 2209c91eab4bSThomas Abraham /* given a slot id, find out the device node representing that slot */ 2210c91eab4bSThomas Abraham static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 2211c91eab4bSThomas Abraham { 2212c91eab4bSThomas Abraham struct device_node *np; 2213c91eab4bSThomas Abraham const __be32 *addr; 2214c91eab4bSThomas Abraham int len; 2215c91eab4bSThomas Abraham 2216c91eab4bSThomas Abraham if (!dev || !dev->of_node) 2217c91eab4bSThomas Abraham return NULL; 2218c91eab4bSThomas Abraham 2219c91eab4bSThomas Abraham for_each_child_of_node(dev->of_node, np) { 2220c91eab4bSThomas Abraham addr = of_get_property(np, "reg", &len); 2221c91eab4bSThomas Abraham if (!addr || (len < sizeof(int))) 2222c91eab4bSThomas Abraham continue; 2223c91eab4bSThomas Abraham if (be32_to_cpup(addr) == slot) 2224c91eab4bSThomas Abraham return np; 2225c91eab4bSThomas Abraham } 2226c91eab4bSThomas Abraham return NULL; 2227c91eab4bSThomas Abraham } 2228c91eab4bSThomas Abraham 2229a70aaa64SDoug Anderson static struct dw_mci_of_slot_quirks { 2230a70aaa64SDoug Anderson char *quirk; 2231a70aaa64SDoug Anderson int id; 2232a70aaa64SDoug Anderson } of_slot_quirks[] = { 2233a70aaa64SDoug Anderson { 2234a70aaa64SDoug Anderson .quirk = "disable-wp", 2235a70aaa64SDoug Anderson .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, 2236a70aaa64SDoug Anderson }, 2237a70aaa64SDoug Anderson }; 2238a70aaa64SDoug Anderson 2239a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2240a70aaa64SDoug Anderson { 2241a70aaa64SDoug Anderson struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 2242a70aaa64SDoug Anderson int quirks = 0; 2243a70aaa64SDoug Anderson int idx; 2244a70aaa64SDoug Anderson 2245a70aaa64SDoug Anderson /* get quirks */ 2246a70aaa64SDoug Anderson for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) 224726375b5cSJaehoon Chung if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) { 224826375b5cSJaehoon Chung dev_warn(dev, "Slot quirk %s is deprecated\n", 224926375b5cSJaehoon Chung of_slot_quirks[idx].quirk); 2250a70aaa64SDoug Anderson quirks |= of_slot_quirks[idx].id; 225126375b5cSJaehoon Chung } 2252a70aaa64SDoug Anderson 2253a70aaa64SDoug Anderson return quirks; 2254a70aaa64SDoug Anderson } 2255c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2256a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2257a70aaa64SDoug Anderson { 2258a70aaa64SDoug Anderson return 0; 2259a70aaa64SDoug Anderson } 2260c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2261c91eab4bSThomas Abraham 226236c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2263f95f3850SWill Newton { 2264f95f3850SWill Newton struct mmc_host *mmc; 2265f95f3850SWill Newton struct dw_mci_slot *slot; 2266e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2267800d78bfSThomas Abraham int ctrl_id, ret; 22681f44a2a5SSeungwon Jeon u32 freq[2]; 2269f95f3850SWill Newton 22704a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2271f95f3850SWill Newton if (!mmc) 2272f95f3850SWill Newton return -ENOMEM; 2273f95f3850SWill Newton 2274f95f3850SWill Newton slot = mmc_priv(mmc); 2275f95f3850SWill Newton slot->id = id; 227676756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2277f95f3850SWill Newton slot->mmc = mmc; 2278f95f3850SWill Newton slot->host = host; 2279c91eab4bSThomas Abraham host->slot[id] = slot; 2280f95f3850SWill Newton 2281a70aaa64SDoug Anderson slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 2282a70aaa64SDoug Anderson 2283f95f3850SWill Newton mmc->ops = &dw_mci_ops; 22841f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 22851f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 22861f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 22871f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 22881f44a2a5SSeungwon Jeon } else { 22891f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 22901f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 22911f44a2a5SSeungwon Jeon } 2292f95f3850SWill Newton 229351da2240SYuvaraj CD /*if there are external regulators, get them*/ 229451da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 229551da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 22963cf890fcSDoug Anderson goto err_host_allocated; 229751da2240SYuvaraj CD 229851da2240SYuvaraj CD if (!mmc->ocr_avail) 2299f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2300f95f3850SWill Newton 2301fc3d7720SJaehoon Chung if (host->pdata->caps) 2302fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2303fc3d7720SJaehoon Chung 2304ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2305ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2306ab269128SAbhilash Kesavan 2307800d78bfSThomas Abraham if (host->dev->of_node) { 2308800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2309800d78bfSThomas Abraham if (ctrl_id < 0) 2310800d78bfSThomas Abraham ctrl_id = 0; 2311800d78bfSThomas Abraham } else { 2312800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2313800d78bfSThomas Abraham } 2314cb27a843SJames Hogan if (drv_data && drv_data->caps) 2315cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2316800d78bfSThomas Abraham 23174f408cc6SSeungwon Jeon if (host->pdata->caps2) 23184f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 23194f408cc6SSeungwon Jeon 23203cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 23213cf890fcSDoug Anderson if (ret) 23223cf890fcSDoug Anderson goto err_host_allocated; 2323f95f3850SWill Newton 2324f95f3850SWill Newton if (host->pdata->blk_settings) { 2325f95f3850SWill Newton mmc->max_segs = host->pdata->blk_settings->max_segs; 2326f95f3850SWill Newton mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 2327f95f3850SWill Newton mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 2328f95f3850SWill Newton mmc->max_req_size = host->pdata->blk_settings->max_req_size; 2329f95f3850SWill Newton mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 2330f95f3850SWill Newton } else { 2331f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 2332a39e5746SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 2333a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2334a39e5746SJaehoon Chung mmc->max_blk_size = 65536; 2335a39e5746SJaehoon Chung mmc->max_blk_count = host->ring_size; 2336a39e5746SJaehoon Chung mmc->max_seg_size = 0x1000; 2337a39e5746SJaehoon Chung mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; 2338a39e5746SJaehoon Chung #else 2339f95f3850SWill Newton mmc->max_segs = 64; 2340f95f3850SWill Newton mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2341f95f3850SWill Newton mmc->max_blk_count = 512; 2342f95f3850SWill Newton mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2343f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2344f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 2345a39e5746SJaehoon Chung } 2346f95f3850SWill Newton 2347ae0eb348SJaehoon Chung if (dw_mci_get_cd(mmc)) 2348ae0eb348SJaehoon Chung set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2349ae0eb348SJaehoon Chung else 2350ae0eb348SJaehoon Chung clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2351ae0eb348SJaehoon Chung 23520cea529dSJaehoon Chung ret = mmc_add_host(mmc); 23530cea529dSJaehoon Chung if (ret) 23543cf890fcSDoug Anderson goto err_host_allocated; 2355f95f3850SWill Newton 2356f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2357f95f3850SWill Newton dw_mci_init_debugfs(slot); 2358f95f3850SWill Newton #endif 2359f95f3850SWill Newton 2360f95f3850SWill Newton return 0; 2361800d78bfSThomas Abraham 23623cf890fcSDoug Anderson err_host_allocated: 2363800d78bfSThomas Abraham mmc_free_host(mmc); 236451da2240SYuvaraj CD return ret; 2365f95f3850SWill Newton } 2366f95f3850SWill Newton 2367f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2368f95f3850SWill Newton { 2369f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2370f95f3850SWill Newton mmc_remove_host(slot->mmc); 2371f95f3850SWill Newton slot->host->slot[id] = NULL; 2372f95f3850SWill Newton mmc_free_host(slot->mmc); 2373f95f3850SWill Newton } 2374f95f3850SWill Newton 2375f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2376f95f3850SWill Newton { 237769d99fdcSPrabu Thangamuthu int addr_config; 237869d99fdcSPrabu Thangamuthu /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ 237969d99fdcSPrabu Thangamuthu addr_config = (mci_readl(host, HCON) >> 27) & 0x01; 238069d99fdcSPrabu Thangamuthu 238169d99fdcSPrabu Thangamuthu if (addr_config == 1) { 238269d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 238369d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 238469d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); 238569d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 238669d99fdcSPrabu Thangamuthu dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); 238769d99fdcSPrabu Thangamuthu } else { 238869d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 238969d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 239069d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); 239169d99fdcSPrabu Thangamuthu } 239269d99fdcSPrabu Thangamuthu 2393f95f3850SWill Newton /* Alloc memory for sg translation */ 2394780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2395f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2396f95f3850SWill Newton if (!host->sg_cpu) { 23974a90920cSThomas Abraham dev_err(host->dev, "%s: could not alloc DMA memory\n", 2398f95f3850SWill Newton __func__); 2399f95f3850SWill Newton goto no_dma; 2400f95f3850SWill Newton } 2401f95f3850SWill Newton 2402f95f3850SWill Newton /* Determine which DMA interface to use */ 2403f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2404f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 240500956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 2406f95f3850SWill Newton #endif 2407f95f3850SWill Newton 2408f95f3850SWill Newton if (!host->dma_ops) 2409f95f3850SWill Newton goto no_dma; 2410f95f3850SWill Newton 2411e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2412e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2413f95f3850SWill Newton if (host->dma_ops->init(host)) { 24144a90920cSThomas Abraham dev_err(host->dev, "%s: Unable to initialize " 2415f95f3850SWill Newton "DMA Controller.\n", __func__); 2416f95f3850SWill Newton goto no_dma; 2417f95f3850SWill Newton } 2418f95f3850SWill Newton } else { 24194a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2420f95f3850SWill Newton goto no_dma; 2421f95f3850SWill Newton } 2422f95f3850SWill Newton 2423f95f3850SWill Newton host->use_dma = 1; 2424f95f3850SWill Newton return; 2425f95f3850SWill Newton 2426f95f3850SWill Newton no_dma: 24274a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 2428f95f3850SWill Newton host->use_dma = 0; 2429f95f3850SWill Newton return; 2430f95f3850SWill Newton } 2431f95f3850SWill Newton 243231bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2433f95f3850SWill Newton { 2434f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 243531bff450SSeungwon Jeon u32 ctrl; 2436f95f3850SWill Newton 243731bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 243831bff450SSeungwon Jeon ctrl |= reset; 243931bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2440f95f3850SWill Newton 2441f95f3850SWill Newton /* wait till resets clear */ 2442f95f3850SWill Newton do { 2443f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 244431bff450SSeungwon Jeon if (!(ctrl & reset)) 2445f95f3850SWill Newton return true; 2446f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2447f95f3850SWill Newton 244831bff450SSeungwon Jeon dev_err(host->dev, 244931bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 245031bff450SSeungwon Jeon ctrl & reset); 2451f95f3850SWill Newton 2452f95f3850SWill Newton return false; 2453f95f3850SWill Newton } 2454f95f3850SWill Newton 24553a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 245631bff450SSeungwon Jeon { 24573a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 24583a33a94cSSonny Rao bool ret = false; 24593a33a94cSSonny Rao 246031bff450SSeungwon Jeon /* 246131bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 246231bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 246331bff450SSeungwon Jeon */ 246431bff450SSeungwon Jeon if (host->sg) { 246531bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 246631bff450SSeungwon Jeon host->sg = NULL; 246731bff450SSeungwon Jeon } 246831bff450SSeungwon Jeon 24693a33a94cSSonny Rao if (host->use_dma) 24703a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 24713a33a94cSSonny Rao 24723a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 24733a33a94cSSonny Rao /* 24743a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 24753a33a94cSSonny Rao * interrupts. 24763a33a94cSSonny Rao */ 24773a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 24783a33a94cSSonny Rao 24793a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 24803a33a94cSSonny Rao if (host->use_dma) { 24813a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 24823a33a94cSSonny Rao u32 status; 24833a33a94cSSonny Rao do { 24843a33a94cSSonny Rao status = mci_readl(host, STATUS); 24853a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 24863a33a94cSSonny Rao break; 24873a33a94cSSonny Rao cpu_relax(); 24883a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 24893a33a94cSSonny Rao 24903a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 24913a33a94cSSonny Rao dev_err(host->dev, 24923a33a94cSSonny Rao "%s: Timeout waiting for dma_req to " 24933a33a94cSSonny Rao "clear during reset\n", __func__); 24943a33a94cSSonny Rao goto ciu_out; 249531bff450SSeungwon Jeon } 249631bff450SSeungwon Jeon 24973a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 24983a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 24993a33a94cSSonny Rao goto ciu_out; 25003a33a94cSSonny Rao } 25013a33a94cSSonny Rao } else { 25023a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 25033a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 25043a33a94cSSonny Rao dev_err(host->dev, "%s: fifo/dma reset bits didn't " 25053a33a94cSSonny Rao "clear but ciu was reset, doing clock update\n", 25063a33a94cSSonny Rao __func__); 25073a33a94cSSonny Rao goto ciu_out; 25083a33a94cSSonny Rao } 25093a33a94cSSonny Rao } 25103a33a94cSSonny Rao 25113a33a94cSSonny Rao #if IS_ENABLED(CONFIG_MMC_DW_IDMAC) 25123a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 25133a33a94cSSonny Rao dw_mci_idmac_reset(host); 25143a33a94cSSonny Rao #endif 25153a33a94cSSonny Rao 25163a33a94cSSonny Rao ret = true; 25173a33a94cSSonny Rao 25183a33a94cSSonny Rao ciu_out: 25193a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 25203a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 25213a33a94cSSonny Rao 25223a33a94cSSonny Rao return ret; 252331bff450SSeungwon Jeon } 252431bff450SSeungwon Jeon 2525c91eab4bSThomas Abraham #ifdef CONFIG_OF 2526c91eab4bSThomas Abraham static struct dw_mci_of_quirks { 2527c91eab4bSThomas Abraham char *quirk; 2528c91eab4bSThomas Abraham int id; 2529c91eab4bSThomas Abraham } of_quirks[] = { 2530c91eab4bSThomas Abraham { 2531c91eab4bSThomas Abraham .quirk = "broken-cd", 2532c91eab4bSThomas Abraham .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 253326375b5cSJaehoon Chung }, { 253426375b5cSJaehoon Chung .quirk = "disable-wp", 253526375b5cSJaehoon Chung .id = DW_MCI_QUIRK_NO_WRITE_PROTECT, 2536c91eab4bSThomas Abraham }, 2537c91eab4bSThomas Abraham }; 2538c91eab4bSThomas Abraham 2539c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2540c91eab4bSThomas Abraham { 2541c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2542c91eab4bSThomas Abraham struct device *dev = host->dev; 2543c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2544e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2545800d78bfSThomas Abraham int idx, ret; 25463c6d89eaSDoug Anderson u32 clock_frequency; 2547c91eab4bSThomas Abraham 2548c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2549c91eab4bSThomas Abraham if (!pdata) { 2550c91eab4bSThomas Abraham dev_err(dev, "could not allocate memory for pdata\n"); 2551c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2552c91eab4bSThomas Abraham } 2553c91eab4bSThomas Abraham 2554c91eab4bSThomas Abraham /* find out number of slots supported */ 2555c91eab4bSThomas Abraham if (of_property_read_u32(dev->of_node, "num-slots", 2556c91eab4bSThomas Abraham &pdata->num_slots)) { 2557c91eab4bSThomas Abraham dev_info(dev, "num-slots property not found, " 2558c91eab4bSThomas Abraham "assuming 1 slot is available\n"); 2559c91eab4bSThomas Abraham pdata->num_slots = 1; 2560c91eab4bSThomas Abraham } 2561c91eab4bSThomas Abraham 2562c91eab4bSThomas Abraham /* get quirks */ 2563c91eab4bSThomas Abraham for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2564c91eab4bSThomas Abraham if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2565c91eab4bSThomas Abraham pdata->quirks |= of_quirks[idx].id; 2566c91eab4bSThomas Abraham 2567c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2568c91eab4bSThomas Abraham dev_info(dev, "fifo-depth property not found, using " 2569c91eab4bSThomas Abraham "value of FIFOTH register as default\n"); 2570c91eab4bSThomas Abraham 2571c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2572c91eab4bSThomas Abraham 25733c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 25743c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 25753c6d89eaSDoug Anderson 2576cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2577cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2578800d78bfSThomas Abraham if (ret) 2579800d78bfSThomas Abraham return ERR_PTR(ret); 2580800d78bfSThomas Abraham } 2581800d78bfSThomas Abraham 258210b49841SSeungwon Jeon if (of_find_property(np, "supports-highspeed", NULL)) 258310b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 258410b49841SSeungwon Jeon 2585c91eab4bSThomas Abraham return pdata; 2586c91eab4bSThomas Abraham } 2587c91eab4bSThomas Abraham 2588c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2589c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2590c91eab4bSThomas Abraham { 2591c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2592c91eab4bSThomas Abraham } 2593c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2594c91eab4bSThomas Abraham 259562ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2596f95f3850SWill Newton { 2597e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 259862ca8034SShashidhar Hiremath int width, i, ret = 0; 2599f95f3850SWill Newton u32 fifo_size; 26001c2215b7SThomas Abraham int init_slots = 0; 2601f95f3850SWill Newton 2602c91eab4bSThomas Abraham if (!host->pdata) { 2603c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2604c91eab4bSThomas Abraham if (IS_ERR(host->pdata)) { 2605c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2606c91eab4bSThomas Abraham return -EINVAL; 2607c91eab4bSThomas Abraham } 2608f95f3850SWill Newton } 2609f95f3850SWill Newton 2610907abd51SJaehoon Chung if (host->pdata->num_slots > 1) { 26114a90920cSThomas Abraham dev_err(host->dev, 2612907abd51SJaehoon Chung "Platform data must supply num_slots.\n"); 261362ca8034SShashidhar Hiremath return -ENODEV; 2614f95f3850SWill Newton } 2615f95f3850SWill Newton 2616780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2617f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2618f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2619f90a0612SThomas Abraham } else { 2620f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2621f90a0612SThomas Abraham if (ret) { 2622f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2623f90a0612SThomas Abraham return ret; 2624f90a0612SThomas Abraham } 2625f95f3850SWill Newton } 2626f95f3850SWill Newton 2627780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2628f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2629f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 26303c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2631f90a0612SThomas Abraham } else { 2632f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2633f90a0612SThomas Abraham if (ret) { 2634f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2635f90a0612SThomas Abraham goto err_clk_biu; 2636f90a0612SThomas Abraham } 2637f90a0612SThomas Abraham 26383c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 26393c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 26403c6d89eaSDoug Anderson if (ret) 26413c6d89eaSDoug Anderson dev_warn(host->dev, 2642612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 26433c6d89eaSDoug Anderson host->pdata->bus_hz); 26443c6d89eaSDoug Anderson } 2645f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 26463c6d89eaSDoug Anderson } 2647f90a0612SThomas Abraham 2648612de4c1SJaehoon Chung if (!host->bus_hz) { 2649612de4c1SJaehoon Chung dev_err(host->dev, 2650612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 2651612de4c1SJaehoon Chung ret = -ENODEV; 2652612de4c1SJaehoon Chung goto err_clk_ciu; 2653612de4c1SJaehoon Chung } 2654612de4c1SJaehoon Chung 2655002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 2656002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 2657002f0d5cSYuvaraj Kumar C D if (ret) { 2658002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 2659002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 2660002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 2661002f0d5cSYuvaraj Kumar C D } 2662002f0d5cSYuvaraj Kumar C D } 2663002f0d5cSYuvaraj Kumar C D 2664cb27a843SJames Hogan if (drv_data && drv_data->setup_clock) { 2665cb27a843SJames Hogan ret = drv_data->setup_clock(host); 2666800d78bfSThomas Abraham if (ret) { 2667800d78bfSThomas Abraham dev_err(host->dev, 2668800d78bfSThomas Abraham "implementation specific clock setup failed\n"); 2669800d78bfSThomas Abraham goto err_clk_ciu; 2670800d78bfSThomas Abraham } 2671800d78bfSThomas Abraham } 2672800d78bfSThomas Abraham 267362ca8034SShashidhar Hiremath host->quirks = host->pdata->quirks; 2674f95f3850SWill Newton 2675f95f3850SWill Newton spin_lock_init(&host->lock); 2676*f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 2677f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 2678f95f3850SWill Newton 2679f95f3850SWill Newton /* 2680f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 2681f95f3850SWill Newton * the correct values. 2682f95f3850SWill Newton */ 2683f95f3850SWill Newton i = (mci_readl(host, HCON) >> 7) & 0x7; 2684f95f3850SWill Newton if (!i) { 2685f95f3850SWill Newton host->push_data = dw_mci_push_data16; 2686f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 2687f95f3850SWill Newton width = 16; 2688f95f3850SWill Newton host->data_shift = 1; 2689f95f3850SWill Newton } else if (i == 2) { 2690f95f3850SWill Newton host->push_data = dw_mci_push_data64; 2691f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 2692f95f3850SWill Newton width = 64; 2693f95f3850SWill Newton host->data_shift = 3; 2694f95f3850SWill Newton } else { 2695f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 2696f95f3850SWill Newton WARN((i != 1), 2697f95f3850SWill Newton "HCON reports a reserved host data width!\n" 2698f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 2699f95f3850SWill Newton host->push_data = dw_mci_push_data32; 2700f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 2701f95f3850SWill Newton width = 32; 2702f95f3850SWill Newton host->data_shift = 2; 2703f95f3850SWill Newton } 2704f95f3850SWill Newton 2705f95f3850SWill Newton /* Reset all blocks */ 27063a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 2707141a712aSSeungwon Jeon return -ENODEV; 2708141a712aSSeungwon Jeon 2709141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 2710141a712aSSeungwon Jeon dw_mci_init_dma(host); 2711f95f3850SWill Newton 2712f95f3850SWill Newton /* Clear the interrupts for the host controller */ 2713f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2714f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2715f95f3850SWill Newton 2716f95f3850SWill Newton /* Put in max timeout */ 2717f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 2718f95f3850SWill Newton 2719f95f3850SWill Newton /* 2720f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2721f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 2722f95f3850SWill Newton */ 2723b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 2724b86d8253SJames Hogan /* 2725b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2726b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 2727b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 2728b86d8253SJames Hogan * should put it in the platform data. 2729b86d8253SJames Hogan */ 2730f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 27318234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2732b86d8253SJames Hogan } else { 2733b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 2734b86d8253SJames Hogan } 2735b86d8253SJames Hogan host->fifo_depth = fifo_size; 273652426899SSeungwon Jeon host->fifoth_val = 273752426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 2738e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 2739f95f3850SWill Newton 2740f95f3850SWill Newton /* disable clock to CIU */ 2741f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2742f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2743f95f3850SWill Newton 274463008768SJames Hogan /* 274563008768SJames Hogan * In 2.40a spec, Data offset is changed. 274663008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 274763008768SJames Hogan */ 274863008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 274963008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 275063008768SJames Hogan 275163008768SJames Hogan if (host->verid < DW_MMC_240A) 275263008768SJames Hogan host->data_offset = DATA_OFFSET; 275363008768SJames Hogan else 275463008768SJames Hogan host->data_offset = DATA_240A_OFFSET; 275563008768SJames Hogan 2756f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2757780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2758780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 2759f95f3850SWill Newton if (ret) 27606130e7a9SDoug Anderson goto err_dmaunmap; 2761f95f3850SWill Newton 2762f95f3850SWill Newton if (host->pdata->num_slots) 2763f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 2764f95f3850SWill Newton else 2765f95f3850SWill Newton host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2766f95f3850SWill Newton 27672da1d7f2SYuvaraj CD /* 27682da1d7f2SYuvaraj CD * Enable interrupts for command done, data over, data empty, card det, 27692da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 27702da1d7f2SYuvaraj CD */ 27712da1d7f2SYuvaraj CD mci_writel(host, RINTSTS, 0xFFFFFFFF); 27722da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 27732da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 27742da1d7f2SYuvaraj CD DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 27752da1d7f2SYuvaraj CD mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 27762da1d7f2SYuvaraj CD 27772da1d7f2SYuvaraj CD dev_info(host->dev, "DW MMC controller at irq %d, " 27782da1d7f2SYuvaraj CD "%d bit host data width, " 27792da1d7f2SYuvaraj CD "%u deep fifo\n", 27802da1d7f2SYuvaraj CD host->irq, width, fifo_size); 27812da1d7f2SYuvaraj CD 2782f95f3850SWill Newton /* We need at least one slot to succeed */ 2783f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2784f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 27851c2215b7SThomas Abraham if (ret) 27861c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 27871c2215b7SThomas Abraham else 27881c2215b7SThomas Abraham init_slots++; 2789f95f3850SWill Newton } 27901c2215b7SThomas Abraham 27911c2215b7SThomas Abraham if (init_slots) { 27921c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 27931c2215b7SThomas Abraham } else { 27941c2215b7SThomas Abraham dev_dbg(host->dev, "attempted to initialize %d slots, " 27951c2215b7SThomas Abraham "but failed on all\n", host->num_slots); 27966130e7a9SDoug Anderson goto err_dmaunmap; 2797f95f3850SWill Newton } 2798f95f3850SWill Newton 2799f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 28004a90920cSThomas Abraham dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2801f95f3850SWill Newton 2802f95f3850SWill Newton return 0; 2803f95f3850SWill Newton 2804f95f3850SWill Newton err_dmaunmap: 2805f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2806f95f3850SWill Newton host->dma_ops->exit(host); 2807f90a0612SThomas Abraham 2808f90a0612SThomas Abraham err_clk_ciu: 2809780f22afSSeungwon Jeon if (!IS_ERR(host->ciu_clk)) 2810f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2811780f22afSSeungwon Jeon 2812f90a0612SThomas Abraham err_clk_biu: 2813780f22afSSeungwon Jeon if (!IS_ERR(host->biu_clk)) 2814f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2815780f22afSSeungwon Jeon 2816f95f3850SWill Newton return ret; 2817f95f3850SWill Newton } 281862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 2819f95f3850SWill Newton 282062ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 2821f95f3850SWill Newton { 2822f95f3850SWill Newton int i; 2823f95f3850SWill Newton 2824f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2825f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2826f95f3850SWill Newton 2827f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 28284a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 2829f95f3850SWill Newton if (host->slot[i]) 2830f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 2831f95f3850SWill Newton } 2832f95f3850SWill Newton 2833f95f3850SWill Newton /* disable clock to CIU */ 2834f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2835f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2836f95f3850SWill Newton 2837f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2838f95f3850SWill Newton host->dma_ops->exit(host); 2839f95f3850SWill Newton 2840f90a0612SThomas Abraham if (!IS_ERR(host->ciu_clk)) 2841f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2842780f22afSSeungwon Jeon 2843f90a0612SThomas Abraham if (!IS_ERR(host->biu_clk)) 2844f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2845f95f3850SWill Newton } 284662ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 284762ca8034SShashidhar Hiremath 284862ca8034SShashidhar Hiremath 2849f95f3850SWill Newton 28506fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 2851f95f3850SWill Newton /* 2852f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 2853f95f3850SWill Newton */ 285462ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 2855f95f3850SWill Newton { 2856f95f3850SWill Newton return 0; 2857f95f3850SWill Newton } 285862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 2859f95f3850SWill Newton 286062ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 2861f95f3850SWill Newton { 2862f95f3850SWill Newton int i, ret; 2863f95f3850SWill Newton 28643a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 2865e61cf118SJaehoon Chung ret = -ENODEV; 2866e61cf118SJaehoon Chung return ret; 2867e61cf118SJaehoon Chung } 2868e61cf118SJaehoon Chung 28693bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 2870141a712aSSeungwon Jeon host->dma_ops->init(host); 2871141a712aSSeungwon Jeon 287252426899SSeungwon Jeon /* 287352426899SSeungwon Jeon * Restore the initial value at FIFOTH register 287452426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 287552426899SSeungwon Jeon */ 2876e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 287752426899SSeungwon Jeon host->prev_blksz = 0; 2878e61cf118SJaehoon Chung 28792eb2944fSDoug Anderson /* Put in max timeout */ 28802eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 28812eb2944fSDoug Anderson 2882e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 2883e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2884e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2885e61cf118SJaehoon Chung DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2886e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2887e61cf118SJaehoon Chung 2888f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2889f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 2890f95f3850SWill Newton if (!slot) 2891f95f3850SWill Newton continue; 2892ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 2893ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 2894ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 2895ab269128SAbhilash Kesavan } 2896f95f3850SWill Newton } 2897f95f3850SWill Newton return 0; 2898f95f3850SWill Newton } 289962ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 29006fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 29016fe8890dSJaehoon Chung 2902f95f3850SWill Newton static int __init dw_mci_init(void) 2903f95f3850SWill Newton { 29048e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 290562ca8034SShashidhar Hiremath return 0; 2906f95f3850SWill Newton } 2907f95f3850SWill Newton 2908f95f3850SWill Newton static void __exit dw_mci_exit(void) 2909f95f3850SWill Newton { 2910f95f3850SWill Newton } 2911f95f3850SWill Newton 2912f95f3850SWill Newton module_init(dw_mci_init); 2913f95f3850SWill Newton module_exit(dw_mci_exit); 2914f95f3850SWill Newton 2915f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 2916f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 2917f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 2918f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 2919