1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 477a3c5677SDoug Anderson SDMMC_INT_EBE | SDMMC_INT_HLE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 497a3c5677SDoug Anderson SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 517a3c5677SDoug Anderson DW_MCI_CMD_ERROR_FLAGS) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 60fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 63fc79a4d6SJoonyoung Shim 64*cc190d4cSShawn Lin #define DESC_RING_BUF_SZ PAGE_SIZE 65*cc190d4cSShawn Lin 6669d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6769d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6869d99fdcSPrabu Thangamuthu 6969d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 7069d99fdcSPrabu Thangamuthu 7169d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7269d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 736687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 746687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7769d99fdcSPrabu Thangamuthu 7869d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7969d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 8069d99fdcSPrabu Thangamuthu 8169d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8269d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8369d99fdcSPrabu Thangamuthu }; 8469d99fdcSPrabu Thangamuthu 85f95f3850SWill Newton struct idmac_desc { 866687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 87f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 88f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 89f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 90f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 91f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 92f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 93f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 94f95f3850SWill Newton 956687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 96f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 97e5306c3aSBen Dooks ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 98f95f3850SWill Newton 996687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 100f95f3850SWill Newton 1016687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 102f95f3850SWill Newton }; 1035959b32eSAlexey Brodkin 1045959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1055959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 106f95f3850SWill Newton 1073a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 108536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 1090bdbd0e8SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc); 11056f6911cSShawn Lin static int dw_mci_get_cd(struct mmc_host *mmc); 11131bff450SSeungwon Jeon 112f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 113f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 114f95f3850SWill Newton { 115f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 116f95f3850SWill Newton struct mmc_request *mrq; 117f95f3850SWill Newton struct mmc_command *cmd; 118f95f3850SWill Newton struct mmc_command *stop; 119f95f3850SWill Newton struct mmc_data *data; 120f95f3850SWill Newton 121f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 122f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 123f95f3850SWill Newton mrq = slot->mrq; 124f95f3850SWill Newton 125f95f3850SWill Newton if (mrq) { 126f95f3850SWill Newton cmd = mrq->cmd; 127f95f3850SWill Newton data = mrq->data; 128f95f3850SWill Newton stop = mrq->stop; 129f95f3850SWill Newton 130f95f3850SWill Newton if (cmd) 131f95f3850SWill Newton seq_printf(s, 132f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 133f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 134f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 135f95f3850SWill Newton cmd->resp[2], cmd->error); 136f95f3850SWill Newton if (data) 137f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 138f95f3850SWill Newton data->bytes_xfered, data->blocks, 139f95f3850SWill Newton data->blksz, data->flags, data->error); 140f95f3850SWill Newton if (stop) 141f95f3850SWill Newton seq_printf(s, 142f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 143f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 144f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 145f95f3850SWill Newton stop->resp[2], stop->error); 146f95f3850SWill Newton } 147f95f3850SWill Newton 148f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 149f95f3850SWill Newton 150f95f3850SWill Newton return 0; 151f95f3850SWill Newton } 152f95f3850SWill Newton 153f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 154f95f3850SWill Newton { 155f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 156f95f3850SWill Newton } 157f95f3850SWill Newton 158f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 159f95f3850SWill Newton .owner = THIS_MODULE, 160f95f3850SWill Newton .open = dw_mci_req_open, 161f95f3850SWill Newton .read = seq_read, 162f95f3850SWill Newton .llseek = seq_lseek, 163f95f3850SWill Newton .release = single_release, 164f95f3850SWill Newton }; 165f95f3850SWill Newton 166f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 167f95f3850SWill Newton { 168f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 169f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 170f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 171f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 172f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 173f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 174f95f3850SWill Newton 175f95f3850SWill Newton return 0; 176f95f3850SWill Newton } 177f95f3850SWill Newton 178f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 179f95f3850SWill Newton { 180f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 181f95f3850SWill Newton } 182f95f3850SWill Newton 183f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 184f95f3850SWill Newton .owner = THIS_MODULE, 185f95f3850SWill Newton .open = dw_mci_regs_open, 186f95f3850SWill Newton .read = seq_read, 187f95f3850SWill Newton .llseek = seq_lseek, 188f95f3850SWill Newton .release = single_release, 189f95f3850SWill Newton }; 190f95f3850SWill Newton 191f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 192f95f3850SWill Newton { 193f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 194f95f3850SWill Newton struct dw_mci *host = slot->host; 195f95f3850SWill Newton struct dentry *root; 196f95f3850SWill Newton struct dentry *node; 197f95f3850SWill Newton 198f95f3850SWill Newton root = mmc->debugfs_root; 199f95f3850SWill Newton if (!root) 200f95f3850SWill Newton return; 201f95f3850SWill Newton 202f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 203f95f3850SWill Newton &dw_mci_regs_fops); 204f95f3850SWill Newton if (!node) 205f95f3850SWill Newton goto err; 206f95f3850SWill Newton 207f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 208f95f3850SWill Newton &dw_mci_req_fops); 209f95f3850SWill Newton if (!node) 210f95f3850SWill Newton goto err; 211f95f3850SWill Newton 212f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 213f95f3850SWill Newton if (!node) 214f95f3850SWill Newton goto err; 215f95f3850SWill Newton 216f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 217f95f3850SWill Newton (u32 *)&host->pending_events); 218f95f3850SWill Newton if (!node) 219f95f3850SWill Newton goto err; 220f95f3850SWill Newton 221f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 222f95f3850SWill Newton (u32 *)&host->completed_events); 223f95f3850SWill Newton if (!node) 224f95f3850SWill Newton goto err; 225f95f3850SWill Newton 226f95f3850SWill Newton return; 227f95f3850SWill Newton 228f95f3850SWill Newton err: 229f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 230f95f3850SWill Newton } 231f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 232f95f3850SWill Newton 23301730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 23401730558SDoug Anderson 235f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 236f95f3850SWill Newton { 237f95f3850SWill Newton struct mmc_data *data; 238800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23901730558SDoug Anderson struct dw_mci *host = slot->host; 240f95f3850SWill Newton u32 cmdr; 241f95f3850SWill Newton 2420e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 243f95f3850SWill Newton cmdr = cmd->opcode; 244f95f3850SWill Newton 24590c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24690c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24790c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24890c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24990c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 250f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2514a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 252f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 253f95f3850SWill Newton 25401730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25501730558SDoug Anderson u32 clk_en_a; 25601730558SDoug Anderson 25701730558SDoug Anderson /* Special bit makes CMD11 not die */ 25801730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25901730558SDoug Anderson 26001730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 26101730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 26201730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 26301730558SDoug Anderson 26401730558SDoug Anderson /* 26501730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26601730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26701730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26801730558SDoug Anderson * voltage change dance. 26901730558SDoug Anderson * 27001730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 27101730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 27201730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 27301730558SDoug Anderson * until the voltage change is all done. 27401730558SDoug Anderson */ 27501730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27601730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27701730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27801730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27901730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 28001730558SDoug Anderson } 28101730558SDoug Anderson 282f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 283f95f3850SWill Newton /* We expect a response, so set this bit */ 284f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 285f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 286f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 287f95f3850SWill Newton } 288f95f3850SWill Newton 289f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 290f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 291f95f3850SWill Newton 292f95f3850SWill Newton data = cmd->data; 293f95f3850SWill Newton if (data) { 294f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 295f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 296f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 297f95f3850SWill Newton } 298f95f3850SWill Newton 299aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 300aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 301800d78bfSThomas Abraham 302f95f3850SWill Newton return cmdr; 303f95f3850SWill Newton } 304f95f3850SWill Newton 30590c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30690c2143aSSeungwon Jeon { 30790c2143aSSeungwon Jeon struct mmc_command *stop; 30890c2143aSSeungwon Jeon u32 cmdr; 30990c2143aSSeungwon Jeon 31090c2143aSSeungwon Jeon if (!cmd->data) 31190c2143aSSeungwon Jeon return 0; 31290c2143aSSeungwon Jeon 31390c2143aSSeungwon Jeon stop = &host->stop_abort; 31490c2143aSSeungwon Jeon cmdr = cmd->opcode; 31590c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31690c2143aSSeungwon Jeon 31790c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31890c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31990c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3206c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3216c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3226c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 32390c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 32490c2143aSSeungwon Jeon stop->arg = 0; 32590c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32690c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32790c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32890c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32990c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 33090c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 33190c2143aSSeungwon Jeon } else { 33290c2143aSSeungwon Jeon return 0; 33390c2143aSSeungwon Jeon } 33490c2143aSSeungwon Jeon 33590c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33690c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33790c2143aSSeungwon Jeon 33890c2143aSSeungwon Jeon return cmdr; 33990c2143aSSeungwon Jeon } 34090c2143aSSeungwon Jeon 3410bdbd0e8SDoug Anderson static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 3420bdbd0e8SDoug Anderson { 3430bdbd0e8SDoug Anderson unsigned long timeout = jiffies + msecs_to_jiffies(500); 3440bdbd0e8SDoug Anderson 3450bdbd0e8SDoug Anderson /* 3460bdbd0e8SDoug Anderson * Databook says that before issuing a new data transfer command 3470bdbd0e8SDoug Anderson * we need to check to see if the card is busy. Data transfer commands 3480bdbd0e8SDoug Anderson * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 3490bdbd0e8SDoug Anderson * 3500bdbd0e8SDoug Anderson * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 3510bdbd0e8SDoug Anderson * expected. 3520bdbd0e8SDoug Anderson */ 3530bdbd0e8SDoug Anderson if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 3540bdbd0e8SDoug Anderson !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 3550bdbd0e8SDoug Anderson while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 3560bdbd0e8SDoug Anderson if (time_after(jiffies, timeout)) { 3570bdbd0e8SDoug Anderson /* Command will fail; we'll pass error then */ 3580bdbd0e8SDoug Anderson dev_err(host->dev, "Busy; trying anyway\n"); 3590bdbd0e8SDoug Anderson break; 3600bdbd0e8SDoug Anderson } 3610bdbd0e8SDoug Anderson udelay(10); 3620bdbd0e8SDoug Anderson } 3630bdbd0e8SDoug Anderson } 3640bdbd0e8SDoug Anderson } 3650bdbd0e8SDoug Anderson 366f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 367f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 368f95f3850SWill Newton { 369f95f3850SWill Newton host->cmd = cmd; 3704a90920cSThomas Abraham dev_vdbg(host->dev, 371f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 372f95f3850SWill Newton cmd->arg, cmd_flags); 373f95f3850SWill Newton 374f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 3750e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 3760bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 377f95f3850SWill Newton 378f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 379f95f3850SWill Newton } 380f95f3850SWill Newton 38190c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 382f95f3850SWill Newton { 38390c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 3840e3a22c0SShawn Lin 38590c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 386f95f3850SWill Newton } 387f95f3850SWill Newton 388f95f3850SWill Newton /* DMA interface functions */ 389f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 390f95f3850SWill Newton { 39103e8cb53SJames Hogan if (host->using_dma) { 392f95f3850SWill Newton host->dma_ops->stop(host); 393f95f3850SWill Newton host->dma_ops->cleanup(host); 394aa50f259SSeungwon Jeon } 395aa50f259SSeungwon Jeon 396f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 397f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 398f95f3850SWill Newton } 399f95f3850SWill Newton 4009aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 4019aa51408SSeungwon Jeon { 4029aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4039aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4049aa51408SSeungwon Jeon else 4059aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4069aa51408SSeungwon Jeon } 4079aa51408SSeungwon Jeon 408f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 409f95f3850SWill Newton { 410f95f3850SWill Newton struct mmc_data *data = host->data; 411f95f3850SWill Newton 412f95f3850SWill Newton if (data) 4139aa51408SSeungwon Jeon if (!data->host_cookie) 4144a90920cSThomas Abraham dma_unmap_sg(host->dev, 4159aa51408SSeungwon Jeon data->sg, 4169aa51408SSeungwon Jeon data->sg_len, 4179aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 418f95f3850SWill Newton } 419f95f3850SWill Newton 4205ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4215ce9d961SSeungwon Jeon { 4225ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4235ce9d961SSeungwon Jeon /* Software reset of DMA */ 4245ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4255ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4265ce9d961SSeungwon Jeon } 4275ce9d961SSeungwon Jeon 428f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 429f95f3850SWill Newton { 430f95f3850SWill Newton u32 temp; 431f95f3850SWill Newton 432f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 433f95f3850SWill Newton temp = mci_readl(host, CTRL); 434f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 435f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 436f95f3850SWill Newton mci_writel(host, CTRL, temp); 437f95f3850SWill Newton 438f95f3850SWill Newton /* Stop the IDMAC running */ 439f95f3850SWill Newton temp = mci_readl(host, BMOD); 440a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4415ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 442f95f3850SWill Newton mci_writel(host, BMOD, temp); 443f95f3850SWill Newton } 444f95f3850SWill Newton 4453fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 446f95f3850SWill Newton { 4473fc7eaefSShawn Lin struct dw_mci *host = arg; 448f95f3850SWill Newton struct mmc_data *data = host->data; 449f95f3850SWill Newton 4504a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 451f95f3850SWill Newton 4523fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 4533fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 4543fc7eaefSShawn Lin /* Invalidate cache after read */ 4553fc7eaefSShawn Lin dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 4563fc7eaefSShawn Lin data->sg, 4573fc7eaefSShawn Lin data->sg_len, 4583fc7eaefSShawn Lin DMA_FROM_DEVICE); 4593fc7eaefSShawn Lin 460f95f3850SWill Newton host->dma_ops->cleanup(host); 461f95f3850SWill Newton 462f95f3850SWill Newton /* 463f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 464f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 465f95f3850SWill Newton */ 466f95f3850SWill Newton if (data) { 467f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 468f95f3850SWill Newton tasklet_schedule(&host->tasklet); 469f95f3850SWill Newton } 470f95f3850SWill Newton } 471f95f3850SWill Newton 472f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 473f95f3850SWill Newton { 474897b69e7SSeungwon Jeon int i; 475f95f3850SWill Newton 47669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 47769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 47869d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 479*cc190d4cSShawn Lin host->ring_size = 480*cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 48169d99fdcSPrabu Thangamuthu 48269d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 48369d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 48469d99fdcSPrabu Thangamuthu i++, p++) { 48569d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 48669d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 48769d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 48869d99fdcSPrabu Thangamuthu 48969d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 49069d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 49169d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 49269d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 49369d99fdcSPrabu Thangamuthu p->des1 = 0; 49469d99fdcSPrabu Thangamuthu p->des2 = 0; 49569d99fdcSPrabu Thangamuthu p->des3 = 0; 49669d99fdcSPrabu Thangamuthu } 49769d99fdcSPrabu Thangamuthu 49869d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 49969d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 50069d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 50169d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 50269d99fdcSPrabu Thangamuthu 50369d99fdcSPrabu Thangamuthu } else { 50469d99fdcSPrabu Thangamuthu struct idmac_desc *p; 505f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 506*cc190d4cSShawn Lin host->ring_size = 507*cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 508f95f3850SWill Newton 509f95f3850SWill Newton /* Forward link the descriptor list */ 5100e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 5110e3a22c0SShawn Lin i < host->ring_size - 1; 5120e3a22c0SShawn Lin i++, p++) { 5136687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 5146687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 5154b244724SZhangfei Gao p->des1 = 0; 5164b244724SZhangfei Gao } 517f95f3850SWill Newton 518f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 5196687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 5206687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 52169d99fdcSPrabu Thangamuthu } 522f95f3850SWill Newton 5235ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 524141a712aSSeungwon Jeon 52569d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 52669d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 52769d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 52869d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 52969d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 53069d99fdcSPrabu Thangamuthu 53169d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 53269d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 53369d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 53469d99fdcSPrabu Thangamuthu 53569d99fdcSPrabu Thangamuthu } else { 536f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 537fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 53869d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 53969d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 540f95f3850SWill Newton 541f95f3850SWill Newton /* Set the descriptor base address */ 542f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 54369d99fdcSPrabu Thangamuthu } 54469d99fdcSPrabu Thangamuthu 545f95f3850SWill Newton return 0; 546f95f3850SWill Newton } 547f95f3850SWill Newton 5483b2a067bSShawn Lin static inline int dw_mci_prepare_desc64(struct dw_mci *host, 5493b2a067bSShawn Lin struct mmc_data *data, 5503b2a067bSShawn Lin unsigned int sg_len) 5513b2a067bSShawn Lin { 5523b2a067bSShawn Lin unsigned int desc_len; 5533b2a067bSShawn Lin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 5543b2a067bSShawn Lin unsigned long timeout; 5553b2a067bSShawn Lin int i; 5563b2a067bSShawn Lin 5573b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 5583b2a067bSShawn Lin 5593b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 5603b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 5613b2a067bSShawn Lin 5623b2a067bSShawn Lin u64 mem_addr = sg_dma_address(&data->sg[i]); 5633b2a067bSShawn Lin 5643b2a067bSShawn Lin for ( ; length ; desc++) { 5653b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 5663b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 5673b2a067bSShawn Lin 5683b2a067bSShawn Lin length -= desc_len; 5693b2a067bSShawn Lin 5703b2a067bSShawn Lin /* 5713b2a067bSShawn Lin * Wait for the former clear OWN bit operation 5723b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 5733b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 5743b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 5753b2a067bSShawn Lin */ 5763b2a067bSShawn Lin timeout = jiffies + msecs_to_jiffies(100); 5773b2a067bSShawn Lin while (readl(&desc->des0) & IDMAC_DES0_OWN) { 5783b2a067bSShawn Lin if (time_after(jiffies, timeout)) 5793b2a067bSShawn Lin goto err_own_bit; 5803b2a067bSShawn Lin udelay(10); 5813b2a067bSShawn Lin } 5823b2a067bSShawn Lin 5833b2a067bSShawn Lin /* 5843b2a067bSShawn Lin * Set the OWN bit and disable interrupts 5853b2a067bSShawn Lin * for this descriptor 5863b2a067bSShawn Lin */ 5873b2a067bSShawn Lin desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 5883b2a067bSShawn Lin IDMAC_DES0_CH; 5893b2a067bSShawn Lin 5903b2a067bSShawn Lin /* Buffer length */ 5913b2a067bSShawn Lin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 5923b2a067bSShawn Lin 5933b2a067bSShawn Lin /* Physical address to DMA to/from */ 5943b2a067bSShawn Lin desc->des4 = mem_addr & 0xffffffff; 5953b2a067bSShawn Lin desc->des5 = mem_addr >> 32; 5963b2a067bSShawn Lin 5973b2a067bSShawn Lin /* Update physical address for the next desc */ 5983b2a067bSShawn Lin mem_addr += desc_len; 5993b2a067bSShawn Lin 6003b2a067bSShawn Lin /* Save pointer to the last descriptor */ 6013b2a067bSShawn Lin desc_last = desc; 6023b2a067bSShawn Lin } 6033b2a067bSShawn Lin } 6043b2a067bSShawn Lin 6053b2a067bSShawn Lin /* Set first descriptor */ 6063b2a067bSShawn Lin desc_first->des0 |= IDMAC_DES0_FD; 6073b2a067bSShawn Lin 6083b2a067bSShawn Lin /* Set last descriptor */ 6093b2a067bSShawn Lin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 6103b2a067bSShawn Lin desc_last->des0 |= IDMAC_DES0_LD; 6113b2a067bSShawn Lin 6123b2a067bSShawn Lin return 0; 6133b2a067bSShawn Lin err_own_bit: 6143b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 6153b2a067bSShawn Lin dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n"); 616*cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 6173b2a067bSShawn Lin dw_mci_idmac_init(host); 6183b2a067bSShawn Lin return -EINVAL; 6193b2a067bSShawn Lin } 6203b2a067bSShawn Lin 6213b2a067bSShawn Lin 6223b2a067bSShawn Lin static inline int dw_mci_prepare_desc32(struct dw_mci *host, 6233b2a067bSShawn Lin struct mmc_data *data, 6243b2a067bSShawn Lin unsigned int sg_len) 6253b2a067bSShawn Lin { 6263b2a067bSShawn Lin unsigned int desc_len; 6273b2a067bSShawn Lin struct idmac_desc *desc_first, *desc_last, *desc; 6283b2a067bSShawn Lin unsigned long timeout; 6293b2a067bSShawn Lin int i; 6303b2a067bSShawn Lin 6313b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6323b2a067bSShawn Lin 6333b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6343b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6353b2a067bSShawn Lin 6363b2a067bSShawn Lin u32 mem_addr = sg_dma_address(&data->sg[i]); 6373b2a067bSShawn Lin 6383b2a067bSShawn Lin for ( ; length ; desc++) { 6393b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6403b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6413b2a067bSShawn Lin 6423b2a067bSShawn Lin length -= desc_len; 6433b2a067bSShawn Lin 6443b2a067bSShawn Lin /* 6453b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6463b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6473b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6483b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6493b2a067bSShawn Lin */ 6503b2a067bSShawn Lin timeout = jiffies + msecs_to_jiffies(100); 6513b2a067bSShawn Lin while (readl(&desc->des0) & 6523b2a067bSShawn Lin cpu_to_le32(IDMAC_DES0_OWN)) { 6533b2a067bSShawn Lin if (time_after(jiffies, timeout)) 6543b2a067bSShawn Lin goto err_own_bit; 6553b2a067bSShawn Lin udelay(10); 6563b2a067bSShawn Lin } 6573b2a067bSShawn Lin 6583b2a067bSShawn Lin /* 6593b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6603b2a067bSShawn Lin * for this descriptor 6613b2a067bSShawn Lin */ 6623b2a067bSShawn Lin desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 6633b2a067bSShawn Lin IDMAC_DES0_DIC | 6643b2a067bSShawn Lin IDMAC_DES0_CH); 6653b2a067bSShawn Lin 6663b2a067bSShawn Lin /* Buffer length */ 6673b2a067bSShawn Lin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 6683b2a067bSShawn Lin 6693b2a067bSShawn Lin /* Physical address to DMA to/from */ 6703b2a067bSShawn Lin desc->des2 = cpu_to_le32(mem_addr); 6713b2a067bSShawn Lin 6723b2a067bSShawn Lin /* Update physical address for the next desc */ 6733b2a067bSShawn Lin mem_addr += desc_len; 6743b2a067bSShawn Lin 6753b2a067bSShawn Lin /* Save pointer to the last descriptor */ 6763b2a067bSShawn Lin desc_last = desc; 6773b2a067bSShawn Lin } 6783b2a067bSShawn Lin } 6793b2a067bSShawn Lin 6803b2a067bSShawn Lin /* Set first descriptor */ 6813b2a067bSShawn Lin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 6823b2a067bSShawn Lin 6833b2a067bSShawn Lin /* Set last descriptor */ 6843b2a067bSShawn Lin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 6853b2a067bSShawn Lin IDMAC_DES0_DIC)); 6863b2a067bSShawn Lin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 6873b2a067bSShawn Lin 6883b2a067bSShawn Lin return 0; 6893b2a067bSShawn Lin err_own_bit: 6903b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 6913b2a067bSShawn Lin dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n"); 692*cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 6933b2a067bSShawn Lin dw_mci_idmac_init(host); 6943b2a067bSShawn Lin return -EINVAL; 6953b2a067bSShawn Lin } 6963b2a067bSShawn Lin 6973b2a067bSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 6983b2a067bSShawn Lin { 6993b2a067bSShawn Lin u32 temp; 7003b2a067bSShawn Lin int ret; 7013b2a067bSShawn Lin 7023b2a067bSShawn Lin if (host->dma_64bit_address == 1) 7033b2a067bSShawn Lin ret = dw_mci_prepare_desc64(host, host->data, sg_len); 7043b2a067bSShawn Lin else 7053b2a067bSShawn Lin ret = dw_mci_prepare_desc32(host, host->data, sg_len); 7063b2a067bSShawn Lin 7073b2a067bSShawn Lin if (ret) 7083b2a067bSShawn Lin goto out; 7093b2a067bSShawn Lin 7103b2a067bSShawn Lin /* drain writebuffer */ 7113b2a067bSShawn Lin wmb(); 7123b2a067bSShawn Lin 7133b2a067bSShawn Lin /* Make sure to reset DMA in case we did PIO before this */ 7143b2a067bSShawn Lin dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 7153b2a067bSShawn Lin dw_mci_idmac_reset(host); 7163b2a067bSShawn Lin 7173b2a067bSShawn Lin /* Select IDMAC interface */ 7183b2a067bSShawn Lin temp = mci_readl(host, CTRL); 7193b2a067bSShawn Lin temp |= SDMMC_CTRL_USE_IDMAC; 7203b2a067bSShawn Lin mci_writel(host, CTRL, temp); 7213b2a067bSShawn Lin 7223b2a067bSShawn Lin /* drain writebuffer */ 7233b2a067bSShawn Lin wmb(); 7243b2a067bSShawn Lin 7253b2a067bSShawn Lin /* Enable the IDMAC */ 7263b2a067bSShawn Lin temp = mci_readl(host, BMOD); 7273b2a067bSShawn Lin temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 7283b2a067bSShawn Lin mci_writel(host, BMOD, temp); 7293b2a067bSShawn Lin 7303b2a067bSShawn Lin /* Start it running */ 7313b2a067bSShawn Lin mci_writel(host, PLDMND, 1); 7323b2a067bSShawn Lin 7333b2a067bSShawn Lin out: 7343b2a067bSShawn Lin return ret; 7353b2a067bSShawn Lin } 7363b2a067bSShawn Lin 7378e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 738885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 739885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 740885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 7413fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 742885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 743885c3e80SSeungwon Jeon }; 7443fc7eaefSShawn Lin 7453fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 7463fc7eaefSShawn Lin { 747ab925a31SShawn Lin dmaengine_terminate_async(host->dms->ch); 7483fc7eaefSShawn Lin } 7493fc7eaefSShawn Lin 7503fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 7513fc7eaefSShawn Lin unsigned int sg_len) 7523fc7eaefSShawn Lin { 7533fc7eaefSShawn Lin struct dma_slave_config cfg; 7543fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 7553fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 7563fc7eaefSShawn Lin const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 7573fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 7583fc7eaefSShawn Lin u32 fifoth_val; 7593fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 7603fc7eaefSShawn Lin int ret = 0; 7613fc7eaefSShawn Lin 7623fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 763260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 7643fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 7653fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7663fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7673fc7eaefSShawn Lin 7683fc7eaefSShawn Lin /* Match burst msize with external dma config */ 7693fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 7703fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 7713fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 7723fc7eaefSShawn Lin 7733fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7743fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 7753fc7eaefSShawn Lin else 7763fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 7773fc7eaefSShawn Lin 7783fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 7793fc7eaefSShawn Lin if (ret) { 7803fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 7813fc7eaefSShawn Lin return -EBUSY; 7823fc7eaefSShawn Lin } 7833fc7eaefSShawn Lin 7843fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 7853fc7eaefSShawn Lin sg_len, cfg.direction, 7863fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 7873fc7eaefSShawn Lin if (!desc) { 7883fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 7893fc7eaefSShawn Lin return -EBUSY; 7903fc7eaefSShawn Lin } 7913fc7eaefSShawn Lin 7923fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 7933fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 7943fc7eaefSShawn Lin desc->callback_param = (void *)host; 7953fc7eaefSShawn Lin dmaengine_submit(desc); 7963fc7eaefSShawn Lin 7973fc7eaefSShawn Lin /* Flush cache before write */ 7983fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7993fc7eaefSShawn Lin dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 8003fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 8013fc7eaefSShawn Lin 8023fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 8033fc7eaefSShawn Lin 8043fc7eaefSShawn Lin return 0; 8053fc7eaefSShawn Lin } 8063fc7eaefSShawn Lin 8073fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 8083fc7eaefSShawn Lin { 8093fc7eaefSShawn Lin /* Request external dma channel */ 8103fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 8113fc7eaefSShawn Lin if (!host->dms) 8123fc7eaefSShawn Lin return -ENOMEM; 8133fc7eaefSShawn Lin 8143fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 8153fc7eaefSShawn Lin if (!host->dms->ch) { 8164539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 8173fc7eaefSShawn Lin kfree(host->dms); 8183fc7eaefSShawn Lin host->dms = NULL; 8193fc7eaefSShawn Lin return -ENXIO; 8203fc7eaefSShawn Lin } 8213fc7eaefSShawn Lin 8223fc7eaefSShawn Lin return 0; 8233fc7eaefSShawn Lin } 8243fc7eaefSShawn Lin 8253fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 8263fc7eaefSShawn Lin { 8273fc7eaefSShawn Lin if (host->dms) { 8283fc7eaefSShawn Lin if (host->dms->ch) { 8293fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 8303fc7eaefSShawn Lin host->dms->ch = NULL; 8313fc7eaefSShawn Lin } 8323fc7eaefSShawn Lin kfree(host->dms); 8333fc7eaefSShawn Lin host->dms = NULL; 8343fc7eaefSShawn Lin } 8353fc7eaefSShawn Lin } 8363fc7eaefSShawn Lin 8373fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 8383fc7eaefSShawn Lin .init = dw_mci_edmac_init, 8393fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 8403fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 8413fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 8423fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 8433fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 8443fc7eaefSShawn Lin }; 845885c3e80SSeungwon Jeon 8469aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 8479aa51408SSeungwon Jeon struct mmc_data *data, 8489aa51408SSeungwon Jeon bool next) 849f95f3850SWill Newton { 850f95f3850SWill Newton struct scatterlist *sg; 8519aa51408SSeungwon Jeon unsigned int i, sg_len; 852f95f3850SWill Newton 8539aa51408SSeungwon Jeon if (!next && data->host_cookie) 8549aa51408SSeungwon Jeon return data->host_cookie; 855f95f3850SWill Newton 856f95f3850SWill Newton /* 857f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 858f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 859f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 860f95f3850SWill Newton */ 861f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 862f95f3850SWill Newton return -EINVAL; 8639aa51408SSeungwon Jeon 864f95f3850SWill Newton if (data->blksz & 3) 865f95f3850SWill Newton return -EINVAL; 866f95f3850SWill Newton 867f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 868f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 869f95f3850SWill Newton return -EINVAL; 870f95f3850SWill Newton } 871f95f3850SWill Newton 8724a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 8739aa51408SSeungwon Jeon data->sg, 8749aa51408SSeungwon Jeon data->sg_len, 8759aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 8769aa51408SSeungwon Jeon if (sg_len == 0) 8779aa51408SSeungwon Jeon return -EINVAL; 8789aa51408SSeungwon Jeon 8799aa51408SSeungwon Jeon if (next) 8809aa51408SSeungwon Jeon data->host_cookie = sg_len; 8819aa51408SSeungwon Jeon 8829aa51408SSeungwon Jeon return sg_len; 8839aa51408SSeungwon Jeon } 8849aa51408SSeungwon Jeon 8859aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 8869aa51408SSeungwon Jeon struct mmc_request *mrq, 8879aa51408SSeungwon Jeon bool is_first_req) 8889aa51408SSeungwon Jeon { 8899aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 8909aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 8919aa51408SSeungwon Jeon 8929aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 8939aa51408SSeungwon Jeon return; 8949aa51408SSeungwon Jeon 8959aa51408SSeungwon Jeon if (data->host_cookie) { 8969aa51408SSeungwon Jeon data->host_cookie = 0; 8979aa51408SSeungwon Jeon return; 8989aa51408SSeungwon Jeon } 8999aa51408SSeungwon Jeon 9009aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 9019aa51408SSeungwon Jeon data->host_cookie = 0; 9029aa51408SSeungwon Jeon } 9039aa51408SSeungwon Jeon 9049aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 9059aa51408SSeungwon Jeon struct mmc_request *mrq, 9069aa51408SSeungwon Jeon int err) 9079aa51408SSeungwon Jeon { 9089aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9099aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9109aa51408SSeungwon Jeon 9119aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9129aa51408SSeungwon Jeon return; 9139aa51408SSeungwon Jeon 9149aa51408SSeungwon Jeon if (data->host_cookie) 9154a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 9169aa51408SSeungwon Jeon data->sg, 9179aa51408SSeungwon Jeon data->sg_len, 9189aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 9199aa51408SSeungwon Jeon data->host_cookie = 0; 9209aa51408SSeungwon Jeon } 9219aa51408SSeungwon Jeon 92252426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 92352426899SSeungwon Jeon { 92452426899SSeungwon Jeon unsigned int blksz = data->blksz; 92552426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 92652426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 92752426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 92852426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 9290e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 93052426899SSeungwon Jeon 9313fc7eaefSShawn Lin /* pio should ship this scenario */ 9323fc7eaefSShawn Lin if (!host->use_dma) 9333fc7eaefSShawn Lin return; 9343fc7eaefSShawn Lin 93552426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 93652426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 93752426899SSeungwon Jeon 93852426899SSeungwon Jeon /* 93952426899SSeungwon Jeon * MSIZE is '1', 94052426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 94152426899SSeungwon Jeon */ 94252426899SSeungwon Jeon if (blksz % fifo_width) { 94352426899SSeungwon Jeon msize = 0; 94452426899SSeungwon Jeon rx_wmark = 1; 94552426899SSeungwon Jeon goto done; 94652426899SSeungwon Jeon } 94752426899SSeungwon Jeon 94852426899SSeungwon Jeon do { 94952426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 95052426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 95152426899SSeungwon Jeon msize = idx; 95252426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 95352426899SSeungwon Jeon break; 95452426899SSeungwon Jeon } 95552426899SSeungwon Jeon } while (--idx > 0); 95652426899SSeungwon Jeon /* 95752426899SSeungwon Jeon * If idx is '0', it won't be tried 95852426899SSeungwon Jeon * Thus, initial values are uesed 95952426899SSeungwon Jeon */ 96052426899SSeungwon Jeon done: 96152426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 96252426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 96352426899SSeungwon Jeon } 96452426899SSeungwon Jeon 9657e4bf1bcSJaehoon Chung static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 966f1d2736cSSeungwon Jeon { 967f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 968f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 969f1d2736cSSeungwon Jeon u16 thld_size; 9707e4bf1bcSJaehoon Chung u8 enable; 971f1d2736cSSeungwon Jeon 97266dfd101SJames Hogan /* 97366dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 97466dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 97566dfd101SJames Hogan */ 9767e4bf1bcSJaehoon Chung if (host->verid < DW_MMC_240A || 9777e4bf1bcSJaehoon Chung (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 97866dfd101SJames Hogan return; 97966dfd101SJames Hogan 9807e4bf1bcSJaehoon Chung /* 9817e4bf1bcSJaehoon Chung * Card write Threshold is introduced since 2.80a 9827e4bf1bcSJaehoon Chung * It's used when HS400 mode is enabled. 9837e4bf1bcSJaehoon Chung */ 9847e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE && 9857e4bf1bcSJaehoon Chung !(host->timing != MMC_TIMING_MMC_HS400)) 9867e4bf1bcSJaehoon Chung return; 9877e4bf1bcSJaehoon Chung 9887e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE) 9897e4bf1bcSJaehoon Chung enable = SDMMC_CARD_WR_THR_EN; 9907e4bf1bcSJaehoon Chung else 9917e4bf1bcSJaehoon Chung enable = SDMMC_CARD_RD_THR_EN; 9927e4bf1bcSJaehoon Chung 993f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 994f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 995f1d2736cSSeungwon Jeon goto disable; 996f1d2736cSSeungwon Jeon 997f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 998f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 999f1d2736cSSeungwon Jeon 1000f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 1001f1d2736cSSeungwon Jeon goto disable; 1002f1d2736cSSeungwon Jeon 1003f1d2736cSSeungwon Jeon /* 1004f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1005f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1006f1d2736cSSeungwon Jeon * Currently just choose blksz. 1007f1d2736cSSeungwon Jeon */ 1008f1d2736cSSeungwon Jeon thld_size = blksz; 10097e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1010f1d2736cSSeungwon Jeon return; 1011f1d2736cSSeungwon Jeon 1012f1d2736cSSeungwon Jeon disable: 10137e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, 0); 1014f1d2736cSSeungwon Jeon } 1015f1d2736cSSeungwon Jeon 10169aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 10179aa51408SSeungwon Jeon { 1018f8c58c11SDoug Anderson unsigned long irqflags; 10199aa51408SSeungwon Jeon int sg_len; 10209aa51408SSeungwon Jeon u32 temp; 10219aa51408SSeungwon Jeon 10229aa51408SSeungwon Jeon host->using_dma = 0; 10239aa51408SSeungwon Jeon 10249aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 10259aa51408SSeungwon Jeon if (!host->use_dma) 10269aa51408SSeungwon Jeon return -ENODEV; 10279aa51408SSeungwon Jeon 10289aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 1029a99aa9b9SSeungwon Jeon if (sg_len < 0) { 1030a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 10319aa51408SSeungwon Jeon return sg_len; 1032a99aa9b9SSeungwon Jeon } 10339aa51408SSeungwon Jeon 103403e8cb53SJames Hogan host->using_dma = 1; 103503e8cb53SJames Hogan 10363fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 10374a90920cSThomas Abraham dev_vdbg(host->dev, 1038f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 10393fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 10403fc7eaefSShawn Lin (unsigned long)host->sg_dma, 1041f95f3850SWill Newton sg_len); 1042f95f3850SWill Newton 104352426899SSeungwon Jeon /* 104452426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 104552426899SSeungwon Jeon * If current block size is same with previous size, 104652426899SSeungwon Jeon * no need to update fifoth. 104752426899SSeungwon Jeon */ 104852426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 104952426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 105052426899SSeungwon Jeon 1051f95f3850SWill Newton /* Enable the DMA interface */ 1052f95f3850SWill Newton temp = mci_readl(host, CTRL); 1053f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 1054f95f3850SWill Newton mci_writel(host, CTRL, temp); 1055f95f3850SWill Newton 1056f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 1057f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1058f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1059f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1060f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1061f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1062f95f3850SWill Newton 10633fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 1064d12d0cb1SShawn Lin /* We can't do DMA, try PIO for this one */ 1065d12d0cb1SShawn Lin dev_dbg(host->dev, 1066d12d0cb1SShawn Lin "%s: fall back to PIO mode for current transfer\n", 1067d12d0cb1SShawn Lin __func__); 10683fc7eaefSShawn Lin return -ENODEV; 10693fc7eaefSShawn Lin } 1070f95f3850SWill Newton 1071f95f3850SWill Newton return 0; 1072f95f3850SWill Newton } 1073f95f3850SWill Newton 1074f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1075f95f3850SWill Newton { 1076f8c58c11SDoug Anderson unsigned long irqflags; 10770e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1078f95f3850SWill Newton u32 temp; 1079f95f3850SWill Newton 1080f95f3850SWill Newton data->error = -EINPROGRESS; 1081f95f3850SWill Newton 1082f95f3850SWill Newton WARN_ON(host->data); 1083f95f3850SWill Newton host->sg = NULL; 1084f95f3850SWill Newton host->data = data; 1085f95f3850SWill Newton 10867e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_READ) 108755c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 10887e4bf1bcSJaehoon Chung else 108955c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 10907e4bf1bcSJaehoon Chung 10917e4bf1bcSJaehoon Chung dw_mci_ctrl_thld(host, data); 109255c5efbcSJames Hogan 1093f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1094f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1095f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1096f9c2a0dcSSeungwon Jeon else 1097f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1098f9c2a0dcSSeungwon Jeon 1099f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1100f95f3850SWill Newton host->sg = data->sg; 110134b664a2SJames Hogan host->part_buf_start = 0; 110234b664a2SJames Hogan host->part_buf_count = 0; 1103f95f3850SWill Newton 1104b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1105f8c58c11SDoug Anderson 1106f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1107f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1108f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1109f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1110f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1111f95f3850SWill Newton 1112f95f3850SWill Newton temp = mci_readl(host, CTRL); 1113f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1114f95f3850SWill Newton mci_writel(host, CTRL, temp); 111552426899SSeungwon Jeon 111652426899SSeungwon Jeon /* 111752426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 111852426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 111952426899SSeungwon Jeon * prev_blksz should be invalidated. 112052426899SSeungwon Jeon */ 112152426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 112252426899SSeungwon Jeon host->prev_blksz = 0; 112352426899SSeungwon Jeon } else { 112452426899SSeungwon Jeon /* 112552426899SSeungwon Jeon * Keep the current block size. 112652426899SSeungwon Jeon * It will be used to decide whether to update 112752426899SSeungwon Jeon * fifoth register next time. 112852426899SSeungwon Jeon */ 112952426899SSeungwon Jeon host->prev_blksz = data->blksz; 1130f95f3850SWill Newton } 1131f95f3850SWill Newton } 1132f95f3850SWill Newton 1133f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 1134f95f3850SWill Newton { 1135f95f3850SWill Newton struct dw_mci *host = slot->host; 1136f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 1137f95f3850SWill Newton unsigned int cmd_status = 0; 1138f95f3850SWill Newton 1139f95f3850SWill Newton mci_writel(host, CMDARG, arg); 11400e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 11410bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd); 1142f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 1143f95f3850SWill Newton 1144f95f3850SWill Newton while (time_before(jiffies, timeout)) { 1145f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 1146f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 1147f95f3850SWill Newton return; 1148f95f3850SWill Newton } 1149f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 1150f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 1151f95f3850SWill Newton cmd, arg, cmd_status); 1152f95f3850SWill Newton } 1153f95f3850SWill Newton 1154ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1155f95f3850SWill Newton { 1156f95f3850SWill Newton struct dw_mci *host = slot->host; 1157fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1158f95f3850SWill Newton u32 div; 11599623b5b9SDoug Anderson u32 clk_en_a; 116001730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 116101730558SDoug Anderson 116201730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 116301730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 116401730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1165f95f3850SWill Newton 1166fdf492a1SDoug Anderson if (!clock) { 1167fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 116801730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1169fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1170fdf492a1SDoug Anderson div = host->bus_hz / clock; 1171fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1172f95f3850SWill Newton /* 1173f95f3850SWill Newton * move the + 1 after the divide to prevent 1174f95f3850SWill Newton * over-clocking the card. 1175f95f3850SWill Newton */ 1176e419990bSSeungwon Jeon div += 1; 1177e419990bSSeungwon Jeon 1178fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1179f95f3850SWill Newton 1180005d675aSJaehoon Chung if (clock != slot->__clk_old || force_clkinit) 1181f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1182fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1183fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1184fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1185fdf492a1SDoug Anderson host->bus_hz, div); 1186f95f3850SWill Newton 1187f95f3850SWill Newton /* disable clock */ 1188f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1189f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1190f95f3850SWill Newton 1191f95f3850SWill Newton /* inform CIU */ 119201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1193f95f3850SWill Newton 1194f95f3850SWill Newton /* set clock to desired speed */ 1195f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1196f95f3850SWill Newton 1197f95f3850SWill Newton /* inform CIU */ 119801730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1199f95f3850SWill Newton 12009623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 12019623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1202b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 12039623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 12049623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1205f95f3850SWill Newton 1206f95f3850SWill Newton /* inform CIU */ 120701730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1208005d675aSJaehoon Chung 1209005d675aSJaehoon Chung /* keep the last clock value that was requested from core */ 1210005d675aSJaehoon Chung slot->__clk_old = clock; 1211f95f3850SWill Newton } 1212f95f3850SWill Newton 1213fdf492a1SDoug Anderson host->current_speed = clock; 1214fdf492a1SDoug Anderson 1215f95f3850SWill Newton /* Set the current slot bus width */ 12161d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1217f95f3850SWill Newton } 1218f95f3850SWill Newton 1219053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1220053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1221053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1222f95f3850SWill Newton { 1223f95f3850SWill Newton struct mmc_request *mrq; 1224f95f3850SWill Newton struct mmc_data *data; 1225f95f3850SWill Newton u32 cmdflags; 1226f95f3850SWill Newton 1227f95f3850SWill Newton mrq = slot->mrq; 1228f95f3850SWill Newton 1229f95f3850SWill Newton host->cur_slot = slot; 1230f95f3850SWill Newton host->mrq = mrq; 1231f95f3850SWill Newton 1232f95f3850SWill Newton host->pending_events = 0; 1233f95f3850SWill Newton host->completed_events = 0; 1234e352c813SSeungwon Jeon host->cmd_status = 0; 1235f95f3850SWill Newton host->data_status = 0; 1236e352c813SSeungwon Jeon host->dir_status = 0; 1237f95f3850SWill Newton 1238053b3ce6SSeungwon Jeon data = cmd->data; 1239f95f3850SWill Newton if (data) { 1240f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1241f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1242f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1243f95f3850SWill Newton } 1244f95f3850SWill Newton 1245f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1246f95f3850SWill Newton 1247f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1248f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1249f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1250f95f3850SWill Newton 1251f95f3850SWill Newton if (data) { 1252f95f3850SWill Newton dw_mci_submit_data(host, data); 12530e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1254f95f3850SWill Newton } 1255f95f3850SWill Newton 1256f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1257f95f3850SWill Newton 12585c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 125949ba0302SDoug Anderson unsigned long irqflags; 126049ba0302SDoug Anderson 12615c935165SDoug Anderson /* 12628886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 12638886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 12648886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 12658886a6fdSDoug Anderson * is just about to roll over. 126649ba0302SDoug Anderson * 126749ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 126849ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 126949ba0302SDoug Anderson * already ran so we don't want the timeout). 12705c935165SDoug Anderson */ 127149ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 127249ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 12735c935165SDoug Anderson mod_timer(&host->cmd11_timer, 12748886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 127549ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 12765c935165SDoug Anderson } 12775c935165SDoug Anderson 1278f95f3850SWill Newton if (mrq->stop) 1279f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 128090c2143aSSeungwon Jeon else 128190c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1282f95f3850SWill Newton } 1283f95f3850SWill Newton 1284053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1285053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1286053b3ce6SSeungwon Jeon { 1287053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1288053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1289053b3ce6SSeungwon Jeon 1290053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1291053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1292053b3ce6SSeungwon Jeon } 1293053b3ce6SSeungwon Jeon 12947456caaeSJames Hogan /* must be called with host->lock held */ 1295f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1296f95f3850SWill Newton struct mmc_request *mrq) 1297f95f3850SWill Newton { 1298f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1299f95f3850SWill Newton host->state); 1300f95f3850SWill Newton 1301f95f3850SWill Newton slot->mrq = mrq; 1302f95f3850SWill Newton 130301730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 130401730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 130501730558SDoug Anderson "Voltage change didn't complete\n"); 130601730558SDoug Anderson /* 130701730558SDoug Anderson * this case isn't expected to happen, so we can 130801730558SDoug Anderson * either crash here or just try to continue on 130901730558SDoug Anderson * in the closest possible state 131001730558SDoug Anderson */ 131101730558SDoug Anderson host->state = STATE_IDLE; 131201730558SDoug Anderson } 131301730558SDoug Anderson 1314f95f3850SWill Newton if (host->state == STATE_IDLE) { 1315f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1316f95f3850SWill Newton dw_mci_start_request(host, slot); 1317f95f3850SWill Newton } else { 1318f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1319f95f3850SWill Newton } 1320f95f3850SWill Newton } 1321f95f3850SWill Newton 1322f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1323f95f3850SWill Newton { 1324f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1325f95f3850SWill Newton struct dw_mci *host = slot->host; 1326f95f3850SWill Newton 1327f95f3850SWill Newton WARN_ON(slot->mrq); 1328f95f3850SWill Newton 13297456caaeSJames Hogan /* 13307456caaeSJames Hogan * The check for card presence and queueing of the request must be 13317456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 13327456caaeSJames Hogan * request wouldn't fail until another card was inserted. 13337456caaeSJames Hogan */ 13347456caaeSJames Hogan 133556f6911cSShawn Lin if (!dw_mci_get_cd(mmc)) { 1336f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1337f95f3850SWill Newton mmc_request_done(mmc, mrq); 1338f95f3850SWill Newton return; 1339f95f3850SWill Newton } 1340f95f3850SWill Newton 134156f6911cSShawn Lin spin_lock_bh(&host->lock); 134256f6911cSShawn Lin 1343f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 13447456caaeSJames Hogan 13457456caaeSJames Hogan spin_unlock_bh(&host->lock); 1346f95f3850SWill Newton } 1347f95f3850SWill Newton 1348f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1349f95f3850SWill Newton { 1350f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1351e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 135241babf75SJaehoon Chung u32 regs; 135351da2240SYuvaraj CD int ret; 1354f95f3850SWill Newton 1355f95f3850SWill Newton switch (ios->bus_width) { 1356f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1357f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1358f95f3850SWill Newton break; 1359c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1360c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1361c9b2a06fSJaehoon Chung break; 1362b2f7cb45SJaehoon Chung default: 1363b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1364b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1365f95f3850SWill Newton } 1366f95f3850SWill Newton 136741babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 13683f514291SSeungwon Jeon 13693f514291SSeungwon Jeon /* DDR mode set */ 137080113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 13717cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 137280113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1373c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 13743f514291SSeungwon Jeon else 1375c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 13763f514291SSeungwon Jeon 137741babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1378f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 137941babf75SJaehoon Chung 1380f95f3850SWill Newton /* 1381f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1382f95f3850SWill Newton * core ios update when finding the minimum. 1383f95f3850SWill Newton */ 1384f95f3850SWill Newton slot->clock = ios->clock; 1385f95f3850SWill Newton 1386cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1387cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1388800d78bfSThomas Abraham 1389f95f3850SWill Newton switch (ios->power_mode) { 1390f95f3850SWill Newton case MMC_POWER_UP: 139151da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 139251da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 139351da2240SYuvaraj CD ios->vdd); 139451da2240SYuvaraj CD if (ret) { 139551da2240SYuvaraj CD dev_err(slot->host->dev, 139651da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 139751da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 139851da2240SYuvaraj CD return; 139951da2240SYuvaraj CD } 140051da2240SYuvaraj CD } 140129d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 140229d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 140329d0d161SDoug Anderson regs |= (1 << slot->id); 140429d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 140529d0d161SDoug Anderson break; 140629d0d161SDoug Anderson case MMC_POWER_ON: 1407d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1408d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 140951da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 141051da2240SYuvaraj CD if (ret < 0) 141151da2240SYuvaraj CD dev_err(slot->host->dev, 1412d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 141351da2240SYuvaraj CD else 141451da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1415d1f1dd86SDoug Anderson 1416d1f1dd86SDoug Anderson } else { 1417d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1418d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1419d1f1dd86SDoug Anderson } 1420d1f1dd86SDoug Anderson 1421d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1422d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1423d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 142451da2240SYuvaraj CD } 1425655babbdSDoug Anderson 1426655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1427655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1428655babbdSDoug Anderson 1429e6f34e2fSJames Hogan break; 1430e6f34e2fSJames Hogan case MMC_POWER_OFF: 1431655babbdSDoug Anderson /* Turn clock off before power goes down */ 1432655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1433655babbdSDoug Anderson 143451da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 143551da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 143651da2240SYuvaraj CD 1437d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 143851da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 143951da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 144051da2240SYuvaraj CD 14414366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 14424366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 14434366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1444f95f3850SWill Newton break; 1445f95f3850SWill Newton default: 1446f95f3850SWill Newton break; 1447f95f3850SWill Newton } 1448655babbdSDoug Anderson 1449655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1450655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1451f95f3850SWill Newton } 1452f95f3850SWill Newton 145301730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 145401730558SDoug Anderson { 145501730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 145601730558SDoug Anderson u32 status; 145701730558SDoug Anderson 145801730558SDoug Anderson /* 145901730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 146001730558SDoug Anderson * (the data lines) are 0000 146101730558SDoug Anderson */ 146201730558SDoug Anderson status = mci_readl(slot->host, STATUS); 146301730558SDoug Anderson 146401730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 146501730558SDoug Anderson } 146601730558SDoug Anderson 146701730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 146801730558SDoug Anderson { 146901730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 147001730558SDoug Anderson struct dw_mci *host = slot->host; 14718f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 147201730558SDoug Anderson u32 uhs; 147301730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 147401730558SDoug Anderson int ret; 147501730558SDoug Anderson 14768f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 14778f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 14788f7849c4SZhangfei Gao 147901730558SDoug Anderson /* 148001730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 148101730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 148201730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 148301730558SDoug Anderson */ 148401730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1485e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 148601730558SDoug Anderson uhs &= ~v18; 1487e0848f5dSDouglas Anderson else 148801730558SDoug Anderson uhs |= v18; 1489e0848f5dSDouglas Anderson 149001730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1491e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 149201730558SDoug Anderson 149301730558SDoug Anderson if (ret) { 1494b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1495e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1496e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 149701730558SDoug Anderson return ret; 149801730558SDoug Anderson } 149901730558SDoug Anderson } 150001730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 150101730558SDoug Anderson 150201730558SDoug Anderson return 0; 150301730558SDoug Anderson } 150401730558SDoug Anderson 1505f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1506f95f3850SWill Newton { 1507f95f3850SWill Newton int read_only; 1508f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 15099795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1510f95f3850SWill Newton 1511f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1512287980e4SArnd Bergmann if (gpio_ro >= 0) 15139795a846SJaehoon Chung read_only = gpio_ro; 1514f95f3850SWill Newton else 1515f95f3850SWill Newton read_only = 1516f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1517f95f3850SWill Newton 1518f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1519f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1520f95f3850SWill Newton 1521f95f3850SWill Newton return read_only; 1522f95f3850SWill Newton } 1523f95f3850SWill Newton 1524f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1525f95f3850SWill Newton { 1526f95f3850SWill Newton int present; 1527f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 15287cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 15297cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1530f95f3850SWill Newton 1531f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1532860951c5SJaehoon Chung if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc)) 1533fc3d7720SJaehoon Chung present = 1; 1534287980e4SArnd Bergmann else if (gpio_cd >= 0) 15357cf347bdSZhangfei Gao present = gpio_cd; 1536f95f3850SWill Newton else 1537f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1538f95f3850SWill Newton == 0 ? 1 : 0; 1539f95f3850SWill Newton 15407cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1541bf626e55SZhangfei Gao if (present) { 1542bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1543f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1544bf626e55SZhangfei Gao } else { 1545bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1546f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1547bf626e55SZhangfei Gao } 15487cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1549f95f3850SWill Newton 1550f95f3850SWill Newton return present; 1551f95f3850SWill Newton } 1552f95f3850SWill Newton 1553935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1554935a665eSShawn Lin { 1555935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1556935a665eSShawn Lin struct dw_mci *host = slot->host; 1557935a665eSShawn Lin int reset; 1558935a665eSShawn Lin 1559935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1560935a665eSShawn Lin dw_mci_idmac_reset(host); 1561935a665eSShawn Lin 1562935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1563935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1564935a665eSShawn Lin return; 1565935a665eSShawn Lin 1566935a665eSShawn Lin /* 1567935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1568935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1569935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1570935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1571935a665eSShawn Lin */ 1572935a665eSShawn Lin reset = mci_readl(host, RST_N); 1573935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1574935a665eSShawn Lin mci_writel(host, RST_N, reset); 1575935a665eSShawn Lin usleep_range(1, 2); 1576935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1577935a665eSShawn Lin mci_writel(host, RST_N, reset); 1578935a665eSShawn Lin usleep_range(200, 300); 1579935a665eSShawn Lin } 1580935a665eSShawn Lin 1581b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1582b24c8b26SDoug Anderson { 1583b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1584b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1585b24c8b26SDoug Anderson 15869623b5b9SDoug Anderson /* 15879623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 15889623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 15899623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 15909623b5b9SDoug Anderson */ 1591b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 15929623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1593b24c8b26SDoug Anderson u32 clk_en_a_old; 1594b24c8b26SDoug Anderson u32 clk_en_a; 15959623b5b9SDoug Anderson 1596b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 15979623b5b9SDoug Anderson 1598b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1599b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1600b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1601b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1602b24c8b26SDoug Anderson } else { 1603b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1604b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1605b24c8b26SDoug Anderson } 1606b24c8b26SDoug Anderson 1607b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1608b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 16099623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 16109623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 16119623b5b9SDoug Anderson } 16129623b5b9SDoug Anderson } 1613b24c8b26SDoug Anderson } 16149623b5b9SDoug Anderson 16151a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 16161a5c8e1fSShashidhar Hiremath { 16171a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 16181a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1619f8c58c11SDoug Anderson unsigned long irqflags; 16201a5c8e1fSShashidhar Hiremath u32 int_mask; 16211a5c8e1fSShashidhar Hiremath 1622f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1623f8c58c11SDoug Anderson 16241a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 16251a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1626b24c8b26SDoug Anderson if (enb) 1627b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1628b24c8b26SDoug Anderson else 1629b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1630b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1631f8c58c11SDoug Anderson 1632f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 16331a5c8e1fSShashidhar Hiremath } 16341a5c8e1fSShashidhar Hiremath 16350976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 16360976f16dSSeungwon Jeon { 16370976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 16380976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 16390976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 16400e3a22c0SShawn Lin int err = -EINVAL; 16410976f16dSSeungwon Jeon 16420976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 16439979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 16440976f16dSSeungwon Jeon return err; 16450976f16dSSeungwon Jeon } 16460976f16dSSeungwon Jeon 16470e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 16480e3a22c0SShawn Lin struct mmc_ios *ios) 164980113132SSeungwon Jeon { 165080113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 165180113132SSeungwon Jeon struct dw_mci *host = slot->host; 165280113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 165380113132SSeungwon Jeon 165480113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 165580113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 165680113132SSeungwon Jeon 165780113132SSeungwon Jeon return 0; 165880113132SSeungwon Jeon } 165980113132SSeungwon Jeon 1660f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1661f95f3850SWill Newton .request = dw_mci_request, 16629aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 16639aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1664f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1665f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1666f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1667935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 16681a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 16690976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 167001730558SDoug Anderson .card_busy = dw_mci_card_busy, 167101730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1672b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 167380113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1674f95f3850SWill Newton }; 1675f95f3850SWill Newton 1676f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1677f95f3850SWill Newton __releases(&host->lock) 1678f95f3850SWill Newton __acquires(&host->lock) 1679f95f3850SWill Newton { 1680f95f3850SWill Newton struct dw_mci_slot *slot; 1681f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1682f95f3850SWill Newton 1683f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1684f95f3850SWill Newton 1685f95f3850SWill Newton host->cur_slot->mrq = NULL; 1686f95f3850SWill Newton host->mrq = NULL; 1687f95f3850SWill Newton if (!list_empty(&host->queue)) { 1688f95f3850SWill Newton slot = list_entry(host->queue.next, 1689f95f3850SWill Newton struct dw_mci_slot, queue_node); 1690f95f3850SWill Newton list_del(&slot->queue_node); 16914a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1692f95f3850SWill Newton mmc_hostname(slot->mmc)); 1693f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1694f95f3850SWill Newton dw_mci_start_request(host, slot); 1695f95f3850SWill Newton } else { 16964a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 169701730558SDoug Anderson 169801730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 169901730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 170001730558SDoug Anderson else 1701f95f3850SWill Newton host->state = STATE_IDLE; 1702f95f3850SWill Newton } 1703f95f3850SWill Newton 1704f95f3850SWill Newton spin_unlock(&host->lock); 1705f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1706f95f3850SWill Newton spin_lock(&host->lock); 1707f95f3850SWill Newton } 1708f95f3850SWill Newton 1709e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1710f95f3850SWill Newton { 1711f95f3850SWill Newton u32 status = host->cmd_status; 1712f95f3850SWill Newton 1713f95f3850SWill Newton host->cmd_status = 0; 1714f95f3850SWill Newton 1715f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1716f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1717f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1718f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1719f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1720f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1721f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1722f95f3850SWill Newton } else { 1723f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1724f95f3850SWill Newton cmd->resp[1] = 0; 1725f95f3850SWill Newton cmd->resp[2] = 0; 1726f95f3850SWill Newton cmd->resp[3] = 0; 1727f95f3850SWill Newton } 1728f95f3850SWill Newton } 1729f95f3850SWill Newton 1730f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1731f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1732f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1733f95f3850SWill Newton cmd->error = -EILSEQ; 1734f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1735f95f3850SWill Newton cmd->error = -EIO; 1736f95f3850SWill Newton else 1737f95f3850SWill Newton cmd->error = 0; 1738f95f3850SWill Newton 1739e352c813SSeungwon Jeon return cmd->error; 1740e352c813SSeungwon Jeon } 1741e352c813SSeungwon Jeon 1742e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1743e352c813SSeungwon Jeon { 174431bff450SSeungwon Jeon u32 status = host->data_status; 1745e352c813SSeungwon Jeon 1746e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1747e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1748e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1749e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1750e352c813SSeungwon Jeon data->error = -EILSEQ; 1751e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1752e352c813SSeungwon Jeon if (host->dir_status == 1753e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1754e352c813SSeungwon Jeon /* 1755e352c813SSeungwon Jeon * No data CRC status was returned. 1756e352c813SSeungwon Jeon * The number of bytes transferred 1757e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1758e352c813SSeungwon Jeon */ 1759e352c813SSeungwon Jeon data->bytes_xfered = 0; 1760e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1761e352c813SSeungwon Jeon } else if (host->dir_status == 1762e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1763e7a1dec1SShawn Lin data->error = -EILSEQ; 1764e352c813SSeungwon Jeon } 1765e352c813SSeungwon Jeon } else { 1766e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1767e7a1dec1SShawn Lin data->error = -EILSEQ; 1768e352c813SSeungwon Jeon } 1769e352c813SSeungwon Jeon 1770e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1771e352c813SSeungwon Jeon 1772e352c813SSeungwon Jeon /* 1773e352c813SSeungwon Jeon * After an error, there may be data lingering 177431bff450SSeungwon Jeon * in the FIFO 1775e352c813SSeungwon Jeon */ 17763a33a94cSSonny Rao dw_mci_reset(host); 1777e352c813SSeungwon Jeon } else { 1778e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1779e352c813SSeungwon Jeon data->error = 0; 1780e352c813SSeungwon Jeon } 1781e352c813SSeungwon Jeon 1782e352c813SSeungwon Jeon return data->error; 1783f95f3850SWill Newton } 1784f95f3850SWill Newton 178557e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 178657e10486SAddy Ke { 178757e10486SAddy Ke unsigned int drto_clks; 178857e10486SAddy Ke unsigned int drto_ms; 178957e10486SAddy Ke 179057e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 179157e10486SAddy Ke drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 179257e10486SAddy Ke 179357e10486SAddy Ke /* add a bit spare time */ 179457e10486SAddy Ke drto_ms += 10; 179557e10486SAddy Ke 179657e10486SAddy Ke mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 179757e10486SAddy Ke } 179857e10486SAddy Ke 1799f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1800f95f3850SWill Newton { 1801f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1802f95f3850SWill Newton struct mmc_data *data; 1803f95f3850SWill Newton struct mmc_command *cmd; 1804e352c813SSeungwon Jeon struct mmc_request *mrq; 1805f95f3850SWill Newton enum dw_mci_state state; 1806f95f3850SWill Newton enum dw_mci_state prev_state; 1807e352c813SSeungwon Jeon unsigned int err; 1808f95f3850SWill Newton 1809f95f3850SWill Newton spin_lock(&host->lock); 1810f95f3850SWill Newton 1811f95f3850SWill Newton state = host->state; 1812f95f3850SWill Newton data = host->data; 1813e352c813SSeungwon Jeon mrq = host->mrq; 1814f95f3850SWill Newton 1815f95f3850SWill Newton do { 1816f95f3850SWill Newton prev_state = state; 1817f95f3850SWill Newton 1818f95f3850SWill Newton switch (state) { 1819f95f3850SWill Newton case STATE_IDLE: 182001730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1821f95f3850SWill Newton break; 1822f95f3850SWill Newton 182301730558SDoug Anderson case STATE_SENDING_CMD11: 1824f95f3850SWill Newton case STATE_SENDING_CMD: 1825f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1826f95f3850SWill Newton &host->pending_events)) 1827f95f3850SWill Newton break; 1828f95f3850SWill Newton 1829f95f3850SWill Newton cmd = host->cmd; 1830f95f3850SWill Newton host->cmd = NULL; 1831f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1832e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1833e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1834053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1835053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1836e352c813SSeungwon Jeon mrq->cmd); 1837053b3ce6SSeungwon Jeon goto unlock; 1838053b3ce6SSeungwon Jeon } 1839053b3ce6SSeungwon Jeon 1840e352c813SSeungwon Jeon if (cmd->data && err) { 184146d17952SDoug Anderson /* 184246d17952SDoug Anderson * During UHS tuning sequence, sending the stop 184346d17952SDoug Anderson * command after the response CRC error would 184446d17952SDoug Anderson * throw the system into a confused state 184546d17952SDoug Anderson * causing all future tuning phases to report 184646d17952SDoug Anderson * failure. 184746d17952SDoug Anderson * 184846d17952SDoug Anderson * In such case controller will move into a data 184946d17952SDoug Anderson * transfer state after a response error or 185046d17952SDoug Anderson * response CRC error. Let's let that finish 185146d17952SDoug Anderson * before trying to send a stop, so we'll go to 185246d17952SDoug Anderson * STATE_SENDING_DATA. 185346d17952SDoug Anderson * 185446d17952SDoug Anderson * Although letting the data transfer take place 185546d17952SDoug Anderson * will waste a bit of time (we already know 185646d17952SDoug Anderson * the command was bad), it can't cause any 185746d17952SDoug Anderson * errors since it's possible it would have 185846d17952SDoug Anderson * taken place anyway if this tasklet got 185946d17952SDoug Anderson * delayed. Allowing the transfer to take place 186046d17952SDoug Anderson * avoids races and keeps things simple. 186146d17952SDoug Anderson */ 186246d17952SDoug Anderson if ((err != -ETIMEDOUT) && 186346d17952SDoug Anderson (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 186446d17952SDoug Anderson state = STATE_SENDING_DATA; 186546d17952SDoug Anderson continue; 186646d17952SDoug Anderson } 186746d17952SDoug Anderson 186871abb133SSeungwon Jeon dw_mci_stop_dma(host); 186990c2143aSSeungwon Jeon send_stop_abort(host, data); 187071abb133SSeungwon Jeon state = STATE_SENDING_STOP; 187171abb133SSeungwon Jeon break; 187271abb133SSeungwon Jeon } 187371abb133SSeungwon Jeon 1874e352c813SSeungwon Jeon if (!cmd->data || err) { 1875e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1876f95f3850SWill Newton goto unlock; 1877f95f3850SWill Newton } 1878f95f3850SWill Newton 1879f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1880f95f3850SWill Newton /* fall through */ 1881f95f3850SWill Newton 1882f95f3850SWill Newton case STATE_SENDING_DATA: 18832aa35465SDoug Anderson /* 18842aa35465SDoug Anderson * We could get a data error and never a transfer 18852aa35465SDoug Anderson * complete so we'd better check for it here. 18862aa35465SDoug Anderson * 18872aa35465SDoug Anderson * Note that we don't really care if we also got a 18882aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 18892aa35465SDoug Anderson * abort won't hurt. 18902aa35465SDoug Anderson */ 1891f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1892f95f3850SWill Newton &host->pending_events)) { 1893f95f3850SWill Newton dw_mci_stop_dma(host); 1894bdb9a90bSaddy ke if (data->stop || 1895bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1896bdb9a90bSaddy ke SDMMC_INT_EBE))) 189790c2143aSSeungwon Jeon send_stop_abort(host, data); 1898f95f3850SWill Newton state = STATE_DATA_ERROR; 1899f95f3850SWill Newton break; 1900f95f3850SWill Newton } 1901f95f3850SWill Newton 1902f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 190357e10486SAddy Ke &host->pending_events)) { 190457e10486SAddy Ke /* 190557e10486SAddy Ke * If all data-related interrupts don't come 190657e10486SAddy Ke * within the given time in reading data state. 190757e10486SAddy Ke */ 190816a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 190957e10486SAddy Ke dw_mci_set_drto(host); 1910f95f3850SWill Newton break; 191157e10486SAddy Ke } 1912f95f3850SWill Newton 1913f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 19142aa35465SDoug Anderson 19152aa35465SDoug Anderson /* 19162aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 19172aa35465SDoug Anderson * before the transfer completed. This might not have 19182aa35465SDoug Anderson * been caught by the check above because the interrupt 19192aa35465SDoug Anderson * could have gone off between the previous check and 19202aa35465SDoug Anderson * the check for transfer complete. 19212aa35465SDoug Anderson * 19222aa35465SDoug Anderson * Technically this ought not be needed assuming we 19232aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 19242aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 19252aa35465SDoug Anderson * 19262aa35465SDoug Anderson * This has the advantage of sending the stop command. 19272aa35465SDoug Anderson */ 19282aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 19292aa35465SDoug Anderson &host->pending_events)) { 19302aa35465SDoug Anderson dw_mci_stop_dma(host); 1931bdb9a90bSaddy ke if (data->stop || 1932bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1933bdb9a90bSaddy ke SDMMC_INT_EBE))) 19342aa35465SDoug Anderson send_stop_abort(host, data); 19352aa35465SDoug Anderson state = STATE_DATA_ERROR; 19362aa35465SDoug Anderson break; 19372aa35465SDoug Anderson } 1938f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 19392aa35465SDoug Anderson 1940f95f3850SWill Newton /* fall through */ 1941f95f3850SWill Newton 1942f95f3850SWill Newton case STATE_DATA_BUSY: 1943f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 194457e10486SAddy Ke &host->pending_events)) { 194557e10486SAddy Ke /* 194657e10486SAddy Ke * If data error interrupt comes but data over 194757e10486SAddy Ke * interrupt doesn't come within the given time. 194857e10486SAddy Ke * in reading data state. 194957e10486SAddy Ke */ 195016a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 195157e10486SAddy Ke dw_mci_set_drto(host); 1952f95f3850SWill Newton break; 195357e10486SAddy Ke } 1954f95f3850SWill Newton 1955f95f3850SWill Newton host->data = NULL; 1956f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1957e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1958f95f3850SWill Newton 1959e352c813SSeungwon Jeon if (!err) { 1960e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 196117c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1962053b3ce6SSeungwon Jeon data->stop->error = 0; 1963e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1964053b3ce6SSeungwon Jeon goto unlock; 1965053b3ce6SSeungwon Jeon } 1966053b3ce6SSeungwon Jeon 196790c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1968e352c813SSeungwon Jeon if (data->stop) 196990c2143aSSeungwon Jeon send_stop_abort(host, data); 19702aa35465SDoug Anderson } else { 19712aa35465SDoug Anderson /* 19722aa35465SDoug Anderson * If we don't have a command complete now we'll 19732aa35465SDoug Anderson * never get one since we just reset everything; 19742aa35465SDoug Anderson * better end the request. 19752aa35465SDoug Anderson * 19762aa35465SDoug Anderson * If we do have a command complete we'll fall 19772aa35465SDoug Anderson * through to the SENDING_STOP command and 19782aa35465SDoug Anderson * everything will be peachy keen. 19792aa35465SDoug Anderson */ 19802aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 19812aa35465SDoug Anderson &host->pending_events)) { 19822aa35465SDoug Anderson host->cmd = NULL; 19832aa35465SDoug Anderson dw_mci_request_end(host, mrq); 19842aa35465SDoug Anderson goto unlock; 19852aa35465SDoug Anderson } 198690c2143aSSeungwon Jeon } 1987e352c813SSeungwon Jeon 1988e352c813SSeungwon Jeon /* 1989e352c813SSeungwon Jeon * If err has non-zero, 1990e352c813SSeungwon Jeon * stop-abort command has been already issued. 1991e352c813SSeungwon Jeon */ 1992e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1993e352c813SSeungwon Jeon 1994f95f3850SWill Newton /* fall through */ 1995f95f3850SWill Newton 1996f95f3850SWill Newton case STATE_SENDING_STOP: 1997f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1998f95f3850SWill Newton &host->pending_events)) 1999f95f3850SWill Newton break; 2000f95f3850SWill Newton 200171abb133SSeungwon Jeon /* CMD error in data command */ 200231bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 20033a33a94cSSonny Rao dw_mci_reset(host); 200471abb133SSeungwon Jeon 2005f95f3850SWill Newton host->cmd = NULL; 200671abb133SSeungwon Jeon host->data = NULL; 200790c2143aSSeungwon Jeon 2008e352c813SSeungwon Jeon if (mrq->stop) 2009e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 201090c2143aSSeungwon Jeon else 201190c2143aSSeungwon Jeon host->cmd_status = 0; 201290c2143aSSeungwon Jeon 2013e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2014f95f3850SWill Newton goto unlock; 2015f95f3850SWill Newton 2016f95f3850SWill Newton case STATE_DATA_ERROR: 2017f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2018f95f3850SWill Newton &host->pending_events)) 2019f95f3850SWill Newton break; 2020f95f3850SWill Newton 2021f95f3850SWill Newton state = STATE_DATA_BUSY; 2022f95f3850SWill Newton break; 2023f95f3850SWill Newton } 2024f95f3850SWill Newton } while (state != prev_state); 2025f95f3850SWill Newton 2026f95f3850SWill Newton host->state = state; 2027f95f3850SWill Newton unlock: 2028f95f3850SWill Newton spin_unlock(&host->lock); 2029f95f3850SWill Newton 2030f95f3850SWill Newton } 2031f95f3850SWill Newton 203234b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 203334b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 203434b664a2SJames Hogan { 203534b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 203634b664a2SJames Hogan host->part_buf_count = cnt; 203734b664a2SJames Hogan } 203834b664a2SJames Hogan 203934b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 204034b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 204134b664a2SJames Hogan { 204234b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 204334b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 204434b664a2SJames Hogan host->part_buf_count += cnt; 204534b664a2SJames Hogan return cnt; 204634b664a2SJames Hogan } 204734b664a2SJames Hogan 204834b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 204934b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 205034b664a2SJames Hogan { 20510e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 205234b664a2SJames Hogan if (cnt) { 205334b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 205434b664a2SJames Hogan cnt); 205534b664a2SJames Hogan host->part_buf_count -= cnt; 205634b664a2SJames Hogan host->part_buf_start += cnt; 205734b664a2SJames Hogan } 205834b664a2SJames Hogan return cnt; 205934b664a2SJames Hogan } 206034b664a2SJames Hogan 206134b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 206234b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 206334b664a2SJames Hogan { 206434b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 206534b664a2SJames Hogan host->part_buf_start = cnt; 206634b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 206734b664a2SJames Hogan } 206834b664a2SJames Hogan 2069f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2070f95f3850SWill Newton { 2071cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2072cfbeb59cSMarkos Chandras int init_cnt = cnt; 2073cfbeb59cSMarkos Chandras 207434b664a2SJames Hogan /* try and push anything in the part_buf */ 207534b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 207634b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 20770e3a22c0SShawn Lin 207834b664a2SJames Hogan buf += len; 207934b664a2SJames Hogan cnt -= len; 2080cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 208176184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 208234b664a2SJames Hogan host->part_buf_count = 0; 208334b664a2SJames Hogan } 208434b664a2SJames Hogan } 208534b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 208634b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 208734b664a2SJames Hogan while (cnt >= 2) { 208834b664a2SJames Hogan u16 aligned_buf[64]; 208934b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 209034b664a2SJames Hogan int items = len >> 1; 209134b664a2SJames Hogan int i; 209234b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 209334b664a2SJames Hogan memcpy(aligned_buf, buf, len); 209434b664a2SJames Hogan buf += len; 209534b664a2SJames Hogan cnt -= len; 209634b664a2SJames Hogan /* push data from aligned buffer into fifo */ 209734b664a2SJames Hogan for (i = 0; i < items; ++i) 209876184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 209934b664a2SJames Hogan } 210034b664a2SJames Hogan } else 210134b664a2SJames Hogan #endif 210234b664a2SJames Hogan { 210334b664a2SJames Hogan u16 *pdata = buf; 21040e3a22c0SShawn Lin 210534b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 210676184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 210734b664a2SJames Hogan buf = pdata; 210834b664a2SJames Hogan } 210934b664a2SJames Hogan /* put anything remaining in the part_buf */ 211034b664a2SJames Hogan if (cnt) { 211134b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2112cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2113cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2114cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 211576184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2116f95f3850SWill Newton } 2117f95f3850SWill Newton } 2118f95f3850SWill Newton 2119f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2120f95f3850SWill Newton { 212134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 212234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 212334b664a2SJames Hogan while (cnt >= 2) { 212434b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 212534b664a2SJames Hogan u16 aligned_buf[64]; 212634b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 212734b664a2SJames Hogan int items = len >> 1; 212834b664a2SJames Hogan int i; 21290e3a22c0SShawn Lin 213034b664a2SJames Hogan for (i = 0; i < items; ++i) 213176184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 213234b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 213334b664a2SJames Hogan memcpy(buf, aligned_buf, len); 213434b664a2SJames Hogan buf += len; 213534b664a2SJames Hogan cnt -= len; 213634b664a2SJames Hogan } 213734b664a2SJames Hogan } else 213834b664a2SJames Hogan #endif 213934b664a2SJames Hogan { 214034b664a2SJames Hogan u16 *pdata = buf; 21410e3a22c0SShawn Lin 214234b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 214376184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 214434b664a2SJames Hogan buf = pdata; 214534b664a2SJames Hogan } 214634b664a2SJames Hogan if (cnt) { 214776184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 214834b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2149f95f3850SWill Newton } 2150f95f3850SWill Newton } 2151f95f3850SWill Newton 2152f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2153f95f3850SWill Newton { 2154cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2155cfbeb59cSMarkos Chandras int init_cnt = cnt; 2156cfbeb59cSMarkos Chandras 215734b664a2SJames Hogan /* try and push anything in the part_buf */ 215834b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 215934b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 21600e3a22c0SShawn Lin 216134b664a2SJames Hogan buf += len; 216234b664a2SJames Hogan cnt -= len; 2163cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 216476184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 216534b664a2SJames Hogan host->part_buf_count = 0; 216634b664a2SJames Hogan } 216734b664a2SJames Hogan } 216834b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 216934b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 217034b664a2SJames Hogan while (cnt >= 4) { 217134b664a2SJames Hogan u32 aligned_buf[32]; 217234b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 217334b664a2SJames Hogan int items = len >> 2; 217434b664a2SJames Hogan int i; 217534b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 217634b664a2SJames Hogan memcpy(aligned_buf, buf, len); 217734b664a2SJames Hogan buf += len; 217834b664a2SJames Hogan cnt -= len; 217934b664a2SJames Hogan /* push data from aligned buffer into fifo */ 218034b664a2SJames Hogan for (i = 0; i < items; ++i) 218176184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 218234b664a2SJames Hogan } 218334b664a2SJames Hogan } else 218434b664a2SJames Hogan #endif 218534b664a2SJames Hogan { 218634b664a2SJames Hogan u32 *pdata = buf; 21870e3a22c0SShawn Lin 218834b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 218976184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 219034b664a2SJames Hogan buf = pdata; 219134b664a2SJames Hogan } 219234b664a2SJames Hogan /* put anything remaining in the part_buf */ 219334b664a2SJames Hogan if (cnt) { 219434b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2195cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2196cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2197cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 219876184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2199f95f3850SWill Newton } 2200f95f3850SWill Newton } 2201f95f3850SWill Newton 2202f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2203f95f3850SWill Newton { 220434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 220534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 220634b664a2SJames Hogan while (cnt >= 4) { 220734b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 220834b664a2SJames Hogan u32 aligned_buf[32]; 220934b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 221034b664a2SJames Hogan int items = len >> 2; 221134b664a2SJames Hogan int i; 22120e3a22c0SShawn Lin 221334b664a2SJames Hogan for (i = 0; i < items; ++i) 221476184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 221534b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 221634b664a2SJames Hogan memcpy(buf, aligned_buf, len); 221734b664a2SJames Hogan buf += len; 221834b664a2SJames Hogan cnt -= len; 221934b664a2SJames Hogan } 222034b664a2SJames Hogan } else 222134b664a2SJames Hogan #endif 222234b664a2SJames Hogan { 222334b664a2SJames Hogan u32 *pdata = buf; 22240e3a22c0SShawn Lin 222534b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 222676184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 222734b664a2SJames Hogan buf = pdata; 222834b664a2SJames Hogan } 222934b664a2SJames Hogan if (cnt) { 223076184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 223134b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2232f95f3850SWill Newton } 2233f95f3850SWill Newton } 2234f95f3850SWill Newton 2235f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2236f95f3850SWill Newton { 2237cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2238cfbeb59cSMarkos Chandras int init_cnt = cnt; 2239cfbeb59cSMarkos Chandras 224034b664a2SJames Hogan /* try and push anything in the part_buf */ 224134b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 224234b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 22430e3a22c0SShawn Lin 224434b664a2SJames Hogan buf += len; 224534b664a2SJames Hogan cnt -= len; 2246c09fbd74SSeungwon Jeon 2247cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 224876184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 224934b664a2SJames Hogan host->part_buf_count = 0; 225034b664a2SJames Hogan } 225134b664a2SJames Hogan } 225234b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 225334b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 225434b664a2SJames Hogan while (cnt >= 8) { 225534b664a2SJames Hogan u64 aligned_buf[16]; 225634b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 225734b664a2SJames Hogan int items = len >> 3; 225834b664a2SJames Hogan int i; 225934b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 226034b664a2SJames Hogan memcpy(aligned_buf, buf, len); 226134b664a2SJames Hogan buf += len; 226234b664a2SJames Hogan cnt -= len; 226334b664a2SJames Hogan /* push data from aligned buffer into fifo */ 226434b664a2SJames Hogan for (i = 0; i < items; ++i) 226576184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 226634b664a2SJames Hogan } 226734b664a2SJames Hogan } else 226834b664a2SJames Hogan #endif 226934b664a2SJames Hogan { 227034b664a2SJames Hogan u64 *pdata = buf; 22710e3a22c0SShawn Lin 227234b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 227376184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 227434b664a2SJames Hogan buf = pdata; 227534b664a2SJames Hogan } 227634b664a2SJames Hogan /* put anything remaining in the part_buf */ 227734b664a2SJames Hogan if (cnt) { 227834b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2279cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2280cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2281cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 228276184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2283f95f3850SWill Newton } 2284f95f3850SWill Newton } 2285f95f3850SWill Newton 2286f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2287f95f3850SWill Newton { 228834b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 228934b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 229034b664a2SJames Hogan while (cnt >= 8) { 229134b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 229234b664a2SJames Hogan u64 aligned_buf[16]; 229334b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 229434b664a2SJames Hogan int items = len >> 3; 229534b664a2SJames Hogan int i; 22960e3a22c0SShawn Lin 229734b664a2SJames Hogan for (i = 0; i < items; ++i) 229876184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 229976184ac1SBen Dooks 230034b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 230134b664a2SJames Hogan memcpy(buf, aligned_buf, len); 230234b664a2SJames Hogan buf += len; 230334b664a2SJames Hogan cnt -= len; 2304f95f3850SWill Newton } 230534b664a2SJames Hogan } else 230634b664a2SJames Hogan #endif 230734b664a2SJames Hogan { 230834b664a2SJames Hogan u64 *pdata = buf; 23090e3a22c0SShawn Lin 231034b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 231176184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 231234b664a2SJames Hogan buf = pdata; 231334b664a2SJames Hogan } 231434b664a2SJames Hogan if (cnt) { 231576184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 231634b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 231734b664a2SJames Hogan } 231834b664a2SJames Hogan } 231934b664a2SJames Hogan 232034b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 232134b664a2SJames Hogan { 232234b664a2SJames Hogan int len; 232334b664a2SJames Hogan 232434b664a2SJames Hogan /* get remaining partial bytes */ 232534b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 232634b664a2SJames Hogan if (unlikely(len == cnt)) 232734b664a2SJames Hogan return; 232834b664a2SJames Hogan buf += len; 232934b664a2SJames Hogan cnt -= len; 233034b664a2SJames Hogan 233134b664a2SJames Hogan /* get the rest of the data */ 233234b664a2SJames Hogan host->pull_data(host, buf, cnt); 2333f95f3850SWill Newton } 2334f95f3850SWill Newton 233587a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2336f95f3850SWill Newton { 2337f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2338f9c2a0dcSSeungwon Jeon void *buf; 2339f9c2a0dcSSeungwon Jeon unsigned int offset; 2340f95f3850SWill Newton struct mmc_data *data = host->data; 2341f95f3850SWill Newton int shift = host->data_shift; 2342f95f3850SWill Newton u32 status; 23433e4b0d8bSMarkos Chandras unsigned int len; 2344f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2345f95f3850SWill Newton 2346f95f3850SWill Newton do { 2347f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2348f9c2a0dcSSeungwon Jeon goto done; 2349f95f3850SWill Newton 23504225fc85SImre Deak host->sg = sg_miter->piter.sg; 2351f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2352f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2353f9c2a0dcSSeungwon Jeon offset = 0; 2354f9c2a0dcSSeungwon Jeon 2355f9c2a0dcSSeungwon Jeon do { 2356f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2357f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2358f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2359f9c2a0dcSSeungwon Jeon if (!len) 2360f9c2a0dcSSeungwon Jeon break; 2361f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 23623e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2363f95f3850SWill Newton offset += len; 2364f9c2a0dcSSeungwon Jeon remain -= len; 2365f9c2a0dcSSeungwon Jeon } while (remain); 2366f95f3850SWill Newton 2367e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2368f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2369f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 237087a74d39SKyoungil Kim /* if the RXDR is ready read again */ 237187a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 237287a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2373f9c2a0dcSSeungwon Jeon 2374f9c2a0dcSSeungwon Jeon if (!remain) { 2375f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2376f9c2a0dcSSeungwon Jeon goto done; 2377f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2378f9c2a0dcSSeungwon Jeon } 2379f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2380f95f3850SWill Newton return; 2381f95f3850SWill Newton 2382f95f3850SWill Newton done: 2383f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2384f9c2a0dcSSeungwon Jeon host->sg = NULL; 23850e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2386f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2387f95f3850SWill Newton } 2388f95f3850SWill Newton 2389f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2390f95f3850SWill Newton { 2391f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2392f9c2a0dcSSeungwon Jeon void *buf; 2393f9c2a0dcSSeungwon Jeon unsigned int offset; 2394f95f3850SWill Newton struct mmc_data *data = host->data; 2395f95f3850SWill Newton int shift = host->data_shift; 2396f95f3850SWill Newton u32 status; 23973e4b0d8bSMarkos Chandras unsigned int len; 2398f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2399f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2400f95f3850SWill Newton 2401f95f3850SWill Newton do { 2402f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2403f9c2a0dcSSeungwon Jeon goto done; 2404f95f3850SWill Newton 24054225fc85SImre Deak host->sg = sg_miter->piter.sg; 2406f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2407f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2408f9c2a0dcSSeungwon Jeon offset = 0; 2409f9c2a0dcSSeungwon Jeon 2410f9c2a0dcSSeungwon Jeon do { 2411f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2412f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2413f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2414f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2415f9c2a0dcSSeungwon Jeon if (!len) 2416f9c2a0dcSSeungwon Jeon break; 2417f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 24183e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2419f95f3850SWill Newton offset += len; 2420f9c2a0dcSSeungwon Jeon remain -= len; 2421f9c2a0dcSSeungwon Jeon } while (remain); 2422f95f3850SWill Newton 2423e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2424f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2425f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2426f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2427f9c2a0dcSSeungwon Jeon 2428f9c2a0dcSSeungwon Jeon if (!remain) { 2429f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2430f9c2a0dcSSeungwon Jeon goto done; 2431f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2432f9c2a0dcSSeungwon Jeon } 2433f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2434f95f3850SWill Newton return; 2435f95f3850SWill Newton 2436f95f3850SWill Newton done: 2437f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2438f9c2a0dcSSeungwon Jeon host->sg = NULL; 24390e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2440f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2441f95f3850SWill Newton } 2442f95f3850SWill Newton 2443f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2444f95f3850SWill Newton { 2445f95f3850SWill Newton if (!host->cmd_status) 2446f95f3850SWill Newton host->cmd_status = status; 2447f95f3850SWill Newton 24480e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2449f95f3850SWill Newton 2450f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2451f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2452f95f3850SWill Newton } 2453f95f3850SWill Newton 24546130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 24556130e7a9SDoug Anderson { 24566130e7a9SDoug Anderson int i; 24576130e7a9SDoug Anderson 24586130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 24596130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 24606130e7a9SDoug Anderson 24616130e7a9SDoug Anderson if (!slot) 24626130e7a9SDoug Anderson continue; 24636130e7a9SDoug Anderson 24646130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 24656130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 24666130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 24676130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 24686130e7a9SDoug Anderson } 24696130e7a9SDoug Anderson } 24706130e7a9SDoug Anderson 2471f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2472f95f3850SWill Newton { 2473f95f3850SWill Newton struct dw_mci *host = dev_id; 2474182c9081SSeungwon Jeon u32 pending; 24751a5c8e1fSShashidhar Hiremath int i; 2476f95f3850SWill Newton 2477f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2478f95f3850SWill Newton 2479476d79f1SDoug Anderson if (pending) { 248001730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 248101730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 248201730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 248349ba0302SDoug Anderson unsigned long irqflags; 24845c935165SDoug Anderson 248501730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 248601730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 248749ba0302SDoug Anderson 248849ba0302SDoug Anderson /* 248949ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 249049ba0302SDoug Anderson * off after the lock is released, so safe to delete. 249149ba0302SDoug Anderson */ 249249ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 249301730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 249449ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 249549ba0302SDoug Anderson 249649ba0302SDoug Anderson del_timer(&host->cmd11_timer); 249701730558SDoug Anderson } 249801730558SDoug Anderson 2499f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2500f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2501182c9081SSeungwon Jeon host->cmd_status = pending; 25020e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2503f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2504f95f3850SWill Newton } 2505f95f3850SWill Newton 2506f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2507f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2508f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2509182c9081SSeungwon Jeon host->data_status = pending; 25100e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2511f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2512f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2513f95f3850SWill Newton } 2514f95f3850SWill Newton 2515f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 251657e10486SAddy Ke del_timer(&host->dto_timer); 251757e10486SAddy Ke 2518f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2519f95f3850SWill Newton if (!host->data_status) 2520182c9081SSeungwon Jeon host->data_status = pending; 25210e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2522f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2523f95f3850SWill Newton if (host->sg != NULL) 252487a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2525f95f3850SWill Newton } 2526f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2527f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2528f95f3850SWill Newton } 2529f95f3850SWill Newton 2530f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2531f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2532b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 253387a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2534f95f3850SWill Newton } 2535f95f3850SWill Newton 2536f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2537f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2538b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2539f95f3850SWill Newton dw_mci_write_data_pio(host); 2540f95f3850SWill Newton } 2541f95f3850SWill Newton 2542f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2543f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2544182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2545f95f3850SWill Newton } 2546f95f3850SWill Newton 2547f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2548f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 25496130e7a9SDoug Anderson dw_mci_handle_cd(host); 2550f95f3850SWill Newton } 2551f95f3850SWill Newton 25521a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 25531a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 25541a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2555ed2540efSDoug Anderson 2556ed2540efSDoug Anderson if (!slot) 2557ed2540efSDoug Anderson continue; 2558ed2540efSDoug Anderson 255976756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 256076756234SAddy Ke mci_writel(host, RINTSTS, 256176756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 25621a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 25631a5c8e1fSShashidhar Hiremath } 25641a5c8e1fSShashidhar Hiremath } 25651a5c8e1fSShashidhar Hiremath 25661fb5f68aSMarkos Chandras } 2567f95f3850SWill Newton 25683fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 25693fc7eaefSShawn Lin return IRQ_HANDLED; 25703fc7eaefSShawn Lin 25713fc7eaefSShawn Lin /* Handle IDMA interrupts */ 257269d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 257369d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 257469d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 257569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 257669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 257769d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2578faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 25793fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 258069d99fdcSPrabu Thangamuthu } 258169d99fdcSPrabu Thangamuthu } else { 2582f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2583f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 258469d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 258569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2586f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2587faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 25883fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2589f95f3850SWill Newton } 259069d99fdcSPrabu Thangamuthu } 2591f95f3850SWill Newton 2592f95f3850SWill Newton return IRQ_HANDLED; 2593f95f3850SWill Newton } 2594f95f3850SWill Newton 259536c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2596f95f3850SWill Newton { 2597f95f3850SWill Newton struct mmc_host *mmc; 2598f95f3850SWill Newton struct dw_mci_slot *slot; 2599e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2600800d78bfSThomas Abraham int ctrl_id, ret; 26011f44a2a5SSeungwon Jeon u32 freq[2]; 2602f95f3850SWill Newton 26034a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2604f95f3850SWill Newton if (!mmc) 2605f95f3850SWill Newton return -ENOMEM; 2606f95f3850SWill Newton 2607f95f3850SWill Newton slot = mmc_priv(mmc); 2608f95f3850SWill Newton slot->id = id; 260976756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2610f95f3850SWill Newton slot->mmc = mmc; 2611f95f3850SWill Newton slot->host = host; 2612c91eab4bSThomas Abraham host->slot[id] = slot; 2613f95f3850SWill Newton 2614f95f3850SWill Newton mmc->ops = &dw_mci_ops; 26151f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 26161f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 26171f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 26181f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 26191f44a2a5SSeungwon Jeon } else { 26201f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 26211f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 26221f44a2a5SSeungwon Jeon } 2623f95f3850SWill Newton 262451da2240SYuvaraj CD /*if there are external regulators, get them*/ 262551da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 262651da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 26273cf890fcSDoug Anderson goto err_host_allocated; 262851da2240SYuvaraj CD 262951da2240SYuvaraj CD if (!mmc->ocr_avail) 2630f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2631f95f3850SWill Newton 2632fc3d7720SJaehoon Chung if (host->pdata->caps) 2633fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2634fc3d7720SJaehoon Chung 26356024e166SJaehoon Chung /* 26366024e166SJaehoon Chung * Support MMC_CAP_ERASE by default. 26376024e166SJaehoon Chung * It needs to use trim/discard/erase commands. 26386024e166SJaehoon Chung */ 26396024e166SJaehoon Chung mmc->caps |= MMC_CAP_ERASE; 26406024e166SJaehoon Chung 2641ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2642ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2643ab269128SAbhilash Kesavan 2644800d78bfSThomas Abraham if (host->dev->of_node) { 2645800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2646800d78bfSThomas Abraham if (ctrl_id < 0) 2647800d78bfSThomas Abraham ctrl_id = 0; 2648800d78bfSThomas Abraham } else { 2649800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2650800d78bfSThomas Abraham } 2651cb27a843SJames Hogan if (drv_data && drv_data->caps) 2652cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2653800d78bfSThomas Abraham 26544f408cc6SSeungwon Jeon if (host->pdata->caps2) 26554f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 26564f408cc6SSeungwon Jeon 26573cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 26583cf890fcSDoug Anderson if (ret) 26593cf890fcSDoug Anderson goto err_host_allocated; 2660f95f3850SWill Newton 2661f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 26623fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2663a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2664225faf87SJaehoon Chung mmc->max_blk_size = 65535; 2665575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 26661a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 26671a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 26683fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 26693fc7eaefSShawn Lin mmc->max_segs = 64; 2670225faf87SJaehoon Chung mmc->max_blk_size = 65535; 26713fc7eaefSShawn Lin mmc->max_blk_count = 65535; 26723fc7eaefSShawn Lin mmc->max_req_size = 26733fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 26743fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2675575c319dSHeiko Stuebner } else { 26763fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2677f95f3850SWill Newton mmc->max_segs = 64; 2678225faf87SJaehoon Chung mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2679f95f3850SWill Newton mmc->max_blk_count = 512; 2680575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2681575c319dSHeiko Stuebner mmc->max_blk_count; 2682f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2683575c319dSHeiko Stuebner } 2684f95f3850SWill Newton 2685c0834a58SShawn Lin dw_mci_get_cd(mmc); 2686ae0eb348SJaehoon Chung 26870cea529dSJaehoon Chung ret = mmc_add_host(mmc); 26880cea529dSJaehoon Chung if (ret) 26893cf890fcSDoug Anderson goto err_host_allocated; 2690f95f3850SWill Newton 2691f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2692f95f3850SWill Newton dw_mci_init_debugfs(slot); 2693f95f3850SWill Newton #endif 2694f95f3850SWill Newton 2695f95f3850SWill Newton return 0; 2696800d78bfSThomas Abraham 26973cf890fcSDoug Anderson err_host_allocated: 2698800d78bfSThomas Abraham mmc_free_host(mmc); 269951da2240SYuvaraj CD return ret; 2700f95f3850SWill Newton } 2701f95f3850SWill Newton 2702f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2703f95f3850SWill Newton { 2704f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2705f95f3850SWill Newton mmc_remove_host(slot->mmc); 2706f95f3850SWill Newton slot->host->slot[id] = NULL; 2707f95f3850SWill Newton mmc_free_host(slot->mmc); 2708f95f3850SWill Newton } 2709f95f3850SWill Newton 2710f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2711f95f3850SWill Newton { 271269d99fdcSPrabu Thangamuthu int addr_config; 27133fc7eaefSShawn Lin struct device *dev = host->dev; 27143fc7eaefSShawn Lin struct device_node *np = dev->of_node; 27153fc7eaefSShawn Lin 27163fc7eaefSShawn Lin /* 27173fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 27183fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 27193fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 27203fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 27213fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 27223fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 27233fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 27243fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 27253fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 27263fc7eaefSShawn Lin */ 27273fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 27283fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 27293fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 27303fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 27313fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 27323fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 27333fc7eaefSShawn Lin } else { 27343fc7eaefSShawn Lin goto no_dma; 27353fc7eaefSShawn Lin } 27363fc7eaefSShawn Lin 27373fc7eaefSShawn Lin /* Determine which DMA interface to use */ 27383fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 27393fc7eaefSShawn Lin /* 27403fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 27413fc7eaefSShawn Lin * IDMAC address bus width 27423fc7eaefSShawn Lin */ 274370692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 274469d99fdcSPrabu Thangamuthu 274569d99fdcSPrabu Thangamuthu if (addr_config == 1) { 274669d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 274769d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 27483fc7eaefSShawn Lin dev_info(host->dev, 27493fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 275069d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 27513fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 27523fc7eaefSShawn Lin DMA_BIT_MASK(64)); 275369d99fdcSPrabu Thangamuthu } else { 275469d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 275569d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 27563fc7eaefSShawn Lin dev_info(host->dev, 27573fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 275869d99fdcSPrabu Thangamuthu } 275969d99fdcSPrabu Thangamuthu 2760f95f3850SWill Newton /* Alloc memory for sg translation */ 2761*cc190d4cSShawn Lin host->sg_cpu = dmam_alloc_coherent(host->dev, 2762*cc190d4cSShawn Lin DESC_RING_BUF_SZ, 2763f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2764f95f3850SWill Newton if (!host->sg_cpu) { 27653fc7eaefSShawn Lin dev_err(host->dev, 27663fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2767f95f3850SWill Newton __func__); 2768f95f3850SWill Newton goto no_dma; 2769f95f3850SWill Newton } 2770f95f3850SWill Newton 2771f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 277200956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 27733fc7eaefSShawn Lin } else { 27743fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 27753fc7eaefSShawn Lin if ((of_property_count_strings(np, "dma-names") < 0) || 27763fc7eaefSShawn Lin (!of_find_property(np, "dmas", NULL))) { 2777f95f3850SWill Newton goto no_dma; 27783fc7eaefSShawn Lin } 27793fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 27803fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 27813fc7eaefSShawn Lin } 2782f95f3850SWill Newton 2783e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2784e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2785f95f3850SWill Newton if (host->dma_ops->init(host)) { 27860e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 27870e3a22c0SShawn Lin __func__); 2788f95f3850SWill Newton goto no_dma; 2789f95f3850SWill Newton } 2790f95f3850SWill Newton } else { 27914a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2792f95f3850SWill Newton goto no_dma; 2793f95f3850SWill Newton } 2794f95f3850SWill Newton 2795f95f3850SWill Newton return; 2796f95f3850SWill Newton 2797f95f3850SWill Newton no_dma: 27984a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 27993fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2800f95f3850SWill Newton } 2801f95f3850SWill Newton 280231bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2803f95f3850SWill Newton { 2804f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 280531bff450SSeungwon Jeon u32 ctrl; 2806f95f3850SWill Newton 280731bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 280831bff450SSeungwon Jeon ctrl |= reset; 280931bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2810f95f3850SWill Newton 2811f95f3850SWill Newton /* wait till resets clear */ 2812f95f3850SWill Newton do { 2813f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 281431bff450SSeungwon Jeon if (!(ctrl & reset)) 2815f95f3850SWill Newton return true; 2816f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2817f95f3850SWill Newton 281831bff450SSeungwon Jeon dev_err(host->dev, 281931bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 282031bff450SSeungwon Jeon ctrl & reset); 2821f95f3850SWill Newton 2822f95f3850SWill Newton return false; 2823f95f3850SWill Newton } 2824f95f3850SWill Newton 28253a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 282631bff450SSeungwon Jeon { 28273a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 28283a33a94cSSonny Rao bool ret = false; 28293a33a94cSSonny Rao 283031bff450SSeungwon Jeon /* 283131bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 283231bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 283331bff450SSeungwon Jeon */ 283431bff450SSeungwon Jeon if (host->sg) { 283531bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 283631bff450SSeungwon Jeon host->sg = NULL; 283731bff450SSeungwon Jeon } 283831bff450SSeungwon Jeon 28393a33a94cSSonny Rao if (host->use_dma) 28403a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 28413a33a94cSSonny Rao 28423a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 28433a33a94cSSonny Rao /* 28443a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 28453a33a94cSSonny Rao * interrupts. 28463a33a94cSSonny Rao */ 28473a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 28483a33a94cSSonny Rao 28493a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 28503a33a94cSSonny Rao if (host->use_dma) { 28513a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 28523a33a94cSSonny Rao u32 status; 28530e3a22c0SShawn Lin 28543a33a94cSSonny Rao do { 28553a33a94cSSonny Rao status = mci_readl(host, STATUS); 28563a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 28573a33a94cSSonny Rao break; 28583a33a94cSSonny Rao cpu_relax(); 28593a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 28603a33a94cSSonny Rao 28613a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 28623a33a94cSSonny Rao dev_err(host->dev, 28630e3a22c0SShawn Lin "%s: Timeout waiting for dma_req to clear during reset\n", 28640e3a22c0SShawn Lin __func__); 28653a33a94cSSonny Rao goto ciu_out; 286631bff450SSeungwon Jeon } 286731bff450SSeungwon Jeon 28683a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 28693a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 28703a33a94cSSonny Rao goto ciu_out; 28713a33a94cSSonny Rao } 28723a33a94cSSonny Rao } else { 28733a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 28743a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 28750e3a22c0SShawn Lin dev_err(host->dev, 28760e3a22c0SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 28773a33a94cSSonny Rao __func__); 28783a33a94cSSonny Rao goto ciu_out; 28793a33a94cSSonny Rao } 28803a33a94cSSonny Rao } 28813a33a94cSSonny Rao 28823fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 28833a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 28843a33a94cSSonny Rao dw_mci_idmac_reset(host); 28853a33a94cSSonny Rao 28863a33a94cSSonny Rao ret = true; 28873a33a94cSSonny Rao 28883a33a94cSSonny Rao ciu_out: 28893a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 28903a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 28913a33a94cSSonny Rao 28923a33a94cSSonny Rao return ret; 289331bff450SSeungwon Jeon } 289431bff450SSeungwon Jeon 28955c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 28965c935165SDoug Anderson { 28975c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 28985c935165SDoug Anderson 2899fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 2900fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2901fd674198SDoug Anderson return; 2902fd674198SDoug Anderson } 29035c935165SDoug Anderson 29045c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 29055c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 29065c935165SDoug Anderson tasklet_schedule(&host->tasklet); 29075c935165SDoug Anderson } 29085c935165SDoug Anderson 290957e10486SAddy Ke static void dw_mci_dto_timer(unsigned long arg) 291057e10486SAddy Ke { 291157e10486SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 291257e10486SAddy Ke 291357e10486SAddy Ke switch (host->state) { 291457e10486SAddy Ke case STATE_SENDING_DATA: 291557e10486SAddy Ke case STATE_DATA_BUSY: 291657e10486SAddy Ke /* 291757e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 291857e10486SAddy Ke * we should notify the driver to terminate current transfer 291957e10486SAddy Ke * and report a data timeout to the core. 292057e10486SAddy Ke */ 292157e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 292257e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 292357e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 292457e10486SAddy Ke tasklet_schedule(&host->tasklet); 292557e10486SAddy Ke break; 292657e10486SAddy Ke default: 292757e10486SAddy Ke break; 292857e10486SAddy Ke } 292957e10486SAddy Ke } 293057e10486SAddy Ke 2931c91eab4bSThomas Abraham #ifdef CONFIG_OF 2932c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2933c91eab4bSThomas Abraham { 2934c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2935c91eab4bSThomas Abraham struct device *dev = host->dev; 2936c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2937e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2938e8cc37b8SShawn Lin int ret; 29393c6d89eaSDoug Anderson u32 clock_frequency; 2940c91eab4bSThomas Abraham 2941c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2942bf3707eaSBeomho Seo if (!pdata) 2943c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2944c91eab4bSThomas Abraham 2945d6786fefSGuodong Xu /* find reset controller when exist */ 2946d6786fefSGuodong Xu pdata->rstc = devm_reset_control_get_optional(dev, NULL); 2947d6786fefSGuodong Xu if (IS_ERR(pdata->rstc)) { 2948d6786fefSGuodong Xu if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 2949d6786fefSGuodong Xu return ERR_PTR(-EPROBE_DEFER); 2950d6786fefSGuodong Xu } 2951d6786fefSGuodong Xu 2952c91eab4bSThomas Abraham /* find out number of slots supported */ 29538a629d26SShawn Lin of_property_read_u32(np, "num-slots", &pdata->num_slots); 2954c91eab4bSThomas Abraham 2955c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 29560e3a22c0SShawn Lin dev_info(dev, 29570e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 2958c91eab4bSThomas Abraham 2959c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2960c91eab4bSThomas Abraham 29613c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 29623c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 29633c6d89eaSDoug Anderson 2964cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2965cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2966800d78bfSThomas Abraham if (ret) 2967800d78bfSThomas Abraham return ERR_PTR(ret); 2968800d78bfSThomas Abraham } 2969800d78bfSThomas Abraham 297040a7a463SJaehoon Chung if (of_find_property(np, "supports-highspeed", NULL)) { 297140a7a463SJaehoon Chung dev_info(dev, "supports-highspeed property is deprecated.\n"); 297210b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 297340a7a463SJaehoon Chung } 297410b49841SSeungwon Jeon 2975c91eab4bSThomas Abraham return pdata; 2976c91eab4bSThomas Abraham } 2977c91eab4bSThomas Abraham 2978c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2979c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2980c91eab4bSThomas Abraham { 2981c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2982c91eab4bSThomas Abraham } 2983c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2984c91eab4bSThomas Abraham 2985fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2986fa0c3283SDoug Anderson { 2987fa0c3283SDoug Anderson unsigned long irqflags; 2988fa0c3283SDoug Anderson u32 temp; 2989fa0c3283SDoug Anderson int i; 2990e8cc37b8SShawn Lin struct dw_mci_slot *slot; 2991fa0c3283SDoug Anderson 2992e8cc37b8SShawn Lin /* 2993e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 2994e8cc37b8SShawn Lin * as well as broken card detection is found. 2995e8cc37b8SShawn Lin */ 2996fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 2997e8cc37b8SShawn Lin slot = host->slot[i]; 2998e8cc37b8SShawn Lin if (slot->mmc->caps & MMC_CAP_NEEDS_POLL) 2999e8cc37b8SShawn Lin return; 3000fa0c3283SDoug Anderson 3001287980e4SArnd Bergmann if (mmc_gpio_get_cd(slot->mmc) < 0) 3002fa0c3283SDoug Anderson break; 3003fa0c3283SDoug Anderson } 3004fa0c3283SDoug Anderson if (i == host->num_slots) 3005fa0c3283SDoug Anderson return; 3006fa0c3283SDoug Anderson 3007fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 3008fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 3009fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 3010fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 3011fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 3012fa0c3283SDoug Anderson } 3013fa0c3283SDoug Anderson 301462ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 3015f95f3850SWill Newton { 3016e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 301762ca8034SShashidhar Hiremath int width, i, ret = 0; 3018f95f3850SWill Newton u32 fifo_size; 30191c2215b7SThomas Abraham int init_slots = 0; 3020f95f3850SWill Newton 3021c91eab4bSThomas Abraham if (!host->pdata) { 3022c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 3023d6786fefSGuodong Xu if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3024d6786fefSGuodong Xu return -EPROBE_DEFER; 3025d6786fefSGuodong Xu } else if (IS_ERR(host->pdata)) { 3026c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 3027c91eab4bSThomas Abraham return -EINVAL; 3028c91eab4bSThomas Abraham } 3029f95f3850SWill Newton } 3030f95f3850SWill Newton 3031780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 3032f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 3033f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 3034f90a0612SThomas Abraham } else { 3035f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 3036f90a0612SThomas Abraham if (ret) { 3037f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 3038f90a0612SThomas Abraham return ret; 3039f90a0612SThomas Abraham } 3040f95f3850SWill Newton } 3041f95f3850SWill Newton 3042780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3043f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 3044f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 30453c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 3046f90a0612SThomas Abraham } else { 3047f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 3048f90a0612SThomas Abraham if (ret) { 3049f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 3050f90a0612SThomas Abraham goto err_clk_biu; 3051f90a0612SThomas Abraham } 3052f90a0612SThomas Abraham 30533c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 30543c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 30553c6d89eaSDoug Anderson if (ret) 30563c6d89eaSDoug Anderson dev_warn(host->dev, 3057612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 30583c6d89eaSDoug Anderson host->pdata->bus_hz); 30593c6d89eaSDoug Anderson } 3060f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 30613c6d89eaSDoug Anderson } 3062f90a0612SThomas Abraham 3063612de4c1SJaehoon Chung if (!host->bus_hz) { 3064612de4c1SJaehoon Chung dev_err(host->dev, 3065612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3066612de4c1SJaehoon Chung ret = -ENODEV; 3067612de4c1SJaehoon Chung goto err_clk_ciu; 3068612de4c1SJaehoon Chung } 3069612de4c1SJaehoon Chung 3070002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3071002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3072002f0d5cSYuvaraj Kumar C D if (ret) { 3073002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3074002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3075002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3076002f0d5cSYuvaraj Kumar C D } 3077002f0d5cSYuvaraj Kumar C D } 3078002f0d5cSYuvaraj Kumar C D 3079d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) { 3080d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3081d6786fefSGuodong Xu usleep_range(10, 50); 3082d6786fefSGuodong Xu reset_control_deassert(host->pdata->rstc); 3083d6786fefSGuodong Xu } 3084d6786fefSGuodong Xu 30855c935165SDoug Anderson setup_timer(&host->cmd11_timer, 30865c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 30875c935165SDoug Anderson 308857e10486SAddy Ke setup_timer(&host->dto_timer, 308957e10486SAddy Ke dw_mci_dto_timer, (unsigned long)host); 309057e10486SAddy Ke 3091f95f3850SWill Newton spin_lock_init(&host->lock); 3092f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3093f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3094f95f3850SWill Newton 3095f95f3850SWill Newton /* 3096f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3097f95f3850SWill Newton * the correct values. 3098f95f3850SWill Newton */ 309970692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3100f95f3850SWill Newton if (!i) { 3101f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3102f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3103f95f3850SWill Newton width = 16; 3104f95f3850SWill Newton host->data_shift = 1; 3105f95f3850SWill Newton } else if (i == 2) { 3106f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3107f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3108f95f3850SWill Newton width = 64; 3109f95f3850SWill Newton host->data_shift = 3; 3110f95f3850SWill Newton } else { 3111f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3112f95f3850SWill Newton WARN((i != 1), 3113f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3114f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3115f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3116f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3117f95f3850SWill Newton width = 32; 3118f95f3850SWill Newton host->data_shift = 2; 3119f95f3850SWill Newton } 3120f95f3850SWill Newton 3121f95f3850SWill Newton /* Reset all blocks */ 31223744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 31233744415cSShawn Lin ret = -ENODEV; 31243744415cSShawn Lin goto err_clk_ciu; 31253744415cSShawn Lin } 3126141a712aSSeungwon Jeon 3127141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3128141a712aSSeungwon Jeon dw_mci_init_dma(host); 3129f95f3850SWill Newton 3130f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3131f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3132f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3133f95f3850SWill Newton 3134f95f3850SWill Newton /* Put in max timeout */ 3135f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3136f95f3850SWill Newton 3137f95f3850SWill Newton /* 3138f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3139f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3140f95f3850SWill Newton */ 3141b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3142b86d8253SJames Hogan /* 3143b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3144b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3145b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3146b86d8253SJames Hogan * should put it in the platform data. 3147b86d8253SJames Hogan */ 3148f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 31498234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3150b86d8253SJames Hogan } else { 3151b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3152b86d8253SJames Hogan } 3153b86d8253SJames Hogan host->fifo_depth = fifo_size; 315452426899SSeungwon Jeon host->fifoth_val = 315552426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3156e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3157f95f3850SWill Newton 3158f95f3850SWill Newton /* disable clock to CIU */ 3159f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3160f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3161f95f3850SWill Newton 316263008768SJames Hogan /* 316363008768SJames Hogan * In 2.40a spec, Data offset is changed. 316463008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 316563008768SJames Hogan */ 316663008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 316763008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 316863008768SJames Hogan 316963008768SJames Hogan if (host->verid < DW_MMC_240A) 317076184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 317163008768SJames Hogan else 317276184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 317363008768SJames Hogan 3174f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3175780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3176780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3177f95f3850SWill Newton if (ret) 31786130e7a9SDoug Anderson goto err_dmaunmap; 3179f95f3850SWill Newton 3180f95f3850SWill Newton if (host->pdata->num_slots) 3181f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 3182f95f3850SWill Newton else 31838a629d26SShawn Lin host->num_slots = 1; 31848a629d26SShawn Lin 31858a629d26SShawn Lin if (host->num_slots < 1 || 31868a629d26SShawn Lin host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) { 31878a629d26SShawn Lin dev_err(host->dev, 31888a629d26SShawn Lin "Platform data must supply correct num_slots.\n"); 31898a629d26SShawn Lin ret = -ENODEV; 31908a629d26SShawn Lin goto err_clk_ciu; 31918a629d26SShawn Lin } 3192f95f3850SWill Newton 31932da1d7f2SYuvaraj CD /* 3194fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 31952da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 31962da1d7f2SYuvaraj CD */ 31972da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 31982da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3199fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 32000e3a22c0SShawn Lin /* Enable mci interrupt */ 32010e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 32022da1d7f2SYuvaraj CD 32030e3a22c0SShawn Lin dev_info(host->dev, 32040e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 32052da1d7f2SYuvaraj CD host->irq, width, fifo_size); 32062da1d7f2SYuvaraj CD 3207f95f3850SWill Newton /* We need at least one slot to succeed */ 3208f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3209f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 32101c2215b7SThomas Abraham if (ret) 32111c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 32121c2215b7SThomas Abraham else 32131c2215b7SThomas Abraham init_slots++; 3214f95f3850SWill Newton } 32151c2215b7SThomas Abraham 32161c2215b7SThomas Abraham if (init_slots) { 32171c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 32181c2215b7SThomas Abraham } else { 32190e3a22c0SShawn Lin dev_dbg(host->dev, 32200e3a22c0SShawn Lin "attempted to initialize %d slots, but failed on all\n", 32210e3a22c0SShawn Lin host->num_slots); 32226130e7a9SDoug Anderson goto err_dmaunmap; 3223f95f3850SWill Newton } 3224f95f3850SWill Newton 3225b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3226b793f658SDoug Anderson dw_mci_enable_cd(host); 3227b793f658SDoug Anderson 3228f95f3850SWill Newton return 0; 3229f95f3850SWill Newton 3230f95f3850SWill Newton err_dmaunmap: 3231f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3232f95f3850SWill Newton host->dma_ops->exit(host); 3233f90a0612SThomas Abraham 3234d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3235d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3236d6786fefSGuodong Xu 3237f90a0612SThomas Abraham err_clk_ciu: 3238f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3239780f22afSSeungwon Jeon 3240f90a0612SThomas Abraham err_clk_biu: 3241f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3242780f22afSSeungwon Jeon 3243f95f3850SWill Newton return ret; 3244f95f3850SWill Newton } 324562ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3246f95f3850SWill Newton 324762ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3248f95f3850SWill Newton { 3249f95f3850SWill Newton int i; 3250f95f3850SWill Newton 3251f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 32524a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 3253f95f3850SWill Newton if (host->slot[i]) 3254f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 3255f95f3850SWill Newton } 3256f95f3850SWill Newton 3257048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3258048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3259048fd7e6SPrabu Thangamuthu 3260f95f3850SWill Newton /* disable clock to CIU */ 3261f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3262f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3263f95f3850SWill Newton 3264f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3265f95f3850SWill Newton host->dma_ops->exit(host); 3266f95f3850SWill Newton 3267d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3268d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3269d6786fefSGuodong Xu 3270f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3271f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3272f95f3850SWill Newton } 327362ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 327462ca8034SShashidhar Hiremath 327562ca8034SShashidhar Hiremath 3276f95f3850SWill Newton 32776fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 3278f95f3850SWill Newton /* 3279f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 3280f95f3850SWill Newton */ 328162ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 3282f95f3850SWill Newton { 32833fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 32843fc7eaefSShawn Lin host->dma_ops->exit(host); 32853fc7eaefSShawn Lin 3286f95f3850SWill Newton return 0; 3287f95f3850SWill Newton } 328862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 3289f95f3850SWill Newton 329062ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 3291f95f3850SWill Newton { 3292f95f3850SWill Newton int i, ret; 3293f95f3850SWill Newton 32943a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3295e61cf118SJaehoon Chung ret = -ENODEV; 3296e61cf118SJaehoon Chung return ret; 3297e61cf118SJaehoon Chung } 3298e61cf118SJaehoon Chung 32993bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3300141a712aSSeungwon Jeon host->dma_ops->init(host); 3301141a712aSSeungwon Jeon 330252426899SSeungwon Jeon /* 330352426899SSeungwon Jeon * Restore the initial value at FIFOTH register 330452426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 330552426899SSeungwon Jeon */ 3306e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 330752426899SSeungwon Jeon host->prev_blksz = 0; 3308e61cf118SJaehoon Chung 33092eb2944fSDoug Anderson /* Put in max timeout */ 33102eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 33112eb2944fSDoug Anderson 3312e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3313e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3314e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3315fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3316e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3317e61cf118SJaehoon Chung 3318f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3319f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 33200e3a22c0SShawn Lin 3321f95f3850SWill Newton if (!slot) 3322f95f3850SWill Newton continue; 3323ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 3324ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3325ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 3326ab269128SAbhilash Kesavan } 3327f95f3850SWill Newton } 3328fa0c3283SDoug Anderson 3329fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3330fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3331fa0c3283SDoug Anderson 3332f95f3850SWill Newton return 0; 3333f95f3850SWill Newton } 333462ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 33356fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 33366fe8890dSJaehoon Chung 3337f95f3850SWill Newton static int __init dw_mci_init(void) 3338f95f3850SWill Newton { 33398e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 334062ca8034SShashidhar Hiremath return 0; 3341f95f3850SWill Newton } 3342f95f3850SWill Newton 3343f95f3850SWill Newton static void __exit dw_mci_exit(void) 3344f95f3850SWill Newton { 3345f95f3850SWill Newton } 3346f95f3850SWill Newton 3347f95f3850SWill Newton module_init(dw_mci_init); 3348f95f3850SWill Newton module_exit(dw_mci_exit); 3349f95f3850SWill Newton 3350f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3351f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3352f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3353f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3354