12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2f95f3850SWill Newton /* 3f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 4f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 5f95f3850SWill Newton * 6f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 7f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8f95f3850SWill Newton */ 9f95f3850SWill Newton 10f95f3850SWill Newton #include <linux/blkdev.h> 11f95f3850SWill Newton #include <linux/clk.h> 12f95f3850SWill Newton #include <linux/debugfs.h> 13f95f3850SWill Newton #include <linux/device.h> 14f95f3850SWill Newton #include <linux/dma-mapping.h> 15f95f3850SWill Newton #include <linux/err.h> 16f95f3850SWill Newton #include <linux/init.h> 17f95f3850SWill Newton #include <linux/interrupt.h> 18b6d2d81cSShawn Lin #include <linux/iopoll.h> 19f95f3850SWill Newton #include <linux/ioport.h> 202b8ac062SVincent Whitchurch #include <linux/ktime.h> 21f95f3850SWill Newton #include <linux/module.h> 22f95f3850SWill Newton #include <linux/platform_device.h> 23a6db2c86SDouglas Anderson #include <linux/pm_runtime.h> 242b8ac062SVincent Whitchurch #include <linux/prandom.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/bitops.h> 36c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 37c91eab4bSThomas Abraham #include <linux/of.h> 3855a6ceb2SDoug Anderson #include <linux/of_gpio.h> 39bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 40f95f3850SWill Newton 41f95f3850SWill Newton #include "dw_mmc.h" 42f95f3850SWill Newton 43f95f3850SWill Newton /* Common flag combinations */ 443f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 45f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 467a3c5677SDoug Anderson SDMMC_INT_EBE | SDMMC_INT_HLE) 47f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 487a3c5677SDoug Anderson SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 49f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 507a3c5677SDoug Anderson DW_MCI_CMD_ERROR_FLAGS) 51f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 52f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 53f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 54f95f3850SWill Newton 551f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 5672e83577SJaehoon Chung #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon 58fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 59fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 60fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 62fc79a4d6SJoonyoung Shim 63cc190d4cSShawn Lin #define DESC_RING_BUF_SZ PAGE_SIZE 64cc190d4cSShawn Lin 6569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6669d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 67b6d2d81cSShawn Lin #define IDMAC_OWN_CLR64(x) \ 68b6d2d81cSShawn Lin !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 6969d99fdcSPrabu Thangamuthu 7069d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 7169d99fdcSPrabu Thangamuthu 7269d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7369d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 746687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 756687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7669d99fdcSPrabu Thangamuthu 7769d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 8069d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 8169d99fdcSPrabu Thangamuthu 8269d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8369d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8469d99fdcSPrabu Thangamuthu }; 8569d99fdcSPrabu Thangamuthu 86f95f3850SWill Newton struct idmac_desc { 876687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 88f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 89f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 90f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 91f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 92f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 93f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 94f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 95f95f3850SWill Newton 966687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 97f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 98e5306c3aSBen Dooks ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 99f95f3850SWill Newton 1006687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 101f95f3850SWill Newton 1026687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 103f95f3850SWill Newton }; 1045959b32eSAlexey Brodkin 1055959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1065959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 107f95f3850SWill Newton 108f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 109f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 110f95f3850SWill Newton { 111f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 112f95f3850SWill Newton struct mmc_request *mrq; 113f95f3850SWill Newton struct mmc_command *cmd; 114f95f3850SWill Newton struct mmc_command *stop; 115f95f3850SWill Newton struct mmc_data *data; 116f95f3850SWill Newton 117f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 118f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 119f95f3850SWill Newton mrq = slot->mrq; 120f95f3850SWill Newton 121f95f3850SWill Newton if (mrq) { 122f95f3850SWill Newton cmd = mrq->cmd; 123f95f3850SWill Newton data = mrq->data; 124f95f3850SWill Newton stop = mrq->stop; 125f95f3850SWill Newton 126f95f3850SWill Newton if (cmd) 127f95f3850SWill Newton seq_printf(s, 128f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 129f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 130f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 131f95f3850SWill Newton cmd->resp[2], cmd->error); 132f95f3850SWill Newton if (data) 133f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 134f95f3850SWill Newton data->bytes_xfered, data->blocks, 135f95f3850SWill Newton data->blksz, data->flags, data->error); 136f95f3850SWill Newton if (stop) 137f95f3850SWill Newton seq_printf(s, 138f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 139f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 140f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 141f95f3850SWill Newton stop->resp[2], stop->error); 142f95f3850SWill Newton } 143f95f3850SWill Newton 144f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 145f95f3850SWill Newton 146f95f3850SWill Newton return 0; 147f95f3850SWill Newton } 14864c1412bSShawn Lin DEFINE_SHOW_ATTRIBUTE(dw_mci_req); 149f95f3850SWill Newton 150f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 151f95f3850SWill Newton { 15221657ebdSJaehoon Chung struct dw_mci *host = s->private; 15321657ebdSJaehoon Chung 1545b43df8bSShawn Lin pm_runtime_get_sync(host->dev); 1555b43df8bSShawn Lin 15621657ebdSJaehoon Chung seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 15721657ebdSJaehoon Chung seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 15821657ebdSJaehoon Chung seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 15921657ebdSJaehoon Chung seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 16021657ebdSJaehoon Chung seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 16121657ebdSJaehoon Chung seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 162f95f3850SWill Newton 1635b43df8bSShawn Lin pm_runtime_put_autosuspend(host->dev); 1645b43df8bSShawn Lin 165f95f3850SWill Newton return 0; 166f95f3850SWill Newton } 16764c1412bSShawn Lin DEFINE_SHOW_ATTRIBUTE(dw_mci_regs); 168f95f3850SWill Newton 169f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 170f95f3850SWill Newton { 171f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 172f95f3850SWill Newton struct dw_mci *host = slot->host; 173f95f3850SWill Newton struct dentry *root; 174f95f3850SWill Newton 175f95f3850SWill Newton root = mmc->debugfs_root; 176f95f3850SWill Newton if (!root) 177f95f3850SWill Newton return; 178f95f3850SWill Newton 179fcac1527SGreg Kroah-Hartman debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops); 180fcac1527SGreg Kroah-Hartman debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops); 181118e1118SGeert Uytterhoeven debugfs_create_u32("state", S_IRUSR, root, &host->state); 1820c40c1beSGeert Uytterhoeven debugfs_create_xul("pending_events", S_IRUSR, root, 1830c40c1beSGeert Uytterhoeven &host->pending_events); 1840c40c1beSGeert Uytterhoeven debugfs_create_xul("completed_events", S_IRUSR, root, 1850c40c1beSGeert Uytterhoeven &host->completed_events); 1862b8ac062SVincent Whitchurch #ifdef CONFIG_FAULT_INJECTION 1872b8ac062SVincent Whitchurch fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc); 1882b8ac062SVincent Whitchurch #endif 189f95f3850SWill Newton } 190f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 191f95f3850SWill Newton 1928e6db1f6SShawn Lin static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 1938e6db1f6SShawn Lin { 1948e6db1f6SShawn Lin u32 ctrl; 1958e6db1f6SShawn Lin 1968e6db1f6SShawn Lin ctrl = mci_readl(host, CTRL); 1978e6db1f6SShawn Lin ctrl |= reset; 1988e6db1f6SShawn Lin mci_writel(host, CTRL, ctrl); 1998e6db1f6SShawn Lin 2008e6db1f6SShawn Lin /* wait till resets clear */ 2018e6db1f6SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 2028e6db1f6SShawn Lin !(ctrl & reset), 2038e6db1f6SShawn Lin 1, 500 * USEC_PER_MSEC)) { 2048e6db1f6SShawn Lin dev_err(host->dev, 2058e6db1f6SShawn Lin "Timeout resetting block (ctrl reset %#x)\n", 2068e6db1f6SShawn Lin ctrl & reset); 2078e6db1f6SShawn Lin return false; 2088e6db1f6SShawn Lin } 2098e6db1f6SShawn Lin 2108e6db1f6SShawn Lin return true; 2118e6db1f6SShawn Lin } 21201730558SDoug Anderson 2134dba18deSShawn Lin static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 2144dba18deSShawn Lin { 2154dba18deSShawn Lin u32 status; 2164dba18deSShawn Lin 2174dba18deSShawn Lin /* 2184dba18deSShawn Lin * Databook says that before issuing a new data transfer command 2194dba18deSShawn Lin * we need to check to see if the card is busy. Data transfer commands 2204dba18deSShawn Lin * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 2214dba18deSShawn Lin * 2224dba18deSShawn Lin * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 2234dba18deSShawn Lin * expected. 2244dba18deSShawn Lin */ 2254dba18deSShawn Lin if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 2264dba18deSShawn Lin !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 2274dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 2284dba18deSShawn Lin status, 2294dba18deSShawn Lin !(status & SDMMC_STATUS_BUSY), 2304dba18deSShawn Lin 10, 500 * USEC_PER_MSEC)) 2314dba18deSShawn Lin dev_err(host->dev, "Busy; trying anyway\n"); 2324dba18deSShawn Lin } 2334dba18deSShawn Lin } 2344dba18deSShawn Lin 2354dba18deSShawn Lin static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 2364dba18deSShawn Lin { 2374dba18deSShawn Lin struct dw_mci *host = slot->host; 2384dba18deSShawn Lin unsigned int cmd_status = 0; 2394dba18deSShawn Lin 2404dba18deSShawn Lin mci_writel(host, CMDARG, arg); 2414dba18deSShawn Lin wmb(); /* drain writebuffer */ 2424dba18deSShawn Lin dw_mci_wait_while_busy(host, cmd); 2434dba18deSShawn Lin mci_writel(host, CMD, SDMMC_CMD_START | cmd); 2444dba18deSShawn Lin 2454dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 2464dba18deSShawn Lin !(cmd_status & SDMMC_CMD_START), 2474dba18deSShawn Lin 1, 500 * USEC_PER_MSEC)) 2484dba18deSShawn Lin dev_err(&slot->mmc->class_dev, 2494dba18deSShawn Lin "Timeout sending command (cmd %#x arg %#x status %#x)\n", 2504dba18deSShawn Lin cmd, arg, cmd_status); 2514dba18deSShawn Lin } 2524dba18deSShawn Lin 253f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 254f95f3850SWill Newton { 255800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 25601730558SDoug Anderson struct dw_mci *host = slot->host; 257f95f3850SWill Newton u32 cmdr; 258f95f3850SWill Newton 2590e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 260f95f3850SWill Newton cmdr = cmd->opcode; 261f95f3850SWill Newton 26290c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 26390c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 26490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 26590c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 26690c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 267f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2684a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 269f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 270f95f3850SWill Newton 27101730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 27201730558SDoug Anderson u32 clk_en_a; 27301730558SDoug Anderson 27401730558SDoug Anderson /* Special bit makes CMD11 not die */ 27501730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 27601730558SDoug Anderson 27701730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 27801730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 27901730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 28001730558SDoug Anderson 28101730558SDoug Anderson /* 28201730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 28301730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 28401730558SDoug Anderson * since stopping the clock is a specific part of the UHS 28501730558SDoug Anderson * voltage change dance. 28601730558SDoug Anderson * 28701730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 28801730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 28901730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 29001730558SDoug Anderson * until the voltage change is all done. 29101730558SDoug Anderson */ 29201730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 29301730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 29401730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 29501730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 29601730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 29701730558SDoug Anderson } 29801730558SDoug Anderson 299f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 300f95f3850SWill Newton /* We expect a response, so set this bit */ 301f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 302f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 303f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 304f95f3850SWill Newton } 305f95f3850SWill Newton 306f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 307f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 308f95f3850SWill Newton 3090349c085SJaehoon Chung if (cmd->data) { 310f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 3110349c085SJaehoon Chung if (cmd->data->flags & MMC_DATA_WRITE) 312f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 313f95f3850SWill Newton } 314f95f3850SWill Newton 315aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 316aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 317800d78bfSThomas Abraham 318f95f3850SWill Newton return cmdr; 319f95f3850SWill Newton } 320f95f3850SWill Newton 32190c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 32290c2143aSSeungwon Jeon { 32390c2143aSSeungwon Jeon struct mmc_command *stop; 32490c2143aSSeungwon Jeon u32 cmdr; 32590c2143aSSeungwon Jeon 32690c2143aSSeungwon Jeon if (!cmd->data) 32790c2143aSSeungwon Jeon return 0; 32890c2143aSSeungwon Jeon 32990c2143aSSeungwon Jeon stop = &host->stop_abort; 33090c2143aSSeungwon Jeon cmdr = cmd->opcode; 33190c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 33290c2143aSSeungwon Jeon 33390c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 33490c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 33590c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3366c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3376c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3386c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 33990c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 34090c2143aSSeungwon Jeon stop->arg = 0; 34190c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 34290c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 34390c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 34490c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 34590c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 34690c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 34790c2143aSSeungwon Jeon } else { 34890c2143aSSeungwon Jeon return 0; 34990c2143aSSeungwon Jeon } 35090c2143aSSeungwon Jeon 35190c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 35290c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 35390c2143aSSeungwon Jeon 35442f989c0SJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 3558c005b40SJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 3568c005b40SJaehoon Chung 35790c2143aSSeungwon Jeon return cmdr; 35890c2143aSSeungwon Jeon } 35990c2143aSSeungwon Jeon 36003de1921SAddy Ke static inline void dw_mci_set_cto(struct dw_mci *host) 36103de1921SAddy Ke { 36203de1921SAddy Ke unsigned int cto_clks; 3634c2357f5SDouglas Anderson unsigned int cto_div; 36403de1921SAddy Ke unsigned int cto_ms; 3658892b705SDouglas Anderson unsigned long irqflags; 36603de1921SAddy Ke 36703de1921SAddy Ke cto_clks = mci_readl(host, TMOUT) & 0xff; 3684c2357f5SDouglas Anderson cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 3694c2357f5SDouglas Anderson if (cto_div == 0) 3704c2357f5SDouglas Anderson cto_div = 1; 371c7151602SEvgeniy Didin 372c7151602SEvgeniy Didin cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 373c7151602SEvgeniy Didin host->bus_hz); 37403de1921SAddy Ke 37503de1921SAddy Ke /* add a bit spare time */ 37603de1921SAddy Ke cto_ms += 10; 37703de1921SAddy Ke 3788892b705SDouglas Anderson /* 3798892b705SDouglas Anderson * The durations we're working with are fairly short so we have to be 3808892b705SDouglas Anderson * extra careful about synchronization here. Specifically in hardware a 3818892b705SDouglas Anderson * command timeout is _at most_ 5.1 ms, so that means we expect an 3828892b705SDouglas Anderson * interrupt (either command done or timeout) to come rather quickly 3838892b705SDouglas Anderson * after the mci_writel. ...but just in case we have a long interrupt 3848892b705SDouglas Anderson * latency let's add a bit of paranoia. 3858892b705SDouglas Anderson * 3868892b705SDouglas Anderson * In general we'll assume that at least an interrupt will be asserted 3878892b705SDouglas Anderson * in hardware by the time the cto_timer runs. ...and if it hasn't 3888892b705SDouglas Anderson * been asserted in hardware by that time then we'll assume it'll never 3898892b705SDouglas Anderson * come. 3908892b705SDouglas Anderson */ 3918892b705SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 3928892b705SDouglas Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 39303de1921SAddy Ke mod_timer(&host->cto_timer, 39403de1921SAddy Ke jiffies + msecs_to_jiffies(cto_ms) + 1); 3958892b705SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 39603de1921SAddy Ke } 39703de1921SAddy Ke 398f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 399f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 400f95f3850SWill Newton { 401f95f3850SWill Newton host->cmd = cmd; 4024a90920cSThomas Abraham dev_vdbg(host->dev, 403f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 404f95f3850SWill Newton cmd->arg, cmd_flags); 405f95f3850SWill Newton 406f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 4070e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 4080bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 409f95f3850SWill Newton 4108892b705SDouglas Anderson mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 4118892b705SDouglas Anderson 41203de1921SAddy Ke /* response expected command only */ 41303de1921SAddy Ke if (cmd_flags & SDMMC_CMD_RESP_EXP) 41403de1921SAddy Ke dw_mci_set_cto(host); 415f95f3850SWill Newton } 416f95f3850SWill Newton 41790c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 418f95f3850SWill Newton { 419e13c3c08SJaehoon Chung struct mmc_command *stop = &host->stop_abort; 4200e3a22c0SShawn Lin 42190c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 422f95f3850SWill Newton } 423f95f3850SWill Newton 424f95f3850SWill Newton /* DMA interface functions */ 425f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 426f95f3850SWill Newton { 42703e8cb53SJames Hogan if (host->using_dma) { 428f95f3850SWill Newton host->dma_ops->stop(host); 429f95f3850SWill Newton host->dma_ops->cleanup(host); 430aa50f259SSeungwon Jeon } 431aa50f259SSeungwon Jeon 432f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 433f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 434f95f3850SWill Newton } 435f95f3850SWill Newton 436f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 437f95f3850SWill Newton { 438f95f3850SWill Newton struct mmc_data *data = host->data; 439f95f3850SWill Newton 440a4cc7eb4SJaehoon Chung if (data && data->host_cookie == COOKIE_MAPPED) { 4414a90920cSThomas Abraham dma_unmap_sg(host->dev, 4429aa51408SSeungwon Jeon data->sg, 4439aa51408SSeungwon Jeon data->sg_len, 444feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 445a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 446a4cc7eb4SJaehoon Chung } 447f95f3850SWill Newton } 448f95f3850SWill Newton 4495ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4505ce9d961SSeungwon Jeon { 4515ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4525ce9d961SSeungwon Jeon /* Software reset of DMA */ 4535ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4545ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4555ce9d961SSeungwon Jeon } 4565ce9d961SSeungwon Jeon 457f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 458f95f3850SWill Newton { 459f95f3850SWill Newton u32 temp; 460f95f3850SWill Newton 461f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 462f95f3850SWill Newton temp = mci_readl(host, CTRL); 463f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 464f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 465f95f3850SWill Newton mci_writel(host, CTRL, temp); 466f95f3850SWill Newton 467f95f3850SWill Newton /* Stop the IDMAC running */ 468f95f3850SWill Newton temp = mci_readl(host, BMOD); 469a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4705ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 471f95f3850SWill Newton mci_writel(host, BMOD, temp); 472f95f3850SWill Newton } 473f95f3850SWill Newton 4743fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 475f95f3850SWill Newton { 4763fc7eaefSShawn Lin struct dw_mci *host = arg; 477f95f3850SWill Newton struct mmc_data *data = host->data; 478f95f3850SWill Newton 4794a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 480f95f3850SWill Newton 4813fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 4823fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 4833fc7eaefSShawn Lin /* Invalidate cache after read */ 48442f989c0SJaehoon Chung dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 4853fc7eaefSShawn Lin data->sg, 4863fc7eaefSShawn Lin data->sg_len, 4873fc7eaefSShawn Lin DMA_FROM_DEVICE); 4883fc7eaefSShawn Lin 489f95f3850SWill Newton host->dma_ops->cleanup(host); 490f95f3850SWill Newton 491f95f3850SWill Newton /* 492f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 493f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 494f95f3850SWill Newton */ 495f95f3850SWill Newton if (data) { 496f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 497f95f3850SWill Newton tasklet_schedule(&host->tasklet); 498f95f3850SWill Newton } 499f95f3850SWill Newton } 500f95f3850SWill Newton 501f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 502f95f3850SWill Newton { 503897b69e7SSeungwon Jeon int i; 504f95f3850SWill Newton 50569d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 50669d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 50769d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 508cc190d4cSShawn Lin host->ring_size = 509cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 51069d99fdcSPrabu Thangamuthu 51169d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 51269d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 51369d99fdcSPrabu Thangamuthu i++, p++) { 51469d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 51569d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 51669d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 51769d99fdcSPrabu Thangamuthu 51869d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 51969d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 52069d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 52169d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 52247b7de2fSEvgeniy Didin p->des0 = 0; 52369d99fdcSPrabu Thangamuthu p->des1 = 0; 52469d99fdcSPrabu Thangamuthu p->des2 = 0; 52569d99fdcSPrabu Thangamuthu p->des3 = 0; 52669d99fdcSPrabu Thangamuthu } 52769d99fdcSPrabu Thangamuthu 52869d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 52969d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 53069d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 53169d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 53269d99fdcSPrabu Thangamuthu 53369d99fdcSPrabu Thangamuthu } else { 53469d99fdcSPrabu Thangamuthu struct idmac_desc *p; 535f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 536cc190d4cSShawn Lin host->ring_size = 537cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 538f95f3850SWill Newton 539f95f3850SWill Newton /* Forward link the descriptor list */ 5400e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 5410e3a22c0SShawn Lin i < host->ring_size - 1; 5420e3a22c0SShawn Lin i++, p++) { 5436687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 5446687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 54547b7de2fSEvgeniy Didin p->des0 = 0; 5464b244724SZhangfei Gao p->des1 = 0; 5474b244724SZhangfei Gao } 548f95f3850SWill Newton 549f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 5506687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 5516687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 55269d99fdcSPrabu Thangamuthu } 553f95f3850SWill Newton 5545ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 555141a712aSSeungwon Jeon 55669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 55769d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 55869d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 55969d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 56069d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 56169d99fdcSPrabu Thangamuthu 56269d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 56369d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 56469d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 56569d99fdcSPrabu Thangamuthu 56669d99fdcSPrabu Thangamuthu } else { 567f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 568fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 56969d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 57069d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 571f95f3850SWill Newton 572f95f3850SWill Newton /* Set the descriptor base address */ 573f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 57469d99fdcSPrabu Thangamuthu } 57569d99fdcSPrabu Thangamuthu 576f95f3850SWill Newton return 0; 577f95f3850SWill Newton } 578f95f3850SWill Newton 5793b2a067bSShawn Lin static inline int dw_mci_prepare_desc64(struct dw_mci *host, 5803b2a067bSShawn Lin struct mmc_data *data, 5813b2a067bSShawn Lin unsigned int sg_len) 5823b2a067bSShawn Lin { 5833b2a067bSShawn Lin unsigned int desc_len; 5843b2a067bSShawn Lin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 585b6d2d81cSShawn Lin u32 val; 5863b2a067bSShawn Lin int i; 5873b2a067bSShawn Lin 5883b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 5893b2a067bSShawn Lin 5903b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 5913b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 5923b2a067bSShawn Lin 5933b2a067bSShawn Lin u64 mem_addr = sg_dma_address(&data->sg[i]); 5943b2a067bSShawn Lin 5953b2a067bSShawn Lin for ( ; length ; desc++) { 5963b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 5973b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 5983b2a067bSShawn Lin 5993b2a067bSShawn Lin length -= desc_len; 6003b2a067bSShawn Lin 6013b2a067bSShawn Lin /* 6023b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6033b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6043b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6053b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6063b2a067bSShawn Lin */ 607b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 608b6d2d81cSShawn Lin !(val & IDMAC_DES0_OWN), 609b6d2d81cSShawn Lin 10, 100 * USEC_PER_MSEC)) 6103b2a067bSShawn Lin goto err_own_bit; 6113b2a067bSShawn Lin 6123b2a067bSShawn Lin /* 6133b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6143b2a067bSShawn Lin * for this descriptor 6153b2a067bSShawn Lin */ 6163b2a067bSShawn Lin desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 6173b2a067bSShawn Lin IDMAC_DES0_CH; 6183b2a067bSShawn Lin 6193b2a067bSShawn Lin /* Buffer length */ 6203b2a067bSShawn Lin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 6213b2a067bSShawn Lin 6223b2a067bSShawn Lin /* Physical address to DMA to/from */ 6233b2a067bSShawn Lin desc->des4 = mem_addr & 0xffffffff; 6243b2a067bSShawn Lin desc->des5 = mem_addr >> 32; 6253b2a067bSShawn Lin 6263b2a067bSShawn Lin /* Update physical address for the next desc */ 6273b2a067bSShawn Lin mem_addr += desc_len; 6283b2a067bSShawn Lin 6293b2a067bSShawn Lin /* Save pointer to the last descriptor */ 6303b2a067bSShawn Lin desc_last = desc; 6313b2a067bSShawn Lin } 6323b2a067bSShawn Lin } 6333b2a067bSShawn Lin 6343b2a067bSShawn Lin /* Set first descriptor */ 6353b2a067bSShawn Lin desc_first->des0 |= IDMAC_DES0_FD; 6363b2a067bSShawn Lin 6373b2a067bSShawn Lin /* Set last descriptor */ 6383b2a067bSShawn Lin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 6393b2a067bSShawn Lin desc_last->des0 |= IDMAC_DES0_LD; 6403b2a067bSShawn Lin 6413b2a067bSShawn Lin return 0; 6423b2a067bSShawn Lin err_own_bit: 6433b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 64426be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 645cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 6463b2a067bSShawn Lin dw_mci_idmac_init(host); 6473b2a067bSShawn Lin return -EINVAL; 6483b2a067bSShawn Lin } 6493b2a067bSShawn Lin 6503b2a067bSShawn Lin 6513b2a067bSShawn Lin static inline int dw_mci_prepare_desc32(struct dw_mci *host, 6523b2a067bSShawn Lin struct mmc_data *data, 6533b2a067bSShawn Lin unsigned int sg_len) 6543b2a067bSShawn Lin { 6553b2a067bSShawn Lin unsigned int desc_len; 6563b2a067bSShawn Lin struct idmac_desc *desc_first, *desc_last, *desc; 657b6d2d81cSShawn Lin u32 val; 6583b2a067bSShawn Lin int i; 6593b2a067bSShawn Lin 6603b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6613b2a067bSShawn Lin 6623b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6633b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6643b2a067bSShawn Lin 6653b2a067bSShawn Lin u32 mem_addr = sg_dma_address(&data->sg[i]); 6663b2a067bSShawn Lin 6673b2a067bSShawn Lin for ( ; length ; desc++) { 6683b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6693b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6703b2a067bSShawn Lin 6713b2a067bSShawn Lin length -= desc_len; 6723b2a067bSShawn Lin 6733b2a067bSShawn Lin /* 6743b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6753b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6763b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6773b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6783b2a067bSShawn Lin */ 679b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 680b6d2d81cSShawn Lin IDMAC_OWN_CLR64(val), 681b6d2d81cSShawn Lin 10, 682b6d2d81cSShawn Lin 100 * USEC_PER_MSEC)) 6833b2a067bSShawn Lin goto err_own_bit; 6843b2a067bSShawn Lin 6853b2a067bSShawn Lin /* 6863b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6873b2a067bSShawn Lin * for this descriptor 6883b2a067bSShawn Lin */ 6893b2a067bSShawn Lin desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 6903b2a067bSShawn Lin IDMAC_DES0_DIC | 6913b2a067bSShawn Lin IDMAC_DES0_CH); 6923b2a067bSShawn Lin 6933b2a067bSShawn Lin /* Buffer length */ 6943b2a067bSShawn Lin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 6953b2a067bSShawn Lin 6963b2a067bSShawn Lin /* Physical address to DMA to/from */ 6973b2a067bSShawn Lin desc->des2 = cpu_to_le32(mem_addr); 6983b2a067bSShawn Lin 6993b2a067bSShawn Lin /* Update physical address for the next desc */ 7003b2a067bSShawn Lin mem_addr += desc_len; 7013b2a067bSShawn Lin 7023b2a067bSShawn Lin /* Save pointer to the last descriptor */ 7033b2a067bSShawn Lin desc_last = desc; 7043b2a067bSShawn Lin } 7053b2a067bSShawn Lin } 7063b2a067bSShawn Lin 7073b2a067bSShawn Lin /* Set first descriptor */ 7083b2a067bSShawn Lin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 7093b2a067bSShawn Lin 7103b2a067bSShawn Lin /* Set last descriptor */ 7113b2a067bSShawn Lin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 7123b2a067bSShawn Lin IDMAC_DES0_DIC)); 7133b2a067bSShawn Lin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 7143b2a067bSShawn Lin 7153b2a067bSShawn Lin return 0; 7163b2a067bSShawn Lin err_own_bit: 7173b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 71826be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 719cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 7203b2a067bSShawn Lin dw_mci_idmac_init(host); 7213b2a067bSShawn Lin return -EINVAL; 7223b2a067bSShawn Lin } 7233b2a067bSShawn Lin 7243b2a067bSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 7253b2a067bSShawn Lin { 7263b2a067bSShawn Lin u32 temp; 7273b2a067bSShawn Lin int ret; 7283b2a067bSShawn Lin 7293b2a067bSShawn Lin if (host->dma_64bit_address == 1) 7303b2a067bSShawn Lin ret = dw_mci_prepare_desc64(host, host->data, sg_len); 7313b2a067bSShawn Lin else 7323b2a067bSShawn Lin ret = dw_mci_prepare_desc32(host, host->data, sg_len); 7333b2a067bSShawn Lin 7343b2a067bSShawn Lin if (ret) 7353b2a067bSShawn Lin goto out; 7363b2a067bSShawn Lin 7373b2a067bSShawn Lin /* drain writebuffer */ 7383b2a067bSShawn Lin wmb(); 7393b2a067bSShawn Lin 7403b2a067bSShawn Lin /* Make sure to reset DMA in case we did PIO before this */ 7413b2a067bSShawn Lin dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 7423b2a067bSShawn Lin dw_mci_idmac_reset(host); 7433b2a067bSShawn Lin 7443b2a067bSShawn Lin /* Select IDMAC interface */ 7453b2a067bSShawn Lin temp = mci_readl(host, CTRL); 7463b2a067bSShawn Lin temp |= SDMMC_CTRL_USE_IDMAC; 7473b2a067bSShawn Lin mci_writel(host, CTRL, temp); 7483b2a067bSShawn Lin 7493b2a067bSShawn Lin /* drain writebuffer */ 7503b2a067bSShawn Lin wmb(); 7513b2a067bSShawn Lin 7523b2a067bSShawn Lin /* Enable the IDMAC */ 7533b2a067bSShawn Lin temp = mci_readl(host, BMOD); 7543b2a067bSShawn Lin temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 7553b2a067bSShawn Lin mci_writel(host, BMOD, temp); 7563b2a067bSShawn Lin 7573b2a067bSShawn Lin /* Start it running */ 7583b2a067bSShawn Lin mci_writel(host, PLDMND, 1); 7593b2a067bSShawn Lin 7603b2a067bSShawn Lin out: 7613b2a067bSShawn Lin return ret; 7623b2a067bSShawn Lin } 7633b2a067bSShawn Lin 7648e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 765885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 766885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 767885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 7683fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 769885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 770885c3e80SSeungwon Jeon }; 7713fc7eaefSShawn Lin 7723fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 7733fc7eaefSShawn Lin { 774ab925a31SShawn Lin dmaengine_terminate_async(host->dms->ch); 7753fc7eaefSShawn Lin } 7763fc7eaefSShawn Lin 7773fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 7783fc7eaefSShawn Lin unsigned int sg_len) 7793fc7eaefSShawn Lin { 7803fc7eaefSShawn Lin struct dma_slave_config cfg; 7813fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 7823fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 78327d70d36SColin Ian King static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 7843fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 7853fc7eaefSShawn Lin u32 fifoth_val; 7863fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 7873fc7eaefSShawn Lin int ret = 0; 7883fc7eaefSShawn Lin 7893fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 790*c3ff0189STony Lindgren memset(&cfg, 0, sizeof(cfg)); 791260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 7923fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 7933fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7943fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7953fc7eaefSShawn Lin 7963fc7eaefSShawn Lin /* Match burst msize with external dma config */ 7973fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 7983fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 7993fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 8003fc7eaefSShawn Lin 8013fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 8023fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 8033fc7eaefSShawn Lin else 8043fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 8053fc7eaefSShawn Lin 8063fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 8073fc7eaefSShawn Lin if (ret) { 8083fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 8093fc7eaefSShawn Lin return -EBUSY; 8103fc7eaefSShawn Lin } 8113fc7eaefSShawn Lin 8123fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 8133fc7eaefSShawn Lin sg_len, cfg.direction, 8143fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 8153fc7eaefSShawn Lin if (!desc) { 8163fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 8173fc7eaefSShawn Lin return -EBUSY; 8183fc7eaefSShawn Lin } 8193fc7eaefSShawn Lin 8203fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 8213fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 8223fc7eaefSShawn Lin desc->callback_param = (void *)host; 8233fc7eaefSShawn Lin dmaengine_submit(desc); 8243fc7eaefSShawn Lin 8253fc7eaefSShawn Lin /* Flush cache before write */ 8263fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 82742f989c0SJaehoon Chung dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 8283fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 8293fc7eaefSShawn Lin 8303fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 8313fc7eaefSShawn Lin 8323fc7eaefSShawn Lin return 0; 8333fc7eaefSShawn Lin } 8343fc7eaefSShawn Lin 8353fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 8363fc7eaefSShawn Lin { 8373fc7eaefSShawn Lin /* Request external dma channel */ 8383fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 8393fc7eaefSShawn Lin if (!host->dms) 8403fc7eaefSShawn Lin return -ENOMEM; 8413fc7eaefSShawn Lin 842c1fce225SPeter Ujfalusi host->dms->ch = dma_request_chan(host->dev, "rx-tx"); 843c1fce225SPeter Ujfalusi if (IS_ERR(host->dms->ch)) { 844c1fce225SPeter Ujfalusi int ret = PTR_ERR(host->dms->ch); 845c1fce225SPeter Ujfalusi 8464539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 8473fc7eaefSShawn Lin kfree(host->dms); 8483fc7eaefSShawn Lin host->dms = NULL; 849c1fce225SPeter Ujfalusi return ret; 8503fc7eaefSShawn Lin } 8513fc7eaefSShawn Lin 8523fc7eaefSShawn Lin return 0; 8533fc7eaefSShawn Lin } 8543fc7eaefSShawn Lin 8553fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 8563fc7eaefSShawn Lin { 8573fc7eaefSShawn Lin if (host->dms) { 8583fc7eaefSShawn Lin if (host->dms->ch) { 8593fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 8603fc7eaefSShawn Lin host->dms->ch = NULL; 8613fc7eaefSShawn Lin } 8623fc7eaefSShawn Lin kfree(host->dms); 8633fc7eaefSShawn Lin host->dms = NULL; 8643fc7eaefSShawn Lin } 8653fc7eaefSShawn Lin } 8663fc7eaefSShawn Lin 8673fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 8683fc7eaefSShawn Lin .init = dw_mci_edmac_init, 8693fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 8703fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 8713fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 8723fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 8733fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 8743fc7eaefSShawn Lin }; 875885c3e80SSeungwon Jeon 8769aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 8779aa51408SSeungwon Jeon struct mmc_data *data, 878a4cc7eb4SJaehoon Chung int cookie) 879f95f3850SWill Newton { 880f95f3850SWill Newton struct scatterlist *sg; 8819aa51408SSeungwon Jeon unsigned int i, sg_len; 882f95f3850SWill Newton 883a4cc7eb4SJaehoon Chung if (data->host_cookie == COOKIE_PRE_MAPPED) 884a4cc7eb4SJaehoon Chung return data->sg_len; 885f95f3850SWill Newton 886f95f3850SWill Newton /* 887f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 888f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 889f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 890f95f3850SWill Newton */ 891f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 892f95f3850SWill Newton return -EINVAL; 8939aa51408SSeungwon Jeon 894f95f3850SWill Newton if (data->blksz & 3) 895f95f3850SWill Newton return -EINVAL; 896f95f3850SWill Newton 897f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 898f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 899f95f3850SWill Newton return -EINVAL; 900f95f3850SWill Newton } 901f95f3850SWill Newton 9024a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 9039aa51408SSeungwon Jeon data->sg, 9049aa51408SSeungwon Jeon data->sg_len, 905feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 9069aa51408SSeungwon Jeon if (sg_len == 0) 9079aa51408SSeungwon Jeon return -EINVAL; 9089aa51408SSeungwon Jeon 909a4cc7eb4SJaehoon Chung data->host_cookie = cookie; 9109aa51408SSeungwon Jeon 9119aa51408SSeungwon Jeon return sg_len; 9129aa51408SSeungwon Jeon } 9139aa51408SSeungwon Jeon 9149aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 915d3c6aac3SLinus Walleij struct mmc_request *mrq) 9169aa51408SSeungwon Jeon { 9179aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9189aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9199aa51408SSeungwon Jeon 9209aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9219aa51408SSeungwon Jeon return; 9229aa51408SSeungwon Jeon 923a4cc7eb4SJaehoon Chung /* This data might be unmapped at this time */ 924a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9259aa51408SSeungwon Jeon 926a4cc7eb4SJaehoon Chung if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 927a4cc7eb4SJaehoon Chung COOKIE_PRE_MAPPED) < 0) 928a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9299aa51408SSeungwon Jeon } 9309aa51408SSeungwon Jeon 9319aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 9329aa51408SSeungwon Jeon struct mmc_request *mrq, 9339aa51408SSeungwon Jeon int err) 9349aa51408SSeungwon Jeon { 9359aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9369aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9379aa51408SSeungwon Jeon 9389aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9399aa51408SSeungwon Jeon return; 9409aa51408SSeungwon Jeon 941a4cc7eb4SJaehoon Chung if (data->host_cookie != COOKIE_UNMAPPED) 9424a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 9439aa51408SSeungwon Jeon data->sg, 9449aa51408SSeungwon Jeon data->sg_len, 945feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 946a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9479aa51408SSeungwon Jeon } 9489aa51408SSeungwon Jeon 949671fa142SShawn Lin static int dw_mci_get_cd(struct mmc_host *mmc) 950671fa142SShawn Lin { 951671fa142SShawn Lin int present; 952671fa142SShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 953671fa142SShawn Lin struct dw_mci *host = slot->host; 954671fa142SShawn Lin int gpio_cd = mmc_gpio_get_cd(mmc); 955671fa142SShawn Lin 956671fa142SShawn Lin /* Use platform get_cd function, else try onboard card detect */ 957671fa142SShawn Lin if (((mmc->caps & MMC_CAP_NEEDS_POLL) 958671fa142SShawn Lin || !mmc_card_is_removable(mmc))) { 959671fa142SShawn Lin present = 1; 960671fa142SShawn Lin 961671fa142SShawn Lin if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 962671fa142SShawn Lin if (mmc->caps & MMC_CAP_NEEDS_POLL) { 963671fa142SShawn Lin dev_info(&mmc->class_dev, 964671fa142SShawn Lin "card is polling.\n"); 965671fa142SShawn Lin } else { 966671fa142SShawn Lin dev_info(&mmc->class_dev, 967671fa142SShawn Lin "card is non-removable.\n"); 968671fa142SShawn Lin } 969671fa142SShawn Lin set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 970671fa142SShawn Lin } 971671fa142SShawn Lin 972671fa142SShawn Lin return present; 973671fa142SShawn Lin } else if (gpio_cd >= 0) 974671fa142SShawn Lin present = gpio_cd; 975671fa142SShawn Lin else 976671fa142SShawn Lin present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 977671fa142SShawn Lin == 0 ? 1 : 0; 978671fa142SShawn Lin 979671fa142SShawn Lin spin_lock_bh(&host->lock); 980671fa142SShawn Lin if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 981671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is present\n"); 982671fa142SShawn Lin else if (!present && 983671fa142SShawn Lin !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 984671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is not present\n"); 985671fa142SShawn Lin spin_unlock_bh(&host->lock); 986671fa142SShawn Lin 987671fa142SShawn Lin return present; 988671fa142SShawn Lin } 989671fa142SShawn Lin 99052426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 99152426899SSeungwon Jeon { 99252426899SSeungwon Jeon unsigned int blksz = data->blksz; 99327d70d36SColin Ian King static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 99452426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 99552426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 99652426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 9970e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 99852426899SSeungwon Jeon 9993fc7eaefSShawn Lin /* pio should ship this scenario */ 10003fc7eaefSShawn Lin if (!host->use_dma) 10013fc7eaefSShawn Lin return; 10023fc7eaefSShawn Lin 100352426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 100452426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 100552426899SSeungwon Jeon 100652426899SSeungwon Jeon /* 100752426899SSeungwon Jeon * MSIZE is '1', 100852426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 100952426899SSeungwon Jeon */ 101020753569SShawn Lin if (blksz % fifo_width) 101152426899SSeungwon Jeon goto done; 101252426899SSeungwon Jeon 101352426899SSeungwon Jeon do { 101452426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 101552426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 101652426899SSeungwon Jeon msize = idx; 101752426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 101852426899SSeungwon Jeon break; 101952426899SSeungwon Jeon } 102052426899SSeungwon Jeon } while (--idx > 0); 102152426899SSeungwon Jeon /* 102252426899SSeungwon Jeon * If idx is '0', it won't be tried 102352426899SSeungwon Jeon * Thus, initial values are uesed 102452426899SSeungwon Jeon */ 102552426899SSeungwon Jeon done: 102652426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 102752426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 102852426899SSeungwon Jeon } 102952426899SSeungwon Jeon 10307e4bf1bcSJaehoon Chung static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1031f1d2736cSSeungwon Jeon { 1032f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 1033f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 1034f1d2736cSSeungwon Jeon u16 thld_size; 10357e4bf1bcSJaehoon Chung u8 enable; 1036f1d2736cSSeungwon Jeon 103766dfd101SJames Hogan /* 103866dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 103966dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 104066dfd101SJames Hogan */ 10417e4bf1bcSJaehoon Chung if (host->verid < DW_MMC_240A || 10427e4bf1bcSJaehoon Chung (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 104366dfd101SJames Hogan return; 104466dfd101SJames Hogan 10457e4bf1bcSJaehoon Chung /* 10467e4bf1bcSJaehoon Chung * Card write Threshold is introduced since 2.80a 10477e4bf1bcSJaehoon Chung * It's used when HS400 mode is enabled. 10487e4bf1bcSJaehoon Chung */ 10497e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE && 10507a6b9f4dSx00270170 host->timing != MMC_TIMING_MMC_HS400) 10517a6b9f4dSx00270170 goto disable; 10527e4bf1bcSJaehoon Chung 10537e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE) 10547e4bf1bcSJaehoon Chung enable = SDMMC_CARD_WR_THR_EN; 10557e4bf1bcSJaehoon Chung else 10567e4bf1bcSJaehoon Chung enable = SDMMC_CARD_RD_THR_EN; 10577e4bf1bcSJaehoon Chung 1058f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 10597a6b9f4dSx00270170 host->timing != MMC_TIMING_UHS_SDR104 && 10607a6b9f4dSx00270170 host->timing != MMC_TIMING_MMC_HS400) 1061f1d2736cSSeungwon Jeon goto disable; 1062f1d2736cSSeungwon Jeon 1063f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 1064f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 1065f1d2736cSSeungwon Jeon 1066f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 1067f1d2736cSSeungwon Jeon goto disable; 1068f1d2736cSSeungwon Jeon 1069f1d2736cSSeungwon Jeon /* 1070f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1071f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1072f1d2736cSSeungwon Jeon * Currently just choose blksz. 1073f1d2736cSSeungwon Jeon */ 1074f1d2736cSSeungwon Jeon thld_size = blksz; 10757e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1076f1d2736cSSeungwon Jeon return; 1077f1d2736cSSeungwon Jeon 1078f1d2736cSSeungwon Jeon disable: 10797e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, 0); 1080f1d2736cSSeungwon Jeon } 1081f1d2736cSSeungwon Jeon 10829aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 10839aa51408SSeungwon Jeon { 1084f8c58c11SDoug Anderson unsigned long irqflags; 10859aa51408SSeungwon Jeon int sg_len; 10869aa51408SSeungwon Jeon u32 temp; 10879aa51408SSeungwon Jeon 10889aa51408SSeungwon Jeon host->using_dma = 0; 10899aa51408SSeungwon Jeon 10909aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 10919aa51408SSeungwon Jeon if (!host->use_dma) 10929aa51408SSeungwon Jeon return -ENODEV; 10939aa51408SSeungwon Jeon 1094a4cc7eb4SJaehoon Chung sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1095a99aa9b9SSeungwon Jeon if (sg_len < 0) { 1096a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 10979aa51408SSeungwon Jeon return sg_len; 1098a99aa9b9SSeungwon Jeon } 10999aa51408SSeungwon Jeon 110003e8cb53SJames Hogan host->using_dma = 1; 110103e8cb53SJames Hogan 11023fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 11034a90920cSThomas Abraham dev_vdbg(host->dev, 1104f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 11053fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 11063fc7eaefSShawn Lin (unsigned long)host->sg_dma, 1107f95f3850SWill Newton sg_len); 1108f95f3850SWill Newton 110952426899SSeungwon Jeon /* 111052426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 111152426899SSeungwon Jeon * If current block size is same with previous size, 111252426899SSeungwon Jeon * no need to update fifoth. 111352426899SSeungwon Jeon */ 111452426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 111552426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 111652426899SSeungwon Jeon 1117f95f3850SWill Newton /* Enable the DMA interface */ 1118f95f3850SWill Newton temp = mci_readl(host, CTRL); 1119f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 1120f95f3850SWill Newton mci_writel(host, CTRL, temp); 1121f95f3850SWill Newton 1122f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 1123f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1124f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1125f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1126f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1127f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1128f95f3850SWill Newton 11293fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 1130647f80a1SJaehoon Chung host->dma_ops->stop(host); 1131d12d0cb1SShawn Lin /* We can't do DMA, try PIO for this one */ 1132d12d0cb1SShawn Lin dev_dbg(host->dev, 1133d12d0cb1SShawn Lin "%s: fall back to PIO mode for current transfer\n", 1134d12d0cb1SShawn Lin __func__); 11353fc7eaefSShawn Lin return -ENODEV; 11363fc7eaefSShawn Lin } 1137f95f3850SWill Newton 1138f95f3850SWill Newton return 0; 1139f95f3850SWill Newton } 1140f95f3850SWill Newton 1141f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1142f95f3850SWill Newton { 1143f8c58c11SDoug Anderson unsigned long irqflags; 11440e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1145f95f3850SWill Newton u32 temp; 1146f95f3850SWill Newton 1147f95f3850SWill Newton data->error = -EINPROGRESS; 1148f95f3850SWill Newton 1149f95f3850SWill Newton WARN_ON(host->data); 1150f95f3850SWill Newton host->sg = NULL; 1151f95f3850SWill Newton host->data = data; 1152f95f3850SWill Newton 11537e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_READ) 115455c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 11557e4bf1bcSJaehoon Chung else 115655c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 11577e4bf1bcSJaehoon Chung 11587e4bf1bcSJaehoon Chung dw_mci_ctrl_thld(host, data); 115955c5efbcSJames Hogan 1160f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1161f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1162f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1163f9c2a0dcSSeungwon Jeon else 1164f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1165f9c2a0dcSSeungwon Jeon 1166f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1167f95f3850SWill Newton host->sg = data->sg; 116834b664a2SJames Hogan host->part_buf_start = 0; 116934b664a2SJames Hogan host->part_buf_count = 0; 1170f95f3850SWill Newton 1171b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1172f8c58c11SDoug Anderson 1173f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1174f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1175f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1176f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1177f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1178f95f3850SWill Newton 1179f95f3850SWill Newton temp = mci_readl(host, CTRL); 1180f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1181f95f3850SWill Newton mci_writel(host, CTRL, temp); 118252426899SSeungwon Jeon 118352426899SSeungwon Jeon /* 1184d6fced83SJun Nie * Use the initial fifoth_val for PIO mode. If wm_algined 1185d6fced83SJun Nie * is set, we set watermark same as data size. 118652426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 118752426899SSeungwon Jeon * prev_blksz should be invalidated. 118852426899SSeungwon Jeon */ 1189d6fced83SJun Nie if (host->wm_aligned) 1190d6fced83SJun Nie dw_mci_adjust_fifoth(host, data); 1191d6fced83SJun Nie else 119252426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 119352426899SSeungwon Jeon host->prev_blksz = 0; 119452426899SSeungwon Jeon } else { 119552426899SSeungwon Jeon /* 119652426899SSeungwon Jeon * Keep the current block size. 119752426899SSeungwon Jeon * It will be used to decide whether to update 119852426899SSeungwon Jeon * fifoth register next time. 119952426899SSeungwon Jeon */ 120052426899SSeungwon Jeon host->prev_blksz = data->blksz; 1201f95f3850SWill Newton } 1202f95f3850SWill Newton } 1203f95f3850SWill Newton 1204ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1205f95f3850SWill Newton { 1206f95f3850SWill Newton struct dw_mci *host = slot->host; 1207fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1208f95f3850SWill Newton u32 div; 12099623b5b9SDoug Anderson u32 clk_en_a; 121001730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 121101730558SDoug Anderson 121201730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 121301730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 121401730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1215f95f3850SWill Newton 1216ff178981SShawn Lin slot->mmc->actual_clock = 0; 1217ff178981SShawn Lin 1218fdf492a1SDoug Anderson if (!clock) { 1219fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 122001730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1221fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1222fdf492a1SDoug Anderson div = host->bus_hz / clock; 1223fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1224f95f3850SWill Newton /* 1225f95f3850SWill Newton * move the + 1 after the divide to prevent 1226f95f3850SWill Newton * over-clocking the card. 1227f95f3850SWill Newton */ 1228e419990bSSeungwon Jeon div += 1; 1229e419990bSSeungwon Jeon 1230fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1231f95f3850SWill Newton 1232e6cd7a8eSJaehoon Chung if ((clock != slot->__clk_old && 1233e6cd7a8eSJaehoon Chung !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1234e6cd7a8eSJaehoon Chung force_clkinit) { 1235ce69e2feSShawn Lin /* Silent the verbose log if calling from PM context */ 1236ce69e2feSShawn Lin if (!force_clkinit) 1237f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1238fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1239fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1240fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1241fdf492a1SDoug Anderson host->bus_hz, div); 1242f95f3850SWill Newton 1243e6cd7a8eSJaehoon Chung /* 1244e6cd7a8eSJaehoon Chung * If card is polling, display the message only 1245e6cd7a8eSJaehoon Chung * one time at boot time. 1246e6cd7a8eSJaehoon Chung */ 1247e6cd7a8eSJaehoon Chung if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1248e6cd7a8eSJaehoon Chung slot->mmc->f_min == clock) 1249e6cd7a8eSJaehoon Chung set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1250e6cd7a8eSJaehoon Chung } 1251e6cd7a8eSJaehoon Chung 1252f95f3850SWill Newton /* disable clock */ 1253f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1254f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1255f95f3850SWill Newton 1256f95f3850SWill Newton /* inform CIU */ 125701730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1258f95f3850SWill Newton 1259f95f3850SWill Newton /* set clock to desired speed */ 1260f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1261f95f3850SWill Newton 1262f95f3850SWill Newton /* inform CIU */ 126301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1264f95f3850SWill Newton 12659623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 12669623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1267b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 12689623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 12699623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1270f95f3850SWill Newton 1271f95f3850SWill Newton /* inform CIU */ 127201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1273005d675aSJaehoon Chung 1274005d675aSJaehoon Chung /* keep the last clock value that was requested from core */ 1275005d675aSJaehoon Chung slot->__clk_old = clock; 1276ff178981SShawn Lin slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : 1277ff178981SShawn Lin host->bus_hz; 1278f95f3850SWill Newton } 1279f95f3850SWill Newton 1280fdf492a1SDoug Anderson host->current_speed = clock; 1281fdf492a1SDoug Anderson 1282f95f3850SWill Newton /* Set the current slot bus width */ 12831d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1284f95f3850SWill Newton } 1285f95f3850SWill Newton 1286053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1287053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1288053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1289f95f3850SWill Newton { 1290f95f3850SWill Newton struct mmc_request *mrq; 1291f95f3850SWill Newton struct mmc_data *data; 1292f95f3850SWill Newton u32 cmdflags; 1293f95f3850SWill Newton 1294f95f3850SWill Newton mrq = slot->mrq; 1295f95f3850SWill Newton 1296f95f3850SWill Newton host->mrq = mrq; 1297f95f3850SWill Newton 1298f95f3850SWill Newton host->pending_events = 0; 1299f95f3850SWill Newton host->completed_events = 0; 1300e352c813SSeungwon Jeon host->cmd_status = 0; 1301f95f3850SWill Newton host->data_status = 0; 1302e352c813SSeungwon Jeon host->dir_status = 0; 1303f95f3850SWill Newton 1304053b3ce6SSeungwon Jeon data = cmd->data; 1305f95f3850SWill Newton if (data) { 1306f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1307f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1308f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1309f95f3850SWill Newton } 1310f95f3850SWill Newton 1311f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1312f95f3850SWill Newton 1313f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1314f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1315f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1316f95f3850SWill Newton 1317f95f3850SWill Newton if (data) { 1318f95f3850SWill Newton dw_mci_submit_data(host, data); 13190e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1320f95f3850SWill Newton } 1321f95f3850SWill Newton 1322f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1323f95f3850SWill Newton 13245c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 132549ba0302SDoug Anderson unsigned long irqflags; 132649ba0302SDoug Anderson 13275c935165SDoug Anderson /* 13288886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 13298886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 13308886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 13318886a6fdSDoug Anderson * is just about to roll over. 133249ba0302SDoug Anderson * 133349ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 133449ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 133549ba0302SDoug Anderson * already ran so we don't want the timeout). 13365c935165SDoug Anderson */ 133749ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 133849ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 13395c935165SDoug Anderson mod_timer(&host->cmd11_timer, 13408886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 134149ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13425c935165SDoug Anderson } 13435c935165SDoug Anderson 134490c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1345f95f3850SWill Newton } 1346f95f3850SWill Newton 1347053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1348053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1349053b3ce6SSeungwon Jeon { 1350053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1351053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1352053b3ce6SSeungwon Jeon 1353053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1354053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1355053b3ce6SSeungwon Jeon } 1356053b3ce6SSeungwon Jeon 13577456caaeSJames Hogan /* must be called with host->lock held */ 1358f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1359f95f3850SWill Newton struct mmc_request *mrq) 1360f95f3850SWill Newton { 1361f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1362f95f3850SWill Newton host->state); 1363f95f3850SWill Newton 1364f95f3850SWill Newton slot->mrq = mrq; 1365f95f3850SWill Newton 136601730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 136701730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 136801730558SDoug Anderson "Voltage change didn't complete\n"); 136901730558SDoug Anderson /* 137001730558SDoug Anderson * this case isn't expected to happen, so we can 137101730558SDoug Anderson * either crash here or just try to continue on 137201730558SDoug Anderson * in the closest possible state 137301730558SDoug Anderson */ 137401730558SDoug Anderson host->state = STATE_IDLE; 137501730558SDoug Anderson } 137601730558SDoug Anderson 1377f95f3850SWill Newton if (host->state == STATE_IDLE) { 1378f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1379f95f3850SWill Newton dw_mci_start_request(host, slot); 1380f95f3850SWill Newton } else { 1381f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1382f95f3850SWill Newton } 1383f95f3850SWill Newton } 1384f95f3850SWill Newton 1385f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1386f95f3850SWill Newton { 1387f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1388f95f3850SWill Newton struct dw_mci *host = slot->host; 1389f95f3850SWill Newton 1390f95f3850SWill Newton WARN_ON(slot->mrq); 1391f95f3850SWill Newton 13927456caaeSJames Hogan /* 13937456caaeSJames Hogan * The check for card presence and queueing of the request must be 13947456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 13957456caaeSJames Hogan * request wouldn't fail until another card was inserted. 13967456caaeSJames Hogan */ 13977456caaeSJames Hogan 139856f6911cSShawn Lin if (!dw_mci_get_cd(mmc)) { 1399f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1400f95f3850SWill Newton mmc_request_done(mmc, mrq); 1401f95f3850SWill Newton return; 1402f95f3850SWill Newton } 1403f95f3850SWill Newton 140456f6911cSShawn Lin spin_lock_bh(&host->lock); 140556f6911cSShawn Lin 1406f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 14077456caaeSJames Hogan 14087456caaeSJames Hogan spin_unlock_bh(&host->lock); 1409f95f3850SWill Newton } 1410f95f3850SWill Newton 1411f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1412f95f3850SWill Newton { 1413f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1414e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 141541babf75SJaehoon Chung u32 regs; 141651da2240SYuvaraj CD int ret; 1417f95f3850SWill Newton 1418f95f3850SWill Newton switch (ios->bus_width) { 1419f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1420f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1421f95f3850SWill Newton break; 1422c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1423c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1424c9b2a06fSJaehoon Chung break; 1425b2f7cb45SJaehoon Chung default: 1426b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1427b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1428f95f3850SWill Newton } 1429f95f3850SWill Newton 143041babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 14313f514291SSeungwon Jeon 14323f514291SSeungwon Jeon /* DDR mode set */ 143380113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 14347cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 143580113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1436c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 14373f514291SSeungwon Jeon else 1438c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 14393f514291SSeungwon Jeon 144041babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1441f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 144241babf75SJaehoon Chung 1443f95f3850SWill Newton /* 1444f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1445f95f3850SWill Newton * core ios update when finding the minimum. 1446f95f3850SWill Newton */ 1447f95f3850SWill Newton slot->clock = ios->clock; 1448f95f3850SWill Newton 1449cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1450cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1451800d78bfSThomas Abraham 1452f95f3850SWill Newton switch (ios->power_mode) { 1453f95f3850SWill Newton case MMC_POWER_UP: 145451da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 145551da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 145651da2240SYuvaraj CD ios->vdd); 145751da2240SYuvaraj CD if (ret) { 145851da2240SYuvaraj CD dev_err(slot->host->dev, 145951da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 146051da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 146151da2240SYuvaraj CD return; 146251da2240SYuvaraj CD } 146351da2240SYuvaraj CD } 146429d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 146529d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 146629d0d161SDoug Anderson regs |= (1 << slot->id); 146729d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 146829d0d161SDoug Anderson break; 146929d0d161SDoug Anderson case MMC_POWER_ON: 1470d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1471d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 147251da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 147351da2240SYuvaraj CD if (ret < 0) 147451da2240SYuvaraj CD dev_err(slot->host->dev, 1475d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 147651da2240SYuvaraj CD else 147751da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1478d1f1dd86SDoug Anderson 1479d1f1dd86SDoug Anderson } else { 1480d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1481d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1482d1f1dd86SDoug Anderson } 1483d1f1dd86SDoug Anderson 1484d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1485d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1486d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 148751da2240SYuvaraj CD } 1488655babbdSDoug Anderson 1489655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1490655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1491655babbdSDoug Anderson 1492e6f34e2fSJames Hogan break; 1493e6f34e2fSJames Hogan case MMC_POWER_OFF: 1494655babbdSDoug Anderson /* Turn clock off before power goes down */ 1495655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1496655babbdSDoug Anderson 149751da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 149851da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 149951da2240SYuvaraj CD 1500d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 150151da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 150251da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 150351da2240SYuvaraj CD 15044366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 15054366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 15064366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1507f95f3850SWill Newton break; 1508f95f3850SWill Newton default: 1509f95f3850SWill Newton break; 1510f95f3850SWill Newton } 1511655babbdSDoug Anderson 1512655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1513655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1514f95f3850SWill Newton } 1515f95f3850SWill Newton 151601730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 151701730558SDoug Anderson { 151801730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 151901730558SDoug Anderson u32 status; 152001730558SDoug Anderson 152101730558SDoug Anderson /* 152201730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 152301730558SDoug Anderson * (the data lines) are 0000 152401730558SDoug Anderson */ 152501730558SDoug Anderson status = mci_readl(slot->host, STATUS); 152601730558SDoug Anderson 152701730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 152801730558SDoug Anderson } 152901730558SDoug Anderson 153001730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 153101730558SDoug Anderson { 153201730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 153301730558SDoug Anderson struct dw_mci *host = slot->host; 15348f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 153501730558SDoug Anderson u32 uhs; 153601730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 153701730558SDoug Anderson int ret; 153801730558SDoug Anderson 15398f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 15408f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 15418f7849c4SZhangfei Gao 154201730558SDoug Anderson /* 154301730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 154401730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 154501730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 154601730558SDoug Anderson */ 154701730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1548e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 154901730558SDoug Anderson uhs &= ~v18; 1550e0848f5dSDouglas Anderson else 155101730558SDoug Anderson uhs |= v18; 1552e0848f5dSDouglas Anderson 155301730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1554e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 15559cbe0fc8SMarek Vasut if (ret < 0) { 1556b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1557e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1558e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 155901730558SDoug Anderson return ret; 156001730558SDoug Anderson } 156101730558SDoug Anderson } 156201730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 156301730558SDoug Anderson 156401730558SDoug Anderson return 0; 156501730558SDoug Anderson } 156601730558SDoug Anderson 1567f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1568f95f3850SWill Newton { 1569f95f3850SWill Newton int read_only; 1570f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 15719795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1572f95f3850SWill Newton 1573f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1574287980e4SArnd Bergmann if (gpio_ro >= 0) 15759795a846SJaehoon Chung read_only = gpio_ro; 1576f95f3850SWill Newton else 1577f95f3850SWill Newton read_only = 1578f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1579f95f3850SWill Newton 1580f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1581f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1582f95f3850SWill Newton 1583f95f3850SWill Newton return read_only; 1584f95f3850SWill Newton } 1585f95f3850SWill Newton 1586935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1587935a665eSShawn Lin { 1588935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1589935a665eSShawn Lin struct dw_mci *host = slot->host; 1590935a665eSShawn Lin int reset; 1591935a665eSShawn Lin 1592935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1593935a665eSShawn Lin dw_mci_idmac_reset(host); 1594935a665eSShawn Lin 1595935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1596935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1597935a665eSShawn Lin return; 1598935a665eSShawn Lin 1599935a665eSShawn Lin /* 1600935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1601935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1602935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1603935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1604935a665eSShawn Lin */ 1605935a665eSShawn Lin reset = mci_readl(host, RST_N); 1606935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1607935a665eSShawn Lin mci_writel(host, RST_N, reset); 1608935a665eSShawn Lin usleep_range(1, 2); 1609935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1610935a665eSShawn Lin mci_writel(host, RST_N, reset); 1611935a665eSShawn Lin usleep_range(200, 300); 1612935a665eSShawn Lin } 1613935a665eSShawn Lin 1614b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1615b24c8b26SDoug Anderson { 1616b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1617b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1618b24c8b26SDoug Anderson 16199623b5b9SDoug Anderson /* 16209623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 16219623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 16229623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 16239623b5b9SDoug Anderson */ 1624b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 16259623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1626b24c8b26SDoug Anderson u32 clk_en_a_old; 1627b24c8b26SDoug Anderson u32 clk_en_a; 16289623b5b9SDoug Anderson 1629b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 16309623b5b9SDoug Anderson 1631b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1632b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1633b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1634b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1635b24c8b26SDoug Anderson } else { 1636b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1637b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1638b24c8b26SDoug Anderson } 1639b24c8b26SDoug Anderson 1640b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1641b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 16429623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 16439623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 16449623b5b9SDoug Anderson } 16459623b5b9SDoug Anderson } 1646b24c8b26SDoug Anderson } 16479623b5b9SDoug Anderson 164832dba737SUlf Hansson static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 16491a5c8e1fSShashidhar Hiremath { 16501a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1651f8c58c11SDoug Anderson unsigned long irqflags; 16521a5c8e1fSShashidhar Hiremath u32 int_mask; 16531a5c8e1fSShashidhar Hiremath 1654f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1655f8c58c11SDoug Anderson 16561a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 16571a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1658b24c8b26SDoug Anderson if (enb) 1659b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1660b24c8b26SDoug Anderson else 1661b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1662b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1663f8c58c11SDoug Anderson 1664f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 16651a5c8e1fSShashidhar Hiremath } 16661a5c8e1fSShashidhar Hiremath 166732dba737SUlf Hansson static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 166832dba737SUlf Hansson { 166932dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 1670ca8971caSUlf Hansson struct dw_mci *host = slot->host; 167132dba737SUlf Hansson 167232dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, enb); 1673ca8971caSUlf Hansson 1674ca8971caSUlf Hansson /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1675ca8971caSUlf Hansson if (enb) 1676ca8971caSUlf Hansson pm_runtime_get_noresume(host->dev); 1677ca8971caSUlf Hansson else 1678ca8971caSUlf Hansson pm_runtime_put_noidle(host->dev); 167932dba737SUlf Hansson } 168032dba737SUlf Hansson 168132dba737SUlf Hansson static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 168232dba737SUlf Hansson { 168332dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 168432dba737SUlf Hansson 168532dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 1); 168632dba737SUlf Hansson } 168732dba737SUlf Hansson 16880976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 16890976f16dSSeungwon Jeon { 16900976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 16910976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 16920976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 16930e3a22c0SShawn Lin int err = -EINVAL; 16940976f16dSSeungwon Jeon 16950976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 16969979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 16970976f16dSSeungwon Jeon return err; 16980976f16dSSeungwon Jeon } 16990976f16dSSeungwon Jeon 17000e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 17010e3a22c0SShawn Lin struct mmc_ios *ios) 170280113132SSeungwon Jeon { 170380113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 170480113132SSeungwon Jeon struct dw_mci *host = slot->host; 170580113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 170680113132SSeungwon Jeon 170780113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 170880113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 170980113132SSeungwon Jeon 171080113132SSeungwon Jeon return 0; 171180113132SSeungwon Jeon } 171280113132SSeungwon Jeon 17134e7392b2SShawn Lin static bool dw_mci_reset(struct dw_mci *host) 17144e7392b2SShawn Lin { 17154e7392b2SShawn Lin u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 17164e7392b2SShawn Lin bool ret = false; 1717bc2dcc1aSShawn Lin u32 status = 0; 17184e7392b2SShawn Lin 17194e7392b2SShawn Lin /* 17204e7392b2SShawn Lin * Resetting generates a block interrupt, hence setting 17214e7392b2SShawn Lin * the scatter-gather pointer to NULL. 17224e7392b2SShawn Lin */ 17234e7392b2SShawn Lin if (host->sg) { 17244e7392b2SShawn Lin sg_miter_stop(&host->sg_miter); 17254e7392b2SShawn Lin host->sg = NULL; 17264e7392b2SShawn Lin } 17274e7392b2SShawn Lin 17284e7392b2SShawn Lin if (host->use_dma) 17294e7392b2SShawn Lin flags |= SDMMC_CTRL_DMA_RESET; 17304e7392b2SShawn Lin 17314e7392b2SShawn Lin if (dw_mci_ctrl_reset(host, flags)) { 17324e7392b2SShawn Lin /* 1733bc2dcc1aSShawn Lin * In all cases we clear the RAWINTS 1734bc2dcc1aSShawn Lin * register to clear any interrupts. 17354e7392b2SShawn Lin */ 17364e7392b2SShawn Lin mci_writel(host, RINTSTS, 0xFFFFFFFF); 17374e7392b2SShawn Lin 1738bc2dcc1aSShawn Lin if (!host->use_dma) { 1739bc2dcc1aSShawn Lin ret = true; 1740bc2dcc1aSShawn Lin goto ciu_out; 1741bc2dcc1aSShawn Lin } 17424e7392b2SShawn Lin 1743bc2dcc1aSShawn Lin /* Wait for dma_req to be cleared */ 17444e7392b2SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 17454e7392b2SShawn Lin status, 17464e7392b2SShawn Lin !(status & SDMMC_STATUS_DMA_REQ), 17474e7392b2SShawn Lin 1, 500 * USEC_PER_MSEC)) { 17484e7392b2SShawn Lin dev_err(host->dev, 1749bc2dcc1aSShawn Lin "%s: Timeout waiting for dma_req to be cleared\n", 17504e7392b2SShawn Lin __func__); 17514e7392b2SShawn Lin goto ciu_out; 17524e7392b2SShawn Lin } 17534e7392b2SShawn Lin 17544e7392b2SShawn Lin /* when using DMA next we reset the fifo again */ 17554e7392b2SShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 17564e7392b2SShawn Lin goto ciu_out; 17574e7392b2SShawn Lin } else { 17584e7392b2SShawn Lin /* if the controller reset bit did clear, then set clock regs */ 17594e7392b2SShawn Lin if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 17604e7392b2SShawn Lin dev_err(host->dev, 17614e7392b2SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 17624e7392b2SShawn Lin __func__); 17634e7392b2SShawn Lin goto ciu_out; 17644e7392b2SShawn Lin } 17654e7392b2SShawn Lin } 17664e7392b2SShawn Lin 17674e7392b2SShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 176847b7de2fSEvgeniy Didin /* It is also required that we reinit idmac */ 176947b7de2fSEvgeniy Didin dw_mci_idmac_init(host); 17704e7392b2SShawn Lin 17714e7392b2SShawn Lin ret = true; 17724e7392b2SShawn Lin 17734e7392b2SShawn Lin ciu_out: 17744e7392b2SShawn Lin /* After a CTRL reset we need to have CIU set clock registers */ 177542f989c0SJaehoon Chung mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 17764e7392b2SShawn Lin 17774e7392b2SShawn Lin return ret; 17784e7392b2SShawn Lin } 17794e7392b2SShawn Lin 1780f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1781f95f3850SWill Newton .request = dw_mci_request, 17829aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 17839aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1784f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1785f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1786f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1787935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 17881a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 178932dba737SUlf Hansson .ack_sdio_irq = dw_mci_ack_sdio_irq, 17900976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 179101730558SDoug Anderson .card_busy = dw_mci_card_busy, 179201730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1793b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 179480113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1795f95f3850SWill Newton }; 1796f95f3850SWill Newton 17972b8ac062SVincent Whitchurch #ifdef CONFIG_FAULT_INJECTION 17982b8ac062SVincent Whitchurch static enum hrtimer_restart dw_mci_fault_timer(struct hrtimer *t) 17992b8ac062SVincent Whitchurch { 18002b8ac062SVincent Whitchurch struct dw_mci *host = container_of(t, struct dw_mci, fault_timer); 18012b8ac062SVincent Whitchurch unsigned long flags; 18022b8ac062SVincent Whitchurch 18032b8ac062SVincent Whitchurch spin_lock_irqsave(&host->irq_lock, flags); 18042b8ac062SVincent Whitchurch 18052b8ac062SVincent Whitchurch if (!host->data_status) 18062b8ac062SVincent Whitchurch host->data_status = SDMMC_INT_DCRC; 18072b8ac062SVincent Whitchurch set_bit(EVENT_DATA_ERROR, &host->pending_events); 18082b8ac062SVincent Whitchurch tasklet_schedule(&host->tasklet); 18092b8ac062SVincent Whitchurch 18102b8ac062SVincent Whitchurch spin_unlock_irqrestore(&host->irq_lock, flags); 18112b8ac062SVincent Whitchurch 18122b8ac062SVincent Whitchurch return HRTIMER_NORESTART; 18132b8ac062SVincent Whitchurch } 18142b8ac062SVincent Whitchurch 18152b8ac062SVincent Whitchurch static void dw_mci_start_fault_timer(struct dw_mci *host) 18162b8ac062SVincent Whitchurch { 18172b8ac062SVincent Whitchurch struct mmc_data *data = host->data; 18182b8ac062SVincent Whitchurch 18192b8ac062SVincent Whitchurch if (!data || data->blocks <= 1) 18202b8ac062SVincent Whitchurch return; 18212b8ac062SVincent Whitchurch 18222b8ac062SVincent Whitchurch if (!should_fail(&host->fail_data_crc, 1)) 18232b8ac062SVincent Whitchurch return; 18242b8ac062SVincent Whitchurch 18252b8ac062SVincent Whitchurch /* 18262b8ac062SVincent Whitchurch * Try to inject the error at random points during the data transfer. 18272b8ac062SVincent Whitchurch */ 18282b8ac062SVincent Whitchurch hrtimer_start(&host->fault_timer, 18292b8ac062SVincent Whitchurch ms_to_ktime(prandom_u32() % 25), 18302b8ac062SVincent Whitchurch HRTIMER_MODE_REL); 18312b8ac062SVincent Whitchurch } 18322b8ac062SVincent Whitchurch 18332b8ac062SVincent Whitchurch static void dw_mci_stop_fault_timer(struct dw_mci *host) 18342b8ac062SVincent Whitchurch { 18352b8ac062SVincent Whitchurch hrtimer_cancel(&host->fault_timer); 18362b8ac062SVincent Whitchurch } 18372b8ac062SVincent Whitchurch 18382b8ac062SVincent Whitchurch static void dw_mci_init_fault(struct dw_mci *host) 18392b8ac062SVincent Whitchurch { 18402b8ac062SVincent Whitchurch host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER; 18412b8ac062SVincent Whitchurch 18422b8ac062SVincent Whitchurch hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 18432b8ac062SVincent Whitchurch host->fault_timer.function = dw_mci_fault_timer; 18442b8ac062SVincent Whitchurch } 18452b8ac062SVincent Whitchurch #else 18462b8ac062SVincent Whitchurch static void dw_mci_init_fault(struct dw_mci *host) 18472b8ac062SVincent Whitchurch { 18482b8ac062SVincent Whitchurch } 18492b8ac062SVincent Whitchurch 18502b8ac062SVincent Whitchurch static void dw_mci_start_fault_timer(struct dw_mci *host) 18512b8ac062SVincent Whitchurch { 18522b8ac062SVincent Whitchurch } 18532b8ac062SVincent Whitchurch 18542b8ac062SVincent Whitchurch static void dw_mci_stop_fault_timer(struct dw_mci *host) 18552b8ac062SVincent Whitchurch { 18562b8ac062SVincent Whitchurch } 18572b8ac062SVincent Whitchurch #endif 18582b8ac062SVincent Whitchurch 1859f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1860f95f3850SWill Newton __releases(&host->lock) 1861f95f3850SWill Newton __acquires(&host->lock) 1862f95f3850SWill Newton { 1863f95f3850SWill Newton struct dw_mci_slot *slot; 186442f989c0SJaehoon Chung struct mmc_host *prev_mmc = host->slot->mmc; 1865f95f3850SWill Newton 1866f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1867f95f3850SWill Newton 186842f989c0SJaehoon Chung host->slot->mrq = NULL; 1869f95f3850SWill Newton host->mrq = NULL; 1870f95f3850SWill Newton if (!list_empty(&host->queue)) { 1871f95f3850SWill Newton slot = list_entry(host->queue.next, 1872f95f3850SWill Newton struct dw_mci_slot, queue_node); 1873f95f3850SWill Newton list_del(&slot->queue_node); 18744a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1875f95f3850SWill Newton mmc_hostname(slot->mmc)); 1876f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1877f95f3850SWill Newton dw_mci_start_request(host, slot); 1878f95f3850SWill Newton } else { 18794a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 188001730558SDoug Anderson 188101730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 188201730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 188301730558SDoug Anderson else 1884f95f3850SWill Newton host->state = STATE_IDLE; 1885f95f3850SWill Newton } 1886f95f3850SWill Newton 1887f95f3850SWill Newton spin_unlock(&host->lock); 1888f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1889f95f3850SWill Newton spin_lock(&host->lock); 1890f95f3850SWill Newton } 1891f95f3850SWill Newton 1892e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1893f95f3850SWill Newton { 1894f95f3850SWill Newton u32 status = host->cmd_status; 1895f95f3850SWill Newton 1896f95f3850SWill Newton host->cmd_status = 0; 1897f95f3850SWill Newton 1898f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1899f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1900f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1901f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1902f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1903f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1904f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1905f95f3850SWill Newton } else { 1906f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1907f95f3850SWill Newton cmd->resp[1] = 0; 1908f95f3850SWill Newton cmd->resp[2] = 0; 1909f95f3850SWill Newton cmd->resp[3] = 0; 1910f95f3850SWill Newton } 1911f95f3850SWill Newton } 1912f95f3850SWill Newton 1913f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1914f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1915f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1916f95f3850SWill Newton cmd->error = -EILSEQ; 1917f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1918f95f3850SWill Newton cmd->error = -EIO; 1919f95f3850SWill Newton else 1920f95f3850SWill Newton cmd->error = 0; 1921f95f3850SWill Newton 1922e352c813SSeungwon Jeon return cmd->error; 1923e352c813SSeungwon Jeon } 1924e352c813SSeungwon Jeon 1925e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1926e352c813SSeungwon Jeon { 192731bff450SSeungwon Jeon u32 status = host->data_status; 1928e352c813SSeungwon Jeon 1929e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1930e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1931e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1932e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1933e352c813SSeungwon Jeon data->error = -EILSEQ; 1934e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1935e352c813SSeungwon Jeon if (host->dir_status == 1936e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1937e352c813SSeungwon Jeon /* 1938e352c813SSeungwon Jeon * No data CRC status was returned. 1939e352c813SSeungwon Jeon * The number of bytes transferred 1940e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1941e352c813SSeungwon Jeon */ 1942e352c813SSeungwon Jeon data->bytes_xfered = 0; 1943e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1944e352c813SSeungwon Jeon } else if (host->dir_status == 1945e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1946e7a1dec1SShawn Lin data->error = -EILSEQ; 1947e352c813SSeungwon Jeon } 1948e352c813SSeungwon Jeon } else { 1949e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1950e7a1dec1SShawn Lin data->error = -EILSEQ; 1951e352c813SSeungwon Jeon } 1952e352c813SSeungwon Jeon 1953e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1954e352c813SSeungwon Jeon 1955e352c813SSeungwon Jeon /* 1956e352c813SSeungwon Jeon * After an error, there may be data lingering 195731bff450SSeungwon Jeon * in the FIFO 1958e352c813SSeungwon Jeon */ 19593a33a94cSSonny Rao dw_mci_reset(host); 1960e352c813SSeungwon Jeon } else { 1961e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1962e352c813SSeungwon Jeon data->error = 0; 1963e352c813SSeungwon Jeon } 1964e352c813SSeungwon Jeon 1965e352c813SSeungwon Jeon return data->error; 1966f95f3850SWill Newton } 1967f95f3850SWill Newton 196857e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 196957e10486SAddy Ke { 197057e10486SAddy Ke unsigned int drto_clks; 19719d9491a7SDouglas Anderson unsigned int drto_div; 197257e10486SAddy Ke unsigned int drto_ms; 197393c23ae3SDouglas Anderson unsigned long irqflags; 197457e10486SAddy Ke 197557e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 19769d9491a7SDouglas Anderson drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 19779d9491a7SDouglas Anderson if (drto_div == 0) 19789d9491a7SDouglas Anderson drto_div = 1; 1979c7151602SEvgeniy Didin 1980c7151602SEvgeniy Didin drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 19819d9491a7SDouglas Anderson host->bus_hz); 198257e10486SAddy Ke 198357e10486SAddy Ke /* add a bit spare time */ 198457e10486SAddy Ke drto_ms += 10; 198557e10486SAddy Ke 198693c23ae3SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 198793c23ae3SDouglas Anderson if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 198893c23ae3SDouglas Anderson mod_timer(&host->dto_timer, 198993c23ae3SDouglas Anderson jiffies + msecs_to_jiffies(drto_ms)); 199093c23ae3SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 199157e10486SAddy Ke } 199257e10486SAddy Ke 19938892b705SDouglas Anderson static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 19948892b705SDouglas Anderson { 19958892b705SDouglas Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 19968892b705SDouglas Anderson return false; 19978892b705SDouglas Anderson 19988892b705SDouglas Anderson /* 19998892b705SDouglas Anderson * Really be certain that the timer has stopped. This is a bit of 20008892b705SDouglas Anderson * paranoia and could only really happen if we had really bad 20018892b705SDouglas Anderson * interrupt latency and the interrupt routine and timeout were 20028892b705SDouglas Anderson * running concurrently so that the del_timer() in the interrupt 20038892b705SDouglas Anderson * handler couldn't run. 20048892b705SDouglas Anderson */ 20058892b705SDouglas Anderson WARN_ON(del_timer_sync(&host->cto_timer)); 20068892b705SDouglas Anderson clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 20078892b705SDouglas Anderson 20088892b705SDouglas Anderson return true; 20098892b705SDouglas Anderson } 20108892b705SDouglas Anderson 201193c23ae3SDouglas Anderson static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 201293c23ae3SDouglas Anderson { 201393c23ae3SDouglas Anderson if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 201493c23ae3SDouglas Anderson return false; 201593c23ae3SDouglas Anderson 201693c23ae3SDouglas Anderson /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 201793c23ae3SDouglas Anderson WARN_ON(del_timer_sync(&host->dto_timer)); 201893c23ae3SDouglas Anderson clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 201993c23ae3SDouglas Anderson 202093c23ae3SDouglas Anderson return true; 202193c23ae3SDouglas Anderson } 202293c23ae3SDouglas Anderson 20236078df15SEmil Renner Berthing static void dw_mci_tasklet_func(struct tasklet_struct *t) 2024f95f3850SWill Newton { 20256078df15SEmil Renner Berthing struct dw_mci *host = from_tasklet(host, t, tasklet); 2026f95f3850SWill Newton struct mmc_data *data; 2027f95f3850SWill Newton struct mmc_command *cmd; 2028e352c813SSeungwon Jeon struct mmc_request *mrq; 2029f95f3850SWill Newton enum dw_mci_state state; 2030f95f3850SWill Newton enum dw_mci_state prev_state; 2031e352c813SSeungwon Jeon unsigned int err; 2032f95f3850SWill Newton 2033f95f3850SWill Newton spin_lock(&host->lock); 2034f95f3850SWill Newton 2035f95f3850SWill Newton state = host->state; 2036f95f3850SWill Newton data = host->data; 2037e352c813SSeungwon Jeon mrq = host->mrq; 2038f95f3850SWill Newton 2039f95f3850SWill Newton do { 2040f95f3850SWill Newton prev_state = state; 2041f95f3850SWill Newton 2042f95f3850SWill Newton switch (state) { 2043f95f3850SWill Newton case STATE_IDLE: 204401730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 2045f95f3850SWill Newton break; 2046f95f3850SWill Newton 204701730558SDoug Anderson case STATE_SENDING_CMD11: 2048f95f3850SWill Newton case STATE_SENDING_CMD: 20498892b705SDouglas Anderson if (!dw_mci_clear_pending_cmd_complete(host)) 2050f95f3850SWill Newton break; 2051f95f3850SWill Newton 2052f95f3850SWill Newton cmd = host->cmd; 2053f95f3850SWill Newton host->cmd = NULL; 2054f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 2055e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 2056e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 205742f989c0SJaehoon Chung __dw_mci_start_request(host, host->slot, 2058e352c813SSeungwon Jeon mrq->cmd); 2059053b3ce6SSeungwon Jeon goto unlock; 2060053b3ce6SSeungwon Jeon } 2061053b3ce6SSeungwon Jeon 2062e352c813SSeungwon Jeon if (cmd->data && err) { 206346d17952SDoug Anderson /* 206446d17952SDoug Anderson * During UHS tuning sequence, sending the stop 206546d17952SDoug Anderson * command after the response CRC error would 206646d17952SDoug Anderson * throw the system into a confused state 206746d17952SDoug Anderson * causing all future tuning phases to report 206846d17952SDoug Anderson * failure. 206946d17952SDoug Anderson * 207046d17952SDoug Anderson * In such case controller will move into a data 207146d17952SDoug Anderson * transfer state after a response error or 207246d17952SDoug Anderson * response CRC error. Let's let that finish 207346d17952SDoug Anderson * before trying to send a stop, so we'll go to 207446d17952SDoug Anderson * STATE_SENDING_DATA. 207546d17952SDoug Anderson * 207646d17952SDoug Anderson * Although letting the data transfer take place 207746d17952SDoug Anderson * will waste a bit of time (we already know 207846d17952SDoug Anderson * the command was bad), it can't cause any 207946d17952SDoug Anderson * errors since it's possible it would have 208046d17952SDoug Anderson * taken place anyway if this tasklet got 208146d17952SDoug Anderson * delayed. Allowing the transfer to take place 208246d17952SDoug Anderson * avoids races and keeps things simple. 208346d17952SDoug Anderson */ 2084ba2d139bSDouglas Anderson if (err != -ETIMEDOUT) { 208546d17952SDoug Anderson state = STATE_SENDING_DATA; 208646d17952SDoug Anderson continue; 208746d17952SDoug Anderson } 208846d17952SDoug Anderson 208990c2143aSSeungwon Jeon send_stop_abort(host, data); 209025f8203bSVincent Whitchurch dw_mci_stop_dma(host); 209171abb133SSeungwon Jeon state = STATE_SENDING_STOP; 209271abb133SSeungwon Jeon break; 209371abb133SSeungwon Jeon } 209471abb133SSeungwon Jeon 2095e352c813SSeungwon Jeon if (!cmd->data || err) { 2096e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2097f95f3850SWill Newton goto unlock; 2098f95f3850SWill Newton } 2099f95f3850SWill Newton 2100f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 2101df561f66SGustavo A. R. Silva fallthrough; 2102f95f3850SWill Newton 2103f95f3850SWill Newton case STATE_SENDING_DATA: 21042aa35465SDoug Anderson /* 21052aa35465SDoug Anderson * We could get a data error and never a transfer 21062aa35465SDoug Anderson * complete so we'd better check for it here. 21072aa35465SDoug Anderson * 21082aa35465SDoug Anderson * Note that we don't really care if we also got a 21092aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 21102aa35465SDoug Anderson * abort won't hurt. 21112aa35465SDoug Anderson */ 2112f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 2113f95f3850SWill Newton &host->pending_events)) { 2114e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2115bdb9a90bSaddy ke SDMMC_INT_EBE))) 211690c2143aSSeungwon Jeon send_stop_abort(host, data); 211725f8203bSVincent Whitchurch dw_mci_stop_dma(host); 2118f95f3850SWill Newton state = STATE_DATA_ERROR; 2119f95f3850SWill Newton break; 2120f95f3850SWill Newton } 2121f95f3850SWill Newton 2122f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 212357e10486SAddy Ke &host->pending_events)) { 212457e10486SAddy Ke /* 212557e10486SAddy Ke * If all data-related interrupts don't come 212657e10486SAddy Ke * within the given time in reading data state. 212757e10486SAddy Ke */ 212816a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 212957e10486SAddy Ke dw_mci_set_drto(host); 2130f95f3850SWill Newton break; 213157e10486SAddy Ke } 2132f95f3850SWill Newton 2133f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 21342aa35465SDoug Anderson 21352aa35465SDoug Anderson /* 21362aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 21372aa35465SDoug Anderson * before the transfer completed. This might not have 21382aa35465SDoug Anderson * been caught by the check above because the interrupt 21392aa35465SDoug Anderson * could have gone off between the previous check and 21402aa35465SDoug Anderson * the check for transfer complete. 21412aa35465SDoug Anderson * 21422aa35465SDoug Anderson * Technically this ought not be needed assuming we 21432aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 21442aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 21452aa35465SDoug Anderson * 21462aa35465SDoug Anderson * This has the advantage of sending the stop command. 21472aa35465SDoug Anderson */ 21482aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 21492aa35465SDoug Anderson &host->pending_events)) { 2150e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2151bdb9a90bSaddy ke SDMMC_INT_EBE))) 21522aa35465SDoug Anderson send_stop_abort(host, data); 215325f8203bSVincent Whitchurch dw_mci_stop_dma(host); 21542aa35465SDoug Anderson state = STATE_DATA_ERROR; 21552aa35465SDoug Anderson break; 21562aa35465SDoug Anderson } 2157f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 21582aa35465SDoug Anderson 2159df561f66SGustavo A. R. Silva fallthrough; 2160f95f3850SWill Newton 2161f95f3850SWill Newton case STATE_DATA_BUSY: 216293c23ae3SDouglas Anderson if (!dw_mci_clear_pending_data_complete(host)) { 216357e10486SAddy Ke /* 216457e10486SAddy Ke * If data error interrupt comes but data over 216557e10486SAddy Ke * interrupt doesn't come within the given time. 216657e10486SAddy Ke * in reading data state. 216757e10486SAddy Ke */ 216816a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 216957e10486SAddy Ke dw_mci_set_drto(host); 2170f95f3850SWill Newton break; 217157e10486SAddy Ke } 2172f95f3850SWill Newton 21732b8ac062SVincent Whitchurch dw_mci_stop_fault_timer(host); 2174f95f3850SWill Newton host->data = NULL; 2175f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2176e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 2177f95f3850SWill Newton 2178e352c813SSeungwon Jeon if (!err) { 2179e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 218017c8bc85SSachin Kamat if (mrq->sbc && data->stop) 2181053b3ce6SSeungwon Jeon data->stop->error = 0; 2182e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2183053b3ce6SSeungwon Jeon goto unlock; 2184053b3ce6SSeungwon Jeon } 2185053b3ce6SSeungwon Jeon 218690c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 2187e352c813SSeungwon Jeon if (data->stop) 218890c2143aSSeungwon Jeon send_stop_abort(host, data); 21892aa35465SDoug Anderson } else { 21902aa35465SDoug Anderson /* 21912aa35465SDoug Anderson * If we don't have a command complete now we'll 21922aa35465SDoug Anderson * never get one since we just reset everything; 21932aa35465SDoug Anderson * better end the request. 21942aa35465SDoug Anderson * 21952aa35465SDoug Anderson * If we do have a command complete we'll fall 21962aa35465SDoug Anderson * through to the SENDING_STOP command and 21972aa35465SDoug Anderson * everything will be peachy keen. 21982aa35465SDoug Anderson */ 21992aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 22002aa35465SDoug Anderson &host->pending_events)) { 22012aa35465SDoug Anderson host->cmd = NULL; 22022aa35465SDoug Anderson dw_mci_request_end(host, mrq); 22032aa35465SDoug Anderson goto unlock; 22042aa35465SDoug Anderson } 220590c2143aSSeungwon Jeon } 2206e352c813SSeungwon Jeon 2207e352c813SSeungwon Jeon /* 2208e352c813SSeungwon Jeon * If err has non-zero, 2209e352c813SSeungwon Jeon * stop-abort command has been already issued. 2210e352c813SSeungwon Jeon */ 2211e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 2212e352c813SSeungwon Jeon 2213df561f66SGustavo A. R. Silva fallthrough; 2214f95f3850SWill Newton 2215f95f3850SWill Newton case STATE_SENDING_STOP: 22168892b705SDouglas Anderson if (!dw_mci_clear_pending_cmd_complete(host)) 2217f95f3850SWill Newton break; 2218f95f3850SWill Newton 221971abb133SSeungwon Jeon /* CMD error in data command */ 222031bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 22213a33a94cSSonny Rao dw_mci_reset(host); 222271abb133SSeungwon Jeon 22232b8ac062SVincent Whitchurch dw_mci_stop_fault_timer(host); 2224f95f3850SWill Newton host->cmd = NULL; 222571abb133SSeungwon Jeon host->data = NULL; 222690c2143aSSeungwon Jeon 2227e13c3c08SJaehoon Chung if (!mrq->sbc && mrq->stop) 2228e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 222990c2143aSSeungwon Jeon else 223090c2143aSSeungwon Jeon host->cmd_status = 0; 223190c2143aSSeungwon Jeon 2232e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2233f95f3850SWill Newton goto unlock; 2234f95f3850SWill Newton 2235f95f3850SWill Newton case STATE_DATA_ERROR: 2236f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2237f95f3850SWill Newton &host->pending_events)) 2238f95f3850SWill Newton break; 2239f95f3850SWill Newton 2240f95f3850SWill Newton state = STATE_DATA_BUSY; 2241f95f3850SWill Newton break; 2242f95f3850SWill Newton } 2243f95f3850SWill Newton } while (state != prev_state); 2244f95f3850SWill Newton 2245f95f3850SWill Newton host->state = state; 2246f95f3850SWill Newton unlock: 2247f95f3850SWill Newton spin_unlock(&host->lock); 2248f95f3850SWill Newton 2249f95f3850SWill Newton } 2250f95f3850SWill Newton 225134b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 225234b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 225334b664a2SJames Hogan { 225434b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 225534b664a2SJames Hogan host->part_buf_count = cnt; 225634b664a2SJames Hogan } 225734b664a2SJames Hogan 225834b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 225934b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 226034b664a2SJames Hogan { 226134b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 226234b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 226334b664a2SJames Hogan host->part_buf_count += cnt; 226434b664a2SJames Hogan return cnt; 226534b664a2SJames Hogan } 226634b664a2SJames Hogan 226734b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 226834b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 226934b664a2SJames Hogan { 22700e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 227134b664a2SJames Hogan if (cnt) { 227234b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 227334b664a2SJames Hogan cnt); 227434b664a2SJames Hogan host->part_buf_count -= cnt; 227534b664a2SJames Hogan host->part_buf_start += cnt; 227634b664a2SJames Hogan } 227734b664a2SJames Hogan return cnt; 227834b664a2SJames Hogan } 227934b664a2SJames Hogan 228034b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 228134b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 228234b664a2SJames Hogan { 228334b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 228434b664a2SJames Hogan host->part_buf_start = cnt; 228534b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 228634b664a2SJames Hogan } 228734b664a2SJames Hogan 2288f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2289f95f3850SWill Newton { 2290cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2291cfbeb59cSMarkos Chandras int init_cnt = cnt; 2292cfbeb59cSMarkos Chandras 229334b664a2SJames Hogan /* try and push anything in the part_buf */ 229434b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 229534b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 22960e3a22c0SShawn Lin 229734b664a2SJames Hogan buf += len; 229834b664a2SJames Hogan cnt -= len; 2299cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 230076184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 230134b664a2SJames Hogan host->part_buf_count = 0; 230234b664a2SJames Hogan } 230334b664a2SJames Hogan } 230434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 230534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 230634b664a2SJames Hogan while (cnt >= 2) { 230734b664a2SJames Hogan u16 aligned_buf[64]; 230834b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 230934b664a2SJames Hogan int items = len >> 1; 231034b664a2SJames Hogan int i; 231134b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 231234b664a2SJames Hogan memcpy(aligned_buf, buf, len); 231334b664a2SJames Hogan buf += len; 231434b664a2SJames Hogan cnt -= len; 231534b664a2SJames Hogan /* push data from aligned buffer into fifo */ 231634b664a2SJames Hogan for (i = 0; i < items; ++i) 231776184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 231834b664a2SJames Hogan } 231934b664a2SJames Hogan } else 232034b664a2SJames Hogan #endif 232134b664a2SJames Hogan { 232234b664a2SJames Hogan u16 *pdata = buf; 23230e3a22c0SShawn Lin 232434b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 232576184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 232634b664a2SJames Hogan buf = pdata; 232734b664a2SJames Hogan } 232834b664a2SJames Hogan /* put anything remaining in the part_buf */ 232934b664a2SJames Hogan if (cnt) { 233034b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2331cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2332cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2333cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 233476184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2335f95f3850SWill Newton } 2336f95f3850SWill Newton } 2337f95f3850SWill Newton 2338f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2339f95f3850SWill Newton { 234034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 234134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 234234b664a2SJames Hogan while (cnt >= 2) { 234334b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 234434b664a2SJames Hogan u16 aligned_buf[64]; 234534b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 234634b664a2SJames Hogan int items = len >> 1; 234734b664a2SJames Hogan int i; 23480e3a22c0SShawn Lin 234934b664a2SJames Hogan for (i = 0; i < items; ++i) 235076184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 235134b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 235234b664a2SJames Hogan memcpy(buf, aligned_buf, len); 235334b664a2SJames Hogan buf += len; 235434b664a2SJames Hogan cnt -= len; 235534b664a2SJames Hogan } 235634b664a2SJames Hogan } else 235734b664a2SJames Hogan #endif 235834b664a2SJames Hogan { 235934b664a2SJames Hogan u16 *pdata = buf; 23600e3a22c0SShawn Lin 236134b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 236276184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 236334b664a2SJames Hogan buf = pdata; 236434b664a2SJames Hogan } 236534b664a2SJames Hogan if (cnt) { 236676184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 236734b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2368f95f3850SWill Newton } 2369f95f3850SWill Newton } 2370f95f3850SWill Newton 2371f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2372f95f3850SWill Newton { 2373cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2374cfbeb59cSMarkos Chandras int init_cnt = cnt; 2375cfbeb59cSMarkos Chandras 237634b664a2SJames Hogan /* try and push anything in the part_buf */ 237734b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 237834b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 23790e3a22c0SShawn Lin 238034b664a2SJames Hogan buf += len; 238134b664a2SJames Hogan cnt -= len; 2382cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 238376184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 238434b664a2SJames Hogan host->part_buf_count = 0; 238534b664a2SJames Hogan } 238634b664a2SJames Hogan } 238734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 238834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 238934b664a2SJames Hogan while (cnt >= 4) { 239034b664a2SJames Hogan u32 aligned_buf[32]; 239134b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 239234b664a2SJames Hogan int items = len >> 2; 239334b664a2SJames Hogan int i; 239434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 239534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 239634b664a2SJames Hogan buf += len; 239734b664a2SJames Hogan cnt -= len; 239834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 239934b664a2SJames Hogan for (i = 0; i < items; ++i) 240076184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 240134b664a2SJames Hogan } 240234b664a2SJames Hogan } else 240334b664a2SJames Hogan #endif 240434b664a2SJames Hogan { 240534b664a2SJames Hogan u32 *pdata = buf; 24060e3a22c0SShawn Lin 240734b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 240876184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 240934b664a2SJames Hogan buf = pdata; 241034b664a2SJames Hogan } 241134b664a2SJames Hogan /* put anything remaining in the part_buf */ 241234b664a2SJames Hogan if (cnt) { 241334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2414cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2415cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2416cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 241776184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2418f95f3850SWill Newton } 2419f95f3850SWill Newton } 2420f95f3850SWill Newton 2421f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2422f95f3850SWill Newton { 242334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 242434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 242534b664a2SJames Hogan while (cnt >= 4) { 242634b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 242734b664a2SJames Hogan u32 aligned_buf[32]; 242834b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 242934b664a2SJames Hogan int items = len >> 2; 243034b664a2SJames Hogan int i; 24310e3a22c0SShawn Lin 243234b664a2SJames Hogan for (i = 0; i < items; ++i) 243376184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 243434b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 243534b664a2SJames Hogan memcpy(buf, aligned_buf, len); 243634b664a2SJames Hogan buf += len; 243734b664a2SJames Hogan cnt -= len; 243834b664a2SJames Hogan } 243934b664a2SJames Hogan } else 244034b664a2SJames Hogan #endif 244134b664a2SJames Hogan { 244234b664a2SJames Hogan u32 *pdata = buf; 24430e3a22c0SShawn Lin 244434b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 244576184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 244634b664a2SJames Hogan buf = pdata; 244734b664a2SJames Hogan } 244834b664a2SJames Hogan if (cnt) { 244976184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 245034b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2451f95f3850SWill Newton } 2452f95f3850SWill Newton } 2453f95f3850SWill Newton 2454f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2455f95f3850SWill Newton { 2456cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2457cfbeb59cSMarkos Chandras int init_cnt = cnt; 2458cfbeb59cSMarkos Chandras 245934b664a2SJames Hogan /* try and push anything in the part_buf */ 246034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 246134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 24620e3a22c0SShawn Lin 246334b664a2SJames Hogan buf += len; 246434b664a2SJames Hogan cnt -= len; 2465c09fbd74SSeungwon Jeon 2466cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 246776184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 246834b664a2SJames Hogan host->part_buf_count = 0; 246934b664a2SJames Hogan } 247034b664a2SJames Hogan } 247134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 247234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 247334b664a2SJames Hogan while (cnt >= 8) { 247434b664a2SJames Hogan u64 aligned_buf[16]; 247534b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 247634b664a2SJames Hogan int items = len >> 3; 247734b664a2SJames Hogan int i; 247834b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 247934b664a2SJames Hogan memcpy(aligned_buf, buf, len); 248034b664a2SJames Hogan buf += len; 248134b664a2SJames Hogan cnt -= len; 248234b664a2SJames Hogan /* push data from aligned buffer into fifo */ 248334b664a2SJames Hogan for (i = 0; i < items; ++i) 248476184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 248534b664a2SJames Hogan } 248634b664a2SJames Hogan } else 248734b664a2SJames Hogan #endif 248834b664a2SJames Hogan { 248934b664a2SJames Hogan u64 *pdata = buf; 24900e3a22c0SShawn Lin 249134b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 249276184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 249334b664a2SJames Hogan buf = pdata; 249434b664a2SJames Hogan } 249534b664a2SJames Hogan /* put anything remaining in the part_buf */ 249634b664a2SJames Hogan if (cnt) { 249734b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2498cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2499cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2500cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 250176184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2502f95f3850SWill Newton } 2503f95f3850SWill Newton } 2504f95f3850SWill Newton 2505f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2506f95f3850SWill Newton { 250734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 250834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 250934b664a2SJames Hogan while (cnt >= 8) { 251034b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 251134b664a2SJames Hogan u64 aligned_buf[16]; 251234b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 251334b664a2SJames Hogan int items = len >> 3; 251434b664a2SJames Hogan int i; 25150e3a22c0SShawn Lin 251634b664a2SJames Hogan for (i = 0; i < items; ++i) 251776184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 251876184ac1SBen Dooks 251934b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 252034b664a2SJames Hogan memcpy(buf, aligned_buf, len); 252134b664a2SJames Hogan buf += len; 252234b664a2SJames Hogan cnt -= len; 2523f95f3850SWill Newton } 252434b664a2SJames Hogan } else 252534b664a2SJames Hogan #endif 252634b664a2SJames Hogan { 252734b664a2SJames Hogan u64 *pdata = buf; 25280e3a22c0SShawn Lin 252934b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 253076184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 253134b664a2SJames Hogan buf = pdata; 253234b664a2SJames Hogan } 253334b664a2SJames Hogan if (cnt) { 253476184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 253534b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 253634b664a2SJames Hogan } 253734b664a2SJames Hogan } 253834b664a2SJames Hogan 253934b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 254034b664a2SJames Hogan { 254134b664a2SJames Hogan int len; 254234b664a2SJames Hogan 254334b664a2SJames Hogan /* get remaining partial bytes */ 254434b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 254534b664a2SJames Hogan if (unlikely(len == cnt)) 254634b664a2SJames Hogan return; 254734b664a2SJames Hogan buf += len; 254834b664a2SJames Hogan cnt -= len; 254934b664a2SJames Hogan 255034b664a2SJames Hogan /* get the rest of the data */ 255134b664a2SJames Hogan host->pull_data(host, buf, cnt); 2552f95f3850SWill Newton } 2553f95f3850SWill Newton 255487a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2555f95f3850SWill Newton { 2556f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2557f9c2a0dcSSeungwon Jeon void *buf; 2558f9c2a0dcSSeungwon Jeon unsigned int offset; 2559f95f3850SWill Newton struct mmc_data *data = host->data; 2560f95f3850SWill Newton int shift = host->data_shift; 2561f95f3850SWill Newton u32 status; 25623e4b0d8bSMarkos Chandras unsigned int len; 2563f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2564f95f3850SWill Newton 2565f95f3850SWill Newton do { 2566f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2567f9c2a0dcSSeungwon Jeon goto done; 2568f95f3850SWill Newton 25694225fc85SImre Deak host->sg = sg_miter->piter.sg; 2570f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2571f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2572f9c2a0dcSSeungwon Jeon offset = 0; 2573f9c2a0dcSSeungwon Jeon 2574f9c2a0dcSSeungwon Jeon do { 2575f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2576f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2577f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2578f9c2a0dcSSeungwon Jeon if (!len) 2579f9c2a0dcSSeungwon Jeon break; 2580f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 25813e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2582f95f3850SWill Newton offset += len; 2583f9c2a0dcSSeungwon Jeon remain -= len; 2584f9c2a0dcSSeungwon Jeon } while (remain); 2585f95f3850SWill Newton 2586e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2587f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2588f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 258987a74d39SKyoungil Kim /* if the RXDR is ready read again */ 259087a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 259187a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2592f9c2a0dcSSeungwon Jeon 2593f9c2a0dcSSeungwon Jeon if (!remain) { 2594f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2595f9c2a0dcSSeungwon Jeon goto done; 2596f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2597f9c2a0dcSSeungwon Jeon } 2598f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2599f95f3850SWill Newton return; 2600f95f3850SWill Newton 2601f95f3850SWill Newton done: 2602f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2603f9c2a0dcSSeungwon Jeon host->sg = NULL; 26040e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2605f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2606f95f3850SWill Newton } 2607f95f3850SWill Newton 2608f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2609f95f3850SWill Newton { 2610f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2611f9c2a0dcSSeungwon Jeon void *buf; 2612f9c2a0dcSSeungwon Jeon unsigned int offset; 2613f95f3850SWill Newton struct mmc_data *data = host->data; 2614f95f3850SWill Newton int shift = host->data_shift; 2615f95f3850SWill Newton u32 status; 26163e4b0d8bSMarkos Chandras unsigned int len; 2617f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2618f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2619f95f3850SWill Newton 2620f95f3850SWill Newton do { 2621f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2622f9c2a0dcSSeungwon Jeon goto done; 2623f95f3850SWill Newton 26244225fc85SImre Deak host->sg = sg_miter->piter.sg; 2625f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2626f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2627f9c2a0dcSSeungwon Jeon offset = 0; 2628f9c2a0dcSSeungwon Jeon 2629f9c2a0dcSSeungwon Jeon do { 2630f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2631f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2632f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2633f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2634f9c2a0dcSSeungwon Jeon if (!len) 2635f9c2a0dcSSeungwon Jeon break; 2636f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 26373e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2638f95f3850SWill Newton offset += len; 2639f9c2a0dcSSeungwon Jeon remain -= len; 2640f9c2a0dcSSeungwon Jeon } while (remain); 2641f95f3850SWill Newton 2642e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2643f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2644f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2645f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2646f9c2a0dcSSeungwon Jeon 2647f9c2a0dcSSeungwon Jeon if (!remain) { 2648f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2649f9c2a0dcSSeungwon Jeon goto done; 2650f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2651f9c2a0dcSSeungwon Jeon } 2652f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2653f95f3850SWill Newton return; 2654f95f3850SWill Newton 2655f95f3850SWill Newton done: 2656f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2657f9c2a0dcSSeungwon Jeon host->sg = NULL; 26580e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2659f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2660f95f3850SWill Newton } 2661f95f3850SWill Newton 2662f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2663f95f3850SWill Newton { 26640363b12dSDouglas Anderson del_timer(&host->cto_timer); 26650363b12dSDouglas Anderson 2666f95f3850SWill Newton if (!host->cmd_status) 2667f95f3850SWill Newton host->cmd_status = status; 2668f95f3850SWill Newton 26690e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2670f95f3850SWill Newton 2671f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2672f95f3850SWill Newton tasklet_schedule(&host->tasklet); 26732b8ac062SVincent Whitchurch 26742b8ac062SVincent Whitchurch dw_mci_start_fault_timer(host); 2675f95f3850SWill Newton } 2676f95f3850SWill Newton 26776130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 26786130e7a9SDoug Anderson { 2679b23475faSJaehoon Chung struct dw_mci_slot *slot = host->slot; 26806130e7a9SDoug Anderson 26816130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 26826130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 26836130e7a9SDoug Anderson } 26846130e7a9SDoug Anderson 2685f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2686f95f3850SWill Newton { 2687f95f3850SWill Newton struct dw_mci *host = dev_id; 2688182c9081SSeungwon Jeon u32 pending; 2689b23475faSJaehoon Chung struct dw_mci_slot *slot = host->slot; 2690f95f3850SWill Newton 2691f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2692f95f3850SWill Newton 2693476d79f1SDoug Anderson if (pending) { 269401730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 269501730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 269601730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 269701730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 269801730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 269949ba0302SDoug Anderson 270049ba0302SDoug Anderson /* 270149ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 270249ba0302SDoug Anderson * off after the lock is released, so safe to delete. 270349ba0302SDoug Anderson */ 27049f7d4c91STian Tao spin_lock(&host->irq_lock); 270501730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 27069f7d4c91STian Tao spin_unlock(&host->irq_lock); 270749ba0302SDoug Anderson 270849ba0302SDoug Anderson del_timer(&host->cmd11_timer); 270901730558SDoug Anderson } 271001730558SDoug Anderson 2711f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 27129f7d4c91STian Tao spin_lock(&host->irq_lock); 27138892b705SDouglas Anderson 271403de1921SAddy Ke del_timer(&host->cto_timer); 2715f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2716182c9081SSeungwon Jeon host->cmd_status = pending; 27170e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2718f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 27198892b705SDouglas Anderson 27209f7d4c91STian Tao spin_unlock(&host->irq_lock); 2721f95f3850SWill Newton } 2722f95f3850SWill Newton 2723f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2724f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2725f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2726182c9081SSeungwon Jeon host->data_status = pending; 27270e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2728f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2729f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2730f95f3850SWill Newton } 2731f95f3850SWill Newton 2732f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 27339f7d4c91STian Tao spin_lock(&host->irq_lock); 273493c23ae3SDouglas Anderson 273557e10486SAddy Ke del_timer(&host->dto_timer); 273657e10486SAddy Ke 2737f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2738f95f3850SWill Newton if (!host->data_status) 2739182c9081SSeungwon Jeon host->data_status = pending; 27400e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2741f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2742f95f3850SWill Newton if (host->sg != NULL) 274387a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2744f95f3850SWill Newton } 2745f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2746f95f3850SWill Newton tasklet_schedule(&host->tasklet); 274793c23ae3SDouglas Anderson 27489f7d4c91STian Tao spin_unlock(&host->irq_lock); 2749f95f3850SWill Newton } 2750f95f3850SWill Newton 2751f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2752f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2753b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 275487a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2755f95f3850SWill Newton } 2756f95f3850SWill Newton 2757f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2758f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2759b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2760f95f3850SWill Newton dw_mci_write_data_pio(host); 2761f95f3850SWill Newton } 2762f95f3850SWill Newton 2763f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 27649f7d4c91STian Tao spin_lock(&host->irq_lock); 27658892b705SDouglas Anderson 2766f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2767182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 27688892b705SDouglas Anderson 27699f7d4c91STian Tao spin_unlock(&host->irq_lock); 2770f95f3850SWill Newton } 2771f95f3850SWill Newton 2772f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2773f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 27746130e7a9SDoug Anderson dw_mci_handle_cd(host); 2775f95f3850SWill Newton } 2776f95f3850SWill Newton 277776756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 277876756234SAddy Ke mci_writel(host, RINTSTS, 277976756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 278032dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 0); 278132dba737SUlf Hansson sdio_signal_irq(slot->mmc); 27821a5c8e1fSShashidhar Hiremath } 27831a5c8e1fSShashidhar Hiremath 27841fb5f68aSMarkos Chandras } 2785f95f3850SWill Newton 27863fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 27873fc7eaefSShawn Lin return IRQ_HANDLED; 27883fc7eaefSShawn Lin 27893fc7eaefSShawn Lin /* Handle IDMA interrupts */ 279069d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 279169d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 279269d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 279369d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 279469d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 279569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2796faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 27973fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 279869d99fdcSPrabu Thangamuthu } 279969d99fdcSPrabu Thangamuthu } else { 2800f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2801f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 280269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 280369d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2804f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2805faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 28063fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2807f95f3850SWill Newton } 280869d99fdcSPrabu Thangamuthu } 2809f95f3850SWill Newton 2810f95f3850SWill Newton return IRQ_HANDLED; 2811f95f3850SWill Newton } 2812f95f3850SWill Newton 2813a4faa492SShawn Lin static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) 2814a4faa492SShawn Lin { 2815a4faa492SShawn Lin struct dw_mci *host = slot->host; 2816a4faa492SShawn Lin const struct dw_mci_drv_data *drv_data = host->drv_data; 2817a4faa492SShawn Lin struct mmc_host *mmc = slot->mmc; 2818a4faa492SShawn Lin int ctrl_id; 2819a4faa492SShawn Lin 2820a4faa492SShawn Lin if (host->pdata->caps) 2821a4faa492SShawn Lin mmc->caps = host->pdata->caps; 2822a4faa492SShawn Lin 2823a4faa492SShawn Lin if (host->pdata->pm_caps) 2824a4faa492SShawn Lin mmc->pm_caps = host->pdata->pm_caps; 2825a4faa492SShawn Lin 2826a4faa492SShawn Lin if (host->dev->of_node) { 2827a4faa492SShawn Lin ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2828a4faa492SShawn Lin if (ctrl_id < 0) 2829a4faa492SShawn Lin ctrl_id = 0; 2830a4faa492SShawn Lin } else { 2831a4faa492SShawn Lin ctrl_id = to_platform_device(host->dev)->id; 2832a4faa492SShawn Lin } 28330d84b9e5SShawn Lin 28340d84b9e5SShawn Lin if (drv_data && drv_data->caps) { 28350d84b9e5SShawn Lin if (ctrl_id >= drv_data->num_caps) { 28360d84b9e5SShawn Lin dev_err(host->dev, "invalid controller id %d\n", 28370d84b9e5SShawn Lin ctrl_id); 28380d84b9e5SShawn Lin return -EINVAL; 28390d84b9e5SShawn Lin } 2840a4faa492SShawn Lin mmc->caps |= drv_data->caps[ctrl_id]; 28410d84b9e5SShawn Lin } 2842a4faa492SShawn Lin 2843a4faa492SShawn Lin if (host->pdata->caps2) 2844a4faa492SShawn Lin mmc->caps2 = host->pdata->caps2; 2845a4faa492SShawn Lin 284686b93a48SJaehoon Chung mmc->f_min = DW_MCI_FREQ_MIN; 284786b93a48SJaehoon Chung if (!mmc->f_max) 284886b93a48SJaehoon Chung mmc->f_max = DW_MCI_FREQ_MAX; 284986b93a48SJaehoon Chung 2850a4faa492SShawn Lin /* Process SDIO IRQs through the sdio_irq_work. */ 2851a4faa492SShawn Lin if (mmc->caps & MMC_CAP_SDIO_IRQ) 2852a4faa492SShawn Lin mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2853a4faa492SShawn Lin 2854a4faa492SShawn Lin return 0; 2855a4faa492SShawn Lin } 2856a4faa492SShawn Lin 2857e4a65ef7SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host) 2858f95f3850SWill Newton { 2859f95f3850SWill Newton struct mmc_host *mmc; 2860f95f3850SWill Newton struct dw_mci_slot *slot; 2861a4faa492SShawn Lin int ret; 2862f95f3850SWill Newton 28634a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2864f95f3850SWill Newton if (!mmc) 2865f95f3850SWill Newton return -ENOMEM; 2866f95f3850SWill Newton 2867f95f3850SWill Newton slot = mmc_priv(mmc); 2868e4a65ef7SJaehoon Chung slot->id = 0; 2869e4a65ef7SJaehoon Chung slot->sdio_id = host->sdio_id0 + slot->id; 2870f95f3850SWill Newton slot->mmc = mmc; 2871f95f3850SWill Newton slot->host = host; 2872b23475faSJaehoon Chung host->slot = slot; 2873f95f3850SWill Newton 2874f95f3850SWill Newton mmc->ops = &dw_mci_ops; 2875f95f3850SWill Newton 287651da2240SYuvaraj CD /*if there are external regulators, get them*/ 287751da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 28780f3a47b8SWolfram Sang if (ret) 28793cf890fcSDoug Anderson goto err_host_allocated; 288051da2240SYuvaraj CD 288151da2240SYuvaraj CD if (!mmc->ocr_avail) 2882f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2883f95f3850SWill Newton 28843cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 28853cf890fcSDoug Anderson if (ret) 28863cf890fcSDoug Anderson goto err_host_allocated; 2887f95f3850SWill Newton 2888a4faa492SShawn Lin ret = dw_mci_init_slot_caps(slot); 2889a4faa492SShawn Lin if (ret) 2890a4faa492SShawn Lin goto err_host_allocated; 289132dba737SUlf Hansson 2892f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 28933fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2894a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2895225faf87SJaehoon Chung mmc->max_blk_size = 65535; 2896575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 28971a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 28981a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 28993fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 29003fc7eaefSShawn Lin mmc->max_segs = 64; 2901225faf87SJaehoon Chung mmc->max_blk_size = 65535; 29023fc7eaefSShawn Lin mmc->max_blk_count = 65535; 29033fc7eaefSShawn Lin mmc->max_req_size = 29043fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 29053fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2906575c319dSHeiko Stuebner } else { 29073fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2908f95f3850SWill Newton mmc->max_segs = 64; 2909225faf87SJaehoon Chung mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2910f95f3850SWill Newton mmc->max_blk_count = 512; 2911575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2912575c319dSHeiko Stuebner mmc->max_blk_count; 2913f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2914575c319dSHeiko Stuebner } 2915f95f3850SWill Newton 2916c0834a58SShawn Lin dw_mci_get_cd(mmc); 2917ae0eb348SJaehoon Chung 29180cea529dSJaehoon Chung ret = mmc_add_host(mmc); 29190cea529dSJaehoon Chung if (ret) 29203cf890fcSDoug Anderson goto err_host_allocated; 2921f95f3850SWill Newton 2922f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2923f95f3850SWill Newton dw_mci_init_debugfs(slot); 2924f95f3850SWill Newton #endif 2925f95f3850SWill Newton 2926f95f3850SWill Newton return 0; 2927800d78bfSThomas Abraham 29283cf890fcSDoug Anderson err_host_allocated: 2929800d78bfSThomas Abraham mmc_free_host(mmc); 293051da2240SYuvaraj CD return ret; 2931f95f3850SWill Newton } 2932f95f3850SWill Newton 2933e4a65ef7SJaehoon Chung static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2934f95f3850SWill Newton { 2935f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2936f95f3850SWill Newton mmc_remove_host(slot->mmc); 2937b23475faSJaehoon Chung slot->host->slot = NULL; 2938f95f3850SWill Newton mmc_free_host(slot->mmc); 2939f95f3850SWill Newton } 2940f95f3850SWill Newton 2941f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2942f95f3850SWill Newton { 294369d99fdcSPrabu Thangamuthu int addr_config; 29443fc7eaefSShawn Lin struct device *dev = host->dev; 29453fc7eaefSShawn Lin 29463fc7eaefSShawn Lin /* 29473fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 29483fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 29493fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 29503fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 29513fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 29523fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 29533fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 29543fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 29553fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 29563fc7eaefSShawn Lin */ 29573fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 29583fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 29593fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 29603fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 29613fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 29623fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 29633fc7eaefSShawn Lin } else { 29643fc7eaefSShawn Lin goto no_dma; 29653fc7eaefSShawn Lin } 29663fc7eaefSShawn Lin 29673fc7eaefSShawn Lin /* Determine which DMA interface to use */ 29683fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 29693fc7eaefSShawn Lin /* 29703fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 29713fc7eaefSShawn Lin * IDMAC address bus width 29723fc7eaefSShawn Lin */ 297370692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 297469d99fdcSPrabu Thangamuthu 297569d99fdcSPrabu Thangamuthu if (addr_config == 1) { 297669d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 297769d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 29783fc7eaefSShawn Lin dev_info(host->dev, 29793fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 298069d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 29813fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 29823fc7eaefSShawn Lin DMA_BIT_MASK(64)); 298369d99fdcSPrabu Thangamuthu } else { 298469d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 298569d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 29863fc7eaefSShawn Lin dev_info(host->dev, 29873fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 298869d99fdcSPrabu Thangamuthu } 298969d99fdcSPrabu Thangamuthu 2990f95f3850SWill Newton /* Alloc memory for sg translation */ 2991cc190d4cSShawn Lin host->sg_cpu = dmam_alloc_coherent(host->dev, 2992cc190d4cSShawn Lin DESC_RING_BUF_SZ, 2993f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2994f95f3850SWill Newton if (!host->sg_cpu) { 29953fc7eaefSShawn Lin dev_err(host->dev, 29963fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2997f95f3850SWill Newton __func__); 2998f95f3850SWill Newton goto no_dma; 2999f95f3850SWill Newton } 3000f95f3850SWill Newton 3001f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 300200956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 30033fc7eaefSShawn Lin } else { 30043fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 3005852ff5feSDavid Woods if ((device_property_read_string_array(dev, "dma-names", 3006852ff5feSDavid Woods NULL, 0) < 0) || 3007852ff5feSDavid Woods !device_property_present(dev, "dmas")) { 3008f95f3850SWill Newton goto no_dma; 30093fc7eaefSShawn Lin } 30103fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 30113fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 30123fc7eaefSShawn Lin } 3013f95f3850SWill Newton 3014e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 3015e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 3016f95f3850SWill Newton if (host->dma_ops->init(host)) { 30170e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 30180e3a22c0SShawn Lin __func__); 3019f95f3850SWill Newton goto no_dma; 3020f95f3850SWill Newton } 3021f95f3850SWill Newton } else { 30224a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 3023f95f3850SWill Newton goto no_dma; 3024f95f3850SWill Newton } 3025f95f3850SWill Newton 3026f95f3850SWill Newton return; 3027f95f3850SWill Newton 3028f95f3850SWill Newton no_dma: 30294a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 30303fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 3031f95f3850SWill Newton } 3032f95f3850SWill Newton 303337977729SKees Cook static void dw_mci_cmd11_timer(struct timer_list *t) 30345c935165SDoug Anderson { 303537977729SKees Cook struct dw_mci *host = from_timer(host, t, cmd11_timer); 30365c935165SDoug Anderson 3037fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 3038fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 3039fd674198SDoug Anderson return; 3040fd674198SDoug Anderson } 30415c935165SDoug Anderson 30425c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 30435c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 30445c935165SDoug Anderson tasklet_schedule(&host->tasklet); 30455c935165SDoug Anderson } 30465c935165SDoug Anderson 304737977729SKees Cook static void dw_mci_cto_timer(struct timer_list *t) 304803de1921SAddy Ke { 304937977729SKees Cook struct dw_mci *host = from_timer(host, t, cto_timer); 30508892b705SDouglas Anderson unsigned long irqflags; 30518892b705SDouglas Anderson u32 pending; 305203de1921SAddy Ke 30538892b705SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 30548892b705SDouglas Anderson 30558892b705SDouglas Anderson /* 30568892b705SDouglas Anderson * If somehow we have very bad interrupt latency it's remotely possible 30578892b705SDouglas Anderson * that the timer could fire while the interrupt is still pending or 30588892b705SDouglas Anderson * while the interrupt is midway through running. Let's be paranoid 30598892b705SDouglas Anderson * and detect those two cases. Note that this is paranoia is somewhat 30608892b705SDouglas Anderson * justified because in this function we don't actually cancel the 30618892b705SDouglas Anderson * pending command in the controller--we just assume it will never come. 30628892b705SDouglas Anderson */ 30638892b705SDouglas Anderson pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 30648892b705SDouglas Anderson if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 30658892b705SDouglas Anderson /* The interrupt should fire; no need to act but we can warn */ 30668892b705SDouglas Anderson dev_warn(host->dev, "Unexpected interrupt latency\n"); 30678892b705SDouglas Anderson goto exit; 30688892b705SDouglas Anderson } 30698892b705SDouglas Anderson if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 30708892b705SDouglas Anderson /* Presumably interrupt handler couldn't delete the timer */ 30718892b705SDouglas Anderson dev_warn(host->dev, "CTO timeout when already completed\n"); 30728892b705SDouglas Anderson goto exit; 30738892b705SDouglas Anderson } 30748892b705SDouglas Anderson 30758892b705SDouglas Anderson /* 30768892b705SDouglas Anderson * Continued paranoia to make sure we're in the state we expect. 30778892b705SDouglas Anderson * This paranoia isn't really justified but it seems good to be safe. 30788892b705SDouglas Anderson */ 307903de1921SAddy Ke switch (host->state) { 308003de1921SAddy Ke case STATE_SENDING_CMD11: 308103de1921SAddy Ke case STATE_SENDING_CMD: 308203de1921SAddy Ke case STATE_SENDING_STOP: 308303de1921SAddy Ke /* 308403de1921SAddy Ke * If CMD_DONE interrupt does NOT come in sending command 308503de1921SAddy Ke * state, we should notify the driver to terminate current 308603de1921SAddy Ke * transfer and report a command timeout to the core. 308703de1921SAddy Ke */ 308803de1921SAddy Ke host->cmd_status = SDMMC_INT_RTO; 308903de1921SAddy Ke set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 309003de1921SAddy Ke tasklet_schedule(&host->tasklet); 309103de1921SAddy Ke break; 309203de1921SAddy Ke default: 309303de1921SAddy Ke dev_warn(host->dev, "Unexpected command timeout, state %d\n", 309403de1921SAddy Ke host->state); 309503de1921SAddy Ke break; 309603de1921SAddy Ke } 30978892b705SDouglas Anderson 30988892b705SDouglas Anderson exit: 30998892b705SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 310003de1921SAddy Ke } 310103de1921SAddy Ke 310237977729SKees Cook static void dw_mci_dto_timer(struct timer_list *t) 310357e10486SAddy Ke { 310437977729SKees Cook struct dw_mci *host = from_timer(host, t, dto_timer); 310593c23ae3SDouglas Anderson unsigned long irqflags; 310693c23ae3SDouglas Anderson u32 pending; 310757e10486SAddy Ke 310893c23ae3SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 310993c23ae3SDouglas Anderson 311093c23ae3SDouglas Anderson /* 311193c23ae3SDouglas Anderson * The DTO timer is much longer than the CTO timer, so it's even less 311293c23ae3SDouglas Anderson * likely that we'll these cases, but it pays to be paranoid. 311393c23ae3SDouglas Anderson */ 311493c23ae3SDouglas Anderson pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 311593c23ae3SDouglas Anderson if (pending & SDMMC_INT_DATA_OVER) { 311693c23ae3SDouglas Anderson /* The interrupt should fire; no need to act but we can warn */ 311793c23ae3SDouglas Anderson dev_warn(host->dev, "Unexpected data interrupt latency\n"); 311893c23ae3SDouglas Anderson goto exit; 311993c23ae3SDouglas Anderson } 312093c23ae3SDouglas Anderson if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 312193c23ae3SDouglas Anderson /* Presumably interrupt handler couldn't delete the timer */ 312293c23ae3SDouglas Anderson dev_warn(host->dev, "DTO timeout when already completed\n"); 312393c23ae3SDouglas Anderson goto exit; 312493c23ae3SDouglas Anderson } 312593c23ae3SDouglas Anderson 312693c23ae3SDouglas Anderson /* 312793c23ae3SDouglas Anderson * Continued paranoia to make sure we're in the state we expect. 312893c23ae3SDouglas Anderson * This paranoia isn't really justified but it seems good to be safe. 312993c23ae3SDouglas Anderson */ 313057e10486SAddy Ke switch (host->state) { 313157e10486SAddy Ke case STATE_SENDING_DATA: 313257e10486SAddy Ke case STATE_DATA_BUSY: 313357e10486SAddy Ke /* 313457e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 313557e10486SAddy Ke * we should notify the driver to terminate current transfer 313657e10486SAddy Ke * and report a data timeout to the core. 313757e10486SAddy Ke */ 313857e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 313957e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 314057e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 314157e10486SAddy Ke tasklet_schedule(&host->tasklet); 314257e10486SAddy Ke break; 314357e10486SAddy Ke default: 314493c23ae3SDouglas Anderson dev_warn(host->dev, "Unexpected data timeout, state %d\n", 314593c23ae3SDouglas Anderson host->state); 314657e10486SAddy Ke break; 314757e10486SAddy Ke } 314893c23ae3SDouglas Anderson 314993c23ae3SDouglas Anderson exit: 315093c23ae3SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 315157e10486SAddy Ke } 315257e10486SAddy Ke 3153c91eab4bSThomas Abraham #ifdef CONFIG_OF 3154c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3155c91eab4bSThomas Abraham { 3156c91eab4bSThomas Abraham struct dw_mci_board *pdata; 3157c91eab4bSThomas Abraham struct device *dev = host->dev; 3158e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 3159e8cc37b8SShawn Lin int ret; 31603c6d89eaSDoug Anderson u32 clock_frequency; 3161c91eab4bSThomas Abraham 3162c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3163bf3707eaSBeomho Seo if (!pdata) 3164c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 3165c91eab4bSThomas Abraham 3166d6786fefSGuodong Xu /* find reset controller when exist */ 3167a93d6f31SPhilipp Zabel pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3168baf6fe40SPhilipp Zabel if (IS_ERR(pdata->rstc)) 3169baf6fe40SPhilipp Zabel return ERR_CAST(pdata->rstc); 3170d6786fefSGuodong Xu 3171852ff5feSDavid Woods if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 31720e3a22c0SShawn Lin dev_info(dev, 31730e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 3174c91eab4bSThomas Abraham 3175852ff5feSDavid Woods device_property_read_u32(dev, "card-detect-delay", 3176852ff5feSDavid Woods &pdata->detect_delay_ms); 3177c91eab4bSThomas Abraham 3178852ff5feSDavid Woods device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3179a0361c1aSJun Nie 3180852ff5feSDavid Woods if (device_property_present(dev, "fifo-watermark-aligned")) 3181d6fced83SJun Nie host->wm_aligned = true; 3182d6fced83SJun Nie 3183852ff5feSDavid Woods if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 31843c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 31853c6d89eaSDoug Anderson 3186cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 3187cb27a843SJames Hogan ret = drv_data->parse_dt(host); 3188800d78bfSThomas Abraham if (ret) 3189800d78bfSThomas Abraham return ERR_PTR(ret); 3190800d78bfSThomas Abraham } 3191800d78bfSThomas Abraham 3192c91eab4bSThomas Abraham return pdata; 3193c91eab4bSThomas Abraham } 3194c91eab4bSThomas Abraham 3195c91eab4bSThomas Abraham #else /* CONFIG_OF */ 3196c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3197c91eab4bSThomas Abraham { 3198c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 3199c91eab4bSThomas Abraham } 3200c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 3201c91eab4bSThomas Abraham 3202fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 3203fa0c3283SDoug Anderson { 3204fa0c3283SDoug Anderson unsigned long irqflags; 3205fa0c3283SDoug Anderson u32 temp; 3206fa0c3283SDoug Anderson 3207e8cc37b8SShawn Lin /* 3208e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 3209e8cc37b8SShawn Lin * as well as broken card detection is found. 3210e8cc37b8SShawn Lin */ 3211e47c0b96SJaehoon Chung if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3212e8cc37b8SShawn Lin return; 3213fa0c3283SDoug Anderson 3214e47c0b96SJaehoon Chung if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3215fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 3216fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 3217fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 3218fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 3219fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 3220fa0c3283SDoug Anderson } 322158870241SJaehoon Chung } 3222fa0c3283SDoug Anderson 322362ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 3224f95f3850SWill Newton { 3225e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 322662ca8034SShashidhar Hiremath int width, i, ret = 0; 3227f95f3850SWill Newton u32 fifo_size; 3228f95f3850SWill Newton 3229c91eab4bSThomas Abraham if (!host->pdata) { 3230c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 3231308d2722SKrzysztof Kozlowski if (IS_ERR(host->pdata)) 3232308d2722SKrzysztof Kozlowski return dev_err_probe(host->dev, PTR_ERR(host->pdata), 3233308d2722SKrzysztof Kozlowski "platform data not available\n"); 3234f95f3850SWill Newton } 3235f95f3850SWill Newton 3236780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 3237f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 3238f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 3239f90a0612SThomas Abraham } else { 3240f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 3241f90a0612SThomas Abraham if (ret) { 3242f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 3243f90a0612SThomas Abraham return ret; 3244f90a0612SThomas Abraham } 3245f95f3850SWill Newton } 3246f95f3850SWill Newton 3247780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3248f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 3249f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 32503c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 3251f90a0612SThomas Abraham } else { 3252f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 3253f90a0612SThomas Abraham if (ret) { 3254f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 3255f90a0612SThomas Abraham goto err_clk_biu; 3256f90a0612SThomas Abraham } 3257f90a0612SThomas Abraham 32583c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 32593c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 32603c6d89eaSDoug Anderson if (ret) 32613c6d89eaSDoug Anderson dev_warn(host->dev, 3262612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 32633c6d89eaSDoug Anderson host->pdata->bus_hz); 32643c6d89eaSDoug Anderson } 3265f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 32663c6d89eaSDoug Anderson } 3267f90a0612SThomas Abraham 3268612de4c1SJaehoon Chung if (!host->bus_hz) { 3269612de4c1SJaehoon Chung dev_err(host->dev, 3270612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3271612de4c1SJaehoon Chung ret = -ENODEV; 3272612de4c1SJaehoon Chung goto err_clk_ciu; 3273612de4c1SJaehoon Chung } 3274612de4c1SJaehoon Chung 3275baf6fe40SPhilipp Zabel if (host->pdata->rstc) { 3276941e372dSliwei reset_control_assert(host->pdata->rstc); 3277941e372dSliwei usleep_range(10, 50); 3278941e372dSliwei reset_control_deassert(host->pdata->rstc); 3279941e372dSliwei } 3280941e372dSliwei 3281002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3282002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3283002f0d5cSYuvaraj Kumar C D if (ret) { 3284002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3285002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3286002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3287002f0d5cSYuvaraj Kumar C D } 3288002f0d5cSYuvaraj Kumar C D } 3289002f0d5cSYuvaraj Kumar C D 329037977729SKees Cook timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 329137977729SKees Cook timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 329237977729SKees Cook timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 329357e10486SAddy Ke 3294f95f3850SWill Newton spin_lock_init(&host->lock); 3295f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3296f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3297f95f3850SWill Newton 32982b8ac062SVincent Whitchurch dw_mci_init_fault(host); 32992b8ac062SVincent Whitchurch 3300f95f3850SWill Newton /* 3301f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3302f95f3850SWill Newton * the correct values. 3303f95f3850SWill Newton */ 330470692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3305f95f3850SWill Newton if (!i) { 3306f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3307f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3308f95f3850SWill Newton width = 16; 3309f95f3850SWill Newton host->data_shift = 1; 3310f95f3850SWill Newton } else if (i == 2) { 3311f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3312f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3313f95f3850SWill Newton width = 64; 3314f95f3850SWill Newton host->data_shift = 3; 3315f95f3850SWill Newton } else { 3316f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3317f95f3850SWill Newton WARN((i != 1), 3318f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3319f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3320f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3321f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3322f95f3850SWill Newton width = 32; 3323f95f3850SWill Newton host->data_shift = 2; 3324f95f3850SWill Newton } 3325f95f3850SWill Newton 3326f95f3850SWill Newton /* Reset all blocks */ 33273744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 33283744415cSShawn Lin ret = -ENODEV; 33293744415cSShawn Lin goto err_clk_ciu; 33303744415cSShawn Lin } 3331141a712aSSeungwon Jeon 3332141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3333141a712aSSeungwon Jeon dw_mci_init_dma(host); 3334f95f3850SWill Newton 3335f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3336f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3337f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3338f95f3850SWill Newton 3339f95f3850SWill Newton /* Put in max timeout */ 3340f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3341f95f3850SWill Newton 3342f95f3850SWill Newton /* 3343f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3344f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3345f95f3850SWill Newton */ 3346b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3347b86d8253SJames Hogan /* 3348b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3349b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3350b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3351b86d8253SJames Hogan * should put it in the platform data. 3352b86d8253SJames Hogan */ 3353f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 33548234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3355b86d8253SJames Hogan } else { 3356b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3357b86d8253SJames Hogan } 3358b86d8253SJames Hogan host->fifo_depth = fifo_size; 335952426899SSeungwon Jeon host->fifoth_val = 336052426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3361e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3362f95f3850SWill Newton 3363f95f3850SWill Newton /* disable clock to CIU */ 3364f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3365f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3366f95f3850SWill Newton 336763008768SJames Hogan /* 336863008768SJames Hogan * In 2.40a spec, Data offset is changed. 336963008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 337063008768SJames Hogan */ 337163008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 337263008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 337363008768SJames Hogan 3374a0361c1aSJun Nie if (host->data_addr_override) 3375a0361c1aSJun Nie host->fifo_reg = host->regs + host->data_addr_override; 3376a0361c1aSJun Nie else if (host->verid < DW_MMC_240A) 337776184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 337863008768SJames Hogan else 337976184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 338063008768SJames Hogan 33816078df15SEmil Renner Berthing tasklet_setup(&host->tasklet, dw_mci_tasklet_func); 3382780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3383780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3384f95f3850SWill Newton if (ret) 33856130e7a9SDoug Anderson goto err_dmaunmap; 3386f95f3850SWill Newton 3387d30a8f7bSJaehoon Chung /* 3388fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 33892da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 33902da1d7f2SYuvaraj CD */ 33912da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 33922da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3393fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 33940e3a22c0SShawn Lin /* Enable mci interrupt */ 33950e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 33962da1d7f2SYuvaraj CD 33970e3a22c0SShawn Lin dev_info(host->dev, 33980e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 33992da1d7f2SYuvaraj CD host->irq, width, fifo_size); 34002da1d7f2SYuvaraj CD 3401f95f3850SWill Newton /* We need at least one slot to succeed */ 3402e4a65ef7SJaehoon Chung ret = dw_mci_init_slot(host); 340358870241SJaehoon Chung if (ret) { 34041c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 34056130e7a9SDoug Anderson goto err_dmaunmap; 3406f95f3850SWill Newton } 3407f95f3850SWill Newton 3408b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3409b793f658SDoug Anderson dw_mci_enable_cd(host); 3410b793f658SDoug Anderson 3411f95f3850SWill Newton return 0; 3412f95f3850SWill Newton 3413f95f3850SWill Newton err_dmaunmap: 3414f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3415f95f3850SWill Newton host->dma_ops->exit(host); 3416f90a0612SThomas Abraham 3417d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3418d6786fefSGuodong Xu 3419f90a0612SThomas Abraham err_clk_ciu: 3420f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3421780f22afSSeungwon Jeon 3422f90a0612SThomas Abraham err_clk_biu: 3423f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3424780f22afSSeungwon Jeon 3425f95f3850SWill Newton return ret; 3426f95f3850SWill Newton } 342762ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3428f95f3850SWill Newton 342962ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3430f95f3850SWill Newton { 3431e4a65ef7SJaehoon Chung dev_dbg(host->dev, "remove slot\n"); 3432b23475faSJaehoon Chung if (host->slot) 3433e4a65ef7SJaehoon Chung dw_mci_cleanup_slot(host->slot); 3434f95f3850SWill Newton 3435048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3436048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3437048fd7e6SPrabu Thangamuthu 3438f95f3850SWill Newton /* disable clock to CIU */ 3439f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3440f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3441f95f3850SWill Newton 3442f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3443f95f3850SWill Newton host->dma_ops->exit(host); 3444f95f3850SWill Newton 3445d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3446d6786fefSGuodong Xu 3447f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3448f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3449f95f3850SWill Newton } 345062ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 345162ca8034SShashidhar Hiremath 345262ca8034SShashidhar Hiremath 3453f95f3850SWill Newton 3454e9ed8835SShawn Lin #ifdef CONFIG_PM 3455ed24e1ffSShawn Lin int dw_mci_runtime_suspend(struct device *dev) 3456f95f3850SWill Newton { 3457ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3458ed24e1ffSShawn Lin 34593fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 34603fc7eaefSShawn Lin host->dma_ops->exit(host); 34613fc7eaefSShawn Lin 3462ed24e1ffSShawn Lin clk_disable_unprepare(host->ciu_clk); 3463ed24e1ffSShawn Lin 346442f989c0SJaehoon Chung if (host->slot && 346542f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 346642f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) 3467ed24e1ffSShawn Lin clk_disable_unprepare(host->biu_clk); 3468ed24e1ffSShawn Lin 3469f95f3850SWill Newton return 0; 3470f95f3850SWill Newton } 3471ed24e1ffSShawn Lin EXPORT_SYMBOL(dw_mci_runtime_suspend); 3472f95f3850SWill Newton 3473ed24e1ffSShawn Lin int dw_mci_runtime_resume(struct device *dev) 3474f95f3850SWill Newton { 3475b23475faSJaehoon Chung int ret = 0; 3476ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3477f95f3850SWill Newton 347842f989c0SJaehoon Chung if (host->slot && 347942f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 348042f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) { 3481ed24e1ffSShawn Lin ret = clk_prepare_enable(host->biu_clk); 3482ed24e1ffSShawn Lin if (ret) 3483e61cf118SJaehoon Chung return ret; 3484e61cf118SJaehoon Chung } 3485e61cf118SJaehoon Chung 3486ed24e1ffSShawn Lin ret = clk_prepare_enable(host->ciu_clk); 3487ed24e1ffSShawn Lin if (ret) 3488df9bcc2bSJoonyoung Shim goto err; 3489df9bcc2bSJoonyoung Shim 3490df9bcc2bSJoonyoung Shim if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3491df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->ciu_clk); 3492df9bcc2bSJoonyoung Shim ret = -ENODEV; 3493df9bcc2bSJoonyoung Shim goto err; 3494df9bcc2bSJoonyoung Shim } 3495ed24e1ffSShawn Lin 34963bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3497141a712aSSeungwon Jeon host->dma_ops->init(host); 3498141a712aSSeungwon Jeon 349952426899SSeungwon Jeon /* 350052426899SSeungwon Jeon * Restore the initial value at FIFOTH register 350152426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 350252426899SSeungwon Jeon */ 3503e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 350452426899SSeungwon Jeon host->prev_blksz = 0; 3505e61cf118SJaehoon Chung 35062eb2944fSDoug Anderson /* Put in max timeout */ 35072eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 35082eb2944fSDoug Anderson 3509e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3510e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3511e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3512fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3513e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3514e61cf118SJaehoon Chung 35150e3a22c0SShawn Lin 3516e47c0b96SJaehoon Chung if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3517e47c0b96SJaehoon Chung dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3518e9748e03SZiyuan Xu 3519e9748e03SZiyuan Xu /* Force setup bus to guarantee available clock output */ 3520e47c0b96SJaehoon Chung dw_mci_setup_bus(host->slot, true); 3521fa0c3283SDoug Anderson 35227c526608SUlf Hansson /* Re-enable SDIO interrupts. */ 35237c526608SUlf Hansson if (sdio_irq_claimed(host->slot->mmc)) 35247c526608SUlf Hansson __dw_mci_enable_sdio_irq(host->slot, 1); 35257c526608SUlf Hansson 3526fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3527fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3528fa0c3283SDoug Anderson 3529df9bcc2bSJoonyoung Shim return 0; 3530df9bcc2bSJoonyoung Shim 3531df9bcc2bSJoonyoung Shim err: 353242f989c0SJaehoon Chung if (host->slot && 353342f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 353442f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) 3535df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->biu_clk); 3536df9bcc2bSJoonyoung Shim 35371f5c51d7SShawn Lin return ret; 35381f5c51d7SShawn Lin } 3539e9ed8835SShawn Lin EXPORT_SYMBOL(dw_mci_runtime_resume); 3540e9ed8835SShawn Lin #endif /* CONFIG_PM */ 35416fe8890dSJaehoon Chung 3542f95f3850SWill Newton static int __init dw_mci_init(void) 3543f95f3850SWill Newton { 35448e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 354562ca8034SShashidhar Hiremath return 0; 3546f95f3850SWill Newton } 3547f95f3850SWill Newton 3548f95f3850SWill Newton static void __exit dw_mci_exit(void) 3549f95f3850SWill Newton { 3550f95f3850SWill Newton } 3551f95f3850SWill Newton 3552f95f3850SWill Newton module_init(dw_mci_init); 3553f95f3850SWill Newton module_exit(dw_mci_exit); 3554f95f3850SWill Newton 3555f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3556f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3557f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3558f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3559