1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47f95f3850SWill Newton SDMMC_INT_EBE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49f95f3850SWill Newton SDMMC_INT_RESP_ERR) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51f95f3850SWill Newton DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 6569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6669d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6769d99fdcSPrabu Thangamuthu 6869d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6969d99fdcSPrabu Thangamuthu 7069d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7169d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 7269d99fdcSPrabu Thangamuthu ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff)) 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7769d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8069d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu }; 8269d99fdcSPrabu Thangamuthu 83f95f3850SWill Newton struct idmac_desc { 84f95f3850SWill Newton u32 des0; /* Control Descriptor */ 85f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 86f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 87f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 88f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 89f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 90f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 91f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 92f95f3850SWill Newton 93f95f3850SWill Newton u32 des1; /* Buffer sizes */ 94f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 959b7bbe10SShashidhar Hiremath ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 96f95f3850SWill Newton 97f95f3850SWill Newton u32 des2; /* buffer 1 physical address */ 98f95f3850SWill Newton 99f95f3850SWill Newton u32 des3; /* buffer 2 physical address */ 100f95f3850SWill Newton }; 101f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 102f95f3850SWill Newton 1033a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 104536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 1050bdbd0e8SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc); 10631bff450SSeungwon Jeon 107f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 108f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 109f95f3850SWill Newton { 110f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 111f95f3850SWill Newton struct mmc_request *mrq; 112f95f3850SWill Newton struct mmc_command *cmd; 113f95f3850SWill Newton struct mmc_command *stop; 114f95f3850SWill Newton struct mmc_data *data; 115f95f3850SWill Newton 116f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 117f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 118f95f3850SWill Newton mrq = slot->mrq; 119f95f3850SWill Newton 120f95f3850SWill Newton if (mrq) { 121f95f3850SWill Newton cmd = mrq->cmd; 122f95f3850SWill Newton data = mrq->data; 123f95f3850SWill Newton stop = mrq->stop; 124f95f3850SWill Newton 125f95f3850SWill Newton if (cmd) 126f95f3850SWill Newton seq_printf(s, 127f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 128f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 129f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 130f95f3850SWill Newton cmd->resp[2], cmd->error); 131f95f3850SWill Newton if (data) 132f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 133f95f3850SWill Newton data->bytes_xfered, data->blocks, 134f95f3850SWill Newton data->blksz, data->flags, data->error); 135f95f3850SWill Newton if (stop) 136f95f3850SWill Newton seq_printf(s, 137f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 138f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 139f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 140f95f3850SWill Newton stop->resp[2], stop->error); 141f95f3850SWill Newton } 142f95f3850SWill Newton 143f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 144f95f3850SWill Newton 145f95f3850SWill Newton return 0; 146f95f3850SWill Newton } 147f95f3850SWill Newton 148f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 149f95f3850SWill Newton { 150f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 151f95f3850SWill Newton } 152f95f3850SWill Newton 153f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 154f95f3850SWill Newton .owner = THIS_MODULE, 155f95f3850SWill Newton .open = dw_mci_req_open, 156f95f3850SWill Newton .read = seq_read, 157f95f3850SWill Newton .llseek = seq_lseek, 158f95f3850SWill Newton .release = single_release, 159f95f3850SWill Newton }; 160f95f3850SWill Newton 161f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 162f95f3850SWill Newton { 163f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 164f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 165f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 166f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 167f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 168f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 169f95f3850SWill Newton 170f95f3850SWill Newton return 0; 171f95f3850SWill Newton } 172f95f3850SWill Newton 173f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 174f95f3850SWill Newton { 175f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 176f95f3850SWill Newton } 177f95f3850SWill Newton 178f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 179f95f3850SWill Newton .owner = THIS_MODULE, 180f95f3850SWill Newton .open = dw_mci_regs_open, 181f95f3850SWill Newton .read = seq_read, 182f95f3850SWill Newton .llseek = seq_lseek, 183f95f3850SWill Newton .release = single_release, 184f95f3850SWill Newton }; 185f95f3850SWill Newton 186f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 187f95f3850SWill Newton { 188f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 189f95f3850SWill Newton struct dw_mci *host = slot->host; 190f95f3850SWill Newton struct dentry *root; 191f95f3850SWill Newton struct dentry *node; 192f95f3850SWill Newton 193f95f3850SWill Newton root = mmc->debugfs_root; 194f95f3850SWill Newton if (!root) 195f95f3850SWill Newton return; 196f95f3850SWill Newton 197f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 198f95f3850SWill Newton &dw_mci_regs_fops); 199f95f3850SWill Newton if (!node) 200f95f3850SWill Newton goto err; 201f95f3850SWill Newton 202f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 203f95f3850SWill Newton &dw_mci_req_fops); 204f95f3850SWill Newton if (!node) 205f95f3850SWill Newton goto err; 206f95f3850SWill Newton 207f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 208f95f3850SWill Newton if (!node) 209f95f3850SWill Newton goto err; 210f95f3850SWill Newton 211f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 212f95f3850SWill Newton (u32 *)&host->pending_events); 213f95f3850SWill Newton if (!node) 214f95f3850SWill Newton goto err; 215f95f3850SWill Newton 216f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 217f95f3850SWill Newton (u32 *)&host->completed_events); 218f95f3850SWill Newton if (!node) 219f95f3850SWill Newton goto err; 220f95f3850SWill Newton 221f95f3850SWill Newton return; 222f95f3850SWill Newton 223f95f3850SWill Newton err: 224f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 225f95f3850SWill Newton } 226f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 227f95f3850SWill Newton 22801730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 22901730558SDoug Anderson 230f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 231f95f3850SWill Newton { 232f95f3850SWill Newton struct mmc_data *data; 233800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23401730558SDoug Anderson struct dw_mci *host = slot->host; 235e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 236f95f3850SWill Newton u32 cmdr; 237f95f3850SWill Newton cmd->error = -EINPROGRESS; 238f95f3850SWill Newton 239f95f3850SWill Newton cmdr = cmd->opcode; 240f95f3850SWill Newton 24190c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24290c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24390c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24490c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24590c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 246f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2474a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 248f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 249f95f3850SWill Newton 25001730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25101730558SDoug Anderson u32 clk_en_a; 25201730558SDoug Anderson 25301730558SDoug Anderson /* Special bit makes CMD11 not die */ 25401730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25501730558SDoug Anderson 25601730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25701730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 25801730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 25901730558SDoug Anderson 26001730558SDoug Anderson /* 26101730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26201730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26301730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26401730558SDoug Anderson * voltage change dance. 26501730558SDoug Anderson * 26601730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26701730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 26801730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 26901730558SDoug Anderson * until the voltage change is all done. 27001730558SDoug Anderson */ 27101730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27201730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27301730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27401730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27501730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27601730558SDoug Anderson } 27701730558SDoug Anderson 278f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 279f95f3850SWill Newton /* We expect a response, so set this bit */ 280f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 281f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 282f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 283f95f3850SWill Newton } 284f95f3850SWill Newton 285f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 286f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 287f95f3850SWill Newton 288f95f3850SWill Newton data = cmd->data; 289f95f3850SWill Newton if (data) { 290f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 291f95f3850SWill Newton if (data->flags & MMC_DATA_STREAM) 292f95f3850SWill Newton cmdr |= SDMMC_CMD_STRM_MODE; 293f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 294f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 295f95f3850SWill Newton } 296f95f3850SWill Newton 297cb27a843SJames Hogan if (drv_data && drv_data->prepare_command) 298cb27a843SJames Hogan drv_data->prepare_command(slot->host, &cmdr); 299800d78bfSThomas Abraham 300f95f3850SWill Newton return cmdr; 301f95f3850SWill Newton } 302f95f3850SWill Newton 30390c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30490c2143aSSeungwon Jeon { 30590c2143aSSeungwon Jeon struct mmc_command *stop; 30690c2143aSSeungwon Jeon u32 cmdr; 30790c2143aSSeungwon Jeon 30890c2143aSSeungwon Jeon if (!cmd->data) 30990c2143aSSeungwon Jeon return 0; 31090c2143aSSeungwon Jeon 31190c2143aSSeungwon Jeon stop = &host->stop_abort; 31290c2143aSSeungwon Jeon cmdr = cmd->opcode; 31390c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31490c2143aSSeungwon Jeon 31590c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31690c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31790c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3186c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3196c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3206c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 32190c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 32290c2143aSSeungwon Jeon stop->arg = 0; 32390c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32490c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32590c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32690c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32790c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 32890c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 32990c2143aSSeungwon Jeon } else { 33090c2143aSSeungwon Jeon return 0; 33190c2143aSSeungwon Jeon } 33290c2143aSSeungwon Jeon 33390c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33490c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33590c2143aSSeungwon Jeon 33690c2143aSSeungwon Jeon return cmdr; 33790c2143aSSeungwon Jeon } 33890c2143aSSeungwon Jeon 3390bdbd0e8SDoug Anderson static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 3400bdbd0e8SDoug Anderson { 3410bdbd0e8SDoug Anderson unsigned long timeout = jiffies + msecs_to_jiffies(500); 3420bdbd0e8SDoug Anderson 3430bdbd0e8SDoug Anderson /* 3440bdbd0e8SDoug Anderson * Databook says that before issuing a new data transfer command 3450bdbd0e8SDoug Anderson * we need to check to see if the card is busy. Data transfer commands 3460bdbd0e8SDoug Anderson * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 3470bdbd0e8SDoug Anderson * 3480bdbd0e8SDoug Anderson * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 3490bdbd0e8SDoug Anderson * expected. 3500bdbd0e8SDoug Anderson */ 3510bdbd0e8SDoug Anderson if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 3520bdbd0e8SDoug Anderson !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 3530bdbd0e8SDoug Anderson while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 3540bdbd0e8SDoug Anderson if (time_after(jiffies, timeout)) { 3550bdbd0e8SDoug Anderson /* Command will fail; we'll pass error then */ 3560bdbd0e8SDoug Anderson dev_err(host->dev, "Busy; trying anyway\n"); 3570bdbd0e8SDoug Anderson break; 3580bdbd0e8SDoug Anderson } 3590bdbd0e8SDoug Anderson udelay(10); 3600bdbd0e8SDoug Anderson } 3610bdbd0e8SDoug Anderson } 3620bdbd0e8SDoug Anderson } 3630bdbd0e8SDoug Anderson 364f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 365f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 366f95f3850SWill Newton { 367f95f3850SWill Newton host->cmd = cmd; 3684a90920cSThomas Abraham dev_vdbg(host->dev, 369f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 370f95f3850SWill Newton cmd->arg, cmd_flags); 371f95f3850SWill Newton 372f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 373f95f3850SWill Newton wmb(); 3740bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 375f95f3850SWill Newton 376f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 377f95f3850SWill Newton } 378f95f3850SWill Newton 37990c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 380f95f3850SWill Newton { 38190c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 38290c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 383f95f3850SWill Newton } 384f95f3850SWill Newton 385f95f3850SWill Newton /* DMA interface functions */ 386f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 387f95f3850SWill Newton { 38803e8cb53SJames Hogan if (host->using_dma) { 389f95f3850SWill Newton host->dma_ops->stop(host); 390f95f3850SWill Newton host->dma_ops->cleanup(host); 391aa50f259SSeungwon Jeon } 392aa50f259SSeungwon Jeon 393f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 394f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 395f95f3850SWill Newton } 396f95f3850SWill Newton 3979aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 3989aa51408SSeungwon Jeon { 3999aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4009aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4019aa51408SSeungwon Jeon else 4029aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4039aa51408SSeungwon Jeon } 4049aa51408SSeungwon Jeon 4059beee912SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 406f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 407f95f3850SWill Newton { 408f95f3850SWill Newton struct mmc_data *data = host->data; 409f95f3850SWill Newton 410f95f3850SWill Newton if (data) 4119aa51408SSeungwon Jeon if (!data->host_cookie) 4124a90920cSThomas Abraham dma_unmap_sg(host->dev, 4139aa51408SSeungwon Jeon data->sg, 4149aa51408SSeungwon Jeon data->sg_len, 4159aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 416f95f3850SWill Newton } 417f95f3850SWill Newton 4185ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4195ce9d961SSeungwon Jeon { 4205ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4215ce9d961SSeungwon Jeon /* Software reset of DMA */ 4225ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4235ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4245ce9d961SSeungwon Jeon } 4255ce9d961SSeungwon Jeon 426f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 427f95f3850SWill Newton { 428f95f3850SWill Newton u32 temp; 429f95f3850SWill Newton 430f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 431f95f3850SWill Newton temp = mci_readl(host, CTRL); 432f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 433f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 434f95f3850SWill Newton mci_writel(host, CTRL, temp); 435f95f3850SWill Newton 436f95f3850SWill Newton /* Stop the IDMAC running */ 437f95f3850SWill Newton temp = mci_readl(host, BMOD); 438a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4395ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 440f95f3850SWill Newton mci_writel(host, BMOD, temp); 441f95f3850SWill Newton } 442f95f3850SWill Newton 443f95f3850SWill Newton static void dw_mci_idmac_complete_dma(struct dw_mci *host) 444f95f3850SWill Newton { 445f95f3850SWill Newton struct mmc_data *data = host->data; 446f95f3850SWill Newton 4474a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 448f95f3850SWill Newton 449f95f3850SWill Newton host->dma_ops->cleanup(host); 450f95f3850SWill Newton 451f95f3850SWill Newton /* 452f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 453f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 454f95f3850SWill Newton */ 455f95f3850SWill Newton if (data) { 456f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 457f95f3850SWill Newton tasklet_schedule(&host->tasklet); 458f95f3850SWill Newton } 459f95f3850SWill Newton } 460f95f3850SWill Newton 461f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 462f95f3850SWill Newton unsigned int sg_len) 463f95f3850SWill Newton { 464f95f3850SWill Newton int i; 46569d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 46669d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *desc = host->sg_cpu; 46769d99fdcSPrabu Thangamuthu 46869d99fdcSPrabu Thangamuthu for (i = 0; i < sg_len; i++, desc++) { 46969d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 47069d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 47169d99fdcSPrabu Thangamuthu 47269d99fdcSPrabu Thangamuthu /* 47369d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 47469d99fdcSPrabu Thangamuthu * descriptor 47569d99fdcSPrabu Thangamuthu */ 47669d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 47769d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 47869d99fdcSPrabu Thangamuthu /* Buffer length */ 47969d99fdcSPrabu Thangamuthu IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length); 48069d99fdcSPrabu Thangamuthu 48169d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 48269d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 48369d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 48469d99fdcSPrabu Thangamuthu } 48569d99fdcSPrabu Thangamuthu 48669d99fdcSPrabu Thangamuthu /* Set first descriptor */ 48769d99fdcSPrabu Thangamuthu desc = host->sg_cpu; 48869d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_FD; 48969d99fdcSPrabu Thangamuthu 49069d99fdcSPrabu Thangamuthu /* Set last descriptor */ 49169d99fdcSPrabu Thangamuthu desc = host->sg_cpu + (i - 1) * 49269d99fdcSPrabu Thangamuthu sizeof(struct idmac_desc_64addr); 49369d99fdcSPrabu Thangamuthu desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 49469d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_LD; 49569d99fdcSPrabu Thangamuthu 49669d99fdcSPrabu Thangamuthu } else { 497f95f3850SWill Newton struct idmac_desc *desc = host->sg_cpu; 498f95f3850SWill Newton 499f95f3850SWill Newton for (i = 0; i < sg_len; i++, desc++) { 500f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 501f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 502f95f3850SWill Newton 50369d99fdcSPrabu Thangamuthu /* 50469d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 50569d99fdcSPrabu Thangamuthu * descriptor 50669d99fdcSPrabu Thangamuthu */ 50769d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 50869d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 509f95f3850SWill Newton /* Buffer length */ 510f95f3850SWill Newton IDMAC_SET_BUFFER1_SIZE(desc, length); 511f95f3850SWill Newton 512f95f3850SWill Newton /* Physical address to DMA to/from */ 513f95f3850SWill Newton desc->des2 = mem_addr; 514f95f3850SWill Newton } 515f95f3850SWill Newton 516f95f3850SWill Newton /* Set first descriptor */ 517f95f3850SWill Newton desc = host->sg_cpu; 518f95f3850SWill Newton desc->des0 |= IDMAC_DES0_FD; 519f95f3850SWill Newton 520f95f3850SWill Newton /* Set last descriptor */ 521f95f3850SWill Newton desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 522f95f3850SWill Newton desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 523f95f3850SWill Newton desc->des0 |= IDMAC_DES0_LD; 52469d99fdcSPrabu Thangamuthu } 525f95f3850SWill Newton 526f95f3850SWill Newton wmb(); 527f95f3850SWill Newton } 528f95f3850SWill Newton 529f95f3850SWill Newton static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 530f95f3850SWill Newton { 531f95f3850SWill Newton u32 temp; 532f95f3850SWill Newton 533f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 534f95f3850SWill Newton 535536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 536536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 537536f6b91SSonny Rao dw_mci_idmac_reset(host); 538536f6b91SSonny Rao 539f95f3850SWill Newton /* Select IDMAC interface */ 540f95f3850SWill Newton temp = mci_readl(host, CTRL); 541f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 542f95f3850SWill Newton mci_writel(host, CTRL, temp); 543f95f3850SWill Newton 544f95f3850SWill Newton wmb(); 545f95f3850SWill Newton 546f95f3850SWill Newton /* Enable the IDMAC */ 547f95f3850SWill Newton temp = mci_readl(host, BMOD); 548a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 549f95f3850SWill Newton mci_writel(host, BMOD, temp); 550f95f3850SWill Newton 551f95f3850SWill Newton /* Start it running */ 552f95f3850SWill Newton mci_writel(host, PLDMND, 1); 553f95f3850SWill Newton } 554f95f3850SWill Newton 555f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 556f95f3850SWill Newton { 557897b69e7SSeungwon Jeon int i; 558f95f3850SWill Newton 55969d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 56069d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 56169d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 56269d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 56369d99fdcSPrabu Thangamuthu 56469d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 56569d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 56669d99fdcSPrabu Thangamuthu i++, p++) { 56769d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 56869d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 56969d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 57069d99fdcSPrabu Thangamuthu 57169d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 57269d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 57369d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 57469d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 57569d99fdcSPrabu Thangamuthu p->des1 = 0; 57669d99fdcSPrabu Thangamuthu p->des2 = 0; 57769d99fdcSPrabu Thangamuthu p->des3 = 0; 57869d99fdcSPrabu Thangamuthu } 57969d99fdcSPrabu Thangamuthu 58069d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 58169d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 58269d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 58369d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 58469d99fdcSPrabu Thangamuthu 58569d99fdcSPrabu Thangamuthu } else { 58669d99fdcSPrabu Thangamuthu struct idmac_desc *p; 587f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 588f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 589f95f3850SWill Newton 590f95f3850SWill Newton /* Forward link the descriptor list */ 591f95f3850SWill Newton for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 59269d99fdcSPrabu Thangamuthu p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * 59369d99fdcSPrabu Thangamuthu (i + 1)); 594f95f3850SWill Newton 595f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 596f95f3850SWill Newton p->des3 = host->sg_dma; 597f95f3850SWill Newton p->des0 = IDMAC_DES0_ER; 59869d99fdcSPrabu Thangamuthu } 599f95f3850SWill Newton 6005ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 601141a712aSSeungwon Jeon 60269d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 60369d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 60469d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 60569d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 60669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 60769d99fdcSPrabu Thangamuthu 60869d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 60969d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 61069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 61169d99fdcSPrabu Thangamuthu 61269d99fdcSPrabu Thangamuthu } else { 613f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 614fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 61569d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 61669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 617f95f3850SWill Newton 618f95f3850SWill Newton /* Set the descriptor base address */ 619f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 62069d99fdcSPrabu Thangamuthu } 62169d99fdcSPrabu Thangamuthu 622f95f3850SWill Newton return 0; 623f95f3850SWill Newton } 624f95f3850SWill Newton 6258e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 626885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 627885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 628885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 629885c3e80SSeungwon Jeon .complete = dw_mci_idmac_complete_dma, 630885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 631885c3e80SSeungwon Jeon }; 632885c3e80SSeungwon Jeon #endif /* CONFIG_MMC_DW_IDMAC */ 633885c3e80SSeungwon Jeon 6349aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 6359aa51408SSeungwon Jeon struct mmc_data *data, 6369aa51408SSeungwon Jeon bool next) 637f95f3850SWill Newton { 638f95f3850SWill Newton struct scatterlist *sg; 6399aa51408SSeungwon Jeon unsigned int i, sg_len; 640f95f3850SWill Newton 6419aa51408SSeungwon Jeon if (!next && data->host_cookie) 6429aa51408SSeungwon Jeon return data->host_cookie; 643f95f3850SWill Newton 644f95f3850SWill Newton /* 645f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 646f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 647f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 648f95f3850SWill Newton */ 649f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 650f95f3850SWill Newton return -EINVAL; 6519aa51408SSeungwon Jeon 652f95f3850SWill Newton if (data->blksz & 3) 653f95f3850SWill Newton return -EINVAL; 654f95f3850SWill Newton 655f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 656f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 657f95f3850SWill Newton return -EINVAL; 658f95f3850SWill Newton } 659f95f3850SWill Newton 6604a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 6619aa51408SSeungwon Jeon data->sg, 6629aa51408SSeungwon Jeon data->sg_len, 6639aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 6649aa51408SSeungwon Jeon if (sg_len == 0) 6659aa51408SSeungwon Jeon return -EINVAL; 6669aa51408SSeungwon Jeon 6679aa51408SSeungwon Jeon if (next) 6689aa51408SSeungwon Jeon data->host_cookie = sg_len; 6699aa51408SSeungwon Jeon 6709aa51408SSeungwon Jeon return sg_len; 6719aa51408SSeungwon Jeon } 6729aa51408SSeungwon Jeon 6739aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 6749aa51408SSeungwon Jeon struct mmc_request *mrq, 6759aa51408SSeungwon Jeon bool is_first_req) 6769aa51408SSeungwon Jeon { 6779aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6789aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6799aa51408SSeungwon Jeon 6809aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 6819aa51408SSeungwon Jeon return; 6829aa51408SSeungwon Jeon 6839aa51408SSeungwon Jeon if (data->host_cookie) { 6849aa51408SSeungwon Jeon data->host_cookie = 0; 6859aa51408SSeungwon Jeon return; 6869aa51408SSeungwon Jeon } 6879aa51408SSeungwon Jeon 6889aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 6899aa51408SSeungwon Jeon data->host_cookie = 0; 6909aa51408SSeungwon Jeon } 6919aa51408SSeungwon Jeon 6929aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 6939aa51408SSeungwon Jeon struct mmc_request *mrq, 6949aa51408SSeungwon Jeon int err) 6959aa51408SSeungwon Jeon { 6969aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6979aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6989aa51408SSeungwon Jeon 6999aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 7009aa51408SSeungwon Jeon return; 7019aa51408SSeungwon Jeon 7029aa51408SSeungwon Jeon if (data->host_cookie) 7034a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 7049aa51408SSeungwon Jeon data->sg, 7059aa51408SSeungwon Jeon data->sg_len, 7069aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 7079aa51408SSeungwon Jeon data->host_cookie = 0; 7089aa51408SSeungwon Jeon } 7099aa51408SSeungwon Jeon 71052426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 71152426899SSeungwon Jeon { 71252426899SSeungwon Jeon #ifdef CONFIG_MMC_DW_IDMAC 71352426899SSeungwon Jeon unsigned int blksz = data->blksz; 71452426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 71552426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 71652426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 71752426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 71852426899SSeungwon Jeon int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; 71952426899SSeungwon Jeon 72052426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 72152426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 72252426899SSeungwon Jeon 72352426899SSeungwon Jeon /* 72452426899SSeungwon Jeon * MSIZE is '1', 72552426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 72652426899SSeungwon Jeon */ 72752426899SSeungwon Jeon if (blksz % fifo_width) { 72852426899SSeungwon Jeon msize = 0; 72952426899SSeungwon Jeon rx_wmark = 1; 73052426899SSeungwon Jeon goto done; 73152426899SSeungwon Jeon } 73252426899SSeungwon Jeon 73352426899SSeungwon Jeon do { 73452426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 73552426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 73652426899SSeungwon Jeon msize = idx; 73752426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 73852426899SSeungwon Jeon break; 73952426899SSeungwon Jeon } 74052426899SSeungwon Jeon } while (--idx > 0); 74152426899SSeungwon Jeon /* 74252426899SSeungwon Jeon * If idx is '0', it won't be tried 74352426899SSeungwon Jeon * Thus, initial values are uesed 74452426899SSeungwon Jeon */ 74552426899SSeungwon Jeon done: 74652426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 74752426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 74852426899SSeungwon Jeon #endif 74952426899SSeungwon Jeon } 75052426899SSeungwon Jeon 751f1d2736cSSeungwon Jeon static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 752f1d2736cSSeungwon Jeon { 753f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 754f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 755f1d2736cSSeungwon Jeon u16 thld_size; 756f1d2736cSSeungwon Jeon 757f1d2736cSSeungwon Jeon WARN_ON(!(data->flags & MMC_DATA_READ)); 758f1d2736cSSeungwon Jeon 75966dfd101SJames Hogan /* 76066dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 76166dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 76266dfd101SJames Hogan */ 76366dfd101SJames Hogan if (host->verid < DW_MMC_240A) 76466dfd101SJames Hogan return; 76566dfd101SJames Hogan 766f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 767488b8d63SJaehoon Chung host->timing != MMC_TIMING_MMC_HS400 && 768f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 769f1d2736cSSeungwon Jeon goto disable; 770f1d2736cSSeungwon Jeon 771f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 772f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 773f1d2736cSSeungwon Jeon 774f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 775f1d2736cSSeungwon Jeon goto disable; 776f1d2736cSSeungwon Jeon 777f1d2736cSSeungwon Jeon /* 778f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 779f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 780f1d2736cSSeungwon Jeon * Currently just choose blksz. 781f1d2736cSSeungwon Jeon */ 782f1d2736cSSeungwon Jeon thld_size = blksz; 783f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 784f1d2736cSSeungwon Jeon return; 785f1d2736cSSeungwon Jeon 786f1d2736cSSeungwon Jeon disable: 787f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 788f1d2736cSSeungwon Jeon } 789f1d2736cSSeungwon Jeon 7909aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 7919aa51408SSeungwon Jeon { 792f8c58c11SDoug Anderson unsigned long irqflags; 7939aa51408SSeungwon Jeon int sg_len; 7949aa51408SSeungwon Jeon u32 temp; 7959aa51408SSeungwon Jeon 7969aa51408SSeungwon Jeon host->using_dma = 0; 7979aa51408SSeungwon Jeon 7989aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 7999aa51408SSeungwon Jeon if (!host->use_dma) 8009aa51408SSeungwon Jeon return -ENODEV; 8019aa51408SSeungwon Jeon 8029aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 803a99aa9b9SSeungwon Jeon if (sg_len < 0) { 804a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 8059aa51408SSeungwon Jeon return sg_len; 806a99aa9b9SSeungwon Jeon } 8079aa51408SSeungwon Jeon 80803e8cb53SJames Hogan host->using_dma = 1; 80903e8cb53SJames Hogan 8104a90920cSThomas Abraham dev_vdbg(host->dev, 811f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 812f95f3850SWill Newton (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 813f95f3850SWill Newton sg_len); 814f95f3850SWill Newton 81552426899SSeungwon Jeon /* 81652426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 81752426899SSeungwon Jeon * If current block size is same with previous size, 81852426899SSeungwon Jeon * no need to update fifoth. 81952426899SSeungwon Jeon */ 82052426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 82152426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 82252426899SSeungwon Jeon 823f95f3850SWill Newton /* Enable the DMA interface */ 824f95f3850SWill Newton temp = mci_readl(host, CTRL); 825f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 826f95f3850SWill Newton mci_writel(host, CTRL, temp); 827f95f3850SWill Newton 828f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 829f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 830f95f3850SWill Newton temp = mci_readl(host, INTMASK); 831f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 832f95f3850SWill Newton mci_writel(host, INTMASK, temp); 833f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 834f95f3850SWill Newton 835f95f3850SWill Newton host->dma_ops->start(host, sg_len); 836f95f3850SWill Newton 837f95f3850SWill Newton return 0; 838f95f3850SWill Newton } 839f95f3850SWill Newton 840f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 841f95f3850SWill Newton { 842f8c58c11SDoug Anderson unsigned long irqflags; 843f95f3850SWill Newton u32 temp; 844f95f3850SWill Newton 845f95f3850SWill Newton data->error = -EINPROGRESS; 846f95f3850SWill Newton 847f95f3850SWill Newton WARN_ON(host->data); 848f95f3850SWill Newton host->sg = NULL; 849f95f3850SWill Newton host->data = data; 850f95f3850SWill Newton 851f1d2736cSSeungwon Jeon if (data->flags & MMC_DATA_READ) { 85255c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 853f1d2736cSSeungwon Jeon dw_mci_ctrl_rd_thld(host, data); 854f1d2736cSSeungwon Jeon } else { 85555c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 856f1d2736cSSeungwon Jeon } 85755c5efbcSJames Hogan 858f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 859f9c2a0dcSSeungwon Jeon int flags = SG_MITER_ATOMIC; 860f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 861f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 862f9c2a0dcSSeungwon Jeon else 863f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 864f9c2a0dcSSeungwon Jeon 865f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 866f95f3850SWill Newton host->sg = data->sg; 86734b664a2SJames Hogan host->part_buf_start = 0; 86834b664a2SJames Hogan host->part_buf_count = 0; 869f95f3850SWill Newton 870b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 871f8c58c11SDoug Anderson 872f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 873f95f3850SWill Newton temp = mci_readl(host, INTMASK); 874f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 875f95f3850SWill Newton mci_writel(host, INTMASK, temp); 876f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 877f95f3850SWill Newton 878f95f3850SWill Newton temp = mci_readl(host, CTRL); 879f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 880f95f3850SWill Newton mci_writel(host, CTRL, temp); 88152426899SSeungwon Jeon 88252426899SSeungwon Jeon /* 88352426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 88452426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 88552426899SSeungwon Jeon * prev_blksz should be invalidated. 88652426899SSeungwon Jeon */ 88752426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 88852426899SSeungwon Jeon host->prev_blksz = 0; 88952426899SSeungwon Jeon } else { 89052426899SSeungwon Jeon /* 89152426899SSeungwon Jeon * Keep the current block size. 89252426899SSeungwon Jeon * It will be used to decide whether to update 89352426899SSeungwon Jeon * fifoth register next time. 89452426899SSeungwon Jeon */ 89552426899SSeungwon Jeon host->prev_blksz = data->blksz; 896f95f3850SWill Newton } 897f95f3850SWill Newton } 898f95f3850SWill Newton 899f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 900f95f3850SWill Newton { 901f95f3850SWill Newton struct dw_mci *host = slot->host; 902f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 903f95f3850SWill Newton unsigned int cmd_status = 0; 904f95f3850SWill Newton 905f95f3850SWill Newton mci_writel(host, CMDARG, arg); 906f95f3850SWill Newton wmb(); 9070bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd); 908f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 909f95f3850SWill Newton 910f95f3850SWill Newton while (time_before(jiffies, timeout)) { 911f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 912f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 913f95f3850SWill Newton return; 914f95f3850SWill Newton } 915f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 916f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 917f95f3850SWill Newton cmd, arg, cmd_status); 918f95f3850SWill Newton } 919f95f3850SWill Newton 920ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 921f95f3850SWill Newton { 922f95f3850SWill Newton struct dw_mci *host = slot->host; 923fdf492a1SDoug Anderson unsigned int clock = slot->clock; 924f95f3850SWill Newton u32 div; 9259623b5b9SDoug Anderson u32 clk_en_a; 92601730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 92701730558SDoug Anderson 92801730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 92901730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 93001730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 931f95f3850SWill Newton 932fdf492a1SDoug Anderson if (!clock) { 933fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 93401730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 935fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 936fdf492a1SDoug Anderson div = host->bus_hz / clock; 937fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 938f95f3850SWill Newton /* 939f95f3850SWill Newton * move the + 1 after the divide to prevent 940f95f3850SWill Newton * over-clocking the card. 941f95f3850SWill Newton */ 942e419990bSSeungwon Jeon div += 1; 943e419990bSSeungwon Jeon 944fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 945f95f3850SWill Newton 946fdf492a1SDoug Anderson if ((clock << div) != slot->__clk_old || force_clkinit) 947f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 948fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 949fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 950fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 951fdf492a1SDoug Anderson host->bus_hz, div); 952f95f3850SWill Newton 953f95f3850SWill Newton /* disable clock */ 954f95f3850SWill Newton mci_writel(host, CLKENA, 0); 955f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 956f95f3850SWill Newton 957f95f3850SWill Newton /* inform CIU */ 95801730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 959f95f3850SWill Newton 960f95f3850SWill Newton /* set clock to desired speed */ 961f95f3850SWill Newton mci_writel(host, CLKDIV, div); 962f95f3850SWill Newton 963f95f3850SWill Newton /* inform CIU */ 96401730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 965f95f3850SWill Newton 9669623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 9679623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 968b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 9699623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 9709623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 971f95f3850SWill Newton 972f95f3850SWill Newton /* inform CIU */ 97301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 974f95f3850SWill Newton 975fdf492a1SDoug Anderson /* keep the clock with reflecting clock dividor */ 976fdf492a1SDoug Anderson slot->__clk_old = clock << div; 977f95f3850SWill Newton } 978f95f3850SWill Newton 979fdf492a1SDoug Anderson host->current_speed = clock; 980fdf492a1SDoug Anderson 981f95f3850SWill Newton /* Set the current slot bus width */ 9821d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 983f95f3850SWill Newton } 984f95f3850SWill Newton 985053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 986053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 987053b3ce6SSeungwon Jeon struct mmc_command *cmd) 988f95f3850SWill Newton { 989f95f3850SWill Newton struct mmc_request *mrq; 990f95f3850SWill Newton struct mmc_data *data; 991f95f3850SWill Newton u32 cmdflags; 992f95f3850SWill Newton 993f95f3850SWill Newton mrq = slot->mrq; 994f95f3850SWill Newton 995f95f3850SWill Newton host->cur_slot = slot; 996f95f3850SWill Newton host->mrq = mrq; 997f95f3850SWill Newton 998f95f3850SWill Newton host->pending_events = 0; 999f95f3850SWill Newton host->completed_events = 0; 1000e352c813SSeungwon Jeon host->cmd_status = 0; 1001f95f3850SWill Newton host->data_status = 0; 1002e352c813SSeungwon Jeon host->dir_status = 0; 1003f95f3850SWill Newton 1004053b3ce6SSeungwon Jeon data = cmd->data; 1005f95f3850SWill Newton if (data) { 1006f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1007f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1008f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1009f95f3850SWill Newton } 1010f95f3850SWill Newton 1011f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1012f95f3850SWill Newton 1013f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1014f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1015f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1016f95f3850SWill Newton 1017f95f3850SWill Newton if (data) { 1018f95f3850SWill Newton dw_mci_submit_data(host, data); 1019f95f3850SWill Newton wmb(); 1020f95f3850SWill Newton } 1021f95f3850SWill Newton 1022f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1023f95f3850SWill Newton 10245c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 10255c935165SDoug Anderson /* 10265c935165SDoug Anderson * Databook says to fail after 2ms w/ no response; give an 10275c935165SDoug Anderson * extra jiffy just in case we're about to roll over. 10285c935165SDoug Anderson */ 10295c935165SDoug Anderson mod_timer(&host->cmd11_timer, 10305c935165SDoug Anderson jiffies + msecs_to_jiffies(2) + 1); 10315c935165SDoug Anderson } 10325c935165SDoug Anderson 1033f95f3850SWill Newton if (mrq->stop) 1034f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 103590c2143aSSeungwon Jeon else 103690c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1037f95f3850SWill Newton } 1038f95f3850SWill Newton 1039053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1040053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1041053b3ce6SSeungwon Jeon { 1042053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1043053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1044053b3ce6SSeungwon Jeon 1045053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1046053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1047053b3ce6SSeungwon Jeon } 1048053b3ce6SSeungwon Jeon 10497456caaeSJames Hogan /* must be called with host->lock held */ 1050f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1051f95f3850SWill Newton struct mmc_request *mrq) 1052f95f3850SWill Newton { 1053f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1054f95f3850SWill Newton host->state); 1055f95f3850SWill Newton 1056f95f3850SWill Newton slot->mrq = mrq; 1057f95f3850SWill Newton 105801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 105901730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 106001730558SDoug Anderson "Voltage change didn't complete\n"); 106101730558SDoug Anderson /* 106201730558SDoug Anderson * this case isn't expected to happen, so we can 106301730558SDoug Anderson * either crash here or just try to continue on 106401730558SDoug Anderson * in the closest possible state 106501730558SDoug Anderson */ 106601730558SDoug Anderson host->state = STATE_IDLE; 106701730558SDoug Anderson } 106801730558SDoug Anderson 1069f95f3850SWill Newton if (host->state == STATE_IDLE) { 1070f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1071f95f3850SWill Newton dw_mci_start_request(host, slot); 1072f95f3850SWill Newton } else { 1073f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1074f95f3850SWill Newton } 1075f95f3850SWill Newton } 1076f95f3850SWill Newton 1077f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1078f95f3850SWill Newton { 1079f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1080f95f3850SWill Newton struct dw_mci *host = slot->host; 1081f95f3850SWill Newton 1082f95f3850SWill Newton WARN_ON(slot->mrq); 1083f95f3850SWill Newton 10847456caaeSJames Hogan /* 10857456caaeSJames Hogan * The check for card presence and queueing of the request must be 10867456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 10877456caaeSJames Hogan * request wouldn't fail until another card was inserted. 10887456caaeSJames Hogan */ 10897456caaeSJames Hogan spin_lock_bh(&host->lock); 10907456caaeSJames Hogan 1091f95f3850SWill Newton if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 10927456caaeSJames Hogan spin_unlock_bh(&host->lock); 1093f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1094f95f3850SWill Newton mmc_request_done(mmc, mrq); 1095f95f3850SWill Newton return; 1096f95f3850SWill Newton } 1097f95f3850SWill Newton 1098f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 10997456caaeSJames Hogan 11007456caaeSJames Hogan spin_unlock_bh(&host->lock); 1101f95f3850SWill Newton } 1102f95f3850SWill Newton 1103f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1104f95f3850SWill Newton { 1105f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1106e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 110741babf75SJaehoon Chung u32 regs; 110851da2240SYuvaraj CD int ret; 1109f95f3850SWill Newton 1110f95f3850SWill Newton switch (ios->bus_width) { 1111f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1112f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1113f95f3850SWill Newton break; 1114c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1115c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1116c9b2a06fSJaehoon Chung break; 1117b2f7cb45SJaehoon Chung default: 1118b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1119b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1120f95f3850SWill Newton } 1121f95f3850SWill Newton 112241babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 11233f514291SSeungwon Jeon 11243f514291SSeungwon Jeon /* DDR mode set */ 112580113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 112680113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1127c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 11283f514291SSeungwon Jeon else 1129c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 11303f514291SSeungwon Jeon 113141babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1132f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 113341babf75SJaehoon Chung 1134f95f3850SWill Newton /* 1135f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1136f95f3850SWill Newton * core ios update when finding the minimum. 1137f95f3850SWill Newton */ 1138f95f3850SWill Newton slot->clock = ios->clock; 1139f95f3850SWill Newton 1140cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1141cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1142800d78bfSThomas Abraham 1143f95f3850SWill Newton switch (ios->power_mode) { 1144f95f3850SWill Newton case MMC_POWER_UP: 114551da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 114651da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 114751da2240SYuvaraj CD ios->vdd); 114851da2240SYuvaraj CD if (ret) { 114951da2240SYuvaraj CD dev_err(slot->host->dev, 115051da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 115151da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 115251da2240SYuvaraj CD return; 115351da2240SYuvaraj CD } 115451da2240SYuvaraj CD } 115529d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 115629d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 115729d0d161SDoug Anderson regs |= (1 << slot->id); 115829d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 115929d0d161SDoug Anderson break; 116029d0d161SDoug Anderson case MMC_POWER_ON: 1161d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1162d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 116351da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 116451da2240SYuvaraj CD if (ret < 0) 116551da2240SYuvaraj CD dev_err(slot->host->dev, 1166d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 116751da2240SYuvaraj CD else 116851da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1169d1f1dd86SDoug Anderson 1170d1f1dd86SDoug Anderson } else { 1171d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1172d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1173d1f1dd86SDoug Anderson } 1174d1f1dd86SDoug Anderson 1175d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1176d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1177d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 117851da2240SYuvaraj CD } 1179655babbdSDoug Anderson 1180655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1181655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1182655babbdSDoug Anderson 1183e6f34e2fSJames Hogan break; 1184e6f34e2fSJames Hogan case MMC_POWER_OFF: 1185655babbdSDoug Anderson /* Turn clock off before power goes down */ 1186655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1187655babbdSDoug Anderson 118851da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 118951da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 119051da2240SYuvaraj CD 1191d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 119251da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 119351da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 119451da2240SYuvaraj CD 11954366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 11964366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 11974366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1198f95f3850SWill Newton break; 1199f95f3850SWill Newton default: 1200f95f3850SWill Newton break; 1201f95f3850SWill Newton } 1202655babbdSDoug Anderson 1203655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1204655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1205f95f3850SWill Newton } 1206f95f3850SWill Newton 120701730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 120801730558SDoug Anderson { 120901730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 121001730558SDoug Anderson u32 status; 121101730558SDoug Anderson 121201730558SDoug Anderson /* 121301730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 121401730558SDoug Anderson * (the data lines) are 0000 121501730558SDoug Anderson */ 121601730558SDoug Anderson status = mci_readl(slot->host, STATUS); 121701730558SDoug Anderson 121801730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 121901730558SDoug Anderson } 122001730558SDoug Anderson 122101730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 122201730558SDoug Anderson { 122301730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 122401730558SDoug Anderson struct dw_mci *host = slot->host; 122501730558SDoug Anderson u32 uhs; 122601730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 122701730558SDoug Anderson int min_uv, max_uv; 122801730558SDoug Anderson int ret; 122901730558SDoug Anderson 123001730558SDoug Anderson /* 123101730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 123201730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 123301730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 123401730558SDoug Anderson */ 123501730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 123601730558SDoug Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 123701730558SDoug Anderson min_uv = 2700000; 123801730558SDoug Anderson max_uv = 3600000; 123901730558SDoug Anderson uhs &= ~v18; 124001730558SDoug Anderson } else { 124101730558SDoug Anderson min_uv = 1700000; 124201730558SDoug Anderson max_uv = 1950000; 124301730558SDoug Anderson uhs |= v18; 124401730558SDoug Anderson } 124501730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 124601730558SDoug Anderson ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 124701730558SDoug Anderson 124801730558SDoug Anderson if (ret) { 1249b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 125001730558SDoug Anderson "Regulator set error %d: %d - %d\n", 125101730558SDoug Anderson ret, min_uv, max_uv); 125201730558SDoug Anderson return ret; 125301730558SDoug Anderson } 125401730558SDoug Anderson } 125501730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 125601730558SDoug Anderson 125701730558SDoug Anderson return 0; 125801730558SDoug Anderson } 125901730558SDoug Anderson 1260f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1261f95f3850SWill Newton { 1262f95f3850SWill Newton int read_only; 1263f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 12649795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1265f95f3850SWill Newton 1266f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 126726375b5cSJaehoon Chung if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) || 126826375b5cSJaehoon Chung (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)) 1269b4967aa5SThomas Abraham read_only = 0; 12709795a846SJaehoon Chung else if (!IS_ERR_VALUE(gpio_ro)) 12719795a846SJaehoon Chung read_only = gpio_ro; 1272f95f3850SWill Newton else 1273f95f3850SWill Newton read_only = 1274f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1275f95f3850SWill Newton 1276f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1277f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1278f95f3850SWill Newton 1279f95f3850SWill Newton return read_only; 1280f95f3850SWill Newton } 1281f95f3850SWill Newton 1282f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1283f95f3850SWill Newton { 1284f95f3850SWill Newton int present; 1285f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1286f95f3850SWill Newton struct dw_mci_board *brd = slot->host->pdata; 12877cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 12887cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1289f95f3850SWill Newton 1290f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1291fc3d7720SJaehoon Chung if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 1292fc3d7720SJaehoon Chung present = 1; 1293bf626e55SZhangfei Gao else if (!IS_ERR_VALUE(gpio_cd)) 12947cf347bdSZhangfei Gao present = gpio_cd; 1295f95f3850SWill Newton else 1296f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1297f95f3850SWill Newton == 0 ? 1 : 0; 1298f95f3850SWill Newton 12997cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1300bf626e55SZhangfei Gao if (present) { 1301bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1302f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1303bf626e55SZhangfei Gao } else { 1304bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1305f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1306bf626e55SZhangfei Gao } 13077cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1308f95f3850SWill Newton 1309f95f3850SWill Newton return present; 1310f95f3850SWill Newton } 1311f95f3850SWill Newton 1312b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1313b24c8b26SDoug Anderson { 1314b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1315b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1316b24c8b26SDoug Anderson 13179623b5b9SDoug Anderson /* 13189623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 13199623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 13209623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 13219623b5b9SDoug Anderson */ 1322b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 13239623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1324b24c8b26SDoug Anderson u32 clk_en_a_old; 1325b24c8b26SDoug Anderson u32 clk_en_a; 13269623b5b9SDoug Anderson 1327b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 13289623b5b9SDoug Anderson 1329b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1330b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1331b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1332b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1333b24c8b26SDoug Anderson } else { 1334b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1335b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1336b24c8b26SDoug Anderson } 1337b24c8b26SDoug Anderson 1338b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1339b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 13409623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 13419623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 13429623b5b9SDoug Anderson } 13439623b5b9SDoug Anderson } 1344b24c8b26SDoug Anderson } 13459623b5b9SDoug Anderson 13461a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 13471a5c8e1fSShashidhar Hiremath { 13481a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 13491a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1350f8c58c11SDoug Anderson unsigned long irqflags; 13511a5c8e1fSShashidhar Hiremath u32 int_mask; 13521a5c8e1fSShashidhar Hiremath 1353f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1354f8c58c11SDoug Anderson 13551a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 13561a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1357b24c8b26SDoug Anderson if (enb) 1358b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1359b24c8b26SDoug Anderson else 1360b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1361b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1362f8c58c11SDoug Anderson 1363f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13641a5c8e1fSShashidhar Hiremath } 13651a5c8e1fSShashidhar Hiremath 13660976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 13670976f16dSSeungwon Jeon { 13680976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 13690976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 13700976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 13710976f16dSSeungwon Jeon int err = -ENOSYS; 13720976f16dSSeungwon Jeon 13730976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 13746c2c6506SUlf Hansson err = drv_data->execute_tuning(slot); 13750976f16dSSeungwon Jeon return err; 13760976f16dSSeungwon Jeon } 13770976f16dSSeungwon Jeon 1378c22f5e1bSWu Fengguang static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 137980113132SSeungwon Jeon { 138080113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 138180113132SSeungwon Jeon struct dw_mci *host = slot->host; 138280113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 138380113132SSeungwon Jeon 138480113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 138580113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 138680113132SSeungwon Jeon 138780113132SSeungwon Jeon return 0; 138880113132SSeungwon Jeon } 138980113132SSeungwon Jeon 1390f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1391f95f3850SWill Newton .request = dw_mci_request, 13929aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 13939aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1394f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1395f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1396f95f3850SWill Newton .get_cd = dw_mci_get_cd, 13971a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 13980976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 139901730558SDoug Anderson .card_busy = dw_mci_card_busy, 140001730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1401b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 140280113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1403f95f3850SWill Newton }; 1404f95f3850SWill Newton 1405f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1406f95f3850SWill Newton __releases(&host->lock) 1407f95f3850SWill Newton __acquires(&host->lock) 1408f95f3850SWill Newton { 1409f95f3850SWill Newton struct dw_mci_slot *slot; 1410f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1411f95f3850SWill Newton 1412f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1413f95f3850SWill Newton 1414f95f3850SWill Newton host->cur_slot->mrq = NULL; 1415f95f3850SWill Newton host->mrq = NULL; 1416f95f3850SWill Newton if (!list_empty(&host->queue)) { 1417f95f3850SWill Newton slot = list_entry(host->queue.next, 1418f95f3850SWill Newton struct dw_mci_slot, queue_node); 1419f95f3850SWill Newton list_del(&slot->queue_node); 14204a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1421f95f3850SWill Newton mmc_hostname(slot->mmc)); 1422f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1423f95f3850SWill Newton dw_mci_start_request(host, slot); 1424f95f3850SWill Newton } else { 14254a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 142601730558SDoug Anderson 142701730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 142801730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 142901730558SDoug Anderson else 1430f95f3850SWill Newton host->state = STATE_IDLE; 1431f95f3850SWill Newton } 1432f95f3850SWill Newton 1433f95f3850SWill Newton spin_unlock(&host->lock); 1434f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1435f95f3850SWill Newton spin_lock(&host->lock); 1436f95f3850SWill Newton } 1437f95f3850SWill Newton 1438e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1439f95f3850SWill Newton { 1440f95f3850SWill Newton u32 status = host->cmd_status; 1441f95f3850SWill Newton 1442f95f3850SWill Newton host->cmd_status = 0; 1443f95f3850SWill Newton 1444f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1445f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1446f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1447f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1448f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1449f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1450f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1451f95f3850SWill Newton } else { 1452f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1453f95f3850SWill Newton cmd->resp[1] = 0; 1454f95f3850SWill Newton cmd->resp[2] = 0; 1455f95f3850SWill Newton cmd->resp[3] = 0; 1456f95f3850SWill Newton } 1457f95f3850SWill Newton } 1458f95f3850SWill Newton 1459f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1460f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1461f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1462f95f3850SWill Newton cmd->error = -EILSEQ; 1463f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1464f95f3850SWill Newton cmd->error = -EIO; 1465f95f3850SWill Newton else 1466f95f3850SWill Newton cmd->error = 0; 1467f95f3850SWill Newton 1468f95f3850SWill Newton if (cmd->error) { 1469f95f3850SWill Newton /* newer ip versions need a delay between retries */ 1470f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1471f95f3850SWill Newton mdelay(20); 1472f95f3850SWill Newton } 1473e352c813SSeungwon Jeon 1474e352c813SSeungwon Jeon return cmd->error; 1475e352c813SSeungwon Jeon } 1476e352c813SSeungwon Jeon 1477e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1478e352c813SSeungwon Jeon { 147931bff450SSeungwon Jeon u32 status = host->data_status; 1480e352c813SSeungwon Jeon 1481e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1482e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1483e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1484e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1485e352c813SSeungwon Jeon data->error = -EILSEQ; 1486e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1487e352c813SSeungwon Jeon if (host->dir_status == 1488e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1489e352c813SSeungwon Jeon /* 1490e352c813SSeungwon Jeon * No data CRC status was returned. 1491e352c813SSeungwon Jeon * The number of bytes transferred 1492e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1493e352c813SSeungwon Jeon */ 1494e352c813SSeungwon Jeon data->bytes_xfered = 0; 1495e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1496e352c813SSeungwon Jeon } else if (host->dir_status == 1497e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1498e352c813SSeungwon Jeon data->error = -EIO; 1499e352c813SSeungwon Jeon } 1500e352c813SSeungwon Jeon } else { 1501e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1502e352c813SSeungwon Jeon data->error = -EIO; 1503e352c813SSeungwon Jeon } 1504e352c813SSeungwon Jeon 1505e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1506e352c813SSeungwon Jeon 1507e352c813SSeungwon Jeon /* 1508e352c813SSeungwon Jeon * After an error, there may be data lingering 150931bff450SSeungwon Jeon * in the FIFO 1510e352c813SSeungwon Jeon */ 15113a33a94cSSonny Rao dw_mci_reset(host); 1512e352c813SSeungwon Jeon } else { 1513e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1514e352c813SSeungwon Jeon data->error = 0; 1515e352c813SSeungwon Jeon } 1516e352c813SSeungwon Jeon 1517e352c813SSeungwon Jeon return data->error; 1518f95f3850SWill Newton } 1519f95f3850SWill Newton 1520f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1521f95f3850SWill Newton { 1522f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1523f95f3850SWill Newton struct mmc_data *data; 1524f95f3850SWill Newton struct mmc_command *cmd; 1525e352c813SSeungwon Jeon struct mmc_request *mrq; 1526f95f3850SWill Newton enum dw_mci_state state; 1527f95f3850SWill Newton enum dw_mci_state prev_state; 1528e352c813SSeungwon Jeon unsigned int err; 1529f95f3850SWill Newton 1530f95f3850SWill Newton spin_lock(&host->lock); 1531f95f3850SWill Newton 1532f95f3850SWill Newton state = host->state; 1533f95f3850SWill Newton data = host->data; 1534e352c813SSeungwon Jeon mrq = host->mrq; 1535f95f3850SWill Newton 1536f95f3850SWill Newton do { 1537f95f3850SWill Newton prev_state = state; 1538f95f3850SWill Newton 1539f95f3850SWill Newton switch (state) { 1540f95f3850SWill Newton case STATE_IDLE: 154101730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1542f95f3850SWill Newton break; 1543f95f3850SWill Newton 154401730558SDoug Anderson case STATE_SENDING_CMD11: 1545f95f3850SWill Newton case STATE_SENDING_CMD: 1546f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1547f95f3850SWill Newton &host->pending_events)) 1548f95f3850SWill Newton break; 1549f95f3850SWill Newton 1550f95f3850SWill Newton cmd = host->cmd; 1551f95f3850SWill Newton host->cmd = NULL; 1552f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1553e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1554e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1555053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1556053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1557e352c813SSeungwon Jeon mrq->cmd); 1558053b3ce6SSeungwon Jeon goto unlock; 1559053b3ce6SSeungwon Jeon } 1560053b3ce6SSeungwon Jeon 1561e352c813SSeungwon Jeon if (cmd->data && err) { 156271abb133SSeungwon Jeon dw_mci_stop_dma(host); 156390c2143aSSeungwon Jeon send_stop_abort(host, data); 156471abb133SSeungwon Jeon state = STATE_SENDING_STOP; 156571abb133SSeungwon Jeon break; 156671abb133SSeungwon Jeon } 156771abb133SSeungwon Jeon 1568e352c813SSeungwon Jeon if (!cmd->data || err) { 1569e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1570f95f3850SWill Newton goto unlock; 1571f95f3850SWill Newton } 1572f95f3850SWill Newton 1573f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1574f95f3850SWill Newton /* fall through */ 1575f95f3850SWill Newton 1576f95f3850SWill Newton case STATE_SENDING_DATA: 15772aa35465SDoug Anderson /* 15782aa35465SDoug Anderson * We could get a data error and never a transfer 15792aa35465SDoug Anderson * complete so we'd better check for it here. 15802aa35465SDoug Anderson * 15812aa35465SDoug Anderson * Note that we don't really care if we also got a 15822aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 15832aa35465SDoug Anderson * abort won't hurt. 15842aa35465SDoug Anderson */ 1585f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1586f95f3850SWill Newton &host->pending_events)) { 1587f95f3850SWill Newton dw_mci_stop_dma(host); 1588bdb9a90bSaddy ke if (data->stop || 1589bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1590bdb9a90bSaddy ke SDMMC_INT_EBE))) 159190c2143aSSeungwon Jeon send_stop_abort(host, data); 1592f95f3850SWill Newton state = STATE_DATA_ERROR; 1593f95f3850SWill Newton break; 1594f95f3850SWill Newton } 1595f95f3850SWill Newton 1596f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1597f95f3850SWill Newton &host->pending_events)) 1598f95f3850SWill Newton break; 1599f95f3850SWill Newton 1600f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 16012aa35465SDoug Anderson 16022aa35465SDoug Anderson /* 16032aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 16042aa35465SDoug Anderson * before the transfer completed. This might not have 16052aa35465SDoug Anderson * been caught by the check above because the interrupt 16062aa35465SDoug Anderson * could have gone off between the previous check and 16072aa35465SDoug Anderson * the check for transfer complete. 16082aa35465SDoug Anderson * 16092aa35465SDoug Anderson * Technically this ought not be needed assuming we 16102aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 16112aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 16122aa35465SDoug Anderson * 16132aa35465SDoug Anderson * This has the advantage of sending the stop command. 16142aa35465SDoug Anderson */ 16152aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 16162aa35465SDoug Anderson &host->pending_events)) { 16172aa35465SDoug Anderson dw_mci_stop_dma(host); 1618bdb9a90bSaddy ke if (data->stop || 1619bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1620bdb9a90bSaddy ke SDMMC_INT_EBE))) 16212aa35465SDoug Anderson send_stop_abort(host, data); 16222aa35465SDoug Anderson state = STATE_DATA_ERROR; 16232aa35465SDoug Anderson break; 16242aa35465SDoug Anderson } 1625f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 16262aa35465SDoug Anderson 1627f95f3850SWill Newton /* fall through */ 1628f95f3850SWill Newton 1629f95f3850SWill Newton case STATE_DATA_BUSY: 1630f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1631f95f3850SWill Newton &host->pending_events)) 1632f95f3850SWill Newton break; 1633f95f3850SWill Newton 1634f95f3850SWill Newton host->data = NULL; 1635f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1636e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1637f95f3850SWill Newton 1638e352c813SSeungwon Jeon if (!err) { 1639e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 164017c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1641053b3ce6SSeungwon Jeon data->stop->error = 0; 1642e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1643053b3ce6SSeungwon Jeon goto unlock; 1644053b3ce6SSeungwon Jeon } 1645053b3ce6SSeungwon Jeon 164690c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1647e352c813SSeungwon Jeon if (data->stop) 164890c2143aSSeungwon Jeon send_stop_abort(host, data); 16492aa35465SDoug Anderson } else { 16502aa35465SDoug Anderson /* 16512aa35465SDoug Anderson * If we don't have a command complete now we'll 16522aa35465SDoug Anderson * never get one since we just reset everything; 16532aa35465SDoug Anderson * better end the request. 16542aa35465SDoug Anderson * 16552aa35465SDoug Anderson * If we do have a command complete we'll fall 16562aa35465SDoug Anderson * through to the SENDING_STOP command and 16572aa35465SDoug Anderson * everything will be peachy keen. 16582aa35465SDoug Anderson */ 16592aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 16602aa35465SDoug Anderson &host->pending_events)) { 16612aa35465SDoug Anderson host->cmd = NULL; 16622aa35465SDoug Anderson dw_mci_request_end(host, mrq); 16632aa35465SDoug Anderson goto unlock; 16642aa35465SDoug Anderson } 166590c2143aSSeungwon Jeon } 1666e352c813SSeungwon Jeon 1667e352c813SSeungwon Jeon /* 1668e352c813SSeungwon Jeon * If err has non-zero, 1669e352c813SSeungwon Jeon * stop-abort command has been already issued. 1670e352c813SSeungwon Jeon */ 1671e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1672e352c813SSeungwon Jeon 1673f95f3850SWill Newton /* fall through */ 1674f95f3850SWill Newton 1675f95f3850SWill Newton case STATE_SENDING_STOP: 1676f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1677f95f3850SWill Newton &host->pending_events)) 1678f95f3850SWill Newton break; 1679f95f3850SWill Newton 168071abb133SSeungwon Jeon /* CMD error in data command */ 168131bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 16823a33a94cSSonny Rao dw_mci_reset(host); 168371abb133SSeungwon Jeon 1684f95f3850SWill Newton host->cmd = NULL; 168571abb133SSeungwon Jeon host->data = NULL; 168690c2143aSSeungwon Jeon 1687e352c813SSeungwon Jeon if (mrq->stop) 1688e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 168990c2143aSSeungwon Jeon else 169090c2143aSSeungwon Jeon host->cmd_status = 0; 169190c2143aSSeungwon Jeon 1692e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1693f95f3850SWill Newton goto unlock; 1694f95f3850SWill Newton 1695f95f3850SWill Newton case STATE_DATA_ERROR: 1696f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1697f95f3850SWill Newton &host->pending_events)) 1698f95f3850SWill Newton break; 1699f95f3850SWill Newton 1700f95f3850SWill Newton state = STATE_DATA_BUSY; 1701f95f3850SWill Newton break; 1702f95f3850SWill Newton } 1703f95f3850SWill Newton } while (state != prev_state); 1704f95f3850SWill Newton 1705f95f3850SWill Newton host->state = state; 1706f95f3850SWill Newton unlock: 1707f95f3850SWill Newton spin_unlock(&host->lock); 1708f95f3850SWill Newton 1709f95f3850SWill Newton } 1710f95f3850SWill Newton 171134b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 171234b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 171334b664a2SJames Hogan { 171434b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 171534b664a2SJames Hogan host->part_buf_count = cnt; 171634b664a2SJames Hogan } 171734b664a2SJames Hogan 171834b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 171934b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 172034b664a2SJames Hogan { 172134b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 172234b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 172334b664a2SJames Hogan host->part_buf_count += cnt; 172434b664a2SJames Hogan return cnt; 172534b664a2SJames Hogan } 172634b664a2SJames Hogan 172734b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 172834b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 172934b664a2SJames Hogan { 173034b664a2SJames Hogan cnt = min(cnt, (int)host->part_buf_count); 173134b664a2SJames Hogan if (cnt) { 173234b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 173334b664a2SJames Hogan cnt); 173434b664a2SJames Hogan host->part_buf_count -= cnt; 173534b664a2SJames Hogan host->part_buf_start += cnt; 173634b664a2SJames Hogan } 173734b664a2SJames Hogan return cnt; 173834b664a2SJames Hogan } 173934b664a2SJames Hogan 174034b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 174134b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 174234b664a2SJames Hogan { 174334b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 174434b664a2SJames Hogan host->part_buf_start = cnt; 174534b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 174634b664a2SJames Hogan } 174734b664a2SJames Hogan 1748f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1749f95f3850SWill Newton { 1750cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1751cfbeb59cSMarkos Chandras int init_cnt = cnt; 1752cfbeb59cSMarkos Chandras 175334b664a2SJames Hogan /* try and push anything in the part_buf */ 175434b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 175534b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 175634b664a2SJames Hogan buf += len; 175734b664a2SJames Hogan cnt -= len; 1758cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 17594e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17604e0a5adfSJaehoon Chung host->part_buf16); 176134b664a2SJames Hogan host->part_buf_count = 0; 176234b664a2SJames Hogan } 176334b664a2SJames Hogan } 176434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 176534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 176634b664a2SJames Hogan while (cnt >= 2) { 176734b664a2SJames Hogan u16 aligned_buf[64]; 176834b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 176934b664a2SJames Hogan int items = len >> 1; 177034b664a2SJames Hogan int i; 177134b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 177234b664a2SJames Hogan memcpy(aligned_buf, buf, len); 177334b664a2SJames Hogan buf += len; 177434b664a2SJames Hogan cnt -= len; 177534b664a2SJames Hogan /* push data from aligned buffer into fifo */ 177634b664a2SJames Hogan for (i = 0; i < items; ++i) 17774e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17784e0a5adfSJaehoon Chung aligned_buf[i]); 177934b664a2SJames Hogan } 178034b664a2SJames Hogan } else 178134b664a2SJames Hogan #endif 178234b664a2SJames Hogan { 178334b664a2SJames Hogan u16 *pdata = buf; 178434b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 17854e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), *pdata++); 178634b664a2SJames Hogan buf = pdata; 178734b664a2SJames Hogan } 178834b664a2SJames Hogan /* put anything remaining in the part_buf */ 178934b664a2SJames Hogan if (cnt) { 179034b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1791cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1792cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1793cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 17944e0a5adfSJaehoon Chung mci_writew(host, DATA(host->data_offset), 17954e0a5adfSJaehoon Chung host->part_buf16); 1796f95f3850SWill Newton } 1797f95f3850SWill Newton } 1798f95f3850SWill Newton 1799f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1800f95f3850SWill Newton { 180134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 180234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 180334b664a2SJames Hogan while (cnt >= 2) { 180434b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 180534b664a2SJames Hogan u16 aligned_buf[64]; 180634b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 180734b664a2SJames Hogan int items = len >> 1; 180834b664a2SJames Hogan int i; 180934b664a2SJames Hogan for (i = 0; i < items; ++i) 18104e0a5adfSJaehoon Chung aligned_buf[i] = mci_readw(host, 18114e0a5adfSJaehoon Chung DATA(host->data_offset)); 181234b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 181334b664a2SJames Hogan memcpy(buf, aligned_buf, len); 181434b664a2SJames Hogan buf += len; 181534b664a2SJames Hogan cnt -= len; 181634b664a2SJames Hogan } 181734b664a2SJames Hogan } else 181834b664a2SJames Hogan #endif 181934b664a2SJames Hogan { 182034b664a2SJames Hogan u16 *pdata = buf; 182134b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 18224e0a5adfSJaehoon Chung *pdata++ = mci_readw(host, DATA(host->data_offset)); 182334b664a2SJames Hogan buf = pdata; 182434b664a2SJames Hogan } 182534b664a2SJames Hogan if (cnt) { 18264e0a5adfSJaehoon Chung host->part_buf16 = mci_readw(host, DATA(host->data_offset)); 182734b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1828f95f3850SWill Newton } 1829f95f3850SWill Newton } 1830f95f3850SWill Newton 1831f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1832f95f3850SWill Newton { 1833cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1834cfbeb59cSMarkos Chandras int init_cnt = cnt; 1835cfbeb59cSMarkos Chandras 183634b664a2SJames Hogan /* try and push anything in the part_buf */ 183734b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 183834b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 183934b664a2SJames Hogan buf += len; 184034b664a2SJames Hogan cnt -= len; 1841cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 18424e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18434e0a5adfSJaehoon Chung host->part_buf32); 184434b664a2SJames Hogan host->part_buf_count = 0; 184534b664a2SJames Hogan } 184634b664a2SJames Hogan } 184734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 184834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 184934b664a2SJames Hogan while (cnt >= 4) { 185034b664a2SJames Hogan u32 aligned_buf[32]; 185134b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 185234b664a2SJames Hogan int items = len >> 2; 185334b664a2SJames Hogan int i; 185434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 185534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 185634b664a2SJames Hogan buf += len; 185734b664a2SJames Hogan cnt -= len; 185834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 185934b664a2SJames Hogan for (i = 0; i < items; ++i) 18604e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18614e0a5adfSJaehoon Chung aligned_buf[i]); 186234b664a2SJames Hogan } 186334b664a2SJames Hogan } else 186434b664a2SJames Hogan #endif 186534b664a2SJames Hogan { 186634b664a2SJames Hogan u32 *pdata = buf; 186734b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 18684e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), *pdata++); 186934b664a2SJames Hogan buf = pdata; 187034b664a2SJames Hogan } 187134b664a2SJames Hogan /* put anything remaining in the part_buf */ 187234b664a2SJames Hogan if (cnt) { 187334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1874cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1875cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1876cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 18774e0a5adfSJaehoon Chung mci_writel(host, DATA(host->data_offset), 18784e0a5adfSJaehoon Chung host->part_buf32); 1879f95f3850SWill Newton } 1880f95f3850SWill Newton } 1881f95f3850SWill Newton 1882f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1883f95f3850SWill Newton { 188434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 188534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 188634b664a2SJames Hogan while (cnt >= 4) { 188734b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 188834b664a2SJames Hogan u32 aligned_buf[32]; 188934b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 189034b664a2SJames Hogan int items = len >> 2; 189134b664a2SJames Hogan int i; 189234b664a2SJames Hogan for (i = 0; i < items; ++i) 18934e0a5adfSJaehoon Chung aligned_buf[i] = mci_readl(host, 18944e0a5adfSJaehoon Chung DATA(host->data_offset)); 189534b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 189634b664a2SJames Hogan memcpy(buf, aligned_buf, len); 189734b664a2SJames Hogan buf += len; 189834b664a2SJames Hogan cnt -= len; 189934b664a2SJames Hogan } 190034b664a2SJames Hogan } else 190134b664a2SJames Hogan #endif 190234b664a2SJames Hogan { 190334b664a2SJames Hogan u32 *pdata = buf; 190434b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 19054e0a5adfSJaehoon Chung *pdata++ = mci_readl(host, DATA(host->data_offset)); 190634b664a2SJames Hogan buf = pdata; 190734b664a2SJames Hogan } 190834b664a2SJames Hogan if (cnt) { 19094e0a5adfSJaehoon Chung host->part_buf32 = mci_readl(host, DATA(host->data_offset)); 191034b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1911f95f3850SWill Newton } 1912f95f3850SWill Newton } 1913f95f3850SWill Newton 1914f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1915f95f3850SWill Newton { 1916cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1917cfbeb59cSMarkos Chandras int init_cnt = cnt; 1918cfbeb59cSMarkos Chandras 191934b664a2SJames Hogan /* try and push anything in the part_buf */ 192034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 192134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 192234b664a2SJames Hogan buf += len; 192334b664a2SJames Hogan cnt -= len; 1924c09fbd74SSeungwon Jeon 1925cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 1926c09fbd74SSeungwon Jeon mci_writeq(host, DATA(host->data_offset), 19274e0a5adfSJaehoon Chung host->part_buf); 192834b664a2SJames Hogan host->part_buf_count = 0; 192934b664a2SJames Hogan } 193034b664a2SJames Hogan } 193134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 193234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 193334b664a2SJames Hogan while (cnt >= 8) { 193434b664a2SJames Hogan u64 aligned_buf[16]; 193534b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 193634b664a2SJames Hogan int items = len >> 3; 193734b664a2SJames Hogan int i; 193834b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 193934b664a2SJames Hogan memcpy(aligned_buf, buf, len); 194034b664a2SJames Hogan buf += len; 194134b664a2SJames Hogan cnt -= len; 194234b664a2SJames Hogan /* push data from aligned buffer into fifo */ 194334b664a2SJames Hogan for (i = 0; i < items; ++i) 19444e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 19454e0a5adfSJaehoon Chung aligned_buf[i]); 194634b664a2SJames Hogan } 194734b664a2SJames Hogan } else 194834b664a2SJames Hogan #endif 194934b664a2SJames Hogan { 195034b664a2SJames Hogan u64 *pdata = buf; 195134b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 19524e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), *pdata++); 195334b664a2SJames Hogan buf = pdata; 195434b664a2SJames Hogan } 195534b664a2SJames Hogan /* put anything remaining in the part_buf */ 195634b664a2SJames Hogan if (cnt) { 195734b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1958cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1959cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1960cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 19614e0a5adfSJaehoon Chung mci_writeq(host, DATA(host->data_offset), 19624e0a5adfSJaehoon Chung host->part_buf); 1963f95f3850SWill Newton } 1964f95f3850SWill Newton } 1965f95f3850SWill Newton 1966f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1967f95f3850SWill Newton { 196834b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 196934b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 197034b664a2SJames Hogan while (cnt >= 8) { 197134b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 197234b664a2SJames Hogan u64 aligned_buf[16]; 197334b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 197434b664a2SJames Hogan int items = len >> 3; 197534b664a2SJames Hogan int i; 197634b664a2SJames Hogan for (i = 0; i < items; ++i) 19774e0a5adfSJaehoon Chung aligned_buf[i] = mci_readq(host, 19784e0a5adfSJaehoon Chung DATA(host->data_offset)); 197934b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 198034b664a2SJames Hogan memcpy(buf, aligned_buf, len); 198134b664a2SJames Hogan buf += len; 198234b664a2SJames Hogan cnt -= len; 1983f95f3850SWill Newton } 198434b664a2SJames Hogan } else 198534b664a2SJames Hogan #endif 198634b664a2SJames Hogan { 198734b664a2SJames Hogan u64 *pdata = buf; 198834b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 19894e0a5adfSJaehoon Chung *pdata++ = mci_readq(host, DATA(host->data_offset)); 199034b664a2SJames Hogan buf = pdata; 199134b664a2SJames Hogan } 199234b664a2SJames Hogan if (cnt) { 19934e0a5adfSJaehoon Chung host->part_buf = mci_readq(host, DATA(host->data_offset)); 199434b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 199534b664a2SJames Hogan } 199634b664a2SJames Hogan } 199734b664a2SJames Hogan 199834b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 199934b664a2SJames Hogan { 200034b664a2SJames Hogan int len; 200134b664a2SJames Hogan 200234b664a2SJames Hogan /* get remaining partial bytes */ 200334b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 200434b664a2SJames Hogan if (unlikely(len == cnt)) 200534b664a2SJames Hogan return; 200634b664a2SJames Hogan buf += len; 200734b664a2SJames Hogan cnt -= len; 200834b664a2SJames Hogan 200934b664a2SJames Hogan /* get the rest of the data */ 201034b664a2SJames Hogan host->pull_data(host, buf, cnt); 2011f95f3850SWill Newton } 2012f95f3850SWill Newton 201387a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2014f95f3850SWill Newton { 2015f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2016f9c2a0dcSSeungwon Jeon void *buf; 2017f9c2a0dcSSeungwon Jeon unsigned int offset; 2018f95f3850SWill Newton struct mmc_data *data = host->data; 2019f95f3850SWill Newton int shift = host->data_shift; 2020f95f3850SWill Newton u32 status; 20213e4b0d8bSMarkos Chandras unsigned int len; 2022f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2023f95f3850SWill Newton 2024f95f3850SWill Newton do { 2025f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2026f9c2a0dcSSeungwon Jeon goto done; 2027f95f3850SWill Newton 20284225fc85SImre Deak host->sg = sg_miter->piter.sg; 2029f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2030f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2031f9c2a0dcSSeungwon Jeon offset = 0; 2032f9c2a0dcSSeungwon Jeon 2033f9c2a0dcSSeungwon Jeon do { 2034f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2035f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2036f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2037f9c2a0dcSSeungwon Jeon if (!len) 2038f9c2a0dcSSeungwon Jeon break; 2039f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 20403e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2041f95f3850SWill Newton offset += len; 2042f9c2a0dcSSeungwon Jeon remain -= len; 2043f9c2a0dcSSeungwon Jeon } while (remain); 2044f95f3850SWill Newton 2045e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2046f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2047f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 204887a74d39SKyoungil Kim /* if the RXDR is ready read again */ 204987a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 205087a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2051f9c2a0dcSSeungwon Jeon 2052f9c2a0dcSSeungwon Jeon if (!remain) { 2053f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2054f9c2a0dcSSeungwon Jeon goto done; 2055f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2056f9c2a0dcSSeungwon Jeon } 2057f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2058f95f3850SWill Newton return; 2059f95f3850SWill Newton 2060f95f3850SWill Newton done: 2061f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2062f9c2a0dcSSeungwon Jeon host->sg = NULL; 2063f95f3850SWill Newton smp_wmb(); 2064f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2065f95f3850SWill Newton } 2066f95f3850SWill Newton 2067f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2068f95f3850SWill Newton { 2069f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2070f9c2a0dcSSeungwon Jeon void *buf; 2071f9c2a0dcSSeungwon Jeon unsigned int offset; 2072f95f3850SWill Newton struct mmc_data *data = host->data; 2073f95f3850SWill Newton int shift = host->data_shift; 2074f95f3850SWill Newton u32 status; 20753e4b0d8bSMarkos Chandras unsigned int len; 2076f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2077f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2078f95f3850SWill Newton 2079f95f3850SWill Newton do { 2080f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2081f9c2a0dcSSeungwon Jeon goto done; 2082f95f3850SWill Newton 20834225fc85SImre Deak host->sg = sg_miter->piter.sg; 2084f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2085f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2086f9c2a0dcSSeungwon Jeon offset = 0; 2087f9c2a0dcSSeungwon Jeon 2088f9c2a0dcSSeungwon Jeon do { 2089f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2090f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2091f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2092f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2093f9c2a0dcSSeungwon Jeon if (!len) 2094f9c2a0dcSSeungwon Jeon break; 2095f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 20963e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2097f95f3850SWill Newton offset += len; 2098f9c2a0dcSSeungwon Jeon remain -= len; 2099f9c2a0dcSSeungwon Jeon } while (remain); 2100f95f3850SWill Newton 2101e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2102f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2103f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2104f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2105f9c2a0dcSSeungwon Jeon 2106f9c2a0dcSSeungwon Jeon if (!remain) { 2107f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2108f9c2a0dcSSeungwon Jeon goto done; 2109f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2110f9c2a0dcSSeungwon Jeon } 2111f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2112f95f3850SWill Newton return; 2113f95f3850SWill Newton 2114f95f3850SWill Newton done: 2115f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2116f9c2a0dcSSeungwon Jeon host->sg = NULL; 2117f95f3850SWill Newton smp_wmb(); 2118f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2119f95f3850SWill Newton } 2120f95f3850SWill Newton 2121f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2122f95f3850SWill Newton { 2123f95f3850SWill Newton if (!host->cmd_status) 2124f95f3850SWill Newton host->cmd_status = status; 2125f95f3850SWill Newton 2126f95f3850SWill Newton smp_wmb(); 2127f95f3850SWill Newton 2128f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2129f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2130f95f3850SWill Newton } 2131f95f3850SWill Newton 21326130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 21336130e7a9SDoug Anderson { 21346130e7a9SDoug Anderson int i; 21356130e7a9SDoug Anderson 21366130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 21376130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 21386130e7a9SDoug Anderson 21396130e7a9SDoug Anderson if (!slot) 21406130e7a9SDoug Anderson continue; 21416130e7a9SDoug Anderson 21426130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 21436130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 21446130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 21456130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 21466130e7a9SDoug Anderson } 21476130e7a9SDoug Anderson } 21486130e7a9SDoug Anderson 2149f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2150f95f3850SWill Newton { 2151f95f3850SWill Newton struct dw_mci *host = dev_id; 2152182c9081SSeungwon Jeon u32 pending; 21531a5c8e1fSShashidhar Hiremath int i; 2154f95f3850SWill Newton 2155f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2156f95f3850SWill Newton 2157f95f3850SWill Newton /* 2158f95f3850SWill Newton * DTO fix - version 2.10a and below, and only if internal DMA 2159f95f3850SWill Newton * is configured. 2160f95f3850SWill Newton */ 2161f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2162f95f3850SWill Newton if (!pending && 2163f95f3850SWill Newton ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2164f95f3850SWill Newton pending |= SDMMC_INT_DATA_OVER; 2165f95f3850SWill Newton } 2166f95f3850SWill Newton 2167476d79f1SDoug Anderson if (pending) { 216801730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 216901730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 217001730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 21715c935165SDoug Anderson del_timer(&host->cmd11_timer); 21725c935165SDoug Anderson 217301730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 217401730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 217501730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 217601730558SDoug Anderson } 217701730558SDoug Anderson 2178f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2179f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2180182c9081SSeungwon Jeon host->cmd_status = pending; 2181f95f3850SWill Newton smp_wmb(); 2182f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2183f95f3850SWill Newton } 2184f95f3850SWill Newton 2185f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2186f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2187f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2188182c9081SSeungwon Jeon host->data_status = pending; 2189f95f3850SWill Newton smp_wmb(); 2190f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2191f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2192f95f3850SWill Newton } 2193f95f3850SWill Newton 2194f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 2195f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2196f95f3850SWill Newton if (!host->data_status) 2197182c9081SSeungwon Jeon host->data_status = pending; 2198f95f3850SWill Newton smp_wmb(); 2199f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2200f95f3850SWill Newton if (host->sg != NULL) 220187a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2202f95f3850SWill Newton } 2203f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2204f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2205f95f3850SWill Newton } 2206f95f3850SWill Newton 2207f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2208f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2209b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 221087a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2211f95f3850SWill Newton } 2212f95f3850SWill Newton 2213f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2214f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2215b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2216f95f3850SWill Newton dw_mci_write_data_pio(host); 2217f95f3850SWill Newton } 2218f95f3850SWill Newton 2219f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2220f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2221182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2222f95f3850SWill Newton } 2223f95f3850SWill Newton 2224f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2225f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 22266130e7a9SDoug Anderson dw_mci_handle_cd(host); 2227f95f3850SWill Newton } 2228f95f3850SWill Newton 22291a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 22301a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 22311a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2232ed2540efSDoug Anderson 2233ed2540efSDoug Anderson if (!slot) 2234ed2540efSDoug Anderson continue; 2235ed2540efSDoug Anderson 223676756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 223776756234SAddy Ke mci_writel(host, RINTSTS, 223876756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 22391a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 22401a5c8e1fSShashidhar Hiremath } 22411a5c8e1fSShashidhar Hiremath } 22421a5c8e1fSShashidhar Hiremath 22431fb5f68aSMarkos Chandras } 2244f95f3850SWill Newton 2245f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2246f95f3850SWill Newton /* Handle DMA interrupts */ 224769d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 224869d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 224969d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 225069d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 225169d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 225269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 225369d99fdcSPrabu Thangamuthu host->dma_ops->complete(host); 225469d99fdcSPrabu Thangamuthu } 225569d99fdcSPrabu Thangamuthu } else { 2256f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2257f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 225869d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 225969d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2260f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2261f95f3850SWill Newton host->dma_ops->complete(host); 2262f95f3850SWill Newton } 226369d99fdcSPrabu Thangamuthu } 2264f95f3850SWill Newton #endif 2265f95f3850SWill Newton 2266f95f3850SWill Newton return IRQ_HANDLED; 2267f95f3850SWill Newton } 2268f95f3850SWill Newton 2269c91eab4bSThomas Abraham #ifdef CONFIG_OF 2270c91eab4bSThomas Abraham /* given a slot id, find out the device node representing that slot */ 2271c91eab4bSThomas Abraham static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 2272c91eab4bSThomas Abraham { 2273c91eab4bSThomas Abraham struct device_node *np; 2274c91eab4bSThomas Abraham const __be32 *addr; 2275c91eab4bSThomas Abraham int len; 2276c91eab4bSThomas Abraham 2277c91eab4bSThomas Abraham if (!dev || !dev->of_node) 2278c91eab4bSThomas Abraham return NULL; 2279c91eab4bSThomas Abraham 2280c91eab4bSThomas Abraham for_each_child_of_node(dev->of_node, np) { 2281c91eab4bSThomas Abraham addr = of_get_property(np, "reg", &len); 2282c91eab4bSThomas Abraham if (!addr || (len < sizeof(int))) 2283c91eab4bSThomas Abraham continue; 2284c91eab4bSThomas Abraham if (be32_to_cpup(addr) == slot) 2285c91eab4bSThomas Abraham return np; 2286c91eab4bSThomas Abraham } 2287c91eab4bSThomas Abraham return NULL; 2288c91eab4bSThomas Abraham } 2289c91eab4bSThomas Abraham 2290a70aaa64SDoug Anderson static struct dw_mci_of_slot_quirks { 2291a70aaa64SDoug Anderson char *quirk; 2292a70aaa64SDoug Anderson int id; 2293a70aaa64SDoug Anderson } of_slot_quirks[] = { 2294a70aaa64SDoug Anderson { 2295a70aaa64SDoug Anderson .quirk = "disable-wp", 2296a70aaa64SDoug Anderson .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, 2297a70aaa64SDoug Anderson }, 2298a70aaa64SDoug Anderson }; 2299a70aaa64SDoug Anderson 2300a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2301a70aaa64SDoug Anderson { 2302a70aaa64SDoug Anderson struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 2303a70aaa64SDoug Anderson int quirks = 0; 2304a70aaa64SDoug Anderson int idx; 2305a70aaa64SDoug Anderson 2306a70aaa64SDoug Anderson /* get quirks */ 2307a70aaa64SDoug Anderson for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) 230826375b5cSJaehoon Chung if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) { 230926375b5cSJaehoon Chung dev_warn(dev, "Slot quirk %s is deprecated\n", 231026375b5cSJaehoon Chung of_slot_quirks[idx].quirk); 2311a70aaa64SDoug Anderson quirks |= of_slot_quirks[idx].id; 231226375b5cSJaehoon Chung } 2313a70aaa64SDoug Anderson 2314a70aaa64SDoug Anderson return quirks; 2315a70aaa64SDoug Anderson } 2316c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2317a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2318a70aaa64SDoug Anderson { 2319a70aaa64SDoug Anderson return 0; 2320a70aaa64SDoug Anderson } 2321c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2322c91eab4bSThomas Abraham 232336c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2324f95f3850SWill Newton { 2325f95f3850SWill Newton struct mmc_host *mmc; 2326f95f3850SWill Newton struct dw_mci_slot *slot; 2327e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2328800d78bfSThomas Abraham int ctrl_id, ret; 23291f44a2a5SSeungwon Jeon u32 freq[2]; 2330f95f3850SWill Newton 23314a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2332f95f3850SWill Newton if (!mmc) 2333f95f3850SWill Newton return -ENOMEM; 2334f95f3850SWill Newton 2335f95f3850SWill Newton slot = mmc_priv(mmc); 2336f95f3850SWill Newton slot->id = id; 233776756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2338f95f3850SWill Newton slot->mmc = mmc; 2339f95f3850SWill Newton slot->host = host; 2340c91eab4bSThomas Abraham host->slot[id] = slot; 2341f95f3850SWill Newton 2342a70aaa64SDoug Anderson slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 2343a70aaa64SDoug Anderson 2344f95f3850SWill Newton mmc->ops = &dw_mci_ops; 23451f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 23461f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 23471f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 23481f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 23491f44a2a5SSeungwon Jeon } else { 23501f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 23511f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 23521f44a2a5SSeungwon Jeon } 2353f95f3850SWill Newton 235451da2240SYuvaraj CD /*if there are external regulators, get them*/ 235551da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 235651da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 23573cf890fcSDoug Anderson goto err_host_allocated; 235851da2240SYuvaraj CD 235951da2240SYuvaraj CD if (!mmc->ocr_avail) 2360f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2361f95f3850SWill Newton 2362fc3d7720SJaehoon Chung if (host->pdata->caps) 2363fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2364fc3d7720SJaehoon Chung 2365ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2366ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2367ab269128SAbhilash Kesavan 2368800d78bfSThomas Abraham if (host->dev->of_node) { 2369800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2370800d78bfSThomas Abraham if (ctrl_id < 0) 2371800d78bfSThomas Abraham ctrl_id = 0; 2372800d78bfSThomas Abraham } else { 2373800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2374800d78bfSThomas Abraham } 2375cb27a843SJames Hogan if (drv_data && drv_data->caps) 2376cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2377800d78bfSThomas Abraham 23784f408cc6SSeungwon Jeon if (host->pdata->caps2) 23794f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 23804f408cc6SSeungwon Jeon 23813cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 23823cf890fcSDoug Anderson if (ret) 23833cf890fcSDoug Anderson goto err_host_allocated; 2384f95f3850SWill Newton 2385f95f3850SWill Newton if (host->pdata->blk_settings) { 2386f95f3850SWill Newton mmc->max_segs = host->pdata->blk_settings->max_segs; 2387f95f3850SWill Newton mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 2388f95f3850SWill Newton mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 2389f95f3850SWill Newton mmc->max_req_size = host->pdata->blk_settings->max_req_size; 2390f95f3850SWill Newton mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 2391f95f3850SWill Newton } else { 2392f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 2393a39e5746SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 2394a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2395a39e5746SJaehoon Chung mmc->max_blk_size = 65536; 2396a39e5746SJaehoon Chung mmc->max_seg_size = 0x1000; 23971a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 23981a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 2399a39e5746SJaehoon Chung #else 2400f95f3850SWill Newton mmc->max_segs = 64; 2401f95f3850SWill Newton mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2402f95f3850SWill Newton mmc->max_blk_count = 512; 2403f95f3850SWill Newton mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2404f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2405f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 2406a39e5746SJaehoon Chung } 2407f95f3850SWill Newton 2408ae0eb348SJaehoon Chung if (dw_mci_get_cd(mmc)) 2409ae0eb348SJaehoon Chung set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2410ae0eb348SJaehoon Chung else 2411ae0eb348SJaehoon Chung clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2412ae0eb348SJaehoon Chung 24130cea529dSJaehoon Chung ret = mmc_add_host(mmc); 24140cea529dSJaehoon Chung if (ret) 24153cf890fcSDoug Anderson goto err_host_allocated; 2416f95f3850SWill Newton 2417f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2418f95f3850SWill Newton dw_mci_init_debugfs(slot); 2419f95f3850SWill Newton #endif 2420f95f3850SWill Newton 2421f95f3850SWill Newton return 0; 2422800d78bfSThomas Abraham 24233cf890fcSDoug Anderson err_host_allocated: 2424800d78bfSThomas Abraham mmc_free_host(mmc); 242551da2240SYuvaraj CD return ret; 2426f95f3850SWill Newton } 2427f95f3850SWill Newton 2428f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2429f95f3850SWill Newton { 2430f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2431f95f3850SWill Newton mmc_remove_host(slot->mmc); 2432f95f3850SWill Newton slot->host->slot[id] = NULL; 2433f95f3850SWill Newton mmc_free_host(slot->mmc); 2434f95f3850SWill Newton } 2435f95f3850SWill Newton 2436f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2437f95f3850SWill Newton { 243869d99fdcSPrabu Thangamuthu int addr_config; 243969d99fdcSPrabu Thangamuthu /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ 244069d99fdcSPrabu Thangamuthu addr_config = (mci_readl(host, HCON) >> 27) & 0x01; 244169d99fdcSPrabu Thangamuthu 244269d99fdcSPrabu Thangamuthu if (addr_config == 1) { 244369d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 244469d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 244569d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); 244669d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 244769d99fdcSPrabu Thangamuthu dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); 244869d99fdcSPrabu Thangamuthu } else { 244969d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 245069d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 245169d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); 245269d99fdcSPrabu Thangamuthu } 245369d99fdcSPrabu Thangamuthu 2454f95f3850SWill Newton /* Alloc memory for sg translation */ 2455780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2456f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2457f95f3850SWill Newton if (!host->sg_cpu) { 24584a90920cSThomas Abraham dev_err(host->dev, "%s: could not alloc DMA memory\n", 2459f95f3850SWill Newton __func__); 2460f95f3850SWill Newton goto no_dma; 2461f95f3850SWill Newton } 2462f95f3850SWill Newton 2463f95f3850SWill Newton /* Determine which DMA interface to use */ 2464f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2465f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 246600956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 2467f95f3850SWill Newton #endif 2468f95f3850SWill Newton 2469f95f3850SWill Newton if (!host->dma_ops) 2470f95f3850SWill Newton goto no_dma; 2471f95f3850SWill Newton 2472e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2473e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2474f95f3850SWill Newton if (host->dma_ops->init(host)) { 24754a90920cSThomas Abraham dev_err(host->dev, "%s: Unable to initialize " 2476f95f3850SWill Newton "DMA Controller.\n", __func__); 2477f95f3850SWill Newton goto no_dma; 2478f95f3850SWill Newton } 2479f95f3850SWill Newton } else { 24804a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2481f95f3850SWill Newton goto no_dma; 2482f95f3850SWill Newton } 2483f95f3850SWill Newton 2484f95f3850SWill Newton host->use_dma = 1; 2485f95f3850SWill Newton return; 2486f95f3850SWill Newton 2487f95f3850SWill Newton no_dma: 24884a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 2489f95f3850SWill Newton host->use_dma = 0; 2490f95f3850SWill Newton return; 2491f95f3850SWill Newton } 2492f95f3850SWill Newton 249331bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2494f95f3850SWill Newton { 2495f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 249631bff450SSeungwon Jeon u32 ctrl; 2497f95f3850SWill Newton 249831bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 249931bff450SSeungwon Jeon ctrl |= reset; 250031bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2501f95f3850SWill Newton 2502f95f3850SWill Newton /* wait till resets clear */ 2503f95f3850SWill Newton do { 2504f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 250531bff450SSeungwon Jeon if (!(ctrl & reset)) 2506f95f3850SWill Newton return true; 2507f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2508f95f3850SWill Newton 250931bff450SSeungwon Jeon dev_err(host->dev, 251031bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 251131bff450SSeungwon Jeon ctrl & reset); 2512f95f3850SWill Newton 2513f95f3850SWill Newton return false; 2514f95f3850SWill Newton } 2515f95f3850SWill Newton 25163a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 251731bff450SSeungwon Jeon { 25183a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 25193a33a94cSSonny Rao bool ret = false; 25203a33a94cSSonny Rao 252131bff450SSeungwon Jeon /* 252231bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 252331bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 252431bff450SSeungwon Jeon */ 252531bff450SSeungwon Jeon if (host->sg) { 252631bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 252731bff450SSeungwon Jeon host->sg = NULL; 252831bff450SSeungwon Jeon } 252931bff450SSeungwon Jeon 25303a33a94cSSonny Rao if (host->use_dma) 25313a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 25323a33a94cSSonny Rao 25333a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 25343a33a94cSSonny Rao /* 25353a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 25363a33a94cSSonny Rao * interrupts. 25373a33a94cSSonny Rao */ 25383a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 25393a33a94cSSonny Rao 25403a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 25413a33a94cSSonny Rao if (host->use_dma) { 25423a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 25433a33a94cSSonny Rao u32 status; 25443a33a94cSSonny Rao do { 25453a33a94cSSonny Rao status = mci_readl(host, STATUS); 25463a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 25473a33a94cSSonny Rao break; 25483a33a94cSSonny Rao cpu_relax(); 25493a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 25503a33a94cSSonny Rao 25513a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 25523a33a94cSSonny Rao dev_err(host->dev, 25533a33a94cSSonny Rao "%s: Timeout waiting for dma_req to " 25543a33a94cSSonny Rao "clear during reset\n", __func__); 25553a33a94cSSonny Rao goto ciu_out; 255631bff450SSeungwon Jeon } 255731bff450SSeungwon Jeon 25583a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 25593a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 25603a33a94cSSonny Rao goto ciu_out; 25613a33a94cSSonny Rao } 25623a33a94cSSonny Rao } else { 25633a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 25643a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 25653a33a94cSSonny Rao dev_err(host->dev, "%s: fifo/dma reset bits didn't " 25663a33a94cSSonny Rao "clear but ciu was reset, doing clock update\n", 25673a33a94cSSonny Rao __func__); 25683a33a94cSSonny Rao goto ciu_out; 25693a33a94cSSonny Rao } 25703a33a94cSSonny Rao } 25713a33a94cSSonny Rao 25723a33a94cSSonny Rao #if IS_ENABLED(CONFIG_MMC_DW_IDMAC) 25733a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 25743a33a94cSSonny Rao dw_mci_idmac_reset(host); 25753a33a94cSSonny Rao #endif 25763a33a94cSSonny Rao 25773a33a94cSSonny Rao ret = true; 25783a33a94cSSonny Rao 25793a33a94cSSonny Rao ciu_out: 25803a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 25813a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 25823a33a94cSSonny Rao 25833a33a94cSSonny Rao return ret; 258431bff450SSeungwon Jeon } 258531bff450SSeungwon Jeon 25865c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 25875c935165SDoug Anderson { 25885c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 25895c935165SDoug Anderson 25905c935165SDoug Anderson if (host->state != STATE_SENDING_CMD11) 25915c935165SDoug Anderson dev_info(host->dev, "Unexpected CMD11 timeout\n"); 25925c935165SDoug Anderson 25935c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 25945c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 25955c935165SDoug Anderson tasklet_schedule(&host->tasklet); 25965c935165SDoug Anderson } 25975c935165SDoug Anderson 2598c91eab4bSThomas Abraham #ifdef CONFIG_OF 2599c91eab4bSThomas Abraham static struct dw_mci_of_quirks { 2600c91eab4bSThomas Abraham char *quirk; 2601c91eab4bSThomas Abraham int id; 2602c91eab4bSThomas Abraham } of_quirks[] = { 2603c91eab4bSThomas Abraham { 2604c91eab4bSThomas Abraham .quirk = "broken-cd", 2605c91eab4bSThomas Abraham .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 260626375b5cSJaehoon Chung }, { 260726375b5cSJaehoon Chung .quirk = "disable-wp", 260826375b5cSJaehoon Chung .id = DW_MCI_QUIRK_NO_WRITE_PROTECT, 2609c91eab4bSThomas Abraham }, 2610c91eab4bSThomas Abraham }; 2611c91eab4bSThomas Abraham 2612c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2613c91eab4bSThomas Abraham { 2614c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2615c91eab4bSThomas Abraham struct device *dev = host->dev; 2616c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2617e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2618800d78bfSThomas Abraham int idx, ret; 26193c6d89eaSDoug Anderson u32 clock_frequency; 2620c91eab4bSThomas Abraham 2621c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2622bf3707eaSBeomho Seo if (!pdata) 2623c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2624c91eab4bSThomas Abraham 2625c91eab4bSThomas Abraham /* find out number of slots supported */ 2626c91eab4bSThomas Abraham if (of_property_read_u32(dev->of_node, "num-slots", 2627c91eab4bSThomas Abraham &pdata->num_slots)) { 2628c91eab4bSThomas Abraham dev_info(dev, "num-slots property not found, " 2629c91eab4bSThomas Abraham "assuming 1 slot is available\n"); 2630c91eab4bSThomas Abraham pdata->num_slots = 1; 2631c91eab4bSThomas Abraham } 2632c91eab4bSThomas Abraham 2633c91eab4bSThomas Abraham /* get quirks */ 2634c91eab4bSThomas Abraham for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2635c91eab4bSThomas Abraham if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2636c91eab4bSThomas Abraham pdata->quirks |= of_quirks[idx].id; 2637c91eab4bSThomas Abraham 2638c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2639c91eab4bSThomas Abraham dev_info(dev, "fifo-depth property not found, using " 2640c91eab4bSThomas Abraham "value of FIFOTH register as default\n"); 2641c91eab4bSThomas Abraham 2642c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2643c91eab4bSThomas Abraham 26443c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 26453c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 26463c6d89eaSDoug Anderson 2647cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2648cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2649800d78bfSThomas Abraham if (ret) 2650800d78bfSThomas Abraham return ERR_PTR(ret); 2651800d78bfSThomas Abraham } 2652800d78bfSThomas Abraham 265310b49841SSeungwon Jeon if (of_find_property(np, "supports-highspeed", NULL)) 265410b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 265510b49841SSeungwon Jeon 2656c91eab4bSThomas Abraham return pdata; 2657c91eab4bSThomas Abraham } 2658c91eab4bSThomas Abraham 2659c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2660c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2661c91eab4bSThomas Abraham { 2662c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2663c91eab4bSThomas Abraham } 2664c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2665c91eab4bSThomas Abraham 2666fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2667fa0c3283SDoug Anderson { 2668fa0c3283SDoug Anderson struct dw_mci_board *brd = host->pdata; 2669fa0c3283SDoug Anderson unsigned long irqflags; 2670fa0c3283SDoug Anderson u32 temp; 2671fa0c3283SDoug Anderson int i; 2672fa0c3283SDoug Anderson 2673fa0c3283SDoug Anderson /* No need for CD if broken card detection */ 2674fa0c3283SDoug Anderson if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 2675fa0c3283SDoug Anderson return; 2676fa0c3283SDoug Anderson 2677fa0c3283SDoug Anderson /* No need for CD if all slots have a non-error GPIO */ 2678fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 2679fa0c3283SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 2680fa0c3283SDoug Anderson 2681fa0c3283SDoug Anderson if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) 2682fa0c3283SDoug Anderson break; 2683fa0c3283SDoug Anderson } 2684fa0c3283SDoug Anderson if (i == host->num_slots) 2685fa0c3283SDoug Anderson return; 2686fa0c3283SDoug Anderson 2687fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 2688fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 2689fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 2690fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 2691fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2692fa0c3283SDoug Anderson } 2693fa0c3283SDoug Anderson 269462ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2695f95f3850SWill Newton { 2696e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 269762ca8034SShashidhar Hiremath int width, i, ret = 0; 2698f95f3850SWill Newton u32 fifo_size; 26991c2215b7SThomas Abraham int init_slots = 0; 2700f95f3850SWill Newton 2701c91eab4bSThomas Abraham if (!host->pdata) { 2702c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2703c91eab4bSThomas Abraham if (IS_ERR(host->pdata)) { 2704c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2705c91eab4bSThomas Abraham return -EINVAL; 2706c91eab4bSThomas Abraham } 2707f95f3850SWill Newton } 2708f95f3850SWill Newton 2709907abd51SJaehoon Chung if (host->pdata->num_slots > 1) { 27104a90920cSThomas Abraham dev_err(host->dev, 2711907abd51SJaehoon Chung "Platform data must supply num_slots.\n"); 271262ca8034SShashidhar Hiremath return -ENODEV; 2713f95f3850SWill Newton } 2714f95f3850SWill Newton 2715780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2716f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2717f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2718f90a0612SThomas Abraham } else { 2719f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2720f90a0612SThomas Abraham if (ret) { 2721f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2722f90a0612SThomas Abraham return ret; 2723f90a0612SThomas Abraham } 2724f95f3850SWill Newton } 2725f95f3850SWill Newton 2726780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2727f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2728f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 27293c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2730f90a0612SThomas Abraham } else { 2731f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2732f90a0612SThomas Abraham if (ret) { 2733f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2734f90a0612SThomas Abraham goto err_clk_biu; 2735f90a0612SThomas Abraham } 2736f90a0612SThomas Abraham 27373c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 27383c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 27393c6d89eaSDoug Anderson if (ret) 27403c6d89eaSDoug Anderson dev_warn(host->dev, 2741612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 27423c6d89eaSDoug Anderson host->pdata->bus_hz); 27433c6d89eaSDoug Anderson } 2744f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 27453c6d89eaSDoug Anderson } 2746f90a0612SThomas Abraham 2747612de4c1SJaehoon Chung if (!host->bus_hz) { 2748612de4c1SJaehoon Chung dev_err(host->dev, 2749612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 2750612de4c1SJaehoon Chung ret = -ENODEV; 2751612de4c1SJaehoon Chung goto err_clk_ciu; 2752612de4c1SJaehoon Chung } 2753612de4c1SJaehoon Chung 2754002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 2755002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 2756002f0d5cSYuvaraj Kumar C D if (ret) { 2757002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 2758002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 2759002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 2760002f0d5cSYuvaraj Kumar C D } 2761002f0d5cSYuvaraj Kumar C D } 2762002f0d5cSYuvaraj Kumar C D 2763cb27a843SJames Hogan if (drv_data && drv_data->setup_clock) { 2764cb27a843SJames Hogan ret = drv_data->setup_clock(host); 2765800d78bfSThomas Abraham if (ret) { 2766800d78bfSThomas Abraham dev_err(host->dev, 2767800d78bfSThomas Abraham "implementation specific clock setup failed\n"); 2768800d78bfSThomas Abraham goto err_clk_ciu; 2769800d78bfSThomas Abraham } 2770800d78bfSThomas Abraham } 2771800d78bfSThomas Abraham 27725c935165SDoug Anderson setup_timer(&host->cmd11_timer, 27735c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 27745c935165SDoug Anderson 277562ca8034SShashidhar Hiremath host->quirks = host->pdata->quirks; 2776f95f3850SWill Newton 2777f95f3850SWill Newton spin_lock_init(&host->lock); 2778f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 2779f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 2780f95f3850SWill Newton 2781f95f3850SWill Newton /* 2782f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 2783f95f3850SWill Newton * the correct values. 2784f95f3850SWill Newton */ 2785f95f3850SWill Newton i = (mci_readl(host, HCON) >> 7) & 0x7; 2786f95f3850SWill Newton if (!i) { 2787f95f3850SWill Newton host->push_data = dw_mci_push_data16; 2788f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 2789f95f3850SWill Newton width = 16; 2790f95f3850SWill Newton host->data_shift = 1; 2791f95f3850SWill Newton } else if (i == 2) { 2792f95f3850SWill Newton host->push_data = dw_mci_push_data64; 2793f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 2794f95f3850SWill Newton width = 64; 2795f95f3850SWill Newton host->data_shift = 3; 2796f95f3850SWill Newton } else { 2797f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 2798f95f3850SWill Newton WARN((i != 1), 2799f95f3850SWill Newton "HCON reports a reserved host data width!\n" 2800f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 2801f95f3850SWill Newton host->push_data = dw_mci_push_data32; 2802f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 2803f95f3850SWill Newton width = 32; 2804f95f3850SWill Newton host->data_shift = 2; 2805f95f3850SWill Newton } 2806f95f3850SWill Newton 2807f95f3850SWill Newton /* Reset all blocks */ 28083a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 2809141a712aSSeungwon Jeon return -ENODEV; 2810141a712aSSeungwon Jeon 2811141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 2812141a712aSSeungwon Jeon dw_mci_init_dma(host); 2813f95f3850SWill Newton 2814f95f3850SWill Newton /* Clear the interrupts for the host controller */ 2815f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2816f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2817f95f3850SWill Newton 2818f95f3850SWill Newton /* Put in max timeout */ 2819f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 2820f95f3850SWill Newton 2821f95f3850SWill Newton /* 2822f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2823f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 2824f95f3850SWill Newton */ 2825b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 2826b86d8253SJames Hogan /* 2827b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2828b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 2829b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 2830b86d8253SJames Hogan * should put it in the platform data. 2831b86d8253SJames Hogan */ 2832f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 28338234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2834b86d8253SJames Hogan } else { 2835b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 2836b86d8253SJames Hogan } 2837b86d8253SJames Hogan host->fifo_depth = fifo_size; 283852426899SSeungwon Jeon host->fifoth_val = 283952426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 2840e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 2841f95f3850SWill Newton 2842f95f3850SWill Newton /* disable clock to CIU */ 2843f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2844f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2845f95f3850SWill Newton 284663008768SJames Hogan /* 284763008768SJames Hogan * In 2.40a spec, Data offset is changed. 284863008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 284963008768SJames Hogan */ 285063008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 285163008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 285263008768SJames Hogan 285363008768SJames Hogan if (host->verid < DW_MMC_240A) 285463008768SJames Hogan host->data_offset = DATA_OFFSET; 285563008768SJames Hogan else 285663008768SJames Hogan host->data_offset = DATA_240A_OFFSET; 285763008768SJames Hogan 2858f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2859780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2860780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 2861f95f3850SWill Newton if (ret) 28626130e7a9SDoug Anderson goto err_dmaunmap; 2863f95f3850SWill Newton 2864f95f3850SWill Newton if (host->pdata->num_slots) 2865f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 2866f95f3850SWill Newton else 2867f95f3850SWill Newton host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2868f95f3850SWill Newton 28692da1d7f2SYuvaraj CD /* 2870fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 28712da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 28722da1d7f2SYuvaraj CD */ 28732da1d7f2SYuvaraj CD mci_writel(host, RINTSTS, 0xFFFFFFFF); 28742da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 28752da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2876fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 28772da1d7f2SYuvaraj CD mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 28782da1d7f2SYuvaraj CD 28792da1d7f2SYuvaraj CD dev_info(host->dev, "DW MMC controller at irq %d, " 28802da1d7f2SYuvaraj CD "%d bit host data width, " 28812da1d7f2SYuvaraj CD "%u deep fifo\n", 28822da1d7f2SYuvaraj CD host->irq, width, fifo_size); 28832da1d7f2SYuvaraj CD 2884f95f3850SWill Newton /* We need at least one slot to succeed */ 2885f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2886f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 28871c2215b7SThomas Abraham if (ret) 28881c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 28891c2215b7SThomas Abraham else 28901c2215b7SThomas Abraham init_slots++; 2891f95f3850SWill Newton } 28921c2215b7SThomas Abraham 28931c2215b7SThomas Abraham if (init_slots) { 28941c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 28951c2215b7SThomas Abraham } else { 28961c2215b7SThomas Abraham dev_dbg(host->dev, "attempted to initialize %d slots, " 28971c2215b7SThomas Abraham "but failed on all\n", host->num_slots); 28986130e7a9SDoug Anderson goto err_dmaunmap; 2899f95f3850SWill Newton } 2900f95f3850SWill Newton 2901*b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 2902*b793f658SDoug Anderson dw_mci_enable_cd(host); 2903*b793f658SDoug Anderson 2904f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 29054a90920cSThomas Abraham dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2906f95f3850SWill Newton 2907f95f3850SWill Newton return 0; 2908f95f3850SWill Newton 2909f95f3850SWill Newton err_dmaunmap: 2910f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2911f95f3850SWill Newton host->dma_ops->exit(host); 2912f90a0612SThomas Abraham 2913f90a0612SThomas Abraham err_clk_ciu: 2914780f22afSSeungwon Jeon if (!IS_ERR(host->ciu_clk)) 2915f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2916780f22afSSeungwon Jeon 2917f90a0612SThomas Abraham err_clk_biu: 2918780f22afSSeungwon Jeon if (!IS_ERR(host->biu_clk)) 2919f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2920780f22afSSeungwon Jeon 2921f95f3850SWill Newton return ret; 2922f95f3850SWill Newton } 292362ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 2924f95f3850SWill Newton 292562ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 2926f95f3850SWill Newton { 2927f95f3850SWill Newton int i; 2928f95f3850SWill Newton 2929f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2930f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2931f95f3850SWill Newton 2932f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 29334a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 2934f95f3850SWill Newton if (host->slot[i]) 2935f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 2936f95f3850SWill Newton } 2937f95f3850SWill Newton 2938f95f3850SWill Newton /* disable clock to CIU */ 2939f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2940f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2941f95f3850SWill Newton 2942f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2943f95f3850SWill Newton host->dma_ops->exit(host); 2944f95f3850SWill Newton 2945f90a0612SThomas Abraham if (!IS_ERR(host->ciu_clk)) 2946f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2947780f22afSSeungwon Jeon 2948f90a0612SThomas Abraham if (!IS_ERR(host->biu_clk)) 2949f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2950f95f3850SWill Newton } 295162ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 295262ca8034SShashidhar Hiremath 295362ca8034SShashidhar Hiremath 2954f95f3850SWill Newton 29556fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 2956f95f3850SWill Newton /* 2957f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 2958f95f3850SWill Newton */ 295962ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 2960f95f3850SWill Newton { 2961f95f3850SWill Newton return 0; 2962f95f3850SWill Newton } 296362ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 2964f95f3850SWill Newton 296562ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 2966f95f3850SWill Newton { 2967f95f3850SWill Newton int i, ret; 2968f95f3850SWill Newton 29693a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 2970e61cf118SJaehoon Chung ret = -ENODEV; 2971e61cf118SJaehoon Chung return ret; 2972e61cf118SJaehoon Chung } 2973e61cf118SJaehoon Chung 29743bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 2975141a712aSSeungwon Jeon host->dma_ops->init(host); 2976141a712aSSeungwon Jeon 297752426899SSeungwon Jeon /* 297852426899SSeungwon Jeon * Restore the initial value at FIFOTH register 297952426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 298052426899SSeungwon Jeon */ 2981e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 298252426899SSeungwon Jeon host->prev_blksz = 0; 2983e61cf118SJaehoon Chung 29842eb2944fSDoug Anderson /* Put in max timeout */ 29852eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 29862eb2944fSDoug Anderson 2987e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 2988e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2989e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2990fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 2991e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2992e61cf118SJaehoon Chung 2993f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2994f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 2995f95f3850SWill Newton if (!slot) 2996f95f3850SWill Newton continue; 2997ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 2998ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 2999ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 3000ab269128SAbhilash Kesavan } 3001f95f3850SWill Newton } 3002fa0c3283SDoug Anderson 3003fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3004fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3005fa0c3283SDoug Anderson 3006f95f3850SWill Newton return 0; 3007f95f3850SWill Newton } 300862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 30096fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 30106fe8890dSJaehoon Chung 3011f95f3850SWill Newton static int __init dw_mci_init(void) 3012f95f3850SWill Newton { 30138e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 301462ca8034SShashidhar Hiremath return 0; 3015f95f3850SWill Newton } 3016f95f3850SWill Newton 3017f95f3850SWill Newton static void __exit dw_mci_exit(void) 3018f95f3850SWill Newton { 3019f95f3850SWill Newton } 3020f95f3850SWill Newton 3021f95f3850SWill Newton module_init(dw_mci_init); 3022f95f3850SWill Newton module_exit(dw_mci_exit); 3023f95f3850SWill Newton 3024f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3025f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3026f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3027f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3028