1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47f95f3850SWill Newton SDMMC_INT_EBE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49f95f3850SWill Newton SDMMC_INT_RESP_ERR) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51f95f3850SWill Newton DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 60fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 63fc79a4d6SJoonyoung Shim 6469d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6569d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6669d99fdcSPrabu Thangamuthu 6769d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6869d99fdcSPrabu Thangamuthu 6969d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7069d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 716687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 726687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7769d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8069d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu }; 8269d99fdcSPrabu Thangamuthu 83f95f3850SWill Newton struct idmac_desc { 846687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 85f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 86f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 87f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 88f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 89f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 90f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 91f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 92f95f3850SWill Newton 936687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 94f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 959b7bbe10SShashidhar Hiremath ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 96f95f3850SWill Newton 976687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 98f95f3850SWill Newton 996687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 100f95f3850SWill Newton }; 1015959b32eSAlexey Brodkin 1025959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1035959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 104f95f3850SWill Newton 1053a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 106536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 1070bdbd0e8SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc); 10831bff450SSeungwon Jeon 109f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 110f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 111f95f3850SWill Newton { 112f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 113f95f3850SWill Newton struct mmc_request *mrq; 114f95f3850SWill Newton struct mmc_command *cmd; 115f95f3850SWill Newton struct mmc_command *stop; 116f95f3850SWill Newton struct mmc_data *data; 117f95f3850SWill Newton 118f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 119f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 120f95f3850SWill Newton mrq = slot->mrq; 121f95f3850SWill Newton 122f95f3850SWill Newton if (mrq) { 123f95f3850SWill Newton cmd = mrq->cmd; 124f95f3850SWill Newton data = mrq->data; 125f95f3850SWill Newton stop = mrq->stop; 126f95f3850SWill Newton 127f95f3850SWill Newton if (cmd) 128f95f3850SWill Newton seq_printf(s, 129f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 130f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 131f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 132f95f3850SWill Newton cmd->resp[2], cmd->error); 133f95f3850SWill Newton if (data) 134f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 135f95f3850SWill Newton data->bytes_xfered, data->blocks, 136f95f3850SWill Newton data->blksz, data->flags, data->error); 137f95f3850SWill Newton if (stop) 138f95f3850SWill Newton seq_printf(s, 139f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 140f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 141f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 142f95f3850SWill Newton stop->resp[2], stop->error); 143f95f3850SWill Newton } 144f95f3850SWill Newton 145f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 146f95f3850SWill Newton 147f95f3850SWill Newton return 0; 148f95f3850SWill Newton } 149f95f3850SWill Newton 150f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 151f95f3850SWill Newton { 152f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 153f95f3850SWill Newton } 154f95f3850SWill Newton 155f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 156f95f3850SWill Newton .owner = THIS_MODULE, 157f95f3850SWill Newton .open = dw_mci_req_open, 158f95f3850SWill Newton .read = seq_read, 159f95f3850SWill Newton .llseek = seq_lseek, 160f95f3850SWill Newton .release = single_release, 161f95f3850SWill Newton }; 162f95f3850SWill Newton 163f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 164f95f3850SWill Newton { 165f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 166f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 167f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 168f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 169f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 170f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 171f95f3850SWill Newton 172f95f3850SWill Newton return 0; 173f95f3850SWill Newton } 174f95f3850SWill Newton 175f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 176f95f3850SWill Newton { 177f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 178f95f3850SWill Newton } 179f95f3850SWill Newton 180f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 181f95f3850SWill Newton .owner = THIS_MODULE, 182f95f3850SWill Newton .open = dw_mci_regs_open, 183f95f3850SWill Newton .read = seq_read, 184f95f3850SWill Newton .llseek = seq_lseek, 185f95f3850SWill Newton .release = single_release, 186f95f3850SWill Newton }; 187f95f3850SWill Newton 188f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 189f95f3850SWill Newton { 190f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 191f95f3850SWill Newton struct dw_mci *host = slot->host; 192f95f3850SWill Newton struct dentry *root; 193f95f3850SWill Newton struct dentry *node; 194f95f3850SWill Newton 195f95f3850SWill Newton root = mmc->debugfs_root; 196f95f3850SWill Newton if (!root) 197f95f3850SWill Newton return; 198f95f3850SWill Newton 199f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 200f95f3850SWill Newton &dw_mci_regs_fops); 201f95f3850SWill Newton if (!node) 202f95f3850SWill Newton goto err; 203f95f3850SWill Newton 204f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 205f95f3850SWill Newton &dw_mci_req_fops); 206f95f3850SWill Newton if (!node) 207f95f3850SWill Newton goto err; 208f95f3850SWill Newton 209f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 210f95f3850SWill Newton if (!node) 211f95f3850SWill Newton goto err; 212f95f3850SWill Newton 213f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 214f95f3850SWill Newton (u32 *)&host->pending_events); 215f95f3850SWill Newton if (!node) 216f95f3850SWill Newton goto err; 217f95f3850SWill Newton 218f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 219f95f3850SWill Newton (u32 *)&host->completed_events); 220f95f3850SWill Newton if (!node) 221f95f3850SWill Newton goto err; 222f95f3850SWill Newton 223f95f3850SWill Newton return; 224f95f3850SWill Newton 225f95f3850SWill Newton err: 226f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 227f95f3850SWill Newton } 228f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 229f95f3850SWill Newton 23001730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 23101730558SDoug Anderson 232f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 233f95f3850SWill Newton { 234f95f3850SWill Newton struct mmc_data *data; 235800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23601730558SDoug Anderson struct dw_mci *host = slot->host; 237e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 238f95f3850SWill Newton u32 cmdr; 239f95f3850SWill Newton 2400e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 241f95f3850SWill Newton cmdr = cmd->opcode; 242f95f3850SWill Newton 24390c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24590c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24690c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24790c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 248f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2494a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 250f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 251f95f3850SWill Newton 25201730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25301730558SDoug Anderson u32 clk_en_a; 25401730558SDoug Anderson 25501730558SDoug Anderson /* Special bit makes CMD11 not die */ 25601730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25701730558SDoug Anderson 25801730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25901730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 26001730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 26101730558SDoug Anderson 26201730558SDoug Anderson /* 26301730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26401730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26501730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26601730558SDoug Anderson * voltage change dance. 26701730558SDoug Anderson * 26801730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26901730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 27001730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 27101730558SDoug Anderson * until the voltage change is all done. 27201730558SDoug Anderson */ 27301730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27401730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27501730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27601730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27701730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27801730558SDoug Anderson } 27901730558SDoug Anderson 280f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 281f95f3850SWill Newton /* We expect a response, so set this bit */ 282f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 283f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 284f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 285f95f3850SWill Newton } 286f95f3850SWill Newton 287f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 288f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 289f95f3850SWill Newton 290f95f3850SWill Newton data = cmd->data; 291f95f3850SWill Newton if (data) { 292f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 293f95f3850SWill Newton if (data->flags & MMC_DATA_STREAM) 294f95f3850SWill Newton cmdr |= SDMMC_CMD_STRM_MODE; 295f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 296f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 297f95f3850SWill Newton } 298f95f3850SWill Newton 299cb27a843SJames Hogan if (drv_data && drv_data->prepare_command) 300cb27a843SJames Hogan drv_data->prepare_command(slot->host, &cmdr); 301800d78bfSThomas Abraham 302f95f3850SWill Newton return cmdr; 303f95f3850SWill Newton } 304f95f3850SWill Newton 30590c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30690c2143aSSeungwon Jeon { 30790c2143aSSeungwon Jeon struct mmc_command *stop; 30890c2143aSSeungwon Jeon u32 cmdr; 30990c2143aSSeungwon Jeon 31090c2143aSSeungwon Jeon if (!cmd->data) 31190c2143aSSeungwon Jeon return 0; 31290c2143aSSeungwon Jeon 31390c2143aSSeungwon Jeon stop = &host->stop_abort; 31490c2143aSSeungwon Jeon cmdr = cmd->opcode; 31590c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31690c2143aSSeungwon Jeon 31790c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31890c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31990c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3206c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3216c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3226c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 32390c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 32490c2143aSSeungwon Jeon stop->arg = 0; 32590c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32690c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32790c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32890c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32990c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 33090c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 33190c2143aSSeungwon Jeon } else { 33290c2143aSSeungwon Jeon return 0; 33390c2143aSSeungwon Jeon } 33490c2143aSSeungwon Jeon 33590c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33690c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33790c2143aSSeungwon Jeon 33890c2143aSSeungwon Jeon return cmdr; 33990c2143aSSeungwon Jeon } 34090c2143aSSeungwon Jeon 3410bdbd0e8SDoug Anderson static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 3420bdbd0e8SDoug Anderson { 3430bdbd0e8SDoug Anderson unsigned long timeout = jiffies + msecs_to_jiffies(500); 3440bdbd0e8SDoug Anderson 3450bdbd0e8SDoug Anderson /* 3460bdbd0e8SDoug Anderson * Databook says that before issuing a new data transfer command 3470bdbd0e8SDoug Anderson * we need to check to see if the card is busy. Data transfer commands 3480bdbd0e8SDoug Anderson * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 3490bdbd0e8SDoug Anderson * 3500bdbd0e8SDoug Anderson * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 3510bdbd0e8SDoug Anderson * expected. 3520bdbd0e8SDoug Anderson */ 3530bdbd0e8SDoug Anderson if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 3540bdbd0e8SDoug Anderson !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 3550bdbd0e8SDoug Anderson while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 3560bdbd0e8SDoug Anderson if (time_after(jiffies, timeout)) { 3570bdbd0e8SDoug Anderson /* Command will fail; we'll pass error then */ 3580bdbd0e8SDoug Anderson dev_err(host->dev, "Busy; trying anyway\n"); 3590bdbd0e8SDoug Anderson break; 3600bdbd0e8SDoug Anderson } 3610bdbd0e8SDoug Anderson udelay(10); 3620bdbd0e8SDoug Anderson } 3630bdbd0e8SDoug Anderson } 3640bdbd0e8SDoug Anderson } 3650bdbd0e8SDoug Anderson 366f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 367f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 368f95f3850SWill Newton { 369f95f3850SWill Newton host->cmd = cmd; 3704a90920cSThomas Abraham dev_vdbg(host->dev, 371f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 372f95f3850SWill Newton cmd->arg, cmd_flags); 373f95f3850SWill Newton 374f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 3750e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 3760bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 377f95f3850SWill Newton 378f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 379f95f3850SWill Newton } 380f95f3850SWill Newton 38190c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 382f95f3850SWill Newton { 38390c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 3840e3a22c0SShawn Lin 38590c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 386f95f3850SWill Newton } 387f95f3850SWill Newton 388f95f3850SWill Newton /* DMA interface functions */ 389f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 390f95f3850SWill Newton { 39103e8cb53SJames Hogan if (host->using_dma) { 392f95f3850SWill Newton host->dma_ops->stop(host); 393f95f3850SWill Newton host->dma_ops->cleanup(host); 394aa50f259SSeungwon Jeon } 395aa50f259SSeungwon Jeon 396f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 397f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 398f95f3850SWill Newton } 399f95f3850SWill Newton 4009aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 4019aa51408SSeungwon Jeon { 4029aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4039aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4049aa51408SSeungwon Jeon else 4059aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4069aa51408SSeungwon Jeon } 4079aa51408SSeungwon Jeon 408f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 409f95f3850SWill Newton { 410f95f3850SWill Newton struct mmc_data *data = host->data; 411f95f3850SWill Newton 412f95f3850SWill Newton if (data) 4139aa51408SSeungwon Jeon if (!data->host_cookie) 4144a90920cSThomas Abraham dma_unmap_sg(host->dev, 4159aa51408SSeungwon Jeon data->sg, 4169aa51408SSeungwon Jeon data->sg_len, 4179aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 418f95f3850SWill Newton } 419f95f3850SWill Newton 4205ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4215ce9d961SSeungwon Jeon { 4225ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4235ce9d961SSeungwon Jeon /* Software reset of DMA */ 4245ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4255ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4265ce9d961SSeungwon Jeon } 4275ce9d961SSeungwon Jeon 428f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 429f95f3850SWill Newton { 430f95f3850SWill Newton u32 temp; 431f95f3850SWill Newton 432f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 433f95f3850SWill Newton temp = mci_readl(host, CTRL); 434f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 435f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 436f95f3850SWill Newton mci_writel(host, CTRL, temp); 437f95f3850SWill Newton 438f95f3850SWill Newton /* Stop the IDMAC running */ 439f95f3850SWill Newton temp = mci_readl(host, BMOD); 440a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4415ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 442f95f3850SWill Newton mci_writel(host, BMOD, temp); 443f95f3850SWill Newton } 444f95f3850SWill Newton 4453fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 446f95f3850SWill Newton { 4473fc7eaefSShawn Lin struct dw_mci *host = arg; 448f95f3850SWill Newton struct mmc_data *data = host->data; 449f95f3850SWill Newton 4504a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 451f95f3850SWill Newton 4523fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 4533fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 4543fc7eaefSShawn Lin /* Invalidate cache after read */ 4553fc7eaefSShawn Lin dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 4563fc7eaefSShawn Lin data->sg, 4573fc7eaefSShawn Lin data->sg_len, 4583fc7eaefSShawn Lin DMA_FROM_DEVICE); 4593fc7eaefSShawn Lin 460f95f3850SWill Newton host->dma_ops->cleanup(host); 461f95f3850SWill Newton 462f95f3850SWill Newton /* 463f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 464f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 465f95f3850SWill Newton */ 466f95f3850SWill Newton if (data) { 467f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 468f95f3850SWill Newton tasklet_schedule(&host->tasklet); 469f95f3850SWill Newton } 470f95f3850SWill Newton } 471f95f3850SWill Newton 472f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 473f95f3850SWill Newton unsigned int sg_len) 474f95f3850SWill Newton { 4755959b32eSAlexey Brodkin unsigned int desc_len; 476f95f3850SWill Newton int i; 4770e3a22c0SShawn Lin 47869d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 4795959b32eSAlexey Brodkin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 48069d99fdcSPrabu Thangamuthu 4815959b32eSAlexey Brodkin desc_first = desc_last = desc = host->sg_cpu; 4825959b32eSAlexey Brodkin 4835959b32eSAlexey Brodkin for (i = 0; i < sg_len; i++) { 48469d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 4850e3a22c0SShawn Lin 48669d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 48769d99fdcSPrabu Thangamuthu 4885959b32eSAlexey Brodkin for ( ; length ; desc++) { 4895959b32eSAlexey Brodkin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 4905959b32eSAlexey Brodkin length : DW_MCI_DESC_DATA_LENGTH; 4915959b32eSAlexey Brodkin 4925959b32eSAlexey Brodkin length -= desc_len; 4935959b32eSAlexey Brodkin 49469d99fdcSPrabu Thangamuthu /* 4955959b32eSAlexey Brodkin * Set the OWN bit and disable interrupts 4965959b32eSAlexey Brodkin * for this descriptor 49769d99fdcSPrabu Thangamuthu */ 49869d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 49969d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 5005959b32eSAlexey Brodkin 50169d99fdcSPrabu Thangamuthu /* Buffer length */ 5025959b32eSAlexey Brodkin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 50369d99fdcSPrabu Thangamuthu 50469d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 50569d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 50669d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 5075959b32eSAlexey Brodkin 5085959b32eSAlexey Brodkin /* Update physical address for the next desc */ 5095959b32eSAlexey Brodkin mem_addr += desc_len; 5105959b32eSAlexey Brodkin 5115959b32eSAlexey Brodkin /* Save pointer to the last descriptor */ 5125959b32eSAlexey Brodkin desc_last = desc; 5135959b32eSAlexey Brodkin } 51469d99fdcSPrabu Thangamuthu } 51569d99fdcSPrabu Thangamuthu 51669d99fdcSPrabu Thangamuthu /* Set first descriptor */ 5175959b32eSAlexey Brodkin desc_first->des0 |= IDMAC_DES0_FD; 51869d99fdcSPrabu Thangamuthu 51969d99fdcSPrabu Thangamuthu /* Set last descriptor */ 5205959b32eSAlexey Brodkin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 5215959b32eSAlexey Brodkin desc_last->des0 |= IDMAC_DES0_LD; 52269d99fdcSPrabu Thangamuthu 52369d99fdcSPrabu Thangamuthu } else { 5245959b32eSAlexey Brodkin struct idmac_desc *desc_first, *desc_last, *desc; 525f95f3850SWill Newton 5265959b32eSAlexey Brodkin desc_first = desc_last = desc = host->sg_cpu; 5275959b32eSAlexey Brodkin 5285959b32eSAlexey Brodkin for (i = 0; i < sg_len; i++) { 529f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 5300e3a22c0SShawn Lin 531f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 532f95f3850SWill Newton 5335959b32eSAlexey Brodkin for ( ; length ; desc++) { 5345959b32eSAlexey Brodkin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 5355959b32eSAlexey Brodkin length : DW_MCI_DESC_DATA_LENGTH; 5365959b32eSAlexey Brodkin 5375959b32eSAlexey Brodkin length -= desc_len; 5385959b32eSAlexey Brodkin 53969d99fdcSPrabu Thangamuthu /* 5405959b32eSAlexey Brodkin * Set the OWN bit and disable interrupts 5415959b32eSAlexey Brodkin * for this descriptor 54269d99fdcSPrabu Thangamuthu */ 5436687c42fSBen Dooks desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 5445959b32eSAlexey Brodkin IDMAC_DES0_DIC | 5455959b32eSAlexey Brodkin IDMAC_DES0_CH); 5465959b32eSAlexey Brodkin 547f95f3850SWill Newton /* Buffer length */ 5485959b32eSAlexey Brodkin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 549f95f3850SWill Newton 550f95f3850SWill Newton /* Physical address to DMA to/from */ 5516687c42fSBen Dooks desc->des2 = cpu_to_le32(mem_addr); 5525959b32eSAlexey Brodkin 5535959b32eSAlexey Brodkin /* Update physical address for the next desc */ 5545959b32eSAlexey Brodkin mem_addr += desc_len; 5555959b32eSAlexey Brodkin 5565959b32eSAlexey Brodkin /* Save pointer to the last descriptor */ 5575959b32eSAlexey Brodkin desc_last = desc; 5585959b32eSAlexey Brodkin } 559f95f3850SWill Newton } 560f95f3850SWill Newton 561f95f3850SWill Newton /* Set first descriptor */ 5625959b32eSAlexey Brodkin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 563f95f3850SWill Newton 564f95f3850SWill Newton /* Set last descriptor */ 5655959b32eSAlexey Brodkin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 5665959b32eSAlexey Brodkin IDMAC_DES0_DIC)); 5675959b32eSAlexey Brodkin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 56869d99fdcSPrabu Thangamuthu } 569f95f3850SWill Newton 5700e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 571f95f3850SWill Newton } 572f95f3850SWill Newton 5733fc7eaefSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 574f95f3850SWill Newton { 575f95f3850SWill Newton u32 temp; 576f95f3850SWill Newton 577f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 578f95f3850SWill Newton 579536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 580536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 581536f6b91SSonny Rao dw_mci_idmac_reset(host); 582536f6b91SSonny Rao 583f95f3850SWill Newton /* Select IDMAC interface */ 584f95f3850SWill Newton temp = mci_readl(host, CTRL); 585f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 586f95f3850SWill Newton mci_writel(host, CTRL, temp); 587f95f3850SWill Newton 5880e3a22c0SShawn Lin /* drain writebuffer */ 589f95f3850SWill Newton wmb(); 590f95f3850SWill Newton 591f95f3850SWill Newton /* Enable the IDMAC */ 592f95f3850SWill Newton temp = mci_readl(host, BMOD); 593a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 594f95f3850SWill Newton mci_writel(host, BMOD, temp); 595f95f3850SWill Newton 596f95f3850SWill Newton /* Start it running */ 597f95f3850SWill Newton mci_writel(host, PLDMND, 1); 5983fc7eaefSShawn Lin 5993fc7eaefSShawn Lin return 0; 600f95f3850SWill Newton } 601f95f3850SWill Newton 602f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 603f95f3850SWill Newton { 604897b69e7SSeungwon Jeon int i; 605f95f3850SWill Newton 60669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 60769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 60869d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 60969d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 61069d99fdcSPrabu Thangamuthu 61169d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 61269d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 61369d99fdcSPrabu Thangamuthu i++, p++) { 61469d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 61569d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 61669d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 61769d99fdcSPrabu Thangamuthu 61869d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 61969d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 62069d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 62169d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 62269d99fdcSPrabu Thangamuthu p->des1 = 0; 62369d99fdcSPrabu Thangamuthu p->des2 = 0; 62469d99fdcSPrabu Thangamuthu p->des3 = 0; 62569d99fdcSPrabu Thangamuthu } 62669d99fdcSPrabu Thangamuthu 62769d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 62869d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 62969d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 63069d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 63169d99fdcSPrabu Thangamuthu 63269d99fdcSPrabu Thangamuthu } else { 63369d99fdcSPrabu Thangamuthu struct idmac_desc *p; 634f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 635f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 636f95f3850SWill Newton 637f95f3850SWill Newton /* Forward link the descriptor list */ 6380e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 6390e3a22c0SShawn Lin i < host->ring_size - 1; 6400e3a22c0SShawn Lin i++, p++) { 6416687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 6426687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 6434b244724SZhangfei Gao p->des1 = 0; 6444b244724SZhangfei Gao } 645f95f3850SWill Newton 646f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 6476687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 6486687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 64969d99fdcSPrabu Thangamuthu } 650f95f3850SWill Newton 6515ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 652141a712aSSeungwon Jeon 65369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 65469d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 65569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 65669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 65769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 65869d99fdcSPrabu Thangamuthu 65969d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 66069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 66169d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 66269d99fdcSPrabu Thangamuthu 66369d99fdcSPrabu Thangamuthu } else { 664f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 665fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 66669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 66769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 668f95f3850SWill Newton 669f95f3850SWill Newton /* Set the descriptor base address */ 670f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 67169d99fdcSPrabu Thangamuthu } 67269d99fdcSPrabu Thangamuthu 673f95f3850SWill Newton return 0; 674f95f3850SWill Newton } 675f95f3850SWill Newton 6768e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 677885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 678885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 679885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 6803fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 681885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 682885c3e80SSeungwon Jeon }; 6833fc7eaefSShawn Lin 6843fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 6853fc7eaefSShawn Lin { 6863fc7eaefSShawn Lin dmaengine_terminate_all(host->dms->ch); 6873fc7eaefSShawn Lin } 6883fc7eaefSShawn Lin 6893fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 6903fc7eaefSShawn Lin unsigned int sg_len) 6913fc7eaefSShawn Lin { 6923fc7eaefSShawn Lin struct dma_slave_config cfg; 6933fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 6943fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 6953fc7eaefSShawn Lin const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 6963fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 6973fc7eaefSShawn Lin u32 fifoth_val; 6983fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 6993fc7eaefSShawn Lin int ret = 0; 7003fc7eaefSShawn Lin 7013fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 7023fc7eaefSShawn Lin cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset); 7033fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 7043fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7053fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7063fc7eaefSShawn Lin 7073fc7eaefSShawn Lin /* Match burst msize with external dma config */ 7083fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 7093fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 7103fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 7113fc7eaefSShawn Lin 7123fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7133fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 7143fc7eaefSShawn Lin else 7153fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 7163fc7eaefSShawn Lin 7173fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 7183fc7eaefSShawn Lin if (ret) { 7193fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 7203fc7eaefSShawn Lin return -EBUSY; 7213fc7eaefSShawn Lin } 7223fc7eaefSShawn Lin 7233fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 7243fc7eaefSShawn Lin sg_len, cfg.direction, 7253fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 7263fc7eaefSShawn Lin if (!desc) { 7273fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 7283fc7eaefSShawn Lin return -EBUSY; 7293fc7eaefSShawn Lin } 7303fc7eaefSShawn Lin 7313fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 7323fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 7333fc7eaefSShawn Lin desc->callback_param = (void *)host; 7343fc7eaefSShawn Lin dmaengine_submit(desc); 7353fc7eaefSShawn Lin 7363fc7eaefSShawn Lin /* Flush cache before write */ 7373fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7383fc7eaefSShawn Lin dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 7393fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 7403fc7eaefSShawn Lin 7413fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 7423fc7eaefSShawn Lin 7433fc7eaefSShawn Lin return 0; 7443fc7eaefSShawn Lin } 7453fc7eaefSShawn Lin 7463fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 7473fc7eaefSShawn Lin { 7483fc7eaefSShawn Lin /* Request external dma channel */ 7493fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 7503fc7eaefSShawn Lin if (!host->dms) 7513fc7eaefSShawn Lin return -ENOMEM; 7523fc7eaefSShawn Lin 7533fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 7543fc7eaefSShawn Lin if (!host->dms->ch) { 7554539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 7563fc7eaefSShawn Lin kfree(host->dms); 7573fc7eaefSShawn Lin host->dms = NULL; 7583fc7eaefSShawn Lin return -ENXIO; 7593fc7eaefSShawn Lin } 7603fc7eaefSShawn Lin 7613fc7eaefSShawn Lin return 0; 7623fc7eaefSShawn Lin } 7633fc7eaefSShawn Lin 7643fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 7653fc7eaefSShawn Lin { 7663fc7eaefSShawn Lin if (host->dms) { 7673fc7eaefSShawn Lin if (host->dms->ch) { 7683fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 7693fc7eaefSShawn Lin host->dms->ch = NULL; 7703fc7eaefSShawn Lin } 7713fc7eaefSShawn Lin kfree(host->dms); 7723fc7eaefSShawn Lin host->dms = NULL; 7733fc7eaefSShawn Lin } 7743fc7eaefSShawn Lin } 7753fc7eaefSShawn Lin 7763fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 7773fc7eaefSShawn Lin .init = dw_mci_edmac_init, 7783fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 7793fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 7803fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 7813fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 7823fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 7833fc7eaefSShawn Lin }; 784885c3e80SSeungwon Jeon 7859aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 7869aa51408SSeungwon Jeon struct mmc_data *data, 7879aa51408SSeungwon Jeon bool next) 788f95f3850SWill Newton { 789f95f3850SWill Newton struct scatterlist *sg; 7909aa51408SSeungwon Jeon unsigned int i, sg_len; 791f95f3850SWill Newton 7929aa51408SSeungwon Jeon if (!next && data->host_cookie) 7939aa51408SSeungwon Jeon return data->host_cookie; 794f95f3850SWill Newton 795f95f3850SWill Newton /* 796f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 797f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 798f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 799f95f3850SWill Newton */ 800f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 801f95f3850SWill Newton return -EINVAL; 8029aa51408SSeungwon Jeon 803f95f3850SWill Newton if (data->blksz & 3) 804f95f3850SWill Newton return -EINVAL; 805f95f3850SWill Newton 806f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 807f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 808f95f3850SWill Newton return -EINVAL; 809f95f3850SWill Newton } 810f95f3850SWill Newton 8114a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 8129aa51408SSeungwon Jeon data->sg, 8139aa51408SSeungwon Jeon data->sg_len, 8149aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 8159aa51408SSeungwon Jeon if (sg_len == 0) 8169aa51408SSeungwon Jeon return -EINVAL; 8179aa51408SSeungwon Jeon 8189aa51408SSeungwon Jeon if (next) 8199aa51408SSeungwon Jeon data->host_cookie = sg_len; 8209aa51408SSeungwon Jeon 8219aa51408SSeungwon Jeon return sg_len; 8229aa51408SSeungwon Jeon } 8239aa51408SSeungwon Jeon 8249aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 8259aa51408SSeungwon Jeon struct mmc_request *mrq, 8269aa51408SSeungwon Jeon bool is_first_req) 8279aa51408SSeungwon Jeon { 8289aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 8299aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 8309aa51408SSeungwon Jeon 8319aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 8329aa51408SSeungwon Jeon return; 8339aa51408SSeungwon Jeon 8349aa51408SSeungwon Jeon if (data->host_cookie) { 8359aa51408SSeungwon Jeon data->host_cookie = 0; 8369aa51408SSeungwon Jeon return; 8379aa51408SSeungwon Jeon } 8389aa51408SSeungwon Jeon 8399aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 8409aa51408SSeungwon Jeon data->host_cookie = 0; 8419aa51408SSeungwon Jeon } 8429aa51408SSeungwon Jeon 8439aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 8449aa51408SSeungwon Jeon struct mmc_request *mrq, 8459aa51408SSeungwon Jeon int err) 8469aa51408SSeungwon Jeon { 8479aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 8489aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 8499aa51408SSeungwon Jeon 8509aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 8519aa51408SSeungwon Jeon return; 8529aa51408SSeungwon Jeon 8539aa51408SSeungwon Jeon if (data->host_cookie) 8544a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 8559aa51408SSeungwon Jeon data->sg, 8569aa51408SSeungwon Jeon data->sg_len, 8579aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 8589aa51408SSeungwon Jeon data->host_cookie = 0; 8599aa51408SSeungwon Jeon } 8609aa51408SSeungwon Jeon 86152426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 86252426899SSeungwon Jeon { 86352426899SSeungwon Jeon unsigned int blksz = data->blksz; 86452426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 86552426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 86652426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 86752426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 8680e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 86952426899SSeungwon Jeon 8703fc7eaefSShawn Lin /* pio should ship this scenario */ 8713fc7eaefSShawn Lin if (!host->use_dma) 8723fc7eaefSShawn Lin return; 8733fc7eaefSShawn Lin 87452426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 87552426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 87652426899SSeungwon Jeon 87752426899SSeungwon Jeon /* 87852426899SSeungwon Jeon * MSIZE is '1', 87952426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 88052426899SSeungwon Jeon */ 88152426899SSeungwon Jeon if (blksz % fifo_width) { 88252426899SSeungwon Jeon msize = 0; 88352426899SSeungwon Jeon rx_wmark = 1; 88452426899SSeungwon Jeon goto done; 88552426899SSeungwon Jeon } 88652426899SSeungwon Jeon 88752426899SSeungwon Jeon do { 88852426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 88952426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 89052426899SSeungwon Jeon msize = idx; 89152426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 89252426899SSeungwon Jeon break; 89352426899SSeungwon Jeon } 89452426899SSeungwon Jeon } while (--idx > 0); 89552426899SSeungwon Jeon /* 89652426899SSeungwon Jeon * If idx is '0', it won't be tried 89752426899SSeungwon Jeon * Thus, initial values are uesed 89852426899SSeungwon Jeon */ 89952426899SSeungwon Jeon done: 90052426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 90152426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 90252426899SSeungwon Jeon } 90352426899SSeungwon Jeon 904f1d2736cSSeungwon Jeon static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 905f1d2736cSSeungwon Jeon { 906f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 907f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 908f1d2736cSSeungwon Jeon u16 thld_size; 909f1d2736cSSeungwon Jeon 910f1d2736cSSeungwon Jeon WARN_ON(!(data->flags & MMC_DATA_READ)); 911f1d2736cSSeungwon Jeon 91266dfd101SJames Hogan /* 91366dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 91466dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 91566dfd101SJames Hogan */ 91666dfd101SJames Hogan if (host->verid < DW_MMC_240A) 91766dfd101SJames Hogan return; 91866dfd101SJames Hogan 919f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 920488b8d63SJaehoon Chung host->timing != MMC_TIMING_MMC_HS400 && 921f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 922f1d2736cSSeungwon Jeon goto disable; 923f1d2736cSSeungwon Jeon 924f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 925f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 926f1d2736cSSeungwon Jeon 927f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 928f1d2736cSSeungwon Jeon goto disable; 929f1d2736cSSeungwon Jeon 930f1d2736cSSeungwon Jeon /* 931f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 932f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 933f1d2736cSSeungwon Jeon * Currently just choose blksz. 934f1d2736cSSeungwon Jeon */ 935f1d2736cSSeungwon Jeon thld_size = blksz; 936f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 937f1d2736cSSeungwon Jeon return; 938f1d2736cSSeungwon Jeon 939f1d2736cSSeungwon Jeon disable: 940f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 941f1d2736cSSeungwon Jeon } 942f1d2736cSSeungwon Jeon 9439aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 9449aa51408SSeungwon Jeon { 945f8c58c11SDoug Anderson unsigned long irqflags; 9469aa51408SSeungwon Jeon int sg_len; 9479aa51408SSeungwon Jeon u32 temp; 9489aa51408SSeungwon Jeon 9499aa51408SSeungwon Jeon host->using_dma = 0; 9509aa51408SSeungwon Jeon 9519aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 9529aa51408SSeungwon Jeon if (!host->use_dma) 9539aa51408SSeungwon Jeon return -ENODEV; 9549aa51408SSeungwon Jeon 9559aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 956a99aa9b9SSeungwon Jeon if (sg_len < 0) { 957a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 9589aa51408SSeungwon Jeon return sg_len; 959a99aa9b9SSeungwon Jeon } 9609aa51408SSeungwon Jeon 96103e8cb53SJames Hogan host->using_dma = 1; 96203e8cb53SJames Hogan 9633fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 9644a90920cSThomas Abraham dev_vdbg(host->dev, 965f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 9663fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 9673fc7eaefSShawn Lin (unsigned long)host->sg_dma, 968f95f3850SWill Newton sg_len); 969f95f3850SWill Newton 97052426899SSeungwon Jeon /* 97152426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 97252426899SSeungwon Jeon * If current block size is same with previous size, 97352426899SSeungwon Jeon * no need to update fifoth. 97452426899SSeungwon Jeon */ 97552426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 97652426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 97752426899SSeungwon Jeon 978f95f3850SWill Newton /* Enable the DMA interface */ 979f95f3850SWill Newton temp = mci_readl(host, CTRL); 980f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 981f95f3850SWill Newton mci_writel(host, CTRL, temp); 982f95f3850SWill Newton 983f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 984f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 985f95f3850SWill Newton temp = mci_readl(host, INTMASK); 986f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 987f95f3850SWill Newton mci_writel(host, INTMASK, temp); 988f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 989f95f3850SWill Newton 9903fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 9913fc7eaefSShawn Lin /* We can't do DMA */ 9923fc7eaefSShawn Lin dev_err(host->dev, "%s: failed to start DMA.\n", __func__); 9933fc7eaefSShawn Lin return -ENODEV; 9943fc7eaefSShawn Lin } 995f95f3850SWill Newton 996f95f3850SWill Newton return 0; 997f95f3850SWill Newton } 998f95f3850SWill Newton 999f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1000f95f3850SWill Newton { 1001f8c58c11SDoug Anderson unsigned long irqflags; 10020e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1003f95f3850SWill Newton u32 temp; 1004f95f3850SWill Newton 1005f95f3850SWill Newton data->error = -EINPROGRESS; 1006f95f3850SWill Newton 1007f95f3850SWill Newton WARN_ON(host->data); 1008f95f3850SWill Newton host->sg = NULL; 1009f95f3850SWill Newton host->data = data; 1010f95f3850SWill Newton 1011f1d2736cSSeungwon Jeon if (data->flags & MMC_DATA_READ) { 101255c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 1013f1d2736cSSeungwon Jeon dw_mci_ctrl_rd_thld(host, data); 1014f1d2736cSSeungwon Jeon } else { 101555c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 1016f1d2736cSSeungwon Jeon } 101755c5efbcSJames Hogan 1018f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1019f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1020f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1021f9c2a0dcSSeungwon Jeon else 1022f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1023f9c2a0dcSSeungwon Jeon 1024f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1025f95f3850SWill Newton host->sg = data->sg; 102634b664a2SJames Hogan host->part_buf_start = 0; 102734b664a2SJames Hogan host->part_buf_count = 0; 1028f95f3850SWill Newton 1029b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1030f8c58c11SDoug Anderson 1031f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1032f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1033f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1034f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1035f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1036f95f3850SWill Newton 1037f95f3850SWill Newton temp = mci_readl(host, CTRL); 1038f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1039f95f3850SWill Newton mci_writel(host, CTRL, temp); 104052426899SSeungwon Jeon 104152426899SSeungwon Jeon /* 104252426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 104352426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 104452426899SSeungwon Jeon * prev_blksz should be invalidated. 104552426899SSeungwon Jeon */ 104652426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 104752426899SSeungwon Jeon host->prev_blksz = 0; 104852426899SSeungwon Jeon } else { 104952426899SSeungwon Jeon /* 105052426899SSeungwon Jeon * Keep the current block size. 105152426899SSeungwon Jeon * It will be used to decide whether to update 105252426899SSeungwon Jeon * fifoth register next time. 105352426899SSeungwon Jeon */ 105452426899SSeungwon Jeon host->prev_blksz = data->blksz; 1055f95f3850SWill Newton } 1056f95f3850SWill Newton } 1057f95f3850SWill Newton 1058f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 1059f95f3850SWill Newton { 1060f95f3850SWill Newton struct dw_mci *host = slot->host; 1061f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 1062f95f3850SWill Newton unsigned int cmd_status = 0; 1063f95f3850SWill Newton 1064f95f3850SWill Newton mci_writel(host, CMDARG, arg); 10650e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 10660bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd); 1067f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 1068f95f3850SWill Newton 1069f95f3850SWill Newton while (time_before(jiffies, timeout)) { 1070f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 1071f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 1072f95f3850SWill Newton return; 1073f95f3850SWill Newton } 1074f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 1075f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 1076f95f3850SWill Newton cmd, arg, cmd_status); 1077f95f3850SWill Newton } 1078f95f3850SWill Newton 1079ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1080f95f3850SWill Newton { 1081f95f3850SWill Newton struct dw_mci *host = slot->host; 1082fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1083f95f3850SWill Newton u32 div; 10849623b5b9SDoug Anderson u32 clk_en_a; 108501730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 108601730558SDoug Anderson 108701730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 108801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 108901730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1090f95f3850SWill Newton 1091fdf492a1SDoug Anderson if (!clock) { 1092fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 109301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1094fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1095fdf492a1SDoug Anderson div = host->bus_hz / clock; 1096fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1097f95f3850SWill Newton /* 1098f95f3850SWill Newton * move the + 1 after the divide to prevent 1099f95f3850SWill Newton * over-clocking the card. 1100f95f3850SWill Newton */ 1101e419990bSSeungwon Jeon div += 1; 1102e419990bSSeungwon Jeon 1103fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1104f95f3850SWill Newton 1105fdf492a1SDoug Anderson if ((clock << div) != slot->__clk_old || force_clkinit) 1106f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1107fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1108fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1109fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1110fdf492a1SDoug Anderson host->bus_hz, div); 1111f95f3850SWill Newton 1112f95f3850SWill Newton /* disable clock */ 1113f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1114f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1115f95f3850SWill Newton 1116f95f3850SWill Newton /* inform CIU */ 111701730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1118f95f3850SWill Newton 1119f95f3850SWill Newton /* set clock to desired speed */ 1120f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1121f95f3850SWill Newton 1122f95f3850SWill Newton /* inform CIU */ 112301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1124f95f3850SWill Newton 11259623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 11269623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1127b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 11289623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 11299623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1130f95f3850SWill Newton 1131f95f3850SWill Newton /* inform CIU */ 113201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1133f95f3850SWill Newton 1134fdf492a1SDoug Anderson /* keep the clock with reflecting clock dividor */ 1135fdf492a1SDoug Anderson slot->__clk_old = clock << div; 1136f95f3850SWill Newton } 1137f95f3850SWill Newton 1138fdf492a1SDoug Anderson host->current_speed = clock; 1139fdf492a1SDoug Anderson 1140f95f3850SWill Newton /* Set the current slot bus width */ 11411d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1142f95f3850SWill Newton } 1143f95f3850SWill Newton 1144053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1145053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1146053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1147f95f3850SWill Newton { 1148f95f3850SWill Newton struct mmc_request *mrq; 1149f95f3850SWill Newton struct mmc_data *data; 1150f95f3850SWill Newton u32 cmdflags; 1151f95f3850SWill Newton 1152f95f3850SWill Newton mrq = slot->mrq; 1153f95f3850SWill Newton 1154f95f3850SWill Newton host->cur_slot = slot; 1155f95f3850SWill Newton host->mrq = mrq; 1156f95f3850SWill Newton 1157f95f3850SWill Newton host->pending_events = 0; 1158f95f3850SWill Newton host->completed_events = 0; 1159e352c813SSeungwon Jeon host->cmd_status = 0; 1160f95f3850SWill Newton host->data_status = 0; 1161e352c813SSeungwon Jeon host->dir_status = 0; 1162f95f3850SWill Newton 1163053b3ce6SSeungwon Jeon data = cmd->data; 1164f95f3850SWill Newton if (data) { 1165f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1166f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1167f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1168f95f3850SWill Newton } 1169f95f3850SWill Newton 1170f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1171f95f3850SWill Newton 1172f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1173f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1174f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1175f95f3850SWill Newton 1176f95f3850SWill Newton if (data) { 1177f95f3850SWill Newton dw_mci_submit_data(host, data); 11780e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1179f95f3850SWill Newton } 1180f95f3850SWill Newton 1181f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1182f95f3850SWill Newton 11835c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 118449ba0302SDoug Anderson unsigned long irqflags; 118549ba0302SDoug Anderson 11865c935165SDoug Anderson /* 11878886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 11888886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 11898886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 11908886a6fdSDoug Anderson * is just about to roll over. 119149ba0302SDoug Anderson * 119249ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 119349ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 119449ba0302SDoug Anderson * already ran so we don't want the timeout). 11955c935165SDoug Anderson */ 119649ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 119749ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 11985c935165SDoug Anderson mod_timer(&host->cmd11_timer, 11998886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 120049ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 12015c935165SDoug Anderson } 12025c935165SDoug Anderson 1203f95f3850SWill Newton if (mrq->stop) 1204f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 120590c2143aSSeungwon Jeon else 120690c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1207f95f3850SWill Newton } 1208f95f3850SWill Newton 1209053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1210053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1211053b3ce6SSeungwon Jeon { 1212053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1213053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1214053b3ce6SSeungwon Jeon 1215053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1216053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1217053b3ce6SSeungwon Jeon } 1218053b3ce6SSeungwon Jeon 12197456caaeSJames Hogan /* must be called with host->lock held */ 1220f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1221f95f3850SWill Newton struct mmc_request *mrq) 1222f95f3850SWill Newton { 1223f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1224f95f3850SWill Newton host->state); 1225f95f3850SWill Newton 1226f95f3850SWill Newton slot->mrq = mrq; 1227f95f3850SWill Newton 122801730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 122901730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 123001730558SDoug Anderson "Voltage change didn't complete\n"); 123101730558SDoug Anderson /* 123201730558SDoug Anderson * this case isn't expected to happen, so we can 123301730558SDoug Anderson * either crash here or just try to continue on 123401730558SDoug Anderson * in the closest possible state 123501730558SDoug Anderson */ 123601730558SDoug Anderson host->state = STATE_IDLE; 123701730558SDoug Anderson } 123801730558SDoug Anderson 1239f95f3850SWill Newton if (host->state == STATE_IDLE) { 1240f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1241f95f3850SWill Newton dw_mci_start_request(host, slot); 1242f95f3850SWill Newton } else { 1243f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1244f95f3850SWill Newton } 1245f95f3850SWill Newton } 1246f95f3850SWill Newton 1247f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1248f95f3850SWill Newton { 1249f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1250f95f3850SWill Newton struct dw_mci *host = slot->host; 1251f95f3850SWill Newton 1252f95f3850SWill Newton WARN_ON(slot->mrq); 1253f95f3850SWill Newton 12547456caaeSJames Hogan /* 12557456caaeSJames Hogan * The check for card presence and queueing of the request must be 12567456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 12577456caaeSJames Hogan * request wouldn't fail until another card was inserted. 12587456caaeSJames Hogan */ 12597456caaeSJames Hogan spin_lock_bh(&host->lock); 12607456caaeSJames Hogan 1261f95f3850SWill Newton if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 12627456caaeSJames Hogan spin_unlock_bh(&host->lock); 1263f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1264f95f3850SWill Newton mmc_request_done(mmc, mrq); 1265f95f3850SWill Newton return; 1266f95f3850SWill Newton } 1267f95f3850SWill Newton 1268f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 12697456caaeSJames Hogan 12707456caaeSJames Hogan spin_unlock_bh(&host->lock); 1271f95f3850SWill Newton } 1272f95f3850SWill Newton 1273f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1274f95f3850SWill Newton { 1275f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1276e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 127741babf75SJaehoon Chung u32 regs; 127851da2240SYuvaraj CD int ret; 1279f95f3850SWill Newton 1280f95f3850SWill Newton switch (ios->bus_width) { 1281f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1282f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1283f95f3850SWill Newton break; 1284c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1285c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1286c9b2a06fSJaehoon Chung break; 1287b2f7cb45SJaehoon Chung default: 1288b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1289b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1290f95f3850SWill Newton } 1291f95f3850SWill Newton 129241babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 12933f514291SSeungwon Jeon 12943f514291SSeungwon Jeon /* DDR mode set */ 129580113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 1296*7cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 129780113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1298c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 12993f514291SSeungwon Jeon else 1300c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 13013f514291SSeungwon Jeon 130241babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1303f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 130441babf75SJaehoon Chung 1305f95f3850SWill Newton /* 1306f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1307f95f3850SWill Newton * core ios update when finding the minimum. 1308f95f3850SWill Newton */ 1309f95f3850SWill Newton slot->clock = ios->clock; 1310f95f3850SWill Newton 1311cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1312cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1313800d78bfSThomas Abraham 1314f95f3850SWill Newton switch (ios->power_mode) { 1315f95f3850SWill Newton case MMC_POWER_UP: 131651da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 131751da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 131851da2240SYuvaraj CD ios->vdd); 131951da2240SYuvaraj CD if (ret) { 132051da2240SYuvaraj CD dev_err(slot->host->dev, 132151da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 132251da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 132351da2240SYuvaraj CD return; 132451da2240SYuvaraj CD } 132551da2240SYuvaraj CD } 132629d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 132729d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 132829d0d161SDoug Anderson regs |= (1 << slot->id); 132929d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 133029d0d161SDoug Anderson break; 133129d0d161SDoug Anderson case MMC_POWER_ON: 1332d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1333d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 133451da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 133551da2240SYuvaraj CD if (ret < 0) 133651da2240SYuvaraj CD dev_err(slot->host->dev, 1337d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 133851da2240SYuvaraj CD else 133951da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1340d1f1dd86SDoug Anderson 1341d1f1dd86SDoug Anderson } else { 1342d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1343d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1344d1f1dd86SDoug Anderson } 1345d1f1dd86SDoug Anderson 1346d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1347d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1348d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 134951da2240SYuvaraj CD } 1350655babbdSDoug Anderson 1351655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1352655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1353655babbdSDoug Anderson 1354e6f34e2fSJames Hogan break; 1355e6f34e2fSJames Hogan case MMC_POWER_OFF: 1356655babbdSDoug Anderson /* Turn clock off before power goes down */ 1357655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1358655babbdSDoug Anderson 135951da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 136051da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 136151da2240SYuvaraj CD 1362d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 136351da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 136451da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 136551da2240SYuvaraj CD 13664366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 13674366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 13684366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1369f95f3850SWill Newton break; 1370f95f3850SWill Newton default: 1371f95f3850SWill Newton break; 1372f95f3850SWill Newton } 1373655babbdSDoug Anderson 1374655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1375655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1376f95f3850SWill Newton } 1377f95f3850SWill Newton 137801730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 137901730558SDoug Anderson { 138001730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 138101730558SDoug Anderson u32 status; 138201730558SDoug Anderson 138301730558SDoug Anderson /* 138401730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 138501730558SDoug Anderson * (the data lines) are 0000 138601730558SDoug Anderson */ 138701730558SDoug Anderson status = mci_readl(slot->host, STATUS); 138801730558SDoug Anderson 138901730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 139001730558SDoug Anderson } 139101730558SDoug Anderson 139201730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 139301730558SDoug Anderson { 139401730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 139501730558SDoug Anderson struct dw_mci *host = slot->host; 13968f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 139701730558SDoug Anderson u32 uhs; 139801730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 139901730558SDoug Anderson int ret; 140001730558SDoug Anderson 14018f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 14028f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 14038f7849c4SZhangfei Gao 140401730558SDoug Anderson /* 140501730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 140601730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 140701730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 140801730558SDoug Anderson */ 140901730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1410e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 141101730558SDoug Anderson uhs &= ~v18; 1412e0848f5dSDouglas Anderson else 141301730558SDoug Anderson uhs |= v18; 1414e0848f5dSDouglas Anderson 141501730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1416e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 141701730558SDoug Anderson 141801730558SDoug Anderson if (ret) { 1419b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1420e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1421e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 142201730558SDoug Anderson return ret; 142301730558SDoug Anderson } 142401730558SDoug Anderson } 142501730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 142601730558SDoug Anderson 142701730558SDoug Anderson return 0; 142801730558SDoug Anderson } 142901730558SDoug Anderson 1430f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1431f95f3850SWill Newton { 1432f95f3850SWill Newton int read_only; 1433f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 14349795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1435f95f3850SWill Newton 1436f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1437eff8f2f5SLars-Peter Clausen if (!IS_ERR_VALUE(gpio_ro)) 14389795a846SJaehoon Chung read_only = gpio_ro; 1439f95f3850SWill Newton else 1440f95f3850SWill Newton read_only = 1441f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1442f95f3850SWill Newton 1443f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1444f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1445f95f3850SWill Newton 1446f95f3850SWill Newton return read_only; 1447f95f3850SWill Newton } 1448f95f3850SWill Newton 1449f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1450f95f3850SWill Newton { 1451f95f3850SWill Newton int present; 1452f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1453f95f3850SWill Newton struct dw_mci_board *brd = slot->host->pdata; 14547cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 14557cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1456f95f3850SWill Newton 1457f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 14584de3bf66SZhangfei Gao if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) || 14594de3bf66SZhangfei Gao (mmc->caps & MMC_CAP_NONREMOVABLE)) 1460fc3d7720SJaehoon Chung present = 1; 1461bf626e55SZhangfei Gao else if (!IS_ERR_VALUE(gpio_cd)) 14627cf347bdSZhangfei Gao present = gpio_cd; 1463f95f3850SWill Newton else 1464f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1465f95f3850SWill Newton == 0 ? 1 : 0; 1466f95f3850SWill Newton 14677cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1468bf626e55SZhangfei Gao if (present) { 1469bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1470f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1471bf626e55SZhangfei Gao } else { 1472bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1473f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1474bf626e55SZhangfei Gao } 14757cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1476f95f3850SWill Newton 1477f95f3850SWill Newton return present; 1478f95f3850SWill Newton } 1479f95f3850SWill Newton 1480b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1481b24c8b26SDoug Anderson { 1482b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1483b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1484b24c8b26SDoug Anderson 14859623b5b9SDoug Anderson /* 14869623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 14879623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 14889623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 14899623b5b9SDoug Anderson */ 1490b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 14919623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1492b24c8b26SDoug Anderson u32 clk_en_a_old; 1493b24c8b26SDoug Anderson u32 clk_en_a; 14949623b5b9SDoug Anderson 1495b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 14969623b5b9SDoug Anderson 1497b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1498b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1499b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1500b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1501b24c8b26SDoug Anderson } else { 1502b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1503b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1504b24c8b26SDoug Anderson } 1505b24c8b26SDoug Anderson 1506b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1507b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 15089623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 15099623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 15109623b5b9SDoug Anderson } 15119623b5b9SDoug Anderson } 1512b24c8b26SDoug Anderson } 15139623b5b9SDoug Anderson 15141a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 15151a5c8e1fSShashidhar Hiremath { 15161a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 15171a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1518f8c58c11SDoug Anderson unsigned long irqflags; 15191a5c8e1fSShashidhar Hiremath u32 int_mask; 15201a5c8e1fSShashidhar Hiremath 1521f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1522f8c58c11SDoug Anderson 15231a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 15241a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1525b24c8b26SDoug Anderson if (enb) 1526b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1527b24c8b26SDoug Anderson else 1528b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1529b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1530f8c58c11SDoug Anderson 1531f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 15321a5c8e1fSShashidhar Hiremath } 15331a5c8e1fSShashidhar Hiremath 15340976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 15350976f16dSSeungwon Jeon { 15360976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 15370976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 15380976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 15390e3a22c0SShawn Lin int err = -EINVAL; 15400976f16dSSeungwon Jeon 15410976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 15429979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 15430976f16dSSeungwon Jeon return err; 15440976f16dSSeungwon Jeon } 15450976f16dSSeungwon Jeon 15460e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 15470e3a22c0SShawn Lin struct mmc_ios *ios) 154880113132SSeungwon Jeon { 154980113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 155080113132SSeungwon Jeon struct dw_mci *host = slot->host; 155180113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 155280113132SSeungwon Jeon 155380113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 155480113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 155580113132SSeungwon Jeon 155680113132SSeungwon Jeon return 0; 155780113132SSeungwon Jeon } 155880113132SSeungwon Jeon 1559f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1560f95f3850SWill Newton .request = dw_mci_request, 15619aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 15629aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1563f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1564f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1565f95f3850SWill Newton .get_cd = dw_mci_get_cd, 15661a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 15670976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 156801730558SDoug Anderson .card_busy = dw_mci_card_busy, 156901730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1570b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 157180113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1572f95f3850SWill Newton }; 1573f95f3850SWill Newton 1574f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1575f95f3850SWill Newton __releases(&host->lock) 1576f95f3850SWill Newton __acquires(&host->lock) 1577f95f3850SWill Newton { 1578f95f3850SWill Newton struct dw_mci_slot *slot; 1579f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1580f95f3850SWill Newton 1581f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1582f95f3850SWill Newton 1583f95f3850SWill Newton host->cur_slot->mrq = NULL; 1584f95f3850SWill Newton host->mrq = NULL; 1585f95f3850SWill Newton if (!list_empty(&host->queue)) { 1586f95f3850SWill Newton slot = list_entry(host->queue.next, 1587f95f3850SWill Newton struct dw_mci_slot, queue_node); 1588f95f3850SWill Newton list_del(&slot->queue_node); 15894a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1590f95f3850SWill Newton mmc_hostname(slot->mmc)); 1591f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1592f95f3850SWill Newton dw_mci_start_request(host, slot); 1593f95f3850SWill Newton } else { 15944a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 159501730558SDoug Anderson 159601730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 159701730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 159801730558SDoug Anderson else 1599f95f3850SWill Newton host->state = STATE_IDLE; 1600f95f3850SWill Newton } 1601f95f3850SWill Newton 1602f95f3850SWill Newton spin_unlock(&host->lock); 1603f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1604f95f3850SWill Newton spin_lock(&host->lock); 1605f95f3850SWill Newton } 1606f95f3850SWill Newton 1607e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1608f95f3850SWill Newton { 1609f95f3850SWill Newton u32 status = host->cmd_status; 1610f95f3850SWill Newton 1611f95f3850SWill Newton host->cmd_status = 0; 1612f95f3850SWill Newton 1613f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1614f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1615f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1616f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1617f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1618f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1619f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1620f95f3850SWill Newton } else { 1621f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1622f95f3850SWill Newton cmd->resp[1] = 0; 1623f95f3850SWill Newton cmd->resp[2] = 0; 1624f95f3850SWill Newton cmd->resp[3] = 0; 1625f95f3850SWill Newton } 1626f95f3850SWill Newton } 1627f95f3850SWill Newton 1628f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1629f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1630f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1631f95f3850SWill Newton cmd->error = -EILSEQ; 1632f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1633f95f3850SWill Newton cmd->error = -EIO; 1634f95f3850SWill Newton else 1635f95f3850SWill Newton cmd->error = 0; 1636f95f3850SWill Newton 1637f95f3850SWill Newton if (cmd->error) { 1638f95f3850SWill Newton /* newer ip versions need a delay between retries */ 1639f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1640f95f3850SWill Newton mdelay(20); 1641f95f3850SWill Newton } 1642e352c813SSeungwon Jeon 1643e352c813SSeungwon Jeon return cmd->error; 1644e352c813SSeungwon Jeon } 1645e352c813SSeungwon Jeon 1646e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1647e352c813SSeungwon Jeon { 164831bff450SSeungwon Jeon u32 status = host->data_status; 1649e352c813SSeungwon Jeon 1650e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1651e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1652e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1653e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1654e352c813SSeungwon Jeon data->error = -EILSEQ; 1655e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1656e352c813SSeungwon Jeon if (host->dir_status == 1657e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1658e352c813SSeungwon Jeon /* 1659e352c813SSeungwon Jeon * No data CRC status was returned. 1660e352c813SSeungwon Jeon * The number of bytes transferred 1661e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1662e352c813SSeungwon Jeon */ 1663e352c813SSeungwon Jeon data->bytes_xfered = 0; 1664e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1665e352c813SSeungwon Jeon } else if (host->dir_status == 1666e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1667e352c813SSeungwon Jeon data->error = -EIO; 1668e352c813SSeungwon Jeon } 1669e352c813SSeungwon Jeon } else { 1670e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1671e352c813SSeungwon Jeon data->error = -EIO; 1672e352c813SSeungwon Jeon } 1673e352c813SSeungwon Jeon 1674e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1675e352c813SSeungwon Jeon 1676e352c813SSeungwon Jeon /* 1677e352c813SSeungwon Jeon * After an error, there may be data lingering 167831bff450SSeungwon Jeon * in the FIFO 1679e352c813SSeungwon Jeon */ 16803a33a94cSSonny Rao dw_mci_reset(host); 1681e352c813SSeungwon Jeon } else { 1682e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1683e352c813SSeungwon Jeon data->error = 0; 1684e352c813SSeungwon Jeon } 1685e352c813SSeungwon Jeon 1686e352c813SSeungwon Jeon return data->error; 1687f95f3850SWill Newton } 1688f95f3850SWill Newton 168957e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 169057e10486SAddy Ke { 169157e10486SAddy Ke unsigned int drto_clks; 169257e10486SAddy Ke unsigned int drto_ms; 169357e10486SAddy Ke 169457e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 169557e10486SAddy Ke drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 169657e10486SAddy Ke 169757e10486SAddy Ke /* add a bit spare time */ 169857e10486SAddy Ke drto_ms += 10; 169957e10486SAddy Ke 170057e10486SAddy Ke mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 170157e10486SAddy Ke } 170257e10486SAddy Ke 1703f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1704f95f3850SWill Newton { 1705f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1706f95f3850SWill Newton struct mmc_data *data; 1707f95f3850SWill Newton struct mmc_command *cmd; 1708e352c813SSeungwon Jeon struct mmc_request *mrq; 1709f95f3850SWill Newton enum dw_mci_state state; 1710f95f3850SWill Newton enum dw_mci_state prev_state; 1711e352c813SSeungwon Jeon unsigned int err; 1712f95f3850SWill Newton 1713f95f3850SWill Newton spin_lock(&host->lock); 1714f95f3850SWill Newton 1715f95f3850SWill Newton state = host->state; 1716f95f3850SWill Newton data = host->data; 1717e352c813SSeungwon Jeon mrq = host->mrq; 1718f95f3850SWill Newton 1719f95f3850SWill Newton do { 1720f95f3850SWill Newton prev_state = state; 1721f95f3850SWill Newton 1722f95f3850SWill Newton switch (state) { 1723f95f3850SWill Newton case STATE_IDLE: 172401730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1725f95f3850SWill Newton break; 1726f95f3850SWill Newton 172701730558SDoug Anderson case STATE_SENDING_CMD11: 1728f95f3850SWill Newton case STATE_SENDING_CMD: 1729f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1730f95f3850SWill Newton &host->pending_events)) 1731f95f3850SWill Newton break; 1732f95f3850SWill Newton 1733f95f3850SWill Newton cmd = host->cmd; 1734f95f3850SWill Newton host->cmd = NULL; 1735f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1736e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1737e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1738053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1739053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1740e352c813SSeungwon Jeon mrq->cmd); 1741053b3ce6SSeungwon Jeon goto unlock; 1742053b3ce6SSeungwon Jeon } 1743053b3ce6SSeungwon Jeon 1744e352c813SSeungwon Jeon if (cmd->data && err) { 174571abb133SSeungwon Jeon dw_mci_stop_dma(host); 174690c2143aSSeungwon Jeon send_stop_abort(host, data); 174771abb133SSeungwon Jeon state = STATE_SENDING_STOP; 174871abb133SSeungwon Jeon break; 174971abb133SSeungwon Jeon } 175071abb133SSeungwon Jeon 1751e352c813SSeungwon Jeon if (!cmd->data || err) { 1752e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1753f95f3850SWill Newton goto unlock; 1754f95f3850SWill Newton } 1755f95f3850SWill Newton 1756f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1757f95f3850SWill Newton /* fall through */ 1758f95f3850SWill Newton 1759f95f3850SWill Newton case STATE_SENDING_DATA: 17602aa35465SDoug Anderson /* 17612aa35465SDoug Anderson * We could get a data error and never a transfer 17622aa35465SDoug Anderson * complete so we'd better check for it here. 17632aa35465SDoug Anderson * 17642aa35465SDoug Anderson * Note that we don't really care if we also got a 17652aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 17662aa35465SDoug Anderson * abort won't hurt. 17672aa35465SDoug Anderson */ 1768f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1769f95f3850SWill Newton &host->pending_events)) { 1770f95f3850SWill Newton dw_mci_stop_dma(host); 1771bdb9a90bSaddy ke if (data->stop || 1772bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1773bdb9a90bSaddy ke SDMMC_INT_EBE))) 177490c2143aSSeungwon Jeon send_stop_abort(host, data); 1775f95f3850SWill Newton state = STATE_DATA_ERROR; 1776f95f3850SWill Newton break; 1777f95f3850SWill Newton } 1778f95f3850SWill Newton 1779f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 178057e10486SAddy Ke &host->pending_events)) { 178157e10486SAddy Ke /* 178257e10486SAddy Ke * If all data-related interrupts don't come 178357e10486SAddy Ke * within the given time in reading data state. 178457e10486SAddy Ke */ 178557e10486SAddy Ke if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 178657e10486SAddy Ke (host->dir_status == DW_MCI_RECV_STATUS)) 178757e10486SAddy Ke dw_mci_set_drto(host); 1788f95f3850SWill Newton break; 178957e10486SAddy Ke } 1790f95f3850SWill Newton 1791f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 17922aa35465SDoug Anderson 17932aa35465SDoug Anderson /* 17942aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 17952aa35465SDoug Anderson * before the transfer completed. This might not have 17962aa35465SDoug Anderson * been caught by the check above because the interrupt 17972aa35465SDoug Anderson * could have gone off between the previous check and 17982aa35465SDoug Anderson * the check for transfer complete. 17992aa35465SDoug Anderson * 18002aa35465SDoug Anderson * Technically this ought not be needed assuming we 18012aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 18022aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 18032aa35465SDoug Anderson * 18042aa35465SDoug Anderson * This has the advantage of sending the stop command. 18052aa35465SDoug Anderson */ 18062aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 18072aa35465SDoug Anderson &host->pending_events)) { 18082aa35465SDoug Anderson dw_mci_stop_dma(host); 1809bdb9a90bSaddy ke if (data->stop || 1810bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1811bdb9a90bSaddy ke SDMMC_INT_EBE))) 18122aa35465SDoug Anderson send_stop_abort(host, data); 18132aa35465SDoug Anderson state = STATE_DATA_ERROR; 18142aa35465SDoug Anderson break; 18152aa35465SDoug Anderson } 1816f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 18172aa35465SDoug Anderson 1818f95f3850SWill Newton /* fall through */ 1819f95f3850SWill Newton 1820f95f3850SWill Newton case STATE_DATA_BUSY: 1821f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 182257e10486SAddy Ke &host->pending_events)) { 182357e10486SAddy Ke /* 182457e10486SAddy Ke * If data error interrupt comes but data over 182557e10486SAddy Ke * interrupt doesn't come within the given time. 182657e10486SAddy Ke * in reading data state. 182757e10486SAddy Ke */ 182857e10486SAddy Ke if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 182957e10486SAddy Ke (host->dir_status == DW_MCI_RECV_STATUS)) 183057e10486SAddy Ke dw_mci_set_drto(host); 1831f95f3850SWill Newton break; 183257e10486SAddy Ke } 1833f95f3850SWill Newton 1834f95f3850SWill Newton host->data = NULL; 1835f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1836e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1837f95f3850SWill Newton 1838e352c813SSeungwon Jeon if (!err) { 1839e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 184017c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1841053b3ce6SSeungwon Jeon data->stop->error = 0; 1842e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1843053b3ce6SSeungwon Jeon goto unlock; 1844053b3ce6SSeungwon Jeon } 1845053b3ce6SSeungwon Jeon 184690c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1847e352c813SSeungwon Jeon if (data->stop) 184890c2143aSSeungwon Jeon send_stop_abort(host, data); 18492aa35465SDoug Anderson } else { 18502aa35465SDoug Anderson /* 18512aa35465SDoug Anderson * If we don't have a command complete now we'll 18522aa35465SDoug Anderson * never get one since we just reset everything; 18532aa35465SDoug Anderson * better end the request. 18542aa35465SDoug Anderson * 18552aa35465SDoug Anderson * If we do have a command complete we'll fall 18562aa35465SDoug Anderson * through to the SENDING_STOP command and 18572aa35465SDoug Anderson * everything will be peachy keen. 18582aa35465SDoug Anderson */ 18592aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 18602aa35465SDoug Anderson &host->pending_events)) { 18612aa35465SDoug Anderson host->cmd = NULL; 18622aa35465SDoug Anderson dw_mci_request_end(host, mrq); 18632aa35465SDoug Anderson goto unlock; 18642aa35465SDoug Anderson } 186590c2143aSSeungwon Jeon } 1866e352c813SSeungwon Jeon 1867e352c813SSeungwon Jeon /* 1868e352c813SSeungwon Jeon * If err has non-zero, 1869e352c813SSeungwon Jeon * stop-abort command has been already issued. 1870e352c813SSeungwon Jeon */ 1871e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1872e352c813SSeungwon Jeon 1873f95f3850SWill Newton /* fall through */ 1874f95f3850SWill Newton 1875f95f3850SWill Newton case STATE_SENDING_STOP: 1876f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1877f95f3850SWill Newton &host->pending_events)) 1878f95f3850SWill Newton break; 1879f95f3850SWill Newton 188071abb133SSeungwon Jeon /* CMD error in data command */ 188131bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 18823a33a94cSSonny Rao dw_mci_reset(host); 188371abb133SSeungwon Jeon 1884f95f3850SWill Newton host->cmd = NULL; 188571abb133SSeungwon Jeon host->data = NULL; 188690c2143aSSeungwon Jeon 1887e352c813SSeungwon Jeon if (mrq->stop) 1888e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 188990c2143aSSeungwon Jeon else 189090c2143aSSeungwon Jeon host->cmd_status = 0; 189190c2143aSSeungwon Jeon 1892e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1893f95f3850SWill Newton goto unlock; 1894f95f3850SWill Newton 1895f95f3850SWill Newton case STATE_DATA_ERROR: 1896f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1897f95f3850SWill Newton &host->pending_events)) 1898f95f3850SWill Newton break; 1899f95f3850SWill Newton 1900f95f3850SWill Newton state = STATE_DATA_BUSY; 1901f95f3850SWill Newton break; 1902f95f3850SWill Newton } 1903f95f3850SWill Newton } while (state != prev_state); 1904f95f3850SWill Newton 1905f95f3850SWill Newton host->state = state; 1906f95f3850SWill Newton unlock: 1907f95f3850SWill Newton spin_unlock(&host->lock); 1908f95f3850SWill Newton 1909f95f3850SWill Newton } 1910f95f3850SWill Newton 191134b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 191234b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 191334b664a2SJames Hogan { 191434b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 191534b664a2SJames Hogan host->part_buf_count = cnt; 191634b664a2SJames Hogan } 191734b664a2SJames Hogan 191834b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 191934b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 192034b664a2SJames Hogan { 192134b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 192234b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 192334b664a2SJames Hogan host->part_buf_count += cnt; 192434b664a2SJames Hogan return cnt; 192534b664a2SJames Hogan } 192634b664a2SJames Hogan 192734b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 192834b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 192934b664a2SJames Hogan { 19300e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 193134b664a2SJames Hogan if (cnt) { 193234b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 193334b664a2SJames Hogan cnt); 193434b664a2SJames Hogan host->part_buf_count -= cnt; 193534b664a2SJames Hogan host->part_buf_start += cnt; 193634b664a2SJames Hogan } 193734b664a2SJames Hogan return cnt; 193834b664a2SJames Hogan } 193934b664a2SJames Hogan 194034b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 194134b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 194234b664a2SJames Hogan { 194334b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 194434b664a2SJames Hogan host->part_buf_start = cnt; 194534b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 194634b664a2SJames Hogan } 194734b664a2SJames Hogan 1948f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1949f95f3850SWill Newton { 1950cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1951cfbeb59cSMarkos Chandras int init_cnt = cnt; 1952cfbeb59cSMarkos Chandras 195334b664a2SJames Hogan /* try and push anything in the part_buf */ 195434b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 195534b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 19560e3a22c0SShawn Lin 195734b664a2SJames Hogan buf += len; 195834b664a2SJames Hogan cnt -= len; 1959cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 196076184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 196134b664a2SJames Hogan host->part_buf_count = 0; 196234b664a2SJames Hogan } 196334b664a2SJames Hogan } 196434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 196534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 196634b664a2SJames Hogan while (cnt >= 2) { 196734b664a2SJames Hogan u16 aligned_buf[64]; 196834b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 196934b664a2SJames Hogan int items = len >> 1; 197034b664a2SJames Hogan int i; 197134b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 197234b664a2SJames Hogan memcpy(aligned_buf, buf, len); 197334b664a2SJames Hogan buf += len; 197434b664a2SJames Hogan cnt -= len; 197534b664a2SJames Hogan /* push data from aligned buffer into fifo */ 197634b664a2SJames Hogan for (i = 0; i < items; ++i) 197776184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 197834b664a2SJames Hogan } 197934b664a2SJames Hogan } else 198034b664a2SJames Hogan #endif 198134b664a2SJames Hogan { 198234b664a2SJames Hogan u16 *pdata = buf; 19830e3a22c0SShawn Lin 198434b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 198576184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 198634b664a2SJames Hogan buf = pdata; 198734b664a2SJames Hogan } 198834b664a2SJames Hogan /* put anything remaining in the part_buf */ 198934b664a2SJames Hogan if (cnt) { 199034b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1991cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1992cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1993cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 199476184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 1995f95f3850SWill Newton } 1996f95f3850SWill Newton } 1997f95f3850SWill Newton 1998f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1999f95f3850SWill Newton { 200034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 200134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 200234b664a2SJames Hogan while (cnt >= 2) { 200334b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 200434b664a2SJames Hogan u16 aligned_buf[64]; 200534b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 200634b664a2SJames Hogan int items = len >> 1; 200734b664a2SJames Hogan int i; 20080e3a22c0SShawn Lin 200934b664a2SJames Hogan for (i = 0; i < items; ++i) 201076184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 201134b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 201234b664a2SJames Hogan memcpy(buf, aligned_buf, len); 201334b664a2SJames Hogan buf += len; 201434b664a2SJames Hogan cnt -= len; 201534b664a2SJames Hogan } 201634b664a2SJames Hogan } else 201734b664a2SJames Hogan #endif 201834b664a2SJames Hogan { 201934b664a2SJames Hogan u16 *pdata = buf; 20200e3a22c0SShawn Lin 202134b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 202276184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 202334b664a2SJames Hogan buf = pdata; 202434b664a2SJames Hogan } 202534b664a2SJames Hogan if (cnt) { 202676184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 202734b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2028f95f3850SWill Newton } 2029f95f3850SWill Newton } 2030f95f3850SWill Newton 2031f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2032f95f3850SWill Newton { 2033cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2034cfbeb59cSMarkos Chandras int init_cnt = cnt; 2035cfbeb59cSMarkos Chandras 203634b664a2SJames Hogan /* try and push anything in the part_buf */ 203734b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 203834b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 20390e3a22c0SShawn Lin 204034b664a2SJames Hogan buf += len; 204134b664a2SJames Hogan cnt -= len; 2042cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 204376184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 204434b664a2SJames Hogan host->part_buf_count = 0; 204534b664a2SJames Hogan } 204634b664a2SJames Hogan } 204734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 204834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 204934b664a2SJames Hogan while (cnt >= 4) { 205034b664a2SJames Hogan u32 aligned_buf[32]; 205134b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 205234b664a2SJames Hogan int items = len >> 2; 205334b664a2SJames Hogan int i; 205434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 205534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 205634b664a2SJames Hogan buf += len; 205734b664a2SJames Hogan cnt -= len; 205834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 205934b664a2SJames Hogan for (i = 0; i < items; ++i) 206076184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 206134b664a2SJames Hogan } 206234b664a2SJames Hogan } else 206334b664a2SJames Hogan #endif 206434b664a2SJames Hogan { 206534b664a2SJames Hogan u32 *pdata = buf; 20660e3a22c0SShawn Lin 206734b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 206876184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 206934b664a2SJames Hogan buf = pdata; 207034b664a2SJames Hogan } 207134b664a2SJames Hogan /* put anything remaining in the part_buf */ 207234b664a2SJames Hogan if (cnt) { 207334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2074cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2075cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2076cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 207776184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2078f95f3850SWill Newton } 2079f95f3850SWill Newton } 2080f95f3850SWill Newton 2081f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2082f95f3850SWill Newton { 208334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 208434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 208534b664a2SJames Hogan while (cnt >= 4) { 208634b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 208734b664a2SJames Hogan u32 aligned_buf[32]; 208834b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 208934b664a2SJames Hogan int items = len >> 2; 209034b664a2SJames Hogan int i; 20910e3a22c0SShawn Lin 209234b664a2SJames Hogan for (i = 0; i < items; ++i) 209376184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 209434b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 209534b664a2SJames Hogan memcpy(buf, aligned_buf, len); 209634b664a2SJames Hogan buf += len; 209734b664a2SJames Hogan cnt -= len; 209834b664a2SJames Hogan } 209934b664a2SJames Hogan } else 210034b664a2SJames Hogan #endif 210134b664a2SJames Hogan { 210234b664a2SJames Hogan u32 *pdata = buf; 21030e3a22c0SShawn Lin 210434b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 210576184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 210634b664a2SJames Hogan buf = pdata; 210734b664a2SJames Hogan } 210834b664a2SJames Hogan if (cnt) { 210976184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 211034b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2111f95f3850SWill Newton } 2112f95f3850SWill Newton } 2113f95f3850SWill Newton 2114f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2115f95f3850SWill Newton { 2116cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2117cfbeb59cSMarkos Chandras int init_cnt = cnt; 2118cfbeb59cSMarkos Chandras 211934b664a2SJames Hogan /* try and push anything in the part_buf */ 212034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 212134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 21220e3a22c0SShawn Lin 212334b664a2SJames Hogan buf += len; 212434b664a2SJames Hogan cnt -= len; 2125c09fbd74SSeungwon Jeon 2126cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 212776184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 212834b664a2SJames Hogan host->part_buf_count = 0; 212934b664a2SJames Hogan } 213034b664a2SJames Hogan } 213134b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 213234b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 213334b664a2SJames Hogan while (cnt >= 8) { 213434b664a2SJames Hogan u64 aligned_buf[16]; 213534b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 213634b664a2SJames Hogan int items = len >> 3; 213734b664a2SJames Hogan int i; 213834b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 213934b664a2SJames Hogan memcpy(aligned_buf, buf, len); 214034b664a2SJames Hogan buf += len; 214134b664a2SJames Hogan cnt -= len; 214234b664a2SJames Hogan /* push data from aligned buffer into fifo */ 214334b664a2SJames Hogan for (i = 0; i < items; ++i) 214476184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 214534b664a2SJames Hogan } 214634b664a2SJames Hogan } else 214734b664a2SJames Hogan #endif 214834b664a2SJames Hogan { 214934b664a2SJames Hogan u64 *pdata = buf; 21500e3a22c0SShawn Lin 215134b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 215276184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 215334b664a2SJames Hogan buf = pdata; 215434b664a2SJames Hogan } 215534b664a2SJames Hogan /* put anything remaining in the part_buf */ 215634b664a2SJames Hogan if (cnt) { 215734b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2158cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2159cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2160cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 216176184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2162f95f3850SWill Newton } 2163f95f3850SWill Newton } 2164f95f3850SWill Newton 2165f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2166f95f3850SWill Newton { 216734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 216834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 216934b664a2SJames Hogan while (cnt >= 8) { 217034b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 217134b664a2SJames Hogan u64 aligned_buf[16]; 217234b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 217334b664a2SJames Hogan int items = len >> 3; 217434b664a2SJames Hogan int i; 21750e3a22c0SShawn Lin 217634b664a2SJames Hogan for (i = 0; i < items; ++i) 217776184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 217876184ac1SBen Dooks 217934b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 218034b664a2SJames Hogan memcpy(buf, aligned_buf, len); 218134b664a2SJames Hogan buf += len; 218234b664a2SJames Hogan cnt -= len; 2183f95f3850SWill Newton } 218434b664a2SJames Hogan } else 218534b664a2SJames Hogan #endif 218634b664a2SJames Hogan { 218734b664a2SJames Hogan u64 *pdata = buf; 21880e3a22c0SShawn Lin 218934b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 219076184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 219134b664a2SJames Hogan buf = pdata; 219234b664a2SJames Hogan } 219334b664a2SJames Hogan if (cnt) { 219476184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 219534b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 219634b664a2SJames Hogan } 219734b664a2SJames Hogan } 219834b664a2SJames Hogan 219934b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 220034b664a2SJames Hogan { 220134b664a2SJames Hogan int len; 220234b664a2SJames Hogan 220334b664a2SJames Hogan /* get remaining partial bytes */ 220434b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 220534b664a2SJames Hogan if (unlikely(len == cnt)) 220634b664a2SJames Hogan return; 220734b664a2SJames Hogan buf += len; 220834b664a2SJames Hogan cnt -= len; 220934b664a2SJames Hogan 221034b664a2SJames Hogan /* get the rest of the data */ 221134b664a2SJames Hogan host->pull_data(host, buf, cnt); 2212f95f3850SWill Newton } 2213f95f3850SWill Newton 221487a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2215f95f3850SWill Newton { 2216f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2217f9c2a0dcSSeungwon Jeon void *buf; 2218f9c2a0dcSSeungwon Jeon unsigned int offset; 2219f95f3850SWill Newton struct mmc_data *data = host->data; 2220f95f3850SWill Newton int shift = host->data_shift; 2221f95f3850SWill Newton u32 status; 22223e4b0d8bSMarkos Chandras unsigned int len; 2223f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2224f95f3850SWill Newton 2225f95f3850SWill Newton do { 2226f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2227f9c2a0dcSSeungwon Jeon goto done; 2228f95f3850SWill Newton 22294225fc85SImre Deak host->sg = sg_miter->piter.sg; 2230f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2231f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2232f9c2a0dcSSeungwon Jeon offset = 0; 2233f9c2a0dcSSeungwon Jeon 2234f9c2a0dcSSeungwon Jeon do { 2235f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2236f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2237f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2238f9c2a0dcSSeungwon Jeon if (!len) 2239f9c2a0dcSSeungwon Jeon break; 2240f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 22413e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2242f95f3850SWill Newton offset += len; 2243f9c2a0dcSSeungwon Jeon remain -= len; 2244f9c2a0dcSSeungwon Jeon } while (remain); 2245f95f3850SWill Newton 2246e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2247f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2248f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 224987a74d39SKyoungil Kim /* if the RXDR is ready read again */ 225087a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 225187a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2252f9c2a0dcSSeungwon Jeon 2253f9c2a0dcSSeungwon Jeon if (!remain) { 2254f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2255f9c2a0dcSSeungwon Jeon goto done; 2256f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2257f9c2a0dcSSeungwon Jeon } 2258f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2259f95f3850SWill Newton return; 2260f95f3850SWill Newton 2261f95f3850SWill Newton done: 2262f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2263f9c2a0dcSSeungwon Jeon host->sg = NULL; 22640e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2265f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2266f95f3850SWill Newton } 2267f95f3850SWill Newton 2268f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2269f95f3850SWill Newton { 2270f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2271f9c2a0dcSSeungwon Jeon void *buf; 2272f9c2a0dcSSeungwon Jeon unsigned int offset; 2273f95f3850SWill Newton struct mmc_data *data = host->data; 2274f95f3850SWill Newton int shift = host->data_shift; 2275f95f3850SWill Newton u32 status; 22763e4b0d8bSMarkos Chandras unsigned int len; 2277f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2278f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2279f95f3850SWill Newton 2280f95f3850SWill Newton do { 2281f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2282f9c2a0dcSSeungwon Jeon goto done; 2283f95f3850SWill Newton 22844225fc85SImre Deak host->sg = sg_miter->piter.sg; 2285f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2286f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2287f9c2a0dcSSeungwon Jeon offset = 0; 2288f9c2a0dcSSeungwon Jeon 2289f9c2a0dcSSeungwon Jeon do { 2290f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2291f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2292f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2293f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2294f9c2a0dcSSeungwon Jeon if (!len) 2295f9c2a0dcSSeungwon Jeon break; 2296f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 22973e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2298f95f3850SWill Newton offset += len; 2299f9c2a0dcSSeungwon Jeon remain -= len; 2300f9c2a0dcSSeungwon Jeon } while (remain); 2301f95f3850SWill Newton 2302e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2303f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2304f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2305f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2306f9c2a0dcSSeungwon Jeon 2307f9c2a0dcSSeungwon Jeon if (!remain) { 2308f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2309f9c2a0dcSSeungwon Jeon goto done; 2310f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2311f9c2a0dcSSeungwon Jeon } 2312f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2313f95f3850SWill Newton return; 2314f95f3850SWill Newton 2315f95f3850SWill Newton done: 2316f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2317f9c2a0dcSSeungwon Jeon host->sg = NULL; 23180e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2319f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2320f95f3850SWill Newton } 2321f95f3850SWill Newton 2322f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2323f95f3850SWill Newton { 2324f95f3850SWill Newton if (!host->cmd_status) 2325f95f3850SWill Newton host->cmd_status = status; 2326f95f3850SWill Newton 23270e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2328f95f3850SWill Newton 2329f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2330f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2331f95f3850SWill Newton } 2332f95f3850SWill Newton 23336130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 23346130e7a9SDoug Anderson { 23356130e7a9SDoug Anderson int i; 23366130e7a9SDoug Anderson 23376130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 23386130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 23396130e7a9SDoug Anderson 23406130e7a9SDoug Anderson if (!slot) 23416130e7a9SDoug Anderson continue; 23426130e7a9SDoug Anderson 23436130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 23446130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 23456130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 23466130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 23476130e7a9SDoug Anderson } 23486130e7a9SDoug Anderson } 23496130e7a9SDoug Anderson 2350f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2351f95f3850SWill Newton { 2352f95f3850SWill Newton struct dw_mci *host = dev_id; 2353182c9081SSeungwon Jeon u32 pending; 23541a5c8e1fSShashidhar Hiremath int i; 2355f95f3850SWill Newton 2356f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2357f95f3850SWill Newton 2358f95f3850SWill Newton /* 2359f95f3850SWill Newton * DTO fix - version 2.10a and below, and only if internal DMA 2360f95f3850SWill Newton * is configured. 2361f95f3850SWill Newton */ 2362f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2363f95f3850SWill Newton if (!pending && 2364f95f3850SWill Newton ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2365f95f3850SWill Newton pending |= SDMMC_INT_DATA_OVER; 2366f95f3850SWill Newton } 2367f95f3850SWill Newton 2368476d79f1SDoug Anderson if (pending) { 236901730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 237001730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 237101730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 237249ba0302SDoug Anderson unsigned long irqflags; 23735c935165SDoug Anderson 237401730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 237501730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 237649ba0302SDoug Anderson 237749ba0302SDoug Anderson /* 237849ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 237949ba0302SDoug Anderson * off after the lock is released, so safe to delete. 238049ba0302SDoug Anderson */ 238149ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 238201730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 238349ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 238449ba0302SDoug Anderson 238549ba0302SDoug Anderson del_timer(&host->cmd11_timer); 238601730558SDoug Anderson } 238701730558SDoug Anderson 2388f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2389f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2390182c9081SSeungwon Jeon host->cmd_status = pending; 23910e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2392f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2393f95f3850SWill Newton } 2394f95f3850SWill Newton 2395f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2396f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2397f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2398182c9081SSeungwon Jeon host->data_status = pending; 23990e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2400f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2401f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2402f95f3850SWill Newton } 2403f95f3850SWill Newton 2404f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 240557e10486SAddy Ke if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO) 240657e10486SAddy Ke del_timer(&host->dto_timer); 240757e10486SAddy Ke 2408f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2409f95f3850SWill Newton if (!host->data_status) 2410182c9081SSeungwon Jeon host->data_status = pending; 24110e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2412f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2413f95f3850SWill Newton if (host->sg != NULL) 241487a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2415f95f3850SWill Newton } 2416f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2417f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2418f95f3850SWill Newton } 2419f95f3850SWill Newton 2420f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2421f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2422b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 242387a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2424f95f3850SWill Newton } 2425f95f3850SWill Newton 2426f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2427f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2428b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2429f95f3850SWill Newton dw_mci_write_data_pio(host); 2430f95f3850SWill Newton } 2431f95f3850SWill Newton 2432f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2433f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2434182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2435f95f3850SWill Newton } 2436f95f3850SWill Newton 2437f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2438f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 24396130e7a9SDoug Anderson dw_mci_handle_cd(host); 2440f95f3850SWill Newton } 2441f95f3850SWill Newton 24421a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 24431a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 24441a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2445ed2540efSDoug Anderson 2446ed2540efSDoug Anderson if (!slot) 2447ed2540efSDoug Anderson continue; 2448ed2540efSDoug Anderson 244976756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 245076756234SAddy Ke mci_writel(host, RINTSTS, 245176756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 24521a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 24531a5c8e1fSShashidhar Hiremath } 24541a5c8e1fSShashidhar Hiremath } 24551a5c8e1fSShashidhar Hiremath 24561fb5f68aSMarkos Chandras } 2457f95f3850SWill Newton 24583fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 24593fc7eaefSShawn Lin return IRQ_HANDLED; 24603fc7eaefSShawn Lin 24613fc7eaefSShawn Lin /* Handle IDMA interrupts */ 246269d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 246369d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 246469d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 246569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 246669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 246769d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 24683fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 246969d99fdcSPrabu Thangamuthu } 247069d99fdcSPrabu Thangamuthu } else { 2471f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2472f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 247369d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 247469d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2475f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 24763fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2477f95f3850SWill Newton } 247869d99fdcSPrabu Thangamuthu } 2479f95f3850SWill Newton 2480f95f3850SWill Newton return IRQ_HANDLED; 2481f95f3850SWill Newton } 2482f95f3850SWill Newton 2483c91eab4bSThomas Abraham #ifdef CONFIG_OF 2484eff8f2f5SLars-Peter Clausen /* given a slot, find out the device node representing that slot */ 2485eff8f2f5SLars-Peter Clausen static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot) 2486c91eab4bSThomas Abraham { 2487eff8f2f5SLars-Peter Clausen struct device *dev = slot->mmc->parent; 2488c91eab4bSThomas Abraham struct device_node *np; 2489c91eab4bSThomas Abraham const __be32 *addr; 2490c91eab4bSThomas Abraham int len; 2491c91eab4bSThomas Abraham 2492c91eab4bSThomas Abraham if (!dev || !dev->of_node) 2493c91eab4bSThomas Abraham return NULL; 2494c91eab4bSThomas Abraham 2495c91eab4bSThomas Abraham for_each_child_of_node(dev->of_node, np) { 2496c91eab4bSThomas Abraham addr = of_get_property(np, "reg", &len); 2497c91eab4bSThomas Abraham if (!addr || (len < sizeof(int))) 2498c91eab4bSThomas Abraham continue; 2499eff8f2f5SLars-Peter Clausen if (be32_to_cpup(addr) == slot->id) 2500c91eab4bSThomas Abraham return np; 2501c91eab4bSThomas Abraham } 2502c91eab4bSThomas Abraham return NULL; 2503c91eab4bSThomas Abraham } 2504c91eab4bSThomas Abraham 2505eff8f2f5SLars-Peter Clausen static void dw_mci_slot_of_parse(struct dw_mci_slot *slot) 2506a70aaa64SDoug Anderson { 2507eff8f2f5SLars-Peter Clausen struct device_node *np = dw_mci_of_find_slot_node(slot); 2508a70aaa64SDoug Anderson 2509eff8f2f5SLars-Peter Clausen if (!np) 2510eff8f2f5SLars-Peter Clausen return; 2511a70aaa64SDoug Anderson 2512eff8f2f5SLars-Peter Clausen if (of_property_read_bool(np, "disable-wp")) { 2513eff8f2f5SLars-Peter Clausen slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; 2514eff8f2f5SLars-Peter Clausen dev_warn(slot->mmc->parent, 2515eff8f2f5SLars-Peter Clausen "Slot quirk 'disable-wp' is deprecated\n"); 251626375b5cSJaehoon Chung } 2517a70aaa64SDoug Anderson } 2518c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2519eff8f2f5SLars-Peter Clausen static void dw_mci_slot_of_parse(struct dw_mci_slot *slot) 2520a70aaa64SDoug Anderson { 2521a70aaa64SDoug Anderson } 2522c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2523c91eab4bSThomas Abraham 252436c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2525f95f3850SWill Newton { 2526f95f3850SWill Newton struct mmc_host *mmc; 2527f95f3850SWill Newton struct dw_mci_slot *slot; 2528e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2529800d78bfSThomas Abraham int ctrl_id, ret; 25301f44a2a5SSeungwon Jeon u32 freq[2]; 2531f95f3850SWill Newton 25324a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2533f95f3850SWill Newton if (!mmc) 2534f95f3850SWill Newton return -ENOMEM; 2535f95f3850SWill Newton 2536f95f3850SWill Newton slot = mmc_priv(mmc); 2537f95f3850SWill Newton slot->id = id; 253876756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2539f95f3850SWill Newton slot->mmc = mmc; 2540f95f3850SWill Newton slot->host = host; 2541c91eab4bSThomas Abraham host->slot[id] = slot; 2542f95f3850SWill Newton 2543f95f3850SWill Newton mmc->ops = &dw_mci_ops; 25441f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 25451f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 25461f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 25471f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 25481f44a2a5SSeungwon Jeon } else { 25491f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 25501f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 25511f44a2a5SSeungwon Jeon } 2552f95f3850SWill Newton 255351da2240SYuvaraj CD /*if there are external regulators, get them*/ 255451da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 255551da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 25563cf890fcSDoug Anderson goto err_host_allocated; 255751da2240SYuvaraj CD 255851da2240SYuvaraj CD if (!mmc->ocr_avail) 2559f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2560f95f3850SWill Newton 2561fc3d7720SJaehoon Chung if (host->pdata->caps) 2562fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2563fc3d7720SJaehoon Chung 2564ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2565ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2566ab269128SAbhilash Kesavan 2567800d78bfSThomas Abraham if (host->dev->of_node) { 2568800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2569800d78bfSThomas Abraham if (ctrl_id < 0) 2570800d78bfSThomas Abraham ctrl_id = 0; 2571800d78bfSThomas Abraham } else { 2572800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2573800d78bfSThomas Abraham } 2574cb27a843SJames Hogan if (drv_data && drv_data->caps) 2575cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2576800d78bfSThomas Abraham 25774f408cc6SSeungwon Jeon if (host->pdata->caps2) 25784f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 25794f408cc6SSeungwon Jeon 2580eff8f2f5SLars-Peter Clausen dw_mci_slot_of_parse(slot); 2581eff8f2f5SLars-Peter Clausen 25823cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 25833cf890fcSDoug Anderson if (ret) 25843cf890fcSDoug Anderson goto err_host_allocated; 2585f95f3850SWill Newton 2586f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 25873fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2588a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2589a39e5746SJaehoon Chung mmc->max_blk_size = 65536; 2590575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 25911a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 25921a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 25933fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 25943fc7eaefSShawn Lin mmc->max_segs = 64; 25953fc7eaefSShawn Lin mmc->max_blk_size = 65536; 25963fc7eaefSShawn Lin mmc->max_blk_count = 65535; 25973fc7eaefSShawn Lin mmc->max_req_size = 25983fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 25993fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2600575c319dSHeiko Stuebner } else { 26013fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2602f95f3850SWill Newton mmc->max_segs = 64; 2603f95f3850SWill Newton mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2604f95f3850SWill Newton mmc->max_blk_count = 512; 2605575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2606575c319dSHeiko Stuebner mmc->max_blk_count; 2607f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2608575c319dSHeiko Stuebner } 2609f95f3850SWill Newton 2610ae0eb348SJaehoon Chung if (dw_mci_get_cd(mmc)) 2611ae0eb348SJaehoon Chung set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2612ae0eb348SJaehoon Chung else 2613ae0eb348SJaehoon Chung clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2614ae0eb348SJaehoon Chung 26150cea529dSJaehoon Chung ret = mmc_add_host(mmc); 26160cea529dSJaehoon Chung if (ret) 26173cf890fcSDoug Anderson goto err_host_allocated; 2618f95f3850SWill Newton 2619f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2620f95f3850SWill Newton dw_mci_init_debugfs(slot); 2621f95f3850SWill Newton #endif 2622f95f3850SWill Newton 2623f95f3850SWill Newton return 0; 2624800d78bfSThomas Abraham 26253cf890fcSDoug Anderson err_host_allocated: 2626800d78bfSThomas Abraham mmc_free_host(mmc); 262751da2240SYuvaraj CD return ret; 2628f95f3850SWill Newton } 2629f95f3850SWill Newton 2630f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2631f95f3850SWill Newton { 2632f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2633f95f3850SWill Newton mmc_remove_host(slot->mmc); 2634f95f3850SWill Newton slot->host->slot[id] = NULL; 2635f95f3850SWill Newton mmc_free_host(slot->mmc); 2636f95f3850SWill Newton } 2637f95f3850SWill Newton 2638f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2639f95f3850SWill Newton { 264069d99fdcSPrabu Thangamuthu int addr_config; 26413fc7eaefSShawn Lin struct device *dev = host->dev; 26423fc7eaefSShawn Lin struct device_node *np = dev->of_node; 26433fc7eaefSShawn Lin 26443fc7eaefSShawn Lin /* 26453fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 26463fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 26473fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 26483fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 26493fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 26503fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 26513fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 26523fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 26533fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 26543fc7eaefSShawn Lin */ 26553fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 26563fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 26573fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 26583fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 26593fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 26603fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 26613fc7eaefSShawn Lin } else { 26623fc7eaefSShawn Lin goto no_dma; 26633fc7eaefSShawn Lin } 26643fc7eaefSShawn Lin 26653fc7eaefSShawn Lin /* Determine which DMA interface to use */ 26663fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 26673fc7eaefSShawn Lin /* 26683fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 26693fc7eaefSShawn Lin * IDMAC address bus width 26703fc7eaefSShawn Lin */ 267170692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 267269d99fdcSPrabu Thangamuthu 267369d99fdcSPrabu Thangamuthu if (addr_config == 1) { 267469d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 267569d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 26763fc7eaefSShawn Lin dev_info(host->dev, 26773fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 267869d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 26793fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 26803fc7eaefSShawn Lin DMA_BIT_MASK(64)); 268169d99fdcSPrabu Thangamuthu } else { 268269d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 268369d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 26843fc7eaefSShawn Lin dev_info(host->dev, 26853fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 268669d99fdcSPrabu Thangamuthu } 268769d99fdcSPrabu Thangamuthu 2688f95f3850SWill Newton /* Alloc memory for sg translation */ 2689780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2690f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2691f95f3850SWill Newton if (!host->sg_cpu) { 26923fc7eaefSShawn Lin dev_err(host->dev, 26933fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2694f95f3850SWill Newton __func__); 2695f95f3850SWill Newton goto no_dma; 2696f95f3850SWill Newton } 2697f95f3850SWill Newton 2698f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 269900956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 27003fc7eaefSShawn Lin } else { 27013fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 27023fc7eaefSShawn Lin if ((of_property_count_strings(np, "dma-names") < 0) || 27033fc7eaefSShawn Lin (!of_find_property(np, "dmas", NULL))) { 2704f95f3850SWill Newton goto no_dma; 27053fc7eaefSShawn Lin } 27063fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 27073fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 27083fc7eaefSShawn Lin } 2709f95f3850SWill Newton 2710e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2711e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2712f95f3850SWill Newton if (host->dma_ops->init(host)) { 27130e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 27140e3a22c0SShawn Lin __func__); 2715f95f3850SWill Newton goto no_dma; 2716f95f3850SWill Newton } 2717f95f3850SWill Newton } else { 27184a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2719f95f3850SWill Newton goto no_dma; 2720f95f3850SWill Newton } 2721f95f3850SWill Newton 2722f95f3850SWill Newton return; 2723f95f3850SWill Newton 2724f95f3850SWill Newton no_dma: 27254a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 27263fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2727f95f3850SWill Newton } 2728f95f3850SWill Newton 272931bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2730f95f3850SWill Newton { 2731f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 273231bff450SSeungwon Jeon u32 ctrl; 2733f95f3850SWill Newton 273431bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 273531bff450SSeungwon Jeon ctrl |= reset; 273631bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2737f95f3850SWill Newton 2738f95f3850SWill Newton /* wait till resets clear */ 2739f95f3850SWill Newton do { 2740f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 274131bff450SSeungwon Jeon if (!(ctrl & reset)) 2742f95f3850SWill Newton return true; 2743f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2744f95f3850SWill Newton 274531bff450SSeungwon Jeon dev_err(host->dev, 274631bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 274731bff450SSeungwon Jeon ctrl & reset); 2748f95f3850SWill Newton 2749f95f3850SWill Newton return false; 2750f95f3850SWill Newton } 2751f95f3850SWill Newton 27523a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 275331bff450SSeungwon Jeon { 27543a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 27553a33a94cSSonny Rao bool ret = false; 27563a33a94cSSonny Rao 275731bff450SSeungwon Jeon /* 275831bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 275931bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 276031bff450SSeungwon Jeon */ 276131bff450SSeungwon Jeon if (host->sg) { 276231bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 276331bff450SSeungwon Jeon host->sg = NULL; 276431bff450SSeungwon Jeon } 276531bff450SSeungwon Jeon 27663a33a94cSSonny Rao if (host->use_dma) 27673a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 27683a33a94cSSonny Rao 27693a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 27703a33a94cSSonny Rao /* 27713a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 27723a33a94cSSonny Rao * interrupts. 27733a33a94cSSonny Rao */ 27743a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 27753a33a94cSSonny Rao 27763a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 27773a33a94cSSonny Rao if (host->use_dma) { 27783a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 27793a33a94cSSonny Rao u32 status; 27800e3a22c0SShawn Lin 27813a33a94cSSonny Rao do { 27823a33a94cSSonny Rao status = mci_readl(host, STATUS); 27833a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 27843a33a94cSSonny Rao break; 27853a33a94cSSonny Rao cpu_relax(); 27863a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 27873a33a94cSSonny Rao 27883a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 27893a33a94cSSonny Rao dev_err(host->dev, 27900e3a22c0SShawn Lin "%s: Timeout waiting for dma_req to clear during reset\n", 27910e3a22c0SShawn Lin __func__); 27923a33a94cSSonny Rao goto ciu_out; 279331bff450SSeungwon Jeon } 279431bff450SSeungwon Jeon 27953a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 27963a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 27973a33a94cSSonny Rao goto ciu_out; 27983a33a94cSSonny Rao } 27993a33a94cSSonny Rao } else { 28003a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 28013a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 28020e3a22c0SShawn Lin dev_err(host->dev, 28030e3a22c0SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 28043a33a94cSSonny Rao __func__); 28053a33a94cSSonny Rao goto ciu_out; 28063a33a94cSSonny Rao } 28073a33a94cSSonny Rao } 28083a33a94cSSonny Rao 28093fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 28103a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 28113a33a94cSSonny Rao dw_mci_idmac_reset(host); 28123a33a94cSSonny Rao 28133a33a94cSSonny Rao ret = true; 28143a33a94cSSonny Rao 28153a33a94cSSonny Rao ciu_out: 28163a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 28173a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 28183a33a94cSSonny Rao 28193a33a94cSSonny Rao return ret; 282031bff450SSeungwon Jeon } 282131bff450SSeungwon Jeon 28225c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 28235c935165SDoug Anderson { 28245c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 28255c935165SDoug Anderson 2826fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 2827fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2828fd674198SDoug Anderson return; 2829fd674198SDoug Anderson } 28305c935165SDoug Anderson 28315c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 28325c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 28335c935165SDoug Anderson tasklet_schedule(&host->tasklet); 28345c935165SDoug Anderson } 28355c935165SDoug Anderson 283657e10486SAddy Ke static void dw_mci_dto_timer(unsigned long arg) 283757e10486SAddy Ke { 283857e10486SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 283957e10486SAddy Ke 284057e10486SAddy Ke switch (host->state) { 284157e10486SAddy Ke case STATE_SENDING_DATA: 284257e10486SAddy Ke case STATE_DATA_BUSY: 284357e10486SAddy Ke /* 284457e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 284557e10486SAddy Ke * we should notify the driver to terminate current transfer 284657e10486SAddy Ke * and report a data timeout to the core. 284757e10486SAddy Ke */ 284857e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 284957e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 285057e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 285157e10486SAddy Ke tasklet_schedule(&host->tasklet); 285257e10486SAddy Ke break; 285357e10486SAddy Ke default: 285457e10486SAddy Ke break; 285557e10486SAddy Ke } 285657e10486SAddy Ke } 285757e10486SAddy Ke 2858c91eab4bSThomas Abraham #ifdef CONFIG_OF 2859c91eab4bSThomas Abraham static struct dw_mci_of_quirks { 2860c91eab4bSThomas Abraham char *quirk; 2861c91eab4bSThomas Abraham int id; 2862c91eab4bSThomas Abraham } of_quirks[] = { 2863c91eab4bSThomas Abraham { 2864c91eab4bSThomas Abraham .quirk = "broken-cd", 2865c91eab4bSThomas Abraham .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 2866c91eab4bSThomas Abraham }, 2867c91eab4bSThomas Abraham }; 2868c91eab4bSThomas Abraham 2869c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2870c91eab4bSThomas Abraham { 2871c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2872c91eab4bSThomas Abraham struct device *dev = host->dev; 2873c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2874e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2875800d78bfSThomas Abraham int idx, ret; 28763c6d89eaSDoug Anderson u32 clock_frequency; 2877c91eab4bSThomas Abraham 2878c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2879bf3707eaSBeomho Seo if (!pdata) 2880c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2881c91eab4bSThomas Abraham 2882c91eab4bSThomas Abraham /* find out number of slots supported */ 2883c91eab4bSThomas Abraham if (of_property_read_u32(dev->of_node, "num-slots", 2884c91eab4bSThomas Abraham &pdata->num_slots)) { 28850e3a22c0SShawn Lin dev_info(dev, 28860e3a22c0SShawn Lin "num-slots property not found, assuming 1 slot is available\n"); 2887c91eab4bSThomas Abraham pdata->num_slots = 1; 2888c91eab4bSThomas Abraham } 2889c91eab4bSThomas Abraham 2890c91eab4bSThomas Abraham /* get quirks */ 2891c91eab4bSThomas Abraham for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2892c91eab4bSThomas Abraham if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2893c91eab4bSThomas Abraham pdata->quirks |= of_quirks[idx].id; 2894c91eab4bSThomas Abraham 2895c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 28960e3a22c0SShawn Lin dev_info(dev, 28970e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 2898c91eab4bSThomas Abraham 2899c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2900c91eab4bSThomas Abraham 29013c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 29023c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 29033c6d89eaSDoug Anderson 2904cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2905cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2906800d78bfSThomas Abraham if (ret) 2907800d78bfSThomas Abraham return ERR_PTR(ret); 2908800d78bfSThomas Abraham } 2909800d78bfSThomas Abraham 291040a7a463SJaehoon Chung if (of_find_property(np, "supports-highspeed", NULL)) { 291140a7a463SJaehoon Chung dev_info(dev, "supports-highspeed property is deprecated.\n"); 291210b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 291340a7a463SJaehoon Chung } 291410b49841SSeungwon Jeon 2915c91eab4bSThomas Abraham return pdata; 2916c91eab4bSThomas Abraham } 2917c91eab4bSThomas Abraham 2918c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2919c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2920c91eab4bSThomas Abraham { 2921c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2922c91eab4bSThomas Abraham } 2923c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2924c91eab4bSThomas Abraham 2925fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2926fa0c3283SDoug Anderson { 2927fa0c3283SDoug Anderson struct dw_mci_board *brd = host->pdata; 2928fa0c3283SDoug Anderson unsigned long irqflags; 2929fa0c3283SDoug Anderson u32 temp; 2930fa0c3283SDoug Anderson int i; 2931fa0c3283SDoug Anderson 2932fa0c3283SDoug Anderson /* No need for CD if broken card detection */ 2933fa0c3283SDoug Anderson if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 2934fa0c3283SDoug Anderson return; 2935fa0c3283SDoug Anderson 2936fa0c3283SDoug Anderson /* No need for CD if all slots have a non-error GPIO */ 2937fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 2938fa0c3283SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 2939fa0c3283SDoug Anderson 2940fa0c3283SDoug Anderson if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) 2941fa0c3283SDoug Anderson break; 2942fa0c3283SDoug Anderson } 2943fa0c3283SDoug Anderson if (i == host->num_slots) 2944fa0c3283SDoug Anderson return; 2945fa0c3283SDoug Anderson 2946fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 2947fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 2948fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 2949fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 2950fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2951fa0c3283SDoug Anderson } 2952fa0c3283SDoug Anderson 295362ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2954f95f3850SWill Newton { 2955e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 295662ca8034SShashidhar Hiremath int width, i, ret = 0; 2957f95f3850SWill Newton u32 fifo_size; 29581c2215b7SThomas Abraham int init_slots = 0; 2959f95f3850SWill Newton 2960c91eab4bSThomas Abraham if (!host->pdata) { 2961c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2962c91eab4bSThomas Abraham if (IS_ERR(host->pdata)) { 2963c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2964c91eab4bSThomas Abraham return -EINVAL; 2965c91eab4bSThomas Abraham } 2966f95f3850SWill Newton } 2967f95f3850SWill Newton 29689e747b7eSJaehoon Chung if (host->pdata->num_slots < 1) { 29694a90920cSThomas Abraham dev_err(host->dev, 2970907abd51SJaehoon Chung "Platform data must supply num_slots.\n"); 297162ca8034SShashidhar Hiremath return -ENODEV; 2972f95f3850SWill Newton } 2973f95f3850SWill Newton 2974780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2975f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2976f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2977f90a0612SThomas Abraham } else { 2978f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2979f90a0612SThomas Abraham if (ret) { 2980f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2981f90a0612SThomas Abraham return ret; 2982f90a0612SThomas Abraham } 2983f95f3850SWill Newton } 2984f95f3850SWill Newton 2985780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2986f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2987f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 29883c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2989f90a0612SThomas Abraham } else { 2990f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2991f90a0612SThomas Abraham if (ret) { 2992f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2993f90a0612SThomas Abraham goto err_clk_biu; 2994f90a0612SThomas Abraham } 2995f90a0612SThomas Abraham 29963c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 29973c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 29983c6d89eaSDoug Anderson if (ret) 29993c6d89eaSDoug Anderson dev_warn(host->dev, 3000612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 30013c6d89eaSDoug Anderson host->pdata->bus_hz); 30023c6d89eaSDoug Anderson } 3003f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 30043c6d89eaSDoug Anderson } 3005f90a0612SThomas Abraham 3006612de4c1SJaehoon Chung if (!host->bus_hz) { 3007612de4c1SJaehoon Chung dev_err(host->dev, 3008612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3009612de4c1SJaehoon Chung ret = -ENODEV; 3010612de4c1SJaehoon Chung goto err_clk_ciu; 3011612de4c1SJaehoon Chung } 3012612de4c1SJaehoon Chung 3013002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3014002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3015002f0d5cSYuvaraj Kumar C D if (ret) { 3016002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3017002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3018002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3019002f0d5cSYuvaraj Kumar C D } 3020002f0d5cSYuvaraj Kumar C D } 3021002f0d5cSYuvaraj Kumar C D 3022cb27a843SJames Hogan if (drv_data && drv_data->setup_clock) { 3023cb27a843SJames Hogan ret = drv_data->setup_clock(host); 3024800d78bfSThomas Abraham if (ret) { 3025800d78bfSThomas Abraham dev_err(host->dev, 3026800d78bfSThomas Abraham "implementation specific clock setup failed\n"); 3027800d78bfSThomas Abraham goto err_clk_ciu; 3028800d78bfSThomas Abraham } 3029800d78bfSThomas Abraham } 3030800d78bfSThomas Abraham 30315c935165SDoug Anderson setup_timer(&host->cmd11_timer, 30325c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 30335c935165SDoug Anderson 303462ca8034SShashidhar Hiremath host->quirks = host->pdata->quirks; 3035f95f3850SWill Newton 303657e10486SAddy Ke if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO) 303757e10486SAddy Ke setup_timer(&host->dto_timer, 303857e10486SAddy Ke dw_mci_dto_timer, (unsigned long)host); 303957e10486SAddy Ke 3040f95f3850SWill Newton spin_lock_init(&host->lock); 3041f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3042f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3043f95f3850SWill Newton 3044f95f3850SWill Newton /* 3045f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3046f95f3850SWill Newton * the correct values. 3047f95f3850SWill Newton */ 304870692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3049f95f3850SWill Newton if (!i) { 3050f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3051f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3052f95f3850SWill Newton width = 16; 3053f95f3850SWill Newton host->data_shift = 1; 3054f95f3850SWill Newton } else if (i == 2) { 3055f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3056f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3057f95f3850SWill Newton width = 64; 3058f95f3850SWill Newton host->data_shift = 3; 3059f95f3850SWill Newton } else { 3060f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3061f95f3850SWill Newton WARN((i != 1), 3062f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3063f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3064f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3065f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3066f95f3850SWill Newton width = 32; 3067f95f3850SWill Newton host->data_shift = 2; 3068f95f3850SWill Newton } 3069f95f3850SWill Newton 3070f95f3850SWill Newton /* Reset all blocks */ 30713a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 3072141a712aSSeungwon Jeon return -ENODEV; 3073141a712aSSeungwon Jeon 3074141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3075141a712aSSeungwon Jeon dw_mci_init_dma(host); 3076f95f3850SWill Newton 3077f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3078f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3079f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3080f95f3850SWill Newton 3081f95f3850SWill Newton /* Put in max timeout */ 3082f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3083f95f3850SWill Newton 3084f95f3850SWill Newton /* 3085f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3086f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3087f95f3850SWill Newton */ 3088b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3089b86d8253SJames Hogan /* 3090b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3091b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3092b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3093b86d8253SJames Hogan * should put it in the platform data. 3094b86d8253SJames Hogan */ 3095f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 30968234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3097b86d8253SJames Hogan } else { 3098b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3099b86d8253SJames Hogan } 3100b86d8253SJames Hogan host->fifo_depth = fifo_size; 310152426899SSeungwon Jeon host->fifoth_val = 310252426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3103e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3104f95f3850SWill Newton 3105f95f3850SWill Newton /* disable clock to CIU */ 3106f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3107f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3108f95f3850SWill Newton 310963008768SJames Hogan /* 311063008768SJames Hogan * In 2.40a spec, Data offset is changed. 311163008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 311263008768SJames Hogan */ 311363008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 311463008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 311563008768SJames Hogan 311663008768SJames Hogan if (host->verid < DW_MMC_240A) 311776184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 311863008768SJames Hogan else 311976184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 312063008768SJames Hogan 3121f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3122780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3123780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3124f95f3850SWill Newton if (ret) 31256130e7a9SDoug Anderson goto err_dmaunmap; 3126f95f3850SWill Newton 3127f95f3850SWill Newton if (host->pdata->num_slots) 3128f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 3129f95f3850SWill Newton else 313070692752SShawn Lin host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON)); 3131f95f3850SWill Newton 31322da1d7f2SYuvaraj CD /* 3133fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 31342da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 31352da1d7f2SYuvaraj CD */ 31362da1d7f2SYuvaraj CD mci_writel(host, RINTSTS, 0xFFFFFFFF); 31372da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 31382da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3139fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 31400e3a22c0SShawn Lin /* Enable mci interrupt */ 31410e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 31422da1d7f2SYuvaraj CD 31430e3a22c0SShawn Lin dev_info(host->dev, 31440e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 31452da1d7f2SYuvaraj CD host->irq, width, fifo_size); 31462da1d7f2SYuvaraj CD 3147f95f3850SWill Newton /* We need at least one slot to succeed */ 3148f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3149f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 31501c2215b7SThomas Abraham if (ret) 31511c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 31521c2215b7SThomas Abraham else 31531c2215b7SThomas Abraham init_slots++; 3154f95f3850SWill Newton } 31551c2215b7SThomas Abraham 31561c2215b7SThomas Abraham if (init_slots) { 31571c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 31581c2215b7SThomas Abraham } else { 31590e3a22c0SShawn Lin dev_dbg(host->dev, 31600e3a22c0SShawn Lin "attempted to initialize %d slots, but failed on all\n", 31610e3a22c0SShawn Lin host->num_slots); 31626130e7a9SDoug Anderson goto err_dmaunmap; 3163f95f3850SWill Newton } 3164f95f3850SWill Newton 3165b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3166b793f658SDoug Anderson dw_mci_enable_cd(host); 3167b793f658SDoug Anderson 3168f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 31694a90920cSThomas Abraham dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 3170f95f3850SWill Newton 3171f95f3850SWill Newton return 0; 3172f95f3850SWill Newton 3173f95f3850SWill Newton err_dmaunmap: 3174f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3175f95f3850SWill Newton host->dma_ops->exit(host); 3176f90a0612SThomas Abraham 3177f90a0612SThomas Abraham err_clk_ciu: 3178780f22afSSeungwon Jeon if (!IS_ERR(host->ciu_clk)) 3179f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3180780f22afSSeungwon Jeon 3181f90a0612SThomas Abraham err_clk_biu: 3182780f22afSSeungwon Jeon if (!IS_ERR(host->biu_clk)) 3183f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3184780f22afSSeungwon Jeon 3185f95f3850SWill Newton return ret; 3186f95f3850SWill Newton } 318762ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3188f95f3850SWill Newton 318962ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3190f95f3850SWill Newton { 3191f95f3850SWill Newton int i; 3192f95f3850SWill Newton 3193f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 31944a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 3195f95f3850SWill Newton if (host->slot[i]) 3196f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 3197f95f3850SWill Newton } 3198f95f3850SWill Newton 3199048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3200048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3201048fd7e6SPrabu Thangamuthu 3202f95f3850SWill Newton /* disable clock to CIU */ 3203f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3204f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3205f95f3850SWill Newton 3206f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3207f95f3850SWill Newton host->dma_ops->exit(host); 3208f95f3850SWill Newton 3209f90a0612SThomas Abraham if (!IS_ERR(host->ciu_clk)) 3210f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3211780f22afSSeungwon Jeon 3212f90a0612SThomas Abraham if (!IS_ERR(host->biu_clk)) 3213f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3214f95f3850SWill Newton } 321562ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 321662ca8034SShashidhar Hiremath 321762ca8034SShashidhar Hiremath 3218f95f3850SWill Newton 32196fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 3220f95f3850SWill Newton /* 3221f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 3222f95f3850SWill Newton */ 322362ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 3224f95f3850SWill Newton { 32253fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 32263fc7eaefSShawn Lin host->dma_ops->exit(host); 32273fc7eaefSShawn Lin 3228f95f3850SWill Newton return 0; 3229f95f3850SWill Newton } 323062ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 3231f95f3850SWill Newton 323262ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 3233f95f3850SWill Newton { 3234f95f3850SWill Newton int i, ret; 3235f95f3850SWill Newton 32363a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3237e61cf118SJaehoon Chung ret = -ENODEV; 3238e61cf118SJaehoon Chung return ret; 3239e61cf118SJaehoon Chung } 3240e61cf118SJaehoon Chung 32413bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3242141a712aSSeungwon Jeon host->dma_ops->init(host); 3243141a712aSSeungwon Jeon 324452426899SSeungwon Jeon /* 324552426899SSeungwon Jeon * Restore the initial value at FIFOTH register 324652426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 324752426899SSeungwon Jeon */ 3248e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 324952426899SSeungwon Jeon host->prev_blksz = 0; 3250e61cf118SJaehoon Chung 32512eb2944fSDoug Anderson /* Put in max timeout */ 32522eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 32532eb2944fSDoug Anderson 3254e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3255e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3256e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3257fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3258e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3259e61cf118SJaehoon Chung 3260f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3261f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 32620e3a22c0SShawn Lin 3263f95f3850SWill Newton if (!slot) 3264f95f3850SWill Newton continue; 3265ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 3266ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3267ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 3268ab269128SAbhilash Kesavan } 3269f95f3850SWill Newton } 3270fa0c3283SDoug Anderson 3271fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3272fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3273fa0c3283SDoug Anderson 3274f95f3850SWill Newton return 0; 3275f95f3850SWill Newton } 327662ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 32776fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 32786fe8890dSJaehoon Chung 3279f95f3850SWill Newton static int __init dw_mci_init(void) 3280f95f3850SWill Newton { 32818e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 328262ca8034SShashidhar Hiremath return 0; 3283f95f3850SWill Newton } 3284f95f3850SWill Newton 3285f95f3850SWill Newton static void __exit dw_mci_exit(void) 3286f95f3850SWill Newton { 3287f95f3850SWill Newton } 3288f95f3850SWill Newton 3289f95f3850SWill Newton module_init(dw_mci_init); 3290f95f3850SWill Newton module_exit(dw_mci_exit); 3291f95f3850SWill Newton 3292f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3293f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3294f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3295f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3296