1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22b6d2d81cSShawn Lin #include <linux/iopoll.h> 23f95f3850SWill Newton #include <linux/ioport.h> 24f95f3850SWill Newton #include <linux/module.h> 25f95f3850SWill Newton #include <linux/platform_device.h> 26a6db2c86SDouglas Anderson #include <linux/pm_runtime.h> 27f95f3850SWill Newton #include <linux/seq_file.h> 28f95f3850SWill Newton #include <linux/slab.h> 29f95f3850SWill Newton #include <linux/stat.h> 30f95f3850SWill Newton #include <linux/delay.h> 31f95f3850SWill Newton #include <linux/irq.h> 32b24c8b26SDoug Anderson #include <linux/mmc/card.h> 33f95f3850SWill Newton #include <linux/mmc/host.h> 34f95f3850SWill Newton #include <linux/mmc/mmc.h> 3501730558SDoug Anderson #include <linux/mmc/sd.h> 3690c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 37f95f3850SWill Newton #include <linux/bitops.h> 38c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 39c91eab4bSThomas Abraham #include <linux/of.h> 4055a6ceb2SDoug Anderson #include <linux/of_gpio.h> 41bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 42f95f3850SWill Newton 43f95f3850SWill Newton #include "dw_mmc.h" 44f95f3850SWill Newton 45f95f3850SWill Newton /* Common flag combinations */ 463f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 487a3c5677SDoug Anderson SDMMC_INT_EBE | SDMMC_INT_HLE) 49f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 507a3c5677SDoug Anderson SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 527a3c5677SDoug Anderson DW_MCI_CMD_ERROR_FLAGS) 53f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 54f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 55f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 56f95f3850SWill Newton 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 5872e83577SJaehoon Chung #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 591f44a2a5SSeungwon Jeon 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 65cc190d4cSShawn Lin #define DESC_RING_BUF_SZ PAGE_SIZE 66cc190d4cSShawn Lin 6769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6869d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 69b6d2d81cSShawn Lin #define IDMAC_OWN_CLR64(x) \ 70b6d2d81cSShawn Lin !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 7169d99fdcSPrabu Thangamuthu 7269d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7569d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 766687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 776687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 8069d99fdcSPrabu Thangamuthu 8169d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 8269d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 8369d99fdcSPrabu Thangamuthu 8469d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8569d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8669d99fdcSPrabu Thangamuthu }; 8769d99fdcSPrabu Thangamuthu 88f95f3850SWill Newton struct idmac_desc { 896687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 90f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 91f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 92f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 93f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 94f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 95f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 96f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 97f95f3850SWill Newton 986687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 99f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100e5306c3aSBen Dooks ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101f95f3850SWill Newton 1026687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 103f95f3850SWill Newton 1046687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 105f95f3850SWill Newton }; 1065959b32eSAlexey Brodkin 1075959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1085959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 109f95f3850SWill Newton 110f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 111f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 112f95f3850SWill Newton { 113f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 114f95f3850SWill Newton struct mmc_request *mrq; 115f95f3850SWill Newton struct mmc_command *cmd; 116f95f3850SWill Newton struct mmc_command *stop; 117f95f3850SWill Newton struct mmc_data *data; 118f95f3850SWill Newton 119f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 120f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 121f95f3850SWill Newton mrq = slot->mrq; 122f95f3850SWill Newton 123f95f3850SWill Newton if (mrq) { 124f95f3850SWill Newton cmd = mrq->cmd; 125f95f3850SWill Newton data = mrq->data; 126f95f3850SWill Newton stop = mrq->stop; 127f95f3850SWill Newton 128f95f3850SWill Newton if (cmd) 129f95f3850SWill Newton seq_printf(s, 130f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 132f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 133f95f3850SWill Newton cmd->resp[2], cmd->error); 134f95f3850SWill Newton if (data) 135f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136f95f3850SWill Newton data->bytes_xfered, data->blocks, 137f95f3850SWill Newton data->blksz, data->flags, data->error); 138f95f3850SWill Newton if (stop) 139f95f3850SWill Newton seq_printf(s, 140f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 142f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 143f95f3850SWill Newton stop->resp[2], stop->error); 144f95f3850SWill Newton } 145f95f3850SWill Newton 146f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 147f95f3850SWill Newton 148f95f3850SWill Newton return 0; 149f95f3850SWill Newton } 15064c1412bSShawn Lin DEFINE_SHOW_ATTRIBUTE(dw_mci_req); 151f95f3850SWill Newton 152f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 153f95f3850SWill Newton { 15421657ebdSJaehoon Chung struct dw_mci *host = s->private; 15521657ebdSJaehoon Chung 1565b43df8bSShawn Lin pm_runtime_get_sync(host->dev); 1575b43df8bSShawn Lin 15821657ebdSJaehoon Chung seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 15921657ebdSJaehoon Chung seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 16021657ebdSJaehoon Chung seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 16121657ebdSJaehoon Chung seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 16221657ebdSJaehoon Chung seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 16321657ebdSJaehoon Chung seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 164f95f3850SWill Newton 1655b43df8bSShawn Lin pm_runtime_put_autosuspend(host->dev); 1665b43df8bSShawn Lin 167f95f3850SWill Newton return 0; 168f95f3850SWill Newton } 16964c1412bSShawn Lin DEFINE_SHOW_ATTRIBUTE(dw_mci_regs); 170f95f3850SWill Newton 171f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 172f95f3850SWill Newton { 173f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 174f95f3850SWill Newton struct dw_mci *host = slot->host; 175f95f3850SWill Newton struct dentry *root; 176f95f3850SWill Newton struct dentry *node; 177f95f3850SWill Newton 178f95f3850SWill Newton root = mmc->debugfs_root; 179f95f3850SWill Newton if (!root) 180f95f3850SWill Newton return; 181f95f3850SWill Newton 182f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 183f95f3850SWill Newton &dw_mci_regs_fops); 184f95f3850SWill Newton if (!node) 185f95f3850SWill Newton goto err; 186f95f3850SWill Newton 187f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 188f95f3850SWill Newton &dw_mci_req_fops); 189f95f3850SWill Newton if (!node) 190f95f3850SWill Newton goto err; 191f95f3850SWill Newton 192f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 193f95f3850SWill Newton if (!node) 194f95f3850SWill Newton goto err; 195f95f3850SWill Newton 196f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 197f95f3850SWill Newton (u32 *)&host->pending_events); 198f95f3850SWill Newton if (!node) 199f95f3850SWill Newton goto err; 200f95f3850SWill Newton 201f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 202f95f3850SWill Newton (u32 *)&host->completed_events); 203f95f3850SWill Newton if (!node) 204f95f3850SWill Newton goto err; 205f95f3850SWill Newton 206f95f3850SWill Newton return; 207f95f3850SWill Newton 208f95f3850SWill Newton err: 209f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 210f95f3850SWill Newton } 211f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 212f95f3850SWill Newton 2138e6db1f6SShawn Lin static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2148e6db1f6SShawn Lin { 2158e6db1f6SShawn Lin u32 ctrl; 2168e6db1f6SShawn Lin 2178e6db1f6SShawn Lin ctrl = mci_readl(host, CTRL); 2188e6db1f6SShawn Lin ctrl |= reset; 2198e6db1f6SShawn Lin mci_writel(host, CTRL, ctrl); 2208e6db1f6SShawn Lin 2218e6db1f6SShawn Lin /* wait till resets clear */ 2228e6db1f6SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 2238e6db1f6SShawn Lin !(ctrl & reset), 2248e6db1f6SShawn Lin 1, 500 * USEC_PER_MSEC)) { 2258e6db1f6SShawn Lin dev_err(host->dev, 2268e6db1f6SShawn Lin "Timeout resetting block (ctrl reset %#x)\n", 2278e6db1f6SShawn Lin ctrl & reset); 2288e6db1f6SShawn Lin return false; 2298e6db1f6SShawn Lin } 2308e6db1f6SShawn Lin 2318e6db1f6SShawn Lin return true; 2328e6db1f6SShawn Lin } 23301730558SDoug Anderson 2344dba18deSShawn Lin static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 2354dba18deSShawn Lin { 2364dba18deSShawn Lin u32 status; 2374dba18deSShawn Lin 2384dba18deSShawn Lin /* 2394dba18deSShawn Lin * Databook says that before issuing a new data transfer command 2404dba18deSShawn Lin * we need to check to see if the card is busy. Data transfer commands 2414dba18deSShawn Lin * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 2424dba18deSShawn Lin * 2434dba18deSShawn Lin * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 2444dba18deSShawn Lin * expected. 2454dba18deSShawn Lin */ 2464dba18deSShawn Lin if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 2474dba18deSShawn Lin !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 2484dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 2494dba18deSShawn Lin status, 2504dba18deSShawn Lin !(status & SDMMC_STATUS_BUSY), 2514dba18deSShawn Lin 10, 500 * USEC_PER_MSEC)) 2524dba18deSShawn Lin dev_err(host->dev, "Busy; trying anyway\n"); 2534dba18deSShawn Lin } 2544dba18deSShawn Lin } 2554dba18deSShawn Lin 2564dba18deSShawn Lin static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 2574dba18deSShawn Lin { 2584dba18deSShawn Lin struct dw_mci *host = slot->host; 2594dba18deSShawn Lin unsigned int cmd_status = 0; 2604dba18deSShawn Lin 2614dba18deSShawn Lin mci_writel(host, CMDARG, arg); 2624dba18deSShawn Lin wmb(); /* drain writebuffer */ 2634dba18deSShawn Lin dw_mci_wait_while_busy(host, cmd); 2644dba18deSShawn Lin mci_writel(host, CMD, SDMMC_CMD_START | cmd); 2654dba18deSShawn Lin 2664dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 2674dba18deSShawn Lin !(cmd_status & SDMMC_CMD_START), 2684dba18deSShawn Lin 1, 500 * USEC_PER_MSEC)) 2694dba18deSShawn Lin dev_err(&slot->mmc->class_dev, 2704dba18deSShawn Lin "Timeout sending command (cmd %#x arg %#x status %#x)\n", 2714dba18deSShawn Lin cmd, arg, cmd_status); 2724dba18deSShawn Lin } 2734dba18deSShawn Lin 274f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 275f95f3850SWill Newton { 276800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 27701730558SDoug Anderson struct dw_mci *host = slot->host; 278f95f3850SWill Newton u32 cmdr; 279f95f3850SWill Newton 2800e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 281f95f3850SWill Newton cmdr = cmd->opcode; 282f95f3850SWill Newton 28390c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 28490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 28590c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 28690c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 28790c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 288f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2894a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 290f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 291f95f3850SWill Newton 29201730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 29301730558SDoug Anderson u32 clk_en_a; 29401730558SDoug Anderson 29501730558SDoug Anderson /* Special bit makes CMD11 not die */ 29601730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 29701730558SDoug Anderson 29801730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 29901730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 30001730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 30101730558SDoug Anderson 30201730558SDoug Anderson /* 30301730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 30401730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 30501730558SDoug Anderson * since stopping the clock is a specific part of the UHS 30601730558SDoug Anderson * voltage change dance. 30701730558SDoug Anderson * 30801730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 30901730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 31001730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 31101730558SDoug Anderson * until the voltage change is all done. 31201730558SDoug Anderson */ 31301730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 31401730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 31501730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 31601730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 31701730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 31801730558SDoug Anderson } 31901730558SDoug Anderson 320f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 321f95f3850SWill Newton /* We expect a response, so set this bit */ 322f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 323f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 324f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 325f95f3850SWill Newton } 326f95f3850SWill Newton 327f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 328f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 329f95f3850SWill Newton 3300349c085SJaehoon Chung if (cmd->data) { 331f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 3320349c085SJaehoon Chung if (cmd->data->flags & MMC_DATA_WRITE) 333f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 334f95f3850SWill Newton } 335f95f3850SWill Newton 336aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 337aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 338800d78bfSThomas Abraham 339f95f3850SWill Newton return cmdr; 340f95f3850SWill Newton } 341f95f3850SWill Newton 34290c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 34390c2143aSSeungwon Jeon { 34490c2143aSSeungwon Jeon struct mmc_command *stop; 34590c2143aSSeungwon Jeon u32 cmdr; 34690c2143aSSeungwon Jeon 34790c2143aSSeungwon Jeon if (!cmd->data) 34890c2143aSSeungwon Jeon return 0; 34990c2143aSSeungwon Jeon 35090c2143aSSeungwon Jeon stop = &host->stop_abort; 35190c2143aSSeungwon Jeon cmdr = cmd->opcode; 35290c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 35390c2143aSSeungwon Jeon 35490c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 35590c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 35690c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3576c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3586c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3596c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 36090c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 36190c2143aSSeungwon Jeon stop->arg = 0; 36290c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 36390c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 36490c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 36590c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 36690c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 36790c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 36890c2143aSSeungwon Jeon } else { 36990c2143aSSeungwon Jeon return 0; 37090c2143aSSeungwon Jeon } 37190c2143aSSeungwon Jeon 37290c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 37390c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 37490c2143aSSeungwon Jeon 37542f989c0SJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 3768c005b40SJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 3778c005b40SJaehoon Chung 37890c2143aSSeungwon Jeon return cmdr; 37990c2143aSSeungwon Jeon } 38090c2143aSSeungwon Jeon 38103de1921SAddy Ke static inline void dw_mci_set_cto(struct dw_mci *host) 38203de1921SAddy Ke { 38303de1921SAddy Ke unsigned int cto_clks; 3844c2357f5SDouglas Anderson unsigned int cto_div; 38503de1921SAddy Ke unsigned int cto_ms; 3868892b705SDouglas Anderson unsigned long irqflags; 38703de1921SAddy Ke 38803de1921SAddy Ke cto_clks = mci_readl(host, TMOUT) & 0xff; 3894c2357f5SDouglas Anderson cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 3904c2357f5SDouglas Anderson if (cto_div == 0) 3914c2357f5SDouglas Anderson cto_div = 1; 392c7151602SEvgeniy Didin 393c7151602SEvgeniy Didin cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 394c7151602SEvgeniy Didin host->bus_hz); 39503de1921SAddy Ke 39603de1921SAddy Ke /* add a bit spare time */ 39703de1921SAddy Ke cto_ms += 10; 39803de1921SAddy Ke 3998892b705SDouglas Anderson /* 4008892b705SDouglas Anderson * The durations we're working with are fairly short so we have to be 4018892b705SDouglas Anderson * extra careful about synchronization here. Specifically in hardware a 4028892b705SDouglas Anderson * command timeout is _at most_ 5.1 ms, so that means we expect an 4038892b705SDouglas Anderson * interrupt (either command done or timeout) to come rather quickly 4048892b705SDouglas Anderson * after the mci_writel. ...but just in case we have a long interrupt 4058892b705SDouglas Anderson * latency let's add a bit of paranoia. 4068892b705SDouglas Anderson * 4078892b705SDouglas Anderson * In general we'll assume that at least an interrupt will be asserted 4088892b705SDouglas Anderson * in hardware by the time the cto_timer runs. ...and if it hasn't 4098892b705SDouglas Anderson * been asserted in hardware by that time then we'll assume it'll never 4108892b705SDouglas Anderson * come. 4118892b705SDouglas Anderson */ 4128892b705SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 4138892b705SDouglas Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 41403de1921SAddy Ke mod_timer(&host->cto_timer, 41503de1921SAddy Ke jiffies + msecs_to_jiffies(cto_ms) + 1); 4168892b705SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 41703de1921SAddy Ke } 41803de1921SAddy Ke 419f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 420f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 421f95f3850SWill Newton { 422f95f3850SWill Newton host->cmd = cmd; 4234a90920cSThomas Abraham dev_vdbg(host->dev, 424f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 425f95f3850SWill Newton cmd->arg, cmd_flags); 426f95f3850SWill Newton 427f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 4280e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 4290bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 430f95f3850SWill Newton 4318892b705SDouglas Anderson mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 4328892b705SDouglas Anderson 43303de1921SAddy Ke /* response expected command only */ 43403de1921SAddy Ke if (cmd_flags & SDMMC_CMD_RESP_EXP) 43503de1921SAddy Ke dw_mci_set_cto(host); 436f95f3850SWill Newton } 437f95f3850SWill Newton 43890c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 439f95f3850SWill Newton { 440e13c3c08SJaehoon Chung struct mmc_command *stop = &host->stop_abort; 4410e3a22c0SShawn Lin 44290c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 443f95f3850SWill Newton } 444f95f3850SWill Newton 445f95f3850SWill Newton /* DMA interface functions */ 446f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 447f95f3850SWill Newton { 44803e8cb53SJames Hogan if (host->using_dma) { 449f95f3850SWill Newton host->dma_ops->stop(host); 450f95f3850SWill Newton host->dma_ops->cleanup(host); 451aa50f259SSeungwon Jeon } 452aa50f259SSeungwon Jeon 453f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 454f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 455f95f3850SWill Newton } 456f95f3850SWill Newton 457f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 458f95f3850SWill Newton { 459f95f3850SWill Newton struct mmc_data *data = host->data; 460f95f3850SWill Newton 461a4cc7eb4SJaehoon Chung if (data && data->host_cookie == COOKIE_MAPPED) { 4624a90920cSThomas Abraham dma_unmap_sg(host->dev, 4639aa51408SSeungwon Jeon data->sg, 4649aa51408SSeungwon Jeon data->sg_len, 465feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 466a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 467a4cc7eb4SJaehoon Chung } 468f95f3850SWill Newton } 469f95f3850SWill Newton 4705ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4715ce9d961SSeungwon Jeon { 4725ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4735ce9d961SSeungwon Jeon /* Software reset of DMA */ 4745ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4755ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4765ce9d961SSeungwon Jeon } 4775ce9d961SSeungwon Jeon 478f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 479f95f3850SWill Newton { 480f95f3850SWill Newton u32 temp; 481f95f3850SWill Newton 482f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 483f95f3850SWill Newton temp = mci_readl(host, CTRL); 484f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 485f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 486f95f3850SWill Newton mci_writel(host, CTRL, temp); 487f95f3850SWill Newton 488f95f3850SWill Newton /* Stop the IDMAC running */ 489f95f3850SWill Newton temp = mci_readl(host, BMOD); 490a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4915ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 492f95f3850SWill Newton mci_writel(host, BMOD, temp); 493f95f3850SWill Newton } 494f95f3850SWill Newton 4953fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 496f95f3850SWill Newton { 4973fc7eaefSShawn Lin struct dw_mci *host = arg; 498f95f3850SWill Newton struct mmc_data *data = host->data; 499f95f3850SWill Newton 5004a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 501f95f3850SWill Newton 5023fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 5033fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 5043fc7eaefSShawn Lin /* Invalidate cache after read */ 50542f989c0SJaehoon Chung dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 5063fc7eaefSShawn Lin data->sg, 5073fc7eaefSShawn Lin data->sg_len, 5083fc7eaefSShawn Lin DMA_FROM_DEVICE); 5093fc7eaefSShawn Lin 510f95f3850SWill Newton host->dma_ops->cleanup(host); 511f95f3850SWill Newton 512f95f3850SWill Newton /* 513f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 514f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 515f95f3850SWill Newton */ 516f95f3850SWill Newton if (data) { 517f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 518f95f3850SWill Newton tasklet_schedule(&host->tasklet); 519f95f3850SWill Newton } 520f95f3850SWill Newton } 521f95f3850SWill Newton 522f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 523f95f3850SWill Newton { 524897b69e7SSeungwon Jeon int i; 525f95f3850SWill Newton 52669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 52769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 52869d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 529cc190d4cSShawn Lin host->ring_size = 530cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 53169d99fdcSPrabu Thangamuthu 53269d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 53369d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 53469d99fdcSPrabu Thangamuthu i++, p++) { 53569d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 53669d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 53769d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 53869d99fdcSPrabu Thangamuthu 53969d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 54069d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 54169d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 54269d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 54347b7de2fSEvgeniy Didin p->des0 = 0; 54469d99fdcSPrabu Thangamuthu p->des1 = 0; 54569d99fdcSPrabu Thangamuthu p->des2 = 0; 54669d99fdcSPrabu Thangamuthu p->des3 = 0; 54769d99fdcSPrabu Thangamuthu } 54869d99fdcSPrabu Thangamuthu 54969d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 55069d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 55169d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 55269d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 55369d99fdcSPrabu Thangamuthu 55469d99fdcSPrabu Thangamuthu } else { 55569d99fdcSPrabu Thangamuthu struct idmac_desc *p; 556f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 557cc190d4cSShawn Lin host->ring_size = 558cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 559f95f3850SWill Newton 560f95f3850SWill Newton /* Forward link the descriptor list */ 5610e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 5620e3a22c0SShawn Lin i < host->ring_size - 1; 5630e3a22c0SShawn Lin i++, p++) { 5646687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 5656687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 56647b7de2fSEvgeniy Didin p->des0 = 0; 5674b244724SZhangfei Gao p->des1 = 0; 5684b244724SZhangfei Gao } 569f95f3850SWill Newton 570f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 5716687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 5726687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 57369d99fdcSPrabu Thangamuthu } 574f95f3850SWill Newton 5755ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 576141a712aSSeungwon Jeon 57769d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 57869d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 57969d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 58069d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 58169d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 58269d99fdcSPrabu Thangamuthu 58369d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 58469d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 58569d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 58669d99fdcSPrabu Thangamuthu 58769d99fdcSPrabu Thangamuthu } else { 588f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 589fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 59069d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 59169d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 592f95f3850SWill Newton 593f95f3850SWill Newton /* Set the descriptor base address */ 594f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 59569d99fdcSPrabu Thangamuthu } 59669d99fdcSPrabu Thangamuthu 597f95f3850SWill Newton return 0; 598f95f3850SWill Newton } 599f95f3850SWill Newton 6003b2a067bSShawn Lin static inline int dw_mci_prepare_desc64(struct dw_mci *host, 6013b2a067bSShawn Lin struct mmc_data *data, 6023b2a067bSShawn Lin unsigned int sg_len) 6033b2a067bSShawn Lin { 6043b2a067bSShawn Lin unsigned int desc_len; 6053b2a067bSShawn Lin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 606b6d2d81cSShawn Lin u32 val; 6073b2a067bSShawn Lin int i; 6083b2a067bSShawn Lin 6093b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6103b2a067bSShawn Lin 6113b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6123b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6133b2a067bSShawn Lin 6143b2a067bSShawn Lin u64 mem_addr = sg_dma_address(&data->sg[i]); 6153b2a067bSShawn Lin 6163b2a067bSShawn Lin for ( ; length ; desc++) { 6173b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6183b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6193b2a067bSShawn Lin 6203b2a067bSShawn Lin length -= desc_len; 6213b2a067bSShawn Lin 6223b2a067bSShawn Lin /* 6233b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6243b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6253b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6263b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6273b2a067bSShawn Lin */ 628b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 629b6d2d81cSShawn Lin !(val & IDMAC_DES0_OWN), 630b6d2d81cSShawn Lin 10, 100 * USEC_PER_MSEC)) 6313b2a067bSShawn Lin goto err_own_bit; 6323b2a067bSShawn Lin 6333b2a067bSShawn Lin /* 6343b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6353b2a067bSShawn Lin * for this descriptor 6363b2a067bSShawn Lin */ 6373b2a067bSShawn Lin desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 6383b2a067bSShawn Lin IDMAC_DES0_CH; 6393b2a067bSShawn Lin 6403b2a067bSShawn Lin /* Buffer length */ 6413b2a067bSShawn Lin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 6423b2a067bSShawn Lin 6433b2a067bSShawn Lin /* Physical address to DMA to/from */ 6443b2a067bSShawn Lin desc->des4 = mem_addr & 0xffffffff; 6453b2a067bSShawn Lin desc->des5 = mem_addr >> 32; 6463b2a067bSShawn Lin 6473b2a067bSShawn Lin /* Update physical address for the next desc */ 6483b2a067bSShawn Lin mem_addr += desc_len; 6493b2a067bSShawn Lin 6503b2a067bSShawn Lin /* Save pointer to the last descriptor */ 6513b2a067bSShawn Lin desc_last = desc; 6523b2a067bSShawn Lin } 6533b2a067bSShawn Lin } 6543b2a067bSShawn Lin 6553b2a067bSShawn Lin /* Set first descriptor */ 6563b2a067bSShawn Lin desc_first->des0 |= IDMAC_DES0_FD; 6573b2a067bSShawn Lin 6583b2a067bSShawn Lin /* Set last descriptor */ 6593b2a067bSShawn Lin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 6603b2a067bSShawn Lin desc_last->des0 |= IDMAC_DES0_LD; 6613b2a067bSShawn Lin 6623b2a067bSShawn Lin return 0; 6633b2a067bSShawn Lin err_own_bit: 6643b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 66526be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 666cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 6673b2a067bSShawn Lin dw_mci_idmac_init(host); 6683b2a067bSShawn Lin return -EINVAL; 6693b2a067bSShawn Lin } 6703b2a067bSShawn Lin 6713b2a067bSShawn Lin 6723b2a067bSShawn Lin static inline int dw_mci_prepare_desc32(struct dw_mci *host, 6733b2a067bSShawn Lin struct mmc_data *data, 6743b2a067bSShawn Lin unsigned int sg_len) 6753b2a067bSShawn Lin { 6763b2a067bSShawn Lin unsigned int desc_len; 6773b2a067bSShawn Lin struct idmac_desc *desc_first, *desc_last, *desc; 678b6d2d81cSShawn Lin u32 val; 6793b2a067bSShawn Lin int i; 6803b2a067bSShawn Lin 6813b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6823b2a067bSShawn Lin 6833b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6843b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6853b2a067bSShawn Lin 6863b2a067bSShawn Lin u32 mem_addr = sg_dma_address(&data->sg[i]); 6873b2a067bSShawn Lin 6883b2a067bSShawn Lin for ( ; length ; desc++) { 6893b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6903b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6913b2a067bSShawn Lin 6923b2a067bSShawn Lin length -= desc_len; 6933b2a067bSShawn Lin 6943b2a067bSShawn Lin /* 6953b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6963b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6973b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6983b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6993b2a067bSShawn Lin */ 700b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 701b6d2d81cSShawn Lin IDMAC_OWN_CLR64(val), 702b6d2d81cSShawn Lin 10, 703b6d2d81cSShawn Lin 100 * USEC_PER_MSEC)) 7043b2a067bSShawn Lin goto err_own_bit; 7053b2a067bSShawn Lin 7063b2a067bSShawn Lin /* 7073b2a067bSShawn Lin * Set the OWN bit and disable interrupts 7083b2a067bSShawn Lin * for this descriptor 7093b2a067bSShawn Lin */ 7103b2a067bSShawn Lin desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 7113b2a067bSShawn Lin IDMAC_DES0_DIC | 7123b2a067bSShawn Lin IDMAC_DES0_CH); 7133b2a067bSShawn Lin 7143b2a067bSShawn Lin /* Buffer length */ 7153b2a067bSShawn Lin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 7163b2a067bSShawn Lin 7173b2a067bSShawn Lin /* Physical address to DMA to/from */ 7183b2a067bSShawn Lin desc->des2 = cpu_to_le32(mem_addr); 7193b2a067bSShawn Lin 7203b2a067bSShawn Lin /* Update physical address for the next desc */ 7213b2a067bSShawn Lin mem_addr += desc_len; 7223b2a067bSShawn Lin 7233b2a067bSShawn Lin /* Save pointer to the last descriptor */ 7243b2a067bSShawn Lin desc_last = desc; 7253b2a067bSShawn Lin } 7263b2a067bSShawn Lin } 7273b2a067bSShawn Lin 7283b2a067bSShawn Lin /* Set first descriptor */ 7293b2a067bSShawn Lin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 7303b2a067bSShawn Lin 7313b2a067bSShawn Lin /* Set last descriptor */ 7323b2a067bSShawn Lin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 7333b2a067bSShawn Lin IDMAC_DES0_DIC)); 7343b2a067bSShawn Lin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 7353b2a067bSShawn Lin 7363b2a067bSShawn Lin return 0; 7373b2a067bSShawn Lin err_own_bit: 7383b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 73926be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 740cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 7413b2a067bSShawn Lin dw_mci_idmac_init(host); 7423b2a067bSShawn Lin return -EINVAL; 7433b2a067bSShawn Lin } 7443b2a067bSShawn Lin 7453b2a067bSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 7463b2a067bSShawn Lin { 7473b2a067bSShawn Lin u32 temp; 7483b2a067bSShawn Lin int ret; 7493b2a067bSShawn Lin 7503b2a067bSShawn Lin if (host->dma_64bit_address == 1) 7513b2a067bSShawn Lin ret = dw_mci_prepare_desc64(host, host->data, sg_len); 7523b2a067bSShawn Lin else 7533b2a067bSShawn Lin ret = dw_mci_prepare_desc32(host, host->data, sg_len); 7543b2a067bSShawn Lin 7553b2a067bSShawn Lin if (ret) 7563b2a067bSShawn Lin goto out; 7573b2a067bSShawn Lin 7583b2a067bSShawn Lin /* drain writebuffer */ 7593b2a067bSShawn Lin wmb(); 7603b2a067bSShawn Lin 7613b2a067bSShawn Lin /* Make sure to reset DMA in case we did PIO before this */ 7623b2a067bSShawn Lin dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 7633b2a067bSShawn Lin dw_mci_idmac_reset(host); 7643b2a067bSShawn Lin 7653b2a067bSShawn Lin /* Select IDMAC interface */ 7663b2a067bSShawn Lin temp = mci_readl(host, CTRL); 7673b2a067bSShawn Lin temp |= SDMMC_CTRL_USE_IDMAC; 7683b2a067bSShawn Lin mci_writel(host, CTRL, temp); 7693b2a067bSShawn Lin 7703b2a067bSShawn Lin /* drain writebuffer */ 7713b2a067bSShawn Lin wmb(); 7723b2a067bSShawn Lin 7733b2a067bSShawn Lin /* Enable the IDMAC */ 7743b2a067bSShawn Lin temp = mci_readl(host, BMOD); 7753b2a067bSShawn Lin temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 7763b2a067bSShawn Lin mci_writel(host, BMOD, temp); 7773b2a067bSShawn Lin 7783b2a067bSShawn Lin /* Start it running */ 7793b2a067bSShawn Lin mci_writel(host, PLDMND, 1); 7803b2a067bSShawn Lin 7813b2a067bSShawn Lin out: 7823b2a067bSShawn Lin return ret; 7833b2a067bSShawn Lin } 7843b2a067bSShawn Lin 7858e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 786885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 787885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 788885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 7893fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 790885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 791885c3e80SSeungwon Jeon }; 7923fc7eaefSShawn Lin 7933fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 7943fc7eaefSShawn Lin { 795ab925a31SShawn Lin dmaengine_terminate_async(host->dms->ch); 7963fc7eaefSShawn Lin } 7973fc7eaefSShawn Lin 7983fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 7993fc7eaefSShawn Lin unsigned int sg_len) 8003fc7eaefSShawn Lin { 8013fc7eaefSShawn Lin struct dma_slave_config cfg; 8023fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 8033fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 80427d70d36SColin Ian King static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 8053fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 8063fc7eaefSShawn Lin u32 fifoth_val; 8073fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 8083fc7eaefSShawn Lin int ret = 0; 8093fc7eaefSShawn Lin 8103fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 811260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 8123fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 8133fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 8143fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 8153fc7eaefSShawn Lin 8163fc7eaefSShawn Lin /* Match burst msize with external dma config */ 8173fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 8183fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 8193fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 8203fc7eaefSShawn Lin 8213fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 8223fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 8233fc7eaefSShawn Lin else 8243fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 8253fc7eaefSShawn Lin 8263fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 8273fc7eaefSShawn Lin if (ret) { 8283fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 8293fc7eaefSShawn Lin return -EBUSY; 8303fc7eaefSShawn Lin } 8313fc7eaefSShawn Lin 8323fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 8333fc7eaefSShawn Lin sg_len, cfg.direction, 8343fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 8353fc7eaefSShawn Lin if (!desc) { 8363fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 8373fc7eaefSShawn Lin return -EBUSY; 8383fc7eaefSShawn Lin } 8393fc7eaefSShawn Lin 8403fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 8413fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 8423fc7eaefSShawn Lin desc->callback_param = (void *)host; 8433fc7eaefSShawn Lin dmaengine_submit(desc); 8443fc7eaefSShawn Lin 8453fc7eaefSShawn Lin /* Flush cache before write */ 8463fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 84742f989c0SJaehoon Chung dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 8483fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 8493fc7eaefSShawn Lin 8503fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 8513fc7eaefSShawn Lin 8523fc7eaefSShawn Lin return 0; 8533fc7eaefSShawn Lin } 8543fc7eaefSShawn Lin 8553fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 8563fc7eaefSShawn Lin { 8573fc7eaefSShawn Lin /* Request external dma channel */ 8583fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 8593fc7eaefSShawn Lin if (!host->dms) 8603fc7eaefSShawn Lin return -ENOMEM; 8613fc7eaefSShawn Lin 8623fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 8633fc7eaefSShawn Lin if (!host->dms->ch) { 8644539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 8653fc7eaefSShawn Lin kfree(host->dms); 8663fc7eaefSShawn Lin host->dms = NULL; 8673fc7eaefSShawn Lin return -ENXIO; 8683fc7eaefSShawn Lin } 8693fc7eaefSShawn Lin 8703fc7eaefSShawn Lin return 0; 8713fc7eaefSShawn Lin } 8723fc7eaefSShawn Lin 8733fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 8743fc7eaefSShawn Lin { 8753fc7eaefSShawn Lin if (host->dms) { 8763fc7eaefSShawn Lin if (host->dms->ch) { 8773fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 8783fc7eaefSShawn Lin host->dms->ch = NULL; 8793fc7eaefSShawn Lin } 8803fc7eaefSShawn Lin kfree(host->dms); 8813fc7eaefSShawn Lin host->dms = NULL; 8823fc7eaefSShawn Lin } 8833fc7eaefSShawn Lin } 8843fc7eaefSShawn Lin 8853fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 8863fc7eaefSShawn Lin .init = dw_mci_edmac_init, 8873fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 8883fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 8893fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 8903fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 8913fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 8923fc7eaefSShawn Lin }; 893885c3e80SSeungwon Jeon 8949aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 8959aa51408SSeungwon Jeon struct mmc_data *data, 896a4cc7eb4SJaehoon Chung int cookie) 897f95f3850SWill Newton { 898f95f3850SWill Newton struct scatterlist *sg; 8999aa51408SSeungwon Jeon unsigned int i, sg_len; 900f95f3850SWill Newton 901a4cc7eb4SJaehoon Chung if (data->host_cookie == COOKIE_PRE_MAPPED) 902a4cc7eb4SJaehoon Chung return data->sg_len; 903f95f3850SWill Newton 904f95f3850SWill Newton /* 905f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 906f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 907f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 908f95f3850SWill Newton */ 909f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 910f95f3850SWill Newton return -EINVAL; 9119aa51408SSeungwon Jeon 912f95f3850SWill Newton if (data->blksz & 3) 913f95f3850SWill Newton return -EINVAL; 914f95f3850SWill Newton 915f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 916f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 917f95f3850SWill Newton return -EINVAL; 918f95f3850SWill Newton } 919f95f3850SWill Newton 9204a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 9219aa51408SSeungwon Jeon data->sg, 9229aa51408SSeungwon Jeon data->sg_len, 923feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 9249aa51408SSeungwon Jeon if (sg_len == 0) 9259aa51408SSeungwon Jeon return -EINVAL; 9269aa51408SSeungwon Jeon 927a4cc7eb4SJaehoon Chung data->host_cookie = cookie; 9289aa51408SSeungwon Jeon 9299aa51408SSeungwon Jeon return sg_len; 9309aa51408SSeungwon Jeon } 9319aa51408SSeungwon Jeon 9329aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 933d3c6aac3SLinus Walleij struct mmc_request *mrq) 9349aa51408SSeungwon Jeon { 9359aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9369aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9379aa51408SSeungwon Jeon 9389aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9399aa51408SSeungwon Jeon return; 9409aa51408SSeungwon Jeon 941a4cc7eb4SJaehoon Chung /* This data might be unmapped at this time */ 942a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9439aa51408SSeungwon Jeon 944a4cc7eb4SJaehoon Chung if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 945a4cc7eb4SJaehoon Chung COOKIE_PRE_MAPPED) < 0) 946a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9479aa51408SSeungwon Jeon } 9489aa51408SSeungwon Jeon 9499aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 9509aa51408SSeungwon Jeon struct mmc_request *mrq, 9519aa51408SSeungwon Jeon int err) 9529aa51408SSeungwon Jeon { 9539aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9549aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9559aa51408SSeungwon Jeon 9569aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9579aa51408SSeungwon Jeon return; 9589aa51408SSeungwon Jeon 959a4cc7eb4SJaehoon Chung if (data->host_cookie != COOKIE_UNMAPPED) 9604a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 9619aa51408SSeungwon Jeon data->sg, 9629aa51408SSeungwon Jeon data->sg_len, 963feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 964a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9659aa51408SSeungwon Jeon } 9669aa51408SSeungwon Jeon 967671fa142SShawn Lin static int dw_mci_get_cd(struct mmc_host *mmc) 968671fa142SShawn Lin { 969671fa142SShawn Lin int present; 970671fa142SShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 971671fa142SShawn Lin struct dw_mci *host = slot->host; 972671fa142SShawn Lin int gpio_cd = mmc_gpio_get_cd(mmc); 973671fa142SShawn Lin 974671fa142SShawn Lin /* Use platform get_cd function, else try onboard card detect */ 975671fa142SShawn Lin if (((mmc->caps & MMC_CAP_NEEDS_POLL) 976671fa142SShawn Lin || !mmc_card_is_removable(mmc))) { 977671fa142SShawn Lin present = 1; 978671fa142SShawn Lin 979671fa142SShawn Lin if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 980671fa142SShawn Lin if (mmc->caps & MMC_CAP_NEEDS_POLL) { 981671fa142SShawn Lin dev_info(&mmc->class_dev, 982671fa142SShawn Lin "card is polling.\n"); 983671fa142SShawn Lin } else { 984671fa142SShawn Lin dev_info(&mmc->class_dev, 985671fa142SShawn Lin "card is non-removable.\n"); 986671fa142SShawn Lin } 987671fa142SShawn Lin set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 988671fa142SShawn Lin } 989671fa142SShawn Lin 990671fa142SShawn Lin return present; 991671fa142SShawn Lin } else if (gpio_cd >= 0) 992671fa142SShawn Lin present = gpio_cd; 993671fa142SShawn Lin else 994671fa142SShawn Lin present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 995671fa142SShawn Lin == 0 ? 1 : 0; 996671fa142SShawn Lin 997671fa142SShawn Lin spin_lock_bh(&host->lock); 998671fa142SShawn Lin if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 999671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is present\n"); 1000671fa142SShawn Lin else if (!present && 1001671fa142SShawn Lin !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 1002671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is not present\n"); 1003671fa142SShawn Lin spin_unlock_bh(&host->lock); 1004671fa142SShawn Lin 1005671fa142SShawn Lin return present; 1006671fa142SShawn Lin } 1007671fa142SShawn Lin 100852426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 100952426899SSeungwon Jeon { 101052426899SSeungwon Jeon unsigned int blksz = data->blksz; 101127d70d36SColin Ian King static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 101252426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 101352426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 101452426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 10150e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 101652426899SSeungwon Jeon 10173fc7eaefSShawn Lin /* pio should ship this scenario */ 10183fc7eaefSShawn Lin if (!host->use_dma) 10193fc7eaefSShawn Lin return; 10203fc7eaefSShawn Lin 102152426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 102252426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 102352426899SSeungwon Jeon 102452426899SSeungwon Jeon /* 102552426899SSeungwon Jeon * MSIZE is '1', 102652426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 102752426899SSeungwon Jeon */ 102820753569SShawn Lin if (blksz % fifo_width) 102952426899SSeungwon Jeon goto done; 103052426899SSeungwon Jeon 103152426899SSeungwon Jeon do { 103252426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 103352426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 103452426899SSeungwon Jeon msize = idx; 103552426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 103652426899SSeungwon Jeon break; 103752426899SSeungwon Jeon } 103852426899SSeungwon Jeon } while (--idx > 0); 103952426899SSeungwon Jeon /* 104052426899SSeungwon Jeon * If idx is '0', it won't be tried 104152426899SSeungwon Jeon * Thus, initial values are uesed 104252426899SSeungwon Jeon */ 104352426899SSeungwon Jeon done: 104452426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 104552426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 104652426899SSeungwon Jeon } 104752426899SSeungwon Jeon 10487e4bf1bcSJaehoon Chung static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1049f1d2736cSSeungwon Jeon { 1050f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 1051f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 1052f1d2736cSSeungwon Jeon u16 thld_size; 10537e4bf1bcSJaehoon Chung u8 enable; 1054f1d2736cSSeungwon Jeon 105566dfd101SJames Hogan /* 105666dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 105766dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 105866dfd101SJames Hogan */ 10597e4bf1bcSJaehoon Chung if (host->verid < DW_MMC_240A || 10607e4bf1bcSJaehoon Chung (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 106166dfd101SJames Hogan return; 106266dfd101SJames Hogan 10637e4bf1bcSJaehoon Chung /* 10647e4bf1bcSJaehoon Chung * Card write Threshold is introduced since 2.80a 10657e4bf1bcSJaehoon Chung * It's used when HS400 mode is enabled. 10667e4bf1bcSJaehoon Chung */ 10677e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE && 1068*7a6b9f4dSx00270170 host->timing != MMC_TIMING_MMC_HS400) 1069*7a6b9f4dSx00270170 goto disable; 10707e4bf1bcSJaehoon Chung 10717e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE) 10727e4bf1bcSJaehoon Chung enable = SDMMC_CARD_WR_THR_EN; 10737e4bf1bcSJaehoon Chung else 10747e4bf1bcSJaehoon Chung enable = SDMMC_CARD_RD_THR_EN; 10757e4bf1bcSJaehoon Chung 1076f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 1077*7a6b9f4dSx00270170 host->timing != MMC_TIMING_UHS_SDR104 && 1078*7a6b9f4dSx00270170 host->timing != MMC_TIMING_MMC_HS400) 1079f1d2736cSSeungwon Jeon goto disable; 1080f1d2736cSSeungwon Jeon 1081f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 1082f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 1083f1d2736cSSeungwon Jeon 1084f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 1085f1d2736cSSeungwon Jeon goto disable; 1086f1d2736cSSeungwon Jeon 1087f1d2736cSSeungwon Jeon /* 1088f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1089f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1090f1d2736cSSeungwon Jeon * Currently just choose blksz. 1091f1d2736cSSeungwon Jeon */ 1092f1d2736cSSeungwon Jeon thld_size = blksz; 10937e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1094f1d2736cSSeungwon Jeon return; 1095f1d2736cSSeungwon Jeon 1096f1d2736cSSeungwon Jeon disable: 10977e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, 0); 1098f1d2736cSSeungwon Jeon } 1099f1d2736cSSeungwon Jeon 11009aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 11019aa51408SSeungwon Jeon { 1102f8c58c11SDoug Anderson unsigned long irqflags; 11039aa51408SSeungwon Jeon int sg_len; 11049aa51408SSeungwon Jeon u32 temp; 11059aa51408SSeungwon Jeon 11069aa51408SSeungwon Jeon host->using_dma = 0; 11079aa51408SSeungwon Jeon 11089aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 11099aa51408SSeungwon Jeon if (!host->use_dma) 11109aa51408SSeungwon Jeon return -ENODEV; 11119aa51408SSeungwon Jeon 1112a4cc7eb4SJaehoon Chung sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1113a99aa9b9SSeungwon Jeon if (sg_len < 0) { 1114a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 11159aa51408SSeungwon Jeon return sg_len; 1116a99aa9b9SSeungwon Jeon } 11179aa51408SSeungwon Jeon 111803e8cb53SJames Hogan host->using_dma = 1; 111903e8cb53SJames Hogan 11203fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 11214a90920cSThomas Abraham dev_vdbg(host->dev, 1122f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 11233fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 11243fc7eaefSShawn Lin (unsigned long)host->sg_dma, 1125f95f3850SWill Newton sg_len); 1126f95f3850SWill Newton 112752426899SSeungwon Jeon /* 112852426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 112952426899SSeungwon Jeon * If current block size is same with previous size, 113052426899SSeungwon Jeon * no need to update fifoth. 113152426899SSeungwon Jeon */ 113252426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 113352426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 113452426899SSeungwon Jeon 1135f95f3850SWill Newton /* Enable the DMA interface */ 1136f95f3850SWill Newton temp = mci_readl(host, CTRL); 1137f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 1138f95f3850SWill Newton mci_writel(host, CTRL, temp); 1139f95f3850SWill Newton 1140f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 1141f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1142f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1143f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1144f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1145f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1146f95f3850SWill Newton 11473fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 1148647f80a1SJaehoon Chung host->dma_ops->stop(host); 1149d12d0cb1SShawn Lin /* We can't do DMA, try PIO for this one */ 1150d12d0cb1SShawn Lin dev_dbg(host->dev, 1151d12d0cb1SShawn Lin "%s: fall back to PIO mode for current transfer\n", 1152d12d0cb1SShawn Lin __func__); 11533fc7eaefSShawn Lin return -ENODEV; 11543fc7eaefSShawn Lin } 1155f95f3850SWill Newton 1156f95f3850SWill Newton return 0; 1157f95f3850SWill Newton } 1158f95f3850SWill Newton 1159f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1160f95f3850SWill Newton { 1161f8c58c11SDoug Anderson unsigned long irqflags; 11620e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1163f95f3850SWill Newton u32 temp; 1164f95f3850SWill Newton 1165f95f3850SWill Newton data->error = -EINPROGRESS; 1166f95f3850SWill Newton 1167f95f3850SWill Newton WARN_ON(host->data); 1168f95f3850SWill Newton host->sg = NULL; 1169f95f3850SWill Newton host->data = data; 1170f95f3850SWill Newton 11717e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_READ) 117255c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 11737e4bf1bcSJaehoon Chung else 117455c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 11757e4bf1bcSJaehoon Chung 11767e4bf1bcSJaehoon Chung dw_mci_ctrl_thld(host, data); 117755c5efbcSJames Hogan 1178f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1179f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1180f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1181f9c2a0dcSSeungwon Jeon else 1182f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1183f9c2a0dcSSeungwon Jeon 1184f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1185f95f3850SWill Newton host->sg = data->sg; 118634b664a2SJames Hogan host->part_buf_start = 0; 118734b664a2SJames Hogan host->part_buf_count = 0; 1188f95f3850SWill Newton 1189b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1190f8c58c11SDoug Anderson 1191f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1192f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1193f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1194f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1195f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1196f95f3850SWill Newton 1197f95f3850SWill Newton temp = mci_readl(host, CTRL); 1198f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1199f95f3850SWill Newton mci_writel(host, CTRL, temp); 120052426899SSeungwon Jeon 120152426899SSeungwon Jeon /* 1202d6fced83SJun Nie * Use the initial fifoth_val for PIO mode. If wm_algined 1203d6fced83SJun Nie * is set, we set watermark same as data size. 120452426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 120552426899SSeungwon Jeon * prev_blksz should be invalidated. 120652426899SSeungwon Jeon */ 1207d6fced83SJun Nie if (host->wm_aligned) 1208d6fced83SJun Nie dw_mci_adjust_fifoth(host, data); 1209d6fced83SJun Nie else 121052426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 121152426899SSeungwon Jeon host->prev_blksz = 0; 121252426899SSeungwon Jeon } else { 121352426899SSeungwon Jeon /* 121452426899SSeungwon Jeon * Keep the current block size. 121552426899SSeungwon Jeon * It will be used to decide whether to update 121652426899SSeungwon Jeon * fifoth register next time. 121752426899SSeungwon Jeon */ 121852426899SSeungwon Jeon host->prev_blksz = data->blksz; 1219f95f3850SWill Newton } 1220f95f3850SWill Newton } 1221f95f3850SWill Newton 1222ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1223f95f3850SWill Newton { 1224f95f3850SWill Newton struct dw_mci *host = slot->host; 1225fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1226f95f3850SWill Newton u32 div; 12279623b5b9SDoug Anderson u32 clk_en_a; 122801730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 122901730558SDoug Anderson 123001730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 123101730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 123201730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1233f95f3850SWill Newton 1234ff178981SShawn Lin slot->mmc->actual_clock = 0; 1235ff178981SShawn Lin 1236fdf492a1SDoug Anderson if (!clock) { 1237fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 123801730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1239fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1240fdf492a1SDoug Anderson div = host->bus_hz / clock; 1241fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1242f95f3850SWill Newton /* 1243f95f3850SWill Newton * move the + 1 after the divide to prevent 1244f95f3850SWill Newton * over-clocking the card. 1245f95f3850SWill Newton */ 1246e419990bSSeungwon Jeon div += 1; 1247e419990bSSeungwon Jeon 1248fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1249f95f3850SWill Newton 1250e6cd7a8eSJaehoon Chung if ((clock != slot->__clk_old && 1251e6cd7a8eSJaehoon Chung !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1252e6cd7a8eSJaehoon Chung force_clkinit) { 1253ce69e2feSShawn Lin /* Silent the verbose log if calling from PM context */ 1254ce69e2feSShawn Lin if (!force_clkinit) 1255f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1256fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1257fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1258fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1259fdf492a1SDoug Anderson host->bus_hz, div); 1260f95f3850SWill Newton 1261e6cd7a8eSJaehoon Chung /* 1262e6cd7a8eSJaehoon Chung * If card is polling, display the message only 1263e6cd7a8eSJaehoon Chung * one time at boot time. 1264e6cd7a8eSJaehoon Chung */ 1265e6cd7a8eSJaehoon Chung if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1266e6cd7a8eSJaehoon Chung slot->mmc->f_min == clock) 1267e6cd7a8eSJaehoon Chung set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1268e6cd7a8eSJaehoon Chung } 1269e6cd7a8eSJaehoon Chung 1270f95f3850SWill Newton /* disable clock */ 1271f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1272f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1273f95f3850SWill Newton 1274f95f3850SWill Newton /* inform CIU */ 127501730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1276f95f3850SWill Newton 1277f95f3850SWill Newton /* set clock to desired speed */ 1278f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1279f95f3850SWill Newton 1280f95f3850SWill Newton /* inform CIU */ 128101730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1282f95f3850SWill Newton 12839623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 12849623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1285b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 12869623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 12879623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1288f95f3850SWill Newton 1289f95f3850SWill Newton /* inform CIU */ 129001730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1291005d675aSJaehoon Chung 1292005d675aSJaehoon Chung /* keep the last clock value that was requested from core */ 1293005d675aSJaehoon Chung slot->__clk_old = clock; 1294ff178981SShawn Lin slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : 1295ff178981SShawn Lin host->bus_hz; 1296f95f3850SWill Newton } 1297f95f3850SWill Newton 1298fdf492a1SDoug Anderson host->current_speed = clock; 1299fdf492a1SDoug Anderson 1300f95f3850SWill Newton /* Set the current slot bus width */ 13011d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1302f95f3850SWill Newton } 1303f95f3850SWill Newton 1304053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1305053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1306053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1307f95f3850SWill Newton { 1308f95f3850SWill Newton struct mmc_request *mrq; 1309f95f3850SWill Newton struct mmc_data *data; 1310f95f3850SWill Newton u32 cmdflags; 1311f95f3850SWill Newton 1312f95f3850SWill Newton mrq = slot->mrq; 1313f95f3850SWill Newton 1314f95f3850SWill Newton host->mrq = mrq; 1315f95f3850SWill Newton 1316f95f3850SWill Newton host->pending_events = 0; 1317f95f3850SWill Newton host->completed_events = 0; 1318e352c813SSeungwon Jeon host->cmd_status = 0; 1319f95f3850SWill Newton host->data_status = 0; 1320e352c813SSeungwon Jeon host->dir_status = 0; 1321f95f3850SWill Newton 1322053b3ce6SSeungwon Jeon data = cmd->data; 1323f95f3850SWill Newton if (data) { 1324f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1325f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1326f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1327f95f3850SWill Newton } 1328f95f3850SWill Newton 1329f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1330f95f3850SWill Newton 1331f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1332f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1333f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1334f95f3850SWill Newton 1335f95f3850SWill Newton if (data) { 1336f95f3850SWill Newton dw_mci_submit_data(host, data); 13370e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1338f95f3850SWill Newton } 1339f95f3850SWill Newton 1340f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1341f95f3850SWill Newton 13425c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 134349ba0302SDoug Anderson unsigned long irqflags; 134449ba0302SDoug Anderson 13455c935165SDoug Anderson /* 13468886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 13478886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 13488886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 13498886a6fdSDoug Anderson * is just about to roll over. 135049ba0302SDoug Anderson * 135149ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 135249ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 135349ba0302SDoug Anderson * already ran so we don't want the timeout). 13545c935165SDoug Anderson */ 135549ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 135649ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 13575c935165SDoug Anderson mod_timer(&host->cmd11_timer, 13588886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 135949ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13605c935165SDoug Anderson } 13615c935165SDoug Anderson 136290c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1363f95f3850SWill Newton } 1364f95f3850SWill Newton 1365053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1366053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1367053b3ce6SSeungwon Jeon { 1368053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1369053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1370053b3ce6SSeungwon Jeon 1371053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1372053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1373053b3ce6SSeungwon Jeon } 1374053b3ce6SSeungwon Jeon 13757456caaeSJames Hogan /* must be called with host->lock held */ 1376f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1377f95f3850SWill Newton struct mmc_request *mrq) 1378f95f3850SWill Newton { 1379f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1380f95f3850SWill Newton host->state); 1381f95f3850SWill Newton 1382f95f3850SWill Newton slot->mrq = mrq; 1383f95f3850SWill Newton 138401730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 138501730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 138601730558SDoug Anderson "Voltage change didn't complete\n"); 138701730558SDoug Anderson /* 138801730558SDoug Anderson * this case isn't expected to happen, so we can 138901730558SDoug Anderson * either crash here or just try to continue on 139001730558SDoug Anderson * in the closest possible state 139101730558SDoug Anderson */ 139201730558SDoug Anderson host->state = STATE_IDLE; 139301730558SDoug Anderson } 139401730558SDoug Anderson 1395f95f3850SWill Newton if (host->state == STATE_IDLE) { 1396f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1397f95f3850SWill Newton dw_mci_start_request(host, slot); 1398f95f3850SWill Newton } else { 1399f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1400f95f3850SWill Newton } 1401f95f3850SWill Newton } 1402f95f3850SWill Newton 1403f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1404f95f3850SWill Newton { 1405f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1406f95f3850SWill Newton struct dw_mci *host = slot->host; 1407f95f3850SWill Newton 1408f95f3850SWill Newton WARN_ON(slot->mrq); 1409f95f3850SWill Newton 14107456caaeSJames Hogan /* 14117456caaeSJames Hogan * The check for card presence and queueing of the request must be 14127456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 14137456caaeSJames Hogan * request wouldn't fail until another card was inserted. 14147456caaeSJames Hogan */ 14157456caaeSJames Hogan 141656f6911cSShawn Lin if (!dw_mci_get_cd(mmc)) { 1417f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1418f95f3850SWill Newton mmc_request_done(mmc, mrq); 1419f95f3850SWill Newton return; 1420f95f3850SWill Newton } 1421f95f3850SWill Newton 142256f6911cSShawn Lin spin_lock_bh(&host->lock); 142356f6911cSShawn Lin 1424f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 14257456caaeSJames Hogan 14267456caaeSJames Hogan spin_unlock_bh(&host->lock); 1427f95f3850SWill Newton } 1428f95f3850SWill Newton 1429f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1430f95f3850SWill Newton { 1431f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1432e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 143341babf75SJaehoon Chung u32 regs; 143451da2240SYuvaraj CD int ret; 1435f95f3850SWill Newton 1436f95f3850SWill Newton switch (ios->bus_width) { 1437f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1438f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1439f95f3850SWill Newton break; 1440c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1441c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1442c9b2a06fSJaehoon Chung break; 1443b2f7cb45SJaehoon Chung default: 1444b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1445b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1446f95f3850SWill Newton } 1447f95f3850SWill Newton 144841babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 14493f514291SSeungwon Jeon 14503f514291SSeungwon Jeon /* DDR mode set */ 145180113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 14527cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 145380113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1454c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 14553f514291SSeungwon Jeon else 1456c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 14573f514291SSeungwon Jeon 145841babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1459f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 146041babf75SJaehoon Chung 1461f95f3850SWill Newton /* 1462f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1463f95f3850SWill Newton * core ios update when finding the minimum. 1464f95f3850SWill Newton */ 1465f95f3850SWill Newton slot->clock = ios->clock; 1466f95f3850SWill Newton 1467cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1468cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1469800d78bfSThomas Abraham 1470f95f3850SWill Newton switch (ios->power_mode) { 1471f95f3850SWill Newton case MMC_POWER_UP: 147251da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 147351da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 147451da2240SYuvaraj CD ios->vdd); 147551da2240SYuvaraj CD if (ret) { 147651da2240SYuvaraj CD dev_err(slot->host->dev, 147751da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 147851da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 147951da2240SYuvaraj CD return; 148051da2240SYuvaraj CD } 148151da2240SYuvaraj CD } 148229d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 148329d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 148429d0d161SDoug Anderson regs |= (1 << slot->id); 148529d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 148629d0d161SDoug Anderson break; 148729d0d161SDoug Anderson case MMC_POWER_ON: 1488d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1489d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 149051da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 149151da2240SYuvaraj CD if (ret < 0) 149251da2240SYuvaraj CD dev_err(slot->host->dev, 1493d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 149451da2240SYuvaraj CD else 149551da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1496d1f1dd86SDoug Anderson 1497d1f1dd86SDoug Anderson } else { 1498d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1499d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1500d1f1dd86SDoug Anderson } 1501d1f1dd86SDoug Anderson 1502d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1503d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1504d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 150551da2240SYuvaraj CD } 1506655babbdSDoug Anderson 1507655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1508655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1509655babbdSDoug Anderson 1510e6f34e2fSJames Hogan break; 1511e6f34e2fSJames Hogan case MMC_POWER_OFF: 1512655babbdSDoug Anderson /* Turn clock off before power goes down */ 1513655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1514655babbdSDoug Anderson 151551da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 151651da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 151751da2240SYuvaraj CD 1518d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 151951da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 152051da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 152151da2240SYuvaraj CD 15224366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 15234366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 15244366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1525f95f3850SWill Newton break; 1526f95f3850SWill Newton default: 1527f95f3850SWill Newton break; 1528f95f3850SWill Newton } 1529655babbdSDoug Anderson 1530655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1531655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1532f95f3850SWill Newton } 1533f95f3850SWill Newton 153401730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 153501730558SDoug Anderson { 153601730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 153701730558SDoug Anderson u32 status; 153801730558SDoug Anderson 153901730558SDoug Anderson /* 154001730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 154101730558SDoug Anderson * (the data lines) are 0000 154201730558SDoug Anderson */ 154301730558SDoug Anderson status = mci_readl(slot->host, STATUS); 154401730558SDoug Anderson 154501730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 154601730558SDoug Anderson } 154701730558SDoug Anderson 154801730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 154901730558SDoug Anderson { 155001730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 155101730558SDoug Anderson struct dw_mci *host = slot->host; 15528f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 155301730558SDoug Anderson u32 uhs; 155401730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 155501730558SDoug Anderson int ret; 155601730558SDoug Anderson 15578f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 15588f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 15598f7849c4SZhangfei Gao 156001730558SDoug Anderson /* 156101730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 156201730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 156301730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 156401730558SDoug Anderson */ 156501730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1566e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 156701730558SDoug Anderson uhs &= ~v18; 1568e0848f5dSDouglas Anderson else 156901730558SDoug Anderson uhs |= v18; 1570e0848f5dSDouglas Anderson 157101730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1572e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 157301730558SDoug Anderson 157401730558SDoug Anderson if (ret) { 1575b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1576e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1577e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 157801730558SDoug Anderson return ret; 157901730558SDoug Anderson } 158001730558SDoug Anderson } 158101730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 158201730558SDoug Anderson 158301730558SDoug Anderson return 0; 158401730558SDoug Anderson } 158501730558SDoug Anderson 1586f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1587f95f3850SWill Newton { 1588f95f3850SWill Newton int read_only; 1589f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 15909795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1591f95f3850SWill Newton 1592f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1593287980e4SArnd Bergmann if (gpio_ro >= 0) 15949795a846SJaehoon Chung read_only = gpio_ro; 1595f95f3850SWill Newton else 1596f95f3850SWill Newton read_only = 1597f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1598f95f3850SWill Newton 1599f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1600f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1601f95f3850SWill Newton 1602f95f3850SWill Newton return read_only; 1603f95f3850SWill Newton } 1604f95f3850SWill Newton 1605935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1606935a665eSShawn Lin { 1607935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1608935a665eSShawn Lin struct dw_mci *host = slot->host; 1609935a665eSShawn Lin int reset; 1610935a665eSShawn Lin 1611935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1612935a665eSShawn Lin dw_mci_idmac_reset(host); 1613935a665eSShawn Lin 1614935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1615935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1616935a665eSShawn Lin return; 1617935a665eSShawn Lin 1618935a665eSShawn Lin /* 1619935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1620935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1621935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1622935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1623935a665eSShawn Lin */ 1624935a665eSShawn Lin reset = mci_readl(host, RST_N); 1625935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1626935a665eSShawn Lin mci_writel(host, RST_N, reset); 1627935a665eSShawn Lin usleep_range(1, 2); 1628935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1629935a665eSShawn Lin mci_writel(host, RST_N, reset); 1630935a665eSShawn Lin usleep_range(200, 300); 1631935a665eSShawn Lin } 1632935a665eSShawn Lin 1633b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1634b24c8b26SDoug Anderson { 1635b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1636b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1637b24c8b26SDoug Anderson 16389623b5b9SDoug Anderson /* 16399623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 16409623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 16419623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 16429623b5b9SDoug Anderson */ 1643b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 16449623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1645b24c8b26SDoug Anderson u32 clk_en_a_old; 1646b24c8b26SDoug Anderson u32 clk_en_a; 16479623b5b9SDoug Anderson 1648b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 16499623b5b9SDoug Anderson 1650b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1651b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1652b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1653b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1654b24c8b26SDoug Anderson } else { 1655b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1656b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1657b24c8b26SDoug Anderson } 1658b24c8b26SDoug Anderson 1659b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1660b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 16619623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 16629623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 16639623b5b9SDoug Anderson } 16649623b5b9SDoug Anderson } 1665b24c8b26SDoug Anderson } 16669623b5b9SDoug Anderson 166732dba737SUlf Hansson static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 16681a5c8e1fSShashidhar Hiremath { 16691a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1670f8c58c11SDoug Anderson unsigned long irqflags; 16711a5c8e1fSShashidhar Hiremath u32 int_mask; 16721a5c8e1fSShashidhar Hiremath 1673f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1674f8c58c11SDoug Anderson 16751a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 16761a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1677b24c8b26SDoug Anderson if (enb) 1678b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1679b24c8b26SDoug Anderson else 1680b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1681b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1682f8c58c11SDoug Anderson 1683f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 16841a5c8e1fSShashidhar Hiremath } 16851a5c8e1fSShashidhar Hiremath 168632dba737SUlf Hansson static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 168732dba737SUlf Hansson { 168832dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 1689ca8971caSUlf Hansson struct dw_mci *host = slot->host; 169032dba737SUlf Hansson 169132dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, enb); 1692ca8971caSUlf Hansson 1693ca8971caSUlf Hansson /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1694ca8971caSUlf Hansson if (enb) 1695ca8971caSUlf Hansson pm_runtime_get_noresume(host->dev); 1696ca8971caSUlf Hansson else 1697ca8971caSUlf Hansson pm_runtime_put_noidle(host->dev); 169832dba737SUlf Hansson } 169932dba737SUlf Hansson 170032dba737SUlf Hansson static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 170132dba737SUlf Hansson { 170232dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 170332dba737SUlf Hansson 170432dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 1); 170532dba737SUlf Hansson } 170632dba737SUlf Hansson 17070976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 17080976f16dSSeungwon Jeon { 17090976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 17100976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 17110976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 17120e3a22c0SShawn Lin int err = -EINVAL; 17130976f16dSSeungwon Jeon 17140976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 17159979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 17160976f16dSSeungwon Jeon return err; 17170976f16dSSeungwon Jeon } 17180976f16dSSeungwon Jeon 17190e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 17200e3a22c0SShawn Lin struct mmc_ios *ios) 172180113132SSeungwon Jeon { 172280113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 172380113132SSeungwon Jeon struct dw_mci *host = slot->host; 172480113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 172580113132SSeungwon Jeon 172680113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 172780113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 172880113132SSeungwon Jeon 172980113132SSeungwon Jeon return 0; 173080113132SSeungwon Jeon } 173180113132SSeungwon Jeon 17324e7392b2SShawn Lin static bool dw_mci_reset(struct dw_mci *host) 17334e7392b2SShawn Lin { 17344e7392b2SShawn Lin u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 17354e7392b2SShawn Lin bool ret = false; 1736bc2dcc1aSShawn Lin u32 status = 0; 17374e7392b2SShawn Lin 17384e7392b2SShawn Lin /* 17394e7392b2SShawn Lin * Resetting generates a block interrupt, hence setting 17404e7392b2SShawn Lin * the scatter-gather pointer to NULL. 17414e7392b2SShawn Lin */ 17424e7392b2SShawn Lin if (host->sg) { 17434e7392b2SShawn Lin sg_miter_stop(&host->sg_miter); 17444e7392b2SShawn Lin host->sg = NULL; 17454e7392b2SShawn Lin } 17464e7392b2SShawn Lin 17474e7392b2SShawn Lin if (host->use_dma) 17484e7392b2SShawn Lin flags |= SDMMC_CTRL_DMA_RESET; 17494e7392b2SShawn Lin 17504e7392b2SShawn Lin if (dw_mci_ctrl_reset(host, flags)) { 17514e7392b2SShawn Lin /* 1752bc2dcc1aSShawn Lin * In all cases we clear the RAWINTS 1753bc2dcc1aSShawn Lin * register to clear any interrupts. 17544e7392b2SShawn Lin */ 17554e7392b2SShawn Lin mci_writel(host, RINTSTS, 0xFFFFFFFF); 17564e7392b2SShawn Lin 1757bc2dcc1aSShawn Lin if (!host->use_dma) { 1758bc2dcc1aSShawn Lin ret = true; 1759bc2dcc1aSShawn Lin goto ciu_out; 1760bc2dcc1aSShawn Lin } 17614e7392b2SShawn Lin 1762bc2dcc1aSShawn Lin /* Wait for dma_req to be cleared */ 17634e7392b2SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 17644e7392b2SShawn Lin status, 17654e7392b2SShawn Lin !(status & SDMMC_STATUS_DMA_REQ), 17664e7392b2SShawn Lin 1, 500 * USEC_PER_MSEC)) { 17674e7392b2SShawn Lin dev_err(host->dev, 1768bc2dcc1aSShawn Lin "%s: Timeout waiting for dma_req to be cleared\n", 17694e7392b2SShawn Lin __func__); 17704e7392b2SShawn Lin goto ciu_out; 17714e7392b2SShawn Lin } 17724e7392b2SShawn Lin 17734e7392b2SShawn Lin /* when using DMA next we reset the fifo again */ 17744e7392b2SShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 17754e7392b2SShawn Lin goto ciu_out; 17764e7392b2SShawn Lin } else { 17774e7392b2SShawn Lin /* if the controller reset bit did clear, then set clock regs */ 17784e7392b2SShawn Lin if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 17794e7392b2SShawn Lin dev_err(host->dev, 17804e7392b2SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 17814e7392b2SShawn Lin __func__); 17824e7392b2SShawn Lin goto ciu_out; 17834e7392b2SShawn Lin } 17844e7392b2SShawn Lin } 17854e7392b2SShawn Lin 17864e7392b2SShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 178747b7de2fSEvgeniy Didin /* It is also required that we reinit idmac */ 178847b7de2fSEvgeniy Didin dw_mci_idmac_init(host); 17894e7392b2SShawn Lin 17904e7392b2SShawn Lin ret = true; 17914e7392b2SShawn Lin 17924e7392b2SShawn Lin ciu_out: 17934e7392b2SShawn Lin /* After a CTRL reset we need to have CIU set clock registers */ 179442f989c0SJaehoon Chung mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 17954e7392b2SShawn Lin 17964e7392b2SShawn Lin return ret; 17974e7392b2SShawn Lin } 17984e7392b2SShawn Lin 1799f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1800f95f3850SWill Newton .request = dw_mci_request, 18019aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 18029aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1803f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1804f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1805f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1806935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 18071a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 180832dba737SUlf Hansson .ack_sdio_irq = dw_mci_ack_sdio_irq, 18090976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 181001730558SDoug Anderson .card_busy = dw_mci_card_busy, 181101730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1812b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 181380113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1814f95f3850SWill Newton }; 1815f95f3850SWill Newton 1816f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1817f95f3850SWill Newton __releases(&host->lock) 1818f95f3850SWill Newton __acquires(&host->lock) 1819f95f3850SWill Newton { 1820f95f3850SWill Newton struct dw_mci_slot *slot; 182142f989c0SJaehoon Chung struct mmc_host *prev_mmc = host->slot->mmc; 1822f95f3850SWill Newton 1823f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1824f95f3850SWill Newton 182542f989c0SJaehoon Chung host->slot->mrq = NULL; 1826f95f3850SWill Newton host->mrq = NULL; 1827f95f3850SWill Newton if (!list_empty(&host->queue)) { 1828f95f3850SWill Newton slot = list_entry(host->queue.next, 1829f95f3850SWill Newton struct dw_mci_slot, queue_node); 1830f95f3850SWill Newton list_del(&slot->queue_node); 18314a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1832f95f3850SWill Newton mmc_hostname(slot->mmc)); 1833f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1834f95f3850SWill Newton dw_mci_start_request(host, slot); 1835f95f3850SWill Newton } else { 18364a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 183701730558SDoug Anderson 183801730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 183901730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 184001730558SDoug Anderson else 1841f95f3850SWill Newton host->state = STATE_IDLE; 1842f95f3850SWill Newton } 1843f95f3850SWill Newton 1844f95f3850SWill Newton spin_unlock(&host->lock); 1845f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1846f95f3850SWill Newton spin_lock(&host->lock); 1847f95f3850SWill Newton } 1848f95f3850SWill Newton 1849e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1850f95f3850SWill Newton { 1851f95f3850SWill Newton u32 status = host->cmd_status; 1852f95f3850SWill Newton 1853f95f3850SWill Newton host->cmd_status = 0; 1854f95f3850SWill Newton 1855f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1856f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1857f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1858f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1859f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1860f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1861f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1862f95f3850SWill Newton } else { 1863f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1864f95f3850SWill Newton cmd->resp[1] = 0; 1865f95f3850SWill Newton cmd->resp[2] = 0; 1866f95f3850SWill Newton cmd->resp[3] = 0; 1867f95f3850SWill Newton } 1868f95f3850SWill Newton } 1869f95f3850SWill Newton 1870f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1871f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1872f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1873f95f3850SWill Newton cmd->error = -EILSEQ; 1874f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1875f95f3850SWill Newton cmd->error = -EIO; 1876f95f3850SWill Newton else 1877f95f3850SWill Newton cmd->error = 0; 1878f95f3850SWill Newton 1879e352c813SSeungwon Jeon return cmd->error; 1880e352c813SSeungwon Jeon } 1881e352c813SSeungwon Jeon 1882e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1883e352c813SSeungwon Jeon { 188431bff450SSeungwon Jeon u32 status = host->data_status; 1885e352c813SSeungwon Jeon 1886e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1887e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1888e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1889e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1890e352c813SSeungwon Jeon data->error = -EILSEQ; 1891e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1892e352c813SSeungwon Jeon if (host->dir_status == 1893e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1894e352c813SSeungwon Jeon /* 1895e352c813SSeungwon Jeon * No data CRC status was returned. 1896e352c813SSeungwon Jeon * The number of bytes transferred 1897e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1898e352c813SSeungwon Jeon */ 1899e352c813SSeungwon Jeon data->bytes_xfered = 0; 1900e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1901e352c813SSeungwon Jeon } else if (host->dir_status == 1902e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1903e7a1dec1SShawn Lin data->error = -EILSEQ; 1904e352c813SSeungwon Jeon } 1905e352c813SSeungwon Jeon } else { 1906e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1907e7a1dec1SShawn Lin data->error = -EILSEQ; 1908e352c813SSeungwon Jeon } 1909e352c813SSeungwon Jeon 1910e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1911e352c813SSeungwon Jeon 1912e352c813SSeungwon Jeon /* 1913e352c813SSeungwon Jeon * After an error, there may be data lingering 191431bff450SSeungwon Jeon * in the FIFO 1915e352c813SSeungwon Jeon */ 19163a33a94cSSonny Rao dw_mci_reset(host); 1917e352c813SSeungwon Jeon } else { 1918e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1919e352c813SSeungwon Jeon data->error = 0; 1920e352c813SSeungwon Jeon } 1921e352c813SSeungwon Jeon 1922e352c813SSeungwon Jeon return data->error; 1923f95f3850SWill Newton } 1924f95f3850SWill Newton 192557e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 192657e10486SAddy Ke { 192757e10486SAddy Ke unsigned int drto_clks; 19289d9491a7SDouglas Anderson unsigned int drto_div; 192957e10486SAddy Ke unsigned int drto_ms; 193093c23ae3SDouglas Anderson unsigned long irqflags; 193157e10486SAddy Ke 193257e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 19339d9491a7SDouglas Anderson drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 19349d9491a7SDouglas Anderson if (drto_div == 0) 19359d9491a7SDouglas Anderson drto_div = 1; 1936c7151602SEvgeniy Didin 1937c7151602SEvgeniy Didin drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 19389d9491a7SDouglas Anderson host->bus_hz); 193957e10486SAddy Ke 194057e10486SAddy Ke /* add a bit spare time */ 194157e10486SAddy Ke drto_ms += 10; 194257e10486SAddy Ke 194393c23ae3SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 194493c23ae3SDouglas Anderson if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 194593c23ae3SDouglas Anderson mod_timer(&host->dto_timer, 194693c23ae3SDouglas Anderson jiffies + msecs_to_jiffies(drto_ms)); 194793c23ae3SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 194857e10486SAddy Ke } 194957e10486SAddy Ke 19508892b705SDouglas Anderson static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 19518892b705SDouglas Anderson { 19528892b705SDouglas Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 19538892b705SDouglas Anderson return false; 19548892b705SDouglas Anderson 19558892b705SDouglas Anderson /* 19568892b705SDouglas Anderson * Really be certain that the timer has stopped. This is a bit of 19578892b705SDouglas Anderson * paranoia and could only really happen if we had really bad 19588892b705SDouglas Anderson * interrupt latency and the interrupt routine and timeout were 19598892b705SDouglas Anderson * running concurrently so that the del_timer() in the interrupt 19608892b705SDouglas Anderson * handler couldn't run. 19618892b705SDouglas Anderson */ 19628892b705SDouglas Anderson WARN_ON(del_timer_sync(&host->cto_timer)); 19638892b705SDouglas Anderson clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 19648892b705SDouglas Anderson 19658892b705SDouglas Anderson return true; 19668892b705SDouglas Anderson } 19678892b705SDouglas Anderson 196893c23ae3SDouglas Anderson static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 196993c23ae3SDouglas Anderson { 197093c23ae3SDouglas Anderson if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 197193c23ae3SDouglas Anderson return false; 197293c23ae3SDouglas Anderson 197393c23ae3SDouglas Anderson /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 197493c23ae3SDouglas Anderson WARN_ON(del_timer_sync(&host->dto_timer)); 197593c23ae3SDouglas Anderson clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 197693c23ae3SDouglas Anderson 197793c23ae3SDouglas Anderson return true; 197893c23ae3SDouglas Anderson } 197993c23ae3SDouglas Anderson 1980f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1981f95f3850SWill Newton { 1982f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1983f95f3850SWill Newton struct mmc_data *data; 1984f95f3850SWill Newton struct mmc_command *cmd; 1985e352c813SSeungwon Jeon struct mmc_request *mrq; 1986f95f3850SWill Newton enum dw_mci_state state; 1987f95f3850SWill Newton enum dw_mci_state prev_state; 1988e352c813SSeungwon Jeon unsigned int err; 1989f95f3850SWill Newton 1990f95f3850SWill Newton spin_lock(&host->lock); 1991f95f3850SWill Newton 1992f95f3850SWill Newton state = host->state; 1993f95f3850SWill Newton data = host->data; 1994e352c813SSeungwon Jeon mrq = host->mrq; 1995f95f3850SWill Newton 1996f95f3850SWill Newton do { 1997f95f3850SWill Newton prev_state = state; 1998f95f3850SWill Newton 1999f95f3850SWill Newton switch (state) { 2000f95f3850SWill Newton case STATE_IDLE: 200101730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 2002f95f3850SWill Newton break; 2003f95f3850SWill Newton 200401730558SDoug Anderson case STATE_SENDING_CMD11: 2005f95f3850SWill Newton case STATE_SENDING_CMD: 20068892b705SDouglas Anderson if (!dw_mci_clear_pending_cmd_complete(host)) 2007f95f3850SWill Newton break; 2008f95f3850SWill Newton 2009f95f3850SWill Newton cmd = host->cmd; 2010f95f3850SWill Newton host->cmd = NULL; 2011f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 2012e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 2013e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 201442f989c0SJaehoon Chung __dw_mci_start_request(host, host->slot, 2015e352c813SSeungwon Jeon mrq->cmd); 2016053b3ce6SSeungwon Jeon goto unlock; 2017053b3ce6SSeungwon Jeon } 2018053b3ce6SSeungwon Jeon 2019e352c813SSeungwon Jeon if (cmd->data && err) { 202046d17952SDoug Anderson /* 202146d17952SDoug Anderson * During UHS tuning sequence, sending the stop 202246d17952SDoug Anderson * command after the response CRC error would 202346d17952SDoug Anderson * throw the system into a confused state 202446d17952SDoug Anderson * causing all future tuning phases to report 202546d17952SDoug Anderson * failure. 202646d17952SDoug Anderson * 202746d17952SDoug Anderson * In such case controller will move into a data 202846d17952SDoug Anderson * transfer state after a response error or 202946d17952SDoug Anderson * response CRC error. Let's let that finish 203046d17952SDoug Anderson * before trying to send a stop, so we'll go to 203146d17952SDoug Anderson * STATE_SENDING_DATA. 203246d17952SDoug Anderson * 203346d17952SDoug Anderson * Although letting the data transfer take place 203446d17952SDoug Anderson * will waste a bit of time (we already know 203546d17952SDoug Anderson * the command was bad), it can't cause any 203646d17952SDoug Anderson * errors since it's possible it would have 203746d17952SDoug Anderson * taken place anyway if this tasklet got 203846d17952SDoug Anderson * delayed. Allowing the transfer to take place 203946d17952SDoug Anderson * avoids races and keeps things simple. 204046d17952SDoug Anderson */ 204146d17952SDoug Anderson if ((err != -ETIMEDOUT) && 204246d17952SDoug Anderson (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 204346d17952SDoug Anderson state = STATE_SENDING_DATA; 204446d17952SDoug Anderson continue; 204546d17952SDoug Anderson } 204646d17952SDoug Anderson 204771abb133SSeungwon Jeon dw_mci_stop_dma(host); 204890c2143aSSeungwon Jeon send_stop_abort(host, data); 204971abb133SSeungwon Jeon state = STATE_SENDING_STOP; 205071abb133SSeungwon Jeon break; 205171abb133SSeungwon Jeon } 205271abb133SSeungwon Jeon 2053e352c813SSeungwon Jeon if (!cmd->data || err) { 2054e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2055f95f3850SWill Newton goto unlock; 2056f95f3850SWill Newton } 2057f95f3850SWill Newton 2058f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 2059f95f3850SWill Newton /* fall through */ 2060f95f3850SWill Newton 2061f95f3850SWill Newton case STATE_SENDING_DATA: 20622aa35465SDoug Anderson /* 20632aa35465SDoug Anderson * We could get a data error and never a transfer 20642aa35465SDoug Anderson * complete so we'd better check for it here. 20652aa35465SDoug Anderson * 20662aa35465SDoug Anderson * Note that we don't really care if we also got a 20672aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 20682aa35465SDoug Anderson * abort won't hurt. 20692aa35465SDoug Anderson */ 2070f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 2071f95f3850SWill Newton &host->pending_events)) { 2072f95f3850SWill Newton dw_mci_stop_dma(host); 2073e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2074bdb9a90bSaddy ke SDMMC_INT_EBE))) 207590c2143aSSeungwon Jeon send_stop_abort(host, data); 2076f95f3850SWill Newton state = STATE_DATA_ERROR; 2077f95f3850SWill Newton break; 2078f95f3850SWill Newton } 2079f95f3850SWill Newton 2080f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 208157e10486SAddy Ke &host->pending_events)) { 208257e10486SAddy Ke /* 208357e10486SAddy Ke * If all data-related interrupts don't come 208457e10486SAddy Ke * within the given time in reading data state. 208557e10486SAddy Ke */ 208616a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 208757e10486SAddy Ke dw_mci_set_drto(host); 2088f95f3850SWill Newton break; 208957e10486SAddy Ke } 2090f95f3850SWill Newton 2091f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 20922aa35465SDoug Anderson 20932aa35465SDoug Anderson /* 20942aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 20952aa35465SDoug Anderson * before the transfer completed. This might not have 20962aa35465SDoug Anderson * been caught by the check above because the interrupt 20972aa35465SDoug Anderson * could have gone off between the previous check and 20982aa35465SDoug Anderson * the check for transfer complete. 20992aa35465SDoug Anderson * 21002aa35465SDoug Anderson * Technically this ought not be needed assuming we 21012aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 21022aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 21032aa35465SDoug Anderson * 21042aa35465SDoug Anderson * This has the advantage of sending the stop command. 21052aa35465SDoug Anderson */ 21062aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 21072aa35465SDoug Anderson &host->pending_events)) { 21082aa35465SDoug Anderson dw_mci_stop_dma(host); 2109e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2110bdb9a90bSaddy ke SDMMC_INT_EBE))) 21112aa35465SDoug Anderson send_stop_abort(host, data); 21122aa35465SDoug Anderson state = STATE_DATA_ERROR; 21132aa35465SDoug Anderson break; 21142aa35465SDoug Anderson } 2115f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 21162aa35465SDoug Anderson 2117f95f3850SWill Newton /* fall through */ 2118f95f3850SWill Newton 2119f95f3850SWill Newton case STATE_DATA_BUSY: 212093c23ae3SDouglas Anderson if (!dw_mci_clear_pending_data_complete(host)) { 212157e10486SAddy Ke /* 212257e10486SAddy Ke * If data error interrupt comes but data over 212357e10486SAddy Ke * interrupt doesn't come within the given time. 212457e10486SAddy Ke * in reading data state. 212557e10486SAddy Ke */ 212616a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 212757e10486SAddy Ke dw_mci_set_drto(host); 2128f95f3850SWill Newton break; 212957e10486SAddy Ke } 2130f95f3850SWill Newton 2131f95f3850SWill Newton host->data = NULL; 2132f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2133e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 2134f95f3850SWill Newton 2135e352c813SSeungwon Jeon if (!err) { 2136e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 213717c8bc85SSachin Kamat if (mrq->sbc && data->stop) 2138053b3ce6SSeungwon Jeon data->stop->error = 0; 2139e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2140053b3ce6SSeungwon Jeon goto unlock; 2141053b3ce6SSeungwon Jeon } 2142053b3ce6SSeungwon Jeon 214390c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 2144e352c813SSeungwon Jeon if (data->stop) 214590c2143aSSeungwon Jeon send_stop_abort(host, data); 21462aa35465SDoug Anderson } else { 21472aa35465SDoug Anderson /* 21482aa35465SDoug Anderson * If we don't have a command complete now we'll 21492aa35465SDoug Anderson * never get one since we just reset everything; 21502aa35465SDoug Anderson * better end the request. 21512aa35465SDoug Anderson * 21522aa35465SDoug Anderson * If we do have a command complete we'll fall 21532aa35465SDoug Anderson * through to the SENDING_STOP command and 21542aa35465SDoug Anderson * everything will be peachy keen. 21552aa35465SDoug Anderson */ 21562aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 21572aa35465SDoug Anderson &host->pending_events)) { 21582aa35465SDoug Anderson host->cmd = NULL; 21592aa35465SDoug Anderson dw_mci_request_end(host, mrq); 21602aa35465SDoug Anderson goto unlock; 21612aa35465SDoug Anderson } 216290c2143aSSeungwon Jeon } 2163e352c813SSeungwon Jeon 2164e352c813SSeungwon Jeon /* 2165e352c813SSeungwon Jeon * If err has non-zero, 2166e352c813SSeungwon Jeon * stop-abort command has been already issued. 2167e352c813SSeungwon Jeon */ 2168e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 2169e352c813SSeungwon Jeon 2170f95f3850SWill Newton /* fall through */ 2171f95f3850SWill Newton 2172f95f3850SWill Newton case STATE_SENDING_STOP: 21738892b705SDouglas Anderson if (!dw_mci_clear_pending_cmd_complete(host)) 2174f95f3850SWill Newton break; 2175f95f3850SWill Newton 217671abb133SSeungwon Jeon /* CMD error in data command */ 217731bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 21783a33a94cSSonny Rao dw_mci_reset(host); 217971abb133SSeungwon Jeon 2180f95f3850SWill Newton host->cmd = NULL; 218171abb133SSeungwon Jeon host->data = NULL; 218290c2143aSSeungwon Jeon 2183e13c3c08SJaehoon Chung if (!mrq->sbc && mrq->stop) 2184e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 218590c2143aSSeungwon Jeon else 218690c2143aSSeungwon Jeon host->cmd_status = 0; 218790c2143aSSeungwon Jeon 2188e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2189f95f3850SWill Newton goto unlock; 2190f95f3850SWill Newton 2191f95f3850SWill Newton case STATE_DATA_ERROR: 2192f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2193f95f3850SWill Newton &host->pending_events)) 2194f95f3850SWill Newton break; 2195f95f3850SWill Newton 2196f95f3850SWill Newton state = STATE_DATA_BUSY; 2197f95f3850SWill Newton break; 2198f95f3850SWill Newton } 2199f95f3850SWill Newton } while (state != prev_state); 2200f95f3850SWill Newton 2201f95f3850SWill Newton host->state = state; 2202f95f3850SWill Newton unlock: 2203f95f3850SWill Newton spin_unlock(&host->lock); 2204f95f3850SWill Newton 2205f95f3850SWill Newton } 2206f95f3850SWill Newton 220734b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 220834b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 220934b664a2SJames Hogan { 221034b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 221134b664a2SJames Hogan host->part_buf_count = cnt; 221234b664a2SJames Hogan } 221334b664a2SJames Hogan 221434b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 221534b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 221634b664a2SJames Hogan { 221734b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 221834b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 221934b664a2SJames Hogan host->part_buf_count += cnt; 222034b664a2SJames Hogan return cnt; 222134b664a2SJames Hogan } 222234b664a2SJames Hogan 222334b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 222434b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 222534b664a2SJames Hogan { 22260e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 222734b664a2SJames Hogan if (cnt) { 222834b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 222934b664a2SJames Hogan cnt); 223034b664a2SJames Hogan host->part_buf_count -= cnt; 223134b664a2SJames Hogan host->part_buf_start += cnt; 223234b664a2SJames Hogan } 223334b664a2SJames Hogan return cnt; 223434b664a2SJames Hogan } 223534b664a2SJames Hogan 223634b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 223734b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 223834b664a2SJames Hogan { 223934b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 224034b664a2SJames Hogan host->part_buf_start = cnt; 224134b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 224234b664a2SJames Hogan } 224334b664a2SJames Hogan 2244f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2245f95f3850SWill Newton { 2246cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2247cfbeb59cSMarkos Chandras int init_cnt = cnt; 2248cfbeb59cSMarkos Chandras 224934b664a2SJames Hogan /* try and push anything in the part_buf */ 225034b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 225134b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 22520e3a22c0SShawn Lin 225334b664a2SJames Hogan buf += len; 225434b664a2SJames Hogan cnt -= len; 2255cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 225676184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 225734b664a2SJames Hogan host->part_buf_count = 0; 225834b664a2SJames Hogan } 225934b664a2SJames Hogan } 226034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 226134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 226234b664a2SJames Hogan while (cnt >= 2) { 226334b664a2SJames Hogan u16 aligned_buf[64]; 226434b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 226534b664a2SJames Hogan int items = len >> 1; 226634b664a2SJames Hogan int i; 226734b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 226834b664a2SJames Hogan memcpy(aligned_buf, buf, len); 226934b664a2SJames Hogan buf += len; 227034b664a2SJames Hogan cnt -= len; 227134b664a2SJames Hogan /* push data from aligned buffer into fifo */ 227234b664a2SJames Hogan for (i = 0; i < items; ++i) 227376184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 227434b664a2SJames Hogan } 227534b664a2SJames Hogan } else 227634b664a2SJames Hogan #endif 227734b664a2SJames Hogan { 227834b664a2SJames Hogan u16 *pdata = buf; 22790e3a22c0SShawn Lin 228034b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 228176184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 228234b664a2SJames Hogan buf = pdata; 228334b664a2SJames Hogan } 228434b664a2SJames Hogan /* put anything remaining in the part_buf */ 228534b664a2SJames Hogan if (cnt) { 228634b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2287cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2288cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2289cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 229076184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2291f95f3850SWill Newton } 2292f95f3850SWill Newton } 2293f95f3850SWill Newton 2294f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2295f95f3850SWill Newton { 229634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 229734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 229834b664a2SJames Hogan while (cnt >= 2) { 229934b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 230034b664a2SJames Hogan u16 aligned_buf[64]; 230134b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 230234b664a2SJames Hogan int items = len >> 1; 230334b664a2SJames Hogan int i; 23040e3a22c0SShawn Lin 230534b664a2SJames Hogan for (i = 0; i < items; ++i) 230676184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 230734b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 230834b664a2SJames Hogan memcpy(buf, aligned_buf, len); 230934b664a2SJames Hogan buf += len; 231034b664a2SJames Hogan cnt -= len; 231134b664a2SJames Hogan } 231234b664a2SJames Hogan } else 231334b664a2SJames Hogan #endif 231434b664a2SJames Hogan { 231534b664a2SJames Hogan u16 *pdata = buf; 23160e3a22c0SShawn Lin 231734b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 231876184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 231934b664a2SJames Hogan buf = pdata; 232034b664a2SJames Hogan } 232134b664a2SJames Hogan if (cnt) { 232276184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 232334b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2324f95f3850SWill Newton } 2325f95f3850SWill Newton } 2326f95f3850SWill Newton 2327f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2328f95f3850SWill Newton { 2329cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2330cfbeb59cSMarkos Chandras int init_cnt = cnt; 2331cfbeb59cSMarkos Chandras 233234b664a2SJames Hogan /* try and push anything in the part_buf */ 233334b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 233434b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 23350e3a22c0SShawn Lin 233634b664a2SJames Hogan buf += len; 233734b664a2SJames Hogan cnt -= len; 2338cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 233976184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 234034b664a2SJames Hogan host->part_buf_count = 0; 234134b664a2SJames Hogan } 234234b664a2SJames Hogan } 234334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 234434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 234534b664a2SJames Hogan while (cnt >= 4) { 234634b664a2SJames Hogan u32 aligned_buf[32]; 234734b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 234834b664a2SJames Hogan int items = len >> 2; 234934b664a2SJames Hogan int i; 235034b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 235134b664a2SJames Hogan memcpy(aligned_buf, buf, len); 235234b664a2SJames Hogan buf += len; 235334b664a2SJames Hogan cnt -= len; 235434b664a2SJames Hogan /* push data from aligned buffer into fifo */ 235534b664a2SJames Hogan for (i = 0; i < items; ++i) 235676184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 235734b664a2SJames Hogan } 235834b664a2SJames Hogan } else 235934b664a2SJames Hogan #endif 236034b664a2SJames Hogan { 236134b664a2SJames Hogan u32 *pdata = buf; 23620e3a22c0SShawn Lin 236334b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 236476184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 236534b664a2SJames Hogan buf = pdata; 236634b664a2SJames Hogan } 236734b664a2SJames Hogan /* put anything remaining in the part_buf */ 236834b664a2SJames Hogan if (cnt) { 236934b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2370cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2371cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2372cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 237376184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2374f95f3850SWill Newton } 2375f95f3850SWill Newton } 2376f95f3850SWill Newton 2377f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2378f95f3850SWill Newton { 237934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 238034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 238134b664a2SJames Hogan while (cnt >= 4) { 238234b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 238334b664a2SJames Hogan u32 aligned_buf[32]; 238434b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 238534b664a2SJames Hogan int items = len >> 2; 238634b664a2SJames Hogan int i; 23870e3a22c0SShawn Lin 238834b664a2SJames Hogan for (i = 0; i < items; ++i) 238976184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 239034b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 239134b664a2SJames Hogan memcpy(buf, aligned_buf, len); 239234b664a2SJames Hogan buf += len; 239334b664a2SJames Hogan cnt -= len; 239434b664a2SJames Hogan } 239534b664a2SJames Hogan } else 239634b664a2SJames Hogan #endif 239734b664a2SJames Hogan { 239834b664a2SJames Hogan u32 *pdata = buf; 23990e3a22c0SShawn Lin 240034b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 240176184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 240234b664a2SJames Hogan buf = pdata; 240334b664a2SJames Hogan } 240434b664a2SJames Hogan if (cnt) { 240576184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 240634b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2407f95f3850SWill Newton } 2408f95f3850SWill Newton } 2409f95f3850SWill Newton 2410f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2411f95f3850SWill Newton { 2412cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2413cfbeb59cSMarkos Chandras int init_cnt = cnt; 2414cfbeb59cSMarkos Chandras 241534b664a2SJames Hogan /* try and push anything in the part_buf */ 241634b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 241734b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 24180e3a22c0SShawn Lin 241934b664a2SJames Hogan buf += len; 242034b664a2SJames Hogan cnt -= len; 2421c09fbd74SSeungwon Jeon 2422cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 242376184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 242434b664a2SJames Hogan host->part_buf_count = 0; 242534b664a2SJames Hogan } 242634b664a2SJames Hogan } 242734b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 242834b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 242934b664a2SJames Hogan while (cnt >= 8) { 243034b664a2SJames Hogan u64 aligned_buf[16]; 243134b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 243234b664a2SJames Hogan int items = len >> 3; 243334b664a2SJames Hogan int i; 243434b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 243534b664a2SJames Hogan memcpy(aligned_buf, buf, len); 243634b664a2SJames Hogan buf += len; 243734b664a2SJames Hogan cnt -= len; 243834b664a2SJames Hogan /* push data from aligned buffer into fifo */ 243934b664a2SJames Hogan for (i = 0; i < items; ++i) 244076184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 244134b664a2SJames Hogan } 244234b664a2SJames Hogan } else 244334b664a2SJames Hogan #endif 244434b664a2SJames Hogan { 244534b664a2SJames Hogan u64 *pdata = buf; 24460e3a22c0SShawn Lin 244734b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 244876184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 244934b664a2SJames Hogan buf = pdata; 245034b664a2SJames Hogan } 245134b664a2SJames Hogan /* put anything remaining in the part_buf */ 245234b664a2SJames Hogan if (cnt) { 245334b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2454cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2455cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2456cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 245776184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2458f95f3850SWill Newton } 2459f95f3850SWill Newton } 2460f95f3850SWill Newton 2461f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2462f95f3850SWill Newton { 246334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 246434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 246534b664a2SJames Hogan while (cnt >= 8) { 246634b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 246734b664a2SJames Hogan u64 aligned_buf[16]; 246834b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 246934b664a2SJames Hogan int items = len >> 3; 247034b664a2SJames Hogan int i; 24710e3a22c0SShawn Lin 247234b664a2SJames Hogan for (i = 0; i < items; ++i) 247376184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 247476184ac1SBen Dooks 247534b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 247634b664a2SJames Hogan memcpy(buf, aligned_buf, len); 247734b664a2SJames Hogan buf += len; 247834b664a2SJames Hogan cnt -= len; 2479f95f3850SWill Newton } 248034b664a2SJames Hogan } else 248134b664a2SJames Hogan #endif 248234b664a2SJames Hogan { 248334b664a2SJames Hogan u64 *pdata = buf; 24840e3a22c0SShawn Lin 248534b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 248676184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 248734b664a2SJames Hogan buf = pdata; 248834b664a2SJames Hogan } 248934b664a2SJames Hogan if (cnt) { 249076184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 249134b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 249234b664a2SJames Hogan } 249334b664a2SJames Hogan } 249434b664a2SJames Hogan 249534b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 249634b664a2SJames Hogan { 249734b664a2SJames Hogan int len; 249834b664a2SJames Hogan 249934b664a2SJames Hogan /* get remaining partial bytes */ 250034b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 250134b664a2SJames Hogan if (unlikely(len == cnt)) 250234b664a2SJames Hogan return; 250334b664a2SJames Hogan buf += len; 250434b664a2SJames Hogan cnt -= len; 250534b664a2SJames Hogan 250634b664a2SJames Hogan /* get the rest of the data */ 250734b664a2SJames Hogan host->pull_data(host, buf, cnt); 2508f95f3850SWill Newton } 2509f95f3850SWill Newton 251087a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2511f95f3850SWill Newton { 2512f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2513f9c2a0dcSSeungwon Jeon void *buf; 2514f9c2a0dcSSeungwon Jeon unsigned int offset; 2515f95f3850SWill Newton struct mmc_data *data = host->data; 2516f95f3850SWill Newton int shift = host->data_shift; 2517f95f3850SWill Newton u32 status; 25183e4b0d8bSMarkos Chandras unsigned int len; 2519f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2520f95f3850SWill Newton 2521f95f3850SWill Newton do { 2522f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2523f9c2a0dcSSeungwon Jeon goto done; 2524f95f3850SWill Newton 25254225fc85SImre Deak host->sg = sg_miter->piter.sg; 2526f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2527f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2528f9c2a0dcSSeungwon Jeon offset = 0; 2529f9c2a0dcSSeungwon Jeon 2530f9c2a0dcSSeungwon Jeon do { 2531f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2532f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2533f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2534f9c2a0dcSSeungwon Jeon if (!len) 2535f9c2a0dcSSeungwon Jeon break; 2536f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 25373e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2538f95f3850SWill Newton offset += len; 2539f9c2a0dcSSeungwon Jeon remain -= len; 2540f9c2a0dcSSeungwon Jeon } while (remain); 2541f95f3850SWill Newton 2542e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2543f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2544f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 254587a74d39SKyoungil Kim /* if the RXDR is ready read again */ 254687a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 254787a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2548f9c2a0dcSSeungwon Jeon 2549f9c2a0dcSSeungwon Jeon if (!remain) { 2550f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2551f9c2a0dcSSeungwon Jeon goto done; 2552f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2553f9c2a0dcSSeungwon Jeon } 2554f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2555f95f3850SWill Newton return; 2556f95f3850SWill Newton 2557f95f3850SWill Newton done: 2558f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2559f9c2a0dcSSeungwon Jeon host->sg = NULL; 25600e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2561f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2562f95f3850SWill Newton } 2563f95f3850SWill Newton 2564f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2565f95f3850SWill Newton { 2566f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2567f9c2a0dcSSeungwon Jeon void *buf; 2568f9c2a0dcSSeungwon Jeon unsigned int offset; 2569f95f3850SWill Newton struct mmc_data *data = host->data; 2570f95f3850SWill Newton int shift = host->data_shift; 2571f95f3850SWill Newton u32 status; 25723e4b0d8bSMarkos Chandras unsigned int len; 2573f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2574f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2575f95f3850SWill Newton 2576f95f3850SWill Newton do { 2577f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2578f9c2a0dcSSeungwon Jeon goto done; 2579f95f3850SWill Newton 25804225fc85SImre Deak host->sg = sg_miter->piter.sg; 2581f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2582f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2583f9c2a0dcSSeungwon Jeon offset = 0; 2584f9c2a0dcSSeungwon Jeon 2585f9c2a0dcSSeungwon Jeon do { 2586f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2587f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2588f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2589f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2590f9c2a0dcSSeungwon Jeon if (!len) 2591f9c2a0dcSSeungwon Jeon break; 2592f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 25933e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2594f95f3850SWill Newton offset += len; 2595f9c2a0dcSSeungwon Jeon remain -= len; 2596f9c2a0dcSSeungwon Jeon } while (remain); 2597f95f3850SWill Newton 2598e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2599f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2600f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2601f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2602f9c2a0dcSSeungwon Jeon 2603f9c2a0dcSSeungwon Jeon if (!remain) { 2604f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2605f9c2a0dcSSeungwon Jeon goto done; 2606f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2607f9c2a0dcSSeungwon Jeon } 2608f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2609f95f3850SWill Newton return; 2610f95f3850SWill Newton 2611f95f3850SWill Newton done: 2612f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2613f9c2a0dcSSeungwon Jeon host->sg = NULL; 26140e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2615f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2616f95f3850SWill Newton } 2617f95f3850SWill Newton 2618f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2619f95f3850SWill Newton { 26200363b12dSDouglas Anderson del_timer(&host->cto_timer); 26210363b12dSDouglas Anderson 2622f95f3850SWill Newton if (!host->cmd_status) 2623f95f3850SWill Newton host->cmd_status = status; 2624f95f3850SWill Newton 26250e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2626f95f3850SWill Newton 2627f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2628f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2629f95f3850SWill Newton } 2630f95f3850SWill Newton 26316130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 26326130e7a9SDoug Anderson { 2633b23475faSJaehoon Chung struct dw_mci_slot *slot = host->slot; 26346130e7a9SDoug Anderson 26356130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 26366130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 26376130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 26386130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 26396130e7a9SDoug Anderson } 26406130e7a9SDoug Anderson 2641f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2642f95f3850SWill Newton { 2643f95f3850SWill Newton struct dw_mci *host = dev_id; 2644182c9081SSeungwon Jeon u32 pending; 2645b23475faSJaehoon Chung struct dw_mci_slot *slot = host->slot; 26468892b705SDouglas Anderson unsigned long irqflags; 2647f95f3850SWill Newton 2648f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2649f95f3850SWill Newton 2650476d79f1SDoug Anderson if (pending) { 265101730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 265201730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 265301730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 265401730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 265501730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 265649ba0302SDoug Anderson 265749ba0302SDoug Anderson /* 265849ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 265949ba0302SDoug Anderson * off after the lock is released, so safe to delete. 266049ba0302SDoug Anderson */ 266149ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 266201730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 266349ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 266449ba0302SDoug Anderson 266549ba0302SDoug Anderson del_timer(&host->cmd11_timer); 266601730558SDoug Anderson } 266701730558SDoug Anderson 2668f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 26698892b705SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 26708892b705SDouglas Anderson 267103de1921SAddy Ke del_timer(&host->cto_timer); 2672f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2673182c9081SSeungwon Jeon host->cmd_status = pending; 26740e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2675f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 26768892b705SDouglas Anderson 26778892b705SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2678f95f3850SWill Newton } 2679f95f3850SWill Newton 2680f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2681f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2682f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2683182c9081SSeungwon Jeon host->data_status = pending; 26840e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2685f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2686f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2687f95f3850SWill Newton } 2688f95f3850SWill Newton 2689f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 269093c23ae3SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 269193c23ae3SDouglas Anderson 269257e10486SAddy Ke del_timer(&host->dto_timer); 269357e10486SAddy Ke 2694f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2695f95f3850SWill Newton if (!host->data_status) 2696182c9081SSeungwon Jeon host->data_status = pending; 26970e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2698f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2699f95f3850SWill Newton if (host->sg != NULL) 270087a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2701f95f3850SWill Newton } 2702f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2703f95f3850SWill Newton tasklet_schedule(&host->tasklet); 270493c23ae3SDouglas Anderson 270593c23ae3SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2706f95f3850SWill Newton } 2707f95f3850SWill Newton 2708f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2709f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2710b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 271187a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2712f95f3850SWill Newton } 2713f95f3850SWill Newton 2714f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2715f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2716b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2717f95f3850SWill Newton dw_mci_write_data_pio(host); 2718f95f3850SWill Newton } 2719f95f3850SWill Newton 2720f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 27218892b705SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 27228892b705SDouglas Anderson 2723f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2724182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 27258892b705SDouglas Anderson 27268892b705SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2727f95f3850SWill Newton } 2728f95f3850SWill Newton 2729f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2730f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 27316130e7a9SDoug Anderson dw_mci_handle_cd(host); 2732f95f3850SWill Newton } 2733f95f3850SWill Newton 273476756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 273576756234SAddy Ke mci_writel(host, RINTSTS, 273676756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 273732dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 0); 273832dba737SUlf Hansson sdio_signal_irq(slot->mmc); 27391a5c8e1fSShashidhar Hiremath } 27401a5c8e1fSShashidhar Hiremath 27411fb5f68aSMarkos Chandras } 2742f95f3850SWill Newton 27433fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 27443fc7eaefSShawn Lin return IRQ_HANDLED; 27453fc7eaefSShawn Lin 27463fc7eaefSShawn Lin /* Handle IDMA interrupts */ 274769d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 274869d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 274969d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 275069d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 275169d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 275269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2753faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 27543fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 275569d99fdcSPrabu Thangamuthu } 275669d99fdcSPrabu Thangamuthu } else { 2757f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2758f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 275969d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 276069d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2761f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2762faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 27633fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2764f95f3850SWill Newton } 276569d99fdcSPrabu Thangamuthu } 2766f95f3850SWill Newton 2767f95f3850SWill Newton return IRQ_HANDLED; 2768f95f3850SWill Newton } 2769f95f3850SWill Newton 2770a4faa492SShawn Lin static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) 2771a4faa492SShawn Lin { 2772a4faa492SShawn Lin struct dw_mci *host = slot->host; 2773a4faa492SShawn Lin const struct dw_mci_drv_data *drv_data = host->drv_data; 2774a4faa492SShawn Lin struct mmc_host *mmc = slot->mmc; 2775a4faa492SShawn Lin int ctrl_id; 2776a4faa492SShawn Lin 2777a4faa492SShawn Lin if (host->pdata->caps) 2778a4faa492SShawn Lin mmc->caps = host->pdata->caps; 2779a4faa492SShawn Lin 2780a4faa492SShawn Lin /* 2781a4faa492SShawn Lin * Support MMC_CAP_ERASE by default. 2782a4faa492SShawn Lin * It needs to use trim/discard/erase commands. 2783a4faa492SShawn Lin */ 2784a4faa492SShawn Lin mmc->caps |= MMC_CAP_ERASE; 2785a4faa492SShawn Lin 2786a4faa492SShawn Lin if (host->pdata->pm_caps) 2787a4faa492SShawn Lin mmc->pm_caps = host->pdata->pm_caps; 2788a4faa492SShawn Lin 2789a4faa492SShawn Lin if (host->dev->of_node) { 2790a4faa492SShawn Lin ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2791a4faa492SShawn Lin if (ctrl_id < 0) 2792a4faa492SShawn Lin ctrl_id = 0; 2793a4faa492SShawn Lin } else { 2794a4faa492SShawn Lin ctrl_id = to_platform_device(host->dev)->id; 2795a4faa492SShawn Lin } 27960d84b9e5SShawn Lin 27970d84b9e5SShawn Lin if (drv_data && drv_data->caps) { 27980d84b9e5SShawn Lin if (ctrl_id >= drv_data->num_caps) { 27990d84b9e5SShawn Lin dev_err(host->dev, "invalid controller id %d\n", 28000d84b9e5SShawn Lin ctrl_id); 28010d84b9e5SShawn Lin return -EINVAL; 28020d84b9e5SShawn Lin } 2803a4faa492SShawn Lin mmc->caps |= drv_data->caps[ctrl_id]; 28040d84b9e5SShawn Lin } 2805a4faa492SShawn Lin 2806a4faa492SShawn Lin if (host->pdata->caps2) 2807a4faa492SShawn Lin mmc->caps2 = host->pdata->caps2; 2808a4faa492SShawn Lin 280986b93a48SJaehoon Chung mmc->f_min = DW_MCI_FREQ_MIN; 281086b93a48SJaehoon Chung if (!mmc->f_max) 281186b93a48SJaehoon Chung mmc->f_max = DW_MCI_FREQ_MAX; 281286b93a48SJaehoon Chung 2813a4faa492SShawn Lin /* Process SDIO IRQs through the sdio_irq_work. */ 2814a4faa492SShawn Lin if (mmc->caps & MMC_CAP_SDIO_IRQ) 2815a4faa492SShawn Lin mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2816a4faa492SShawn Lin 2817a4faa492SShawn Lin return 0; 2818a4faa492SShawn Lin } 2819a4faa492SShawn Lin 2820e4a65ef7SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host) 2821f95f3850SWill Newton { 2822f95f3850SWill Newton struct mmc_host *mmc; 2823f95f3850SWill Newton struct dw_mci_slot *slot; 2824a4faa492SShawn Lin int ret; 2825f95f3850SWill Newton 28264a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2827f95f3850SWill Newton if (!mmc) 2828f95f3850SWill Newton return -ENOMEM; 2829f95f3850SWill Newton 2830f95f3850SWill Newton slot = mmc_priv(mmc); 2831e4a65ef7SJaehoon Chung slot->id = 0; 2832e4a65ef7SJaehoon Chung slot->sdio_id = host->sdio_id0 + slot->id; 2833f95f3850SWill Newton slot->mmc = mmc; 2834f95f3850SWill Newton slot->host = host; 2835b23475faSJaehoon Chung host->slot = slot; 2836f95f3850SWill Newton 2837f95f3850SWill Newton mmc->ops = &dw_mci_ops; 2838f95f3850SWill Newton 283951da2240SYuvaraj CD /*if there are external regulators, get them*/ 284051da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 28410f3a47b8SWolfram Sang if (ret) 28423cf890fcSDoug Anderson goto err_host_allocated; 284351da2240SYuvaraj CD 284451da2240SYuvaraj CD if (!mmc->ocr_avail) 2845f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2846f95f3850SWill Newton 28473cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 28483cf890fcSDoug Anderson if (ret) 28493cf890fcSDoug Anderson goto err_host_allocated; 2850f95f3850SWill Newton 2851a4faa492SShawn Lin ret = dw_mci_init_slot_caps(slot); 2852a4faa492SShawn Lin if (ret) 2853a4faa492SShawn Lin goto err_host_allocated; 285432dba737SUlf Hansson 2855f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 28563fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2857a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2858225faf87SJaehoon Chung mmc->max_blk_size = 65535; 2859575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 28601a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 28611a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 28623fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 28633fc7eaefSShawn Lin mmc->max_segs = 64; 2864225faf87SJaehoon Chung mmc->max_blk_size = 65535; 28653fc7eaefSShawn Lin mmc->max_blk_count = 65535; 28663fc7eaefSShawn Lin mmc->max_req_size = 28673fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 28683fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2869575c319dSHeiko Stuebner } else { 28703fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2871f95f3850SWill Newton mmc->max_segs = 64; 2872225faf87SJaehoon Chung mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2873f95f3850SWill Newton mmc->max_blk_count = 512; 2874575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2875575c319dSHeiko Stuebner mmc->max_blk_count; 2876f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2877575c319dSHeiko Stuebner } 2878f95f3850SWill Newton 2879c0834a58SShawn Lin dw_mci_get_cd(mmc); 2880ae0eb348SJaehoon Chung 28810cea529dSJaehoon Chung ret = mmc_add_host(mmc); 28820cea529dSJaehoon Chung if (ret) 28833cf890fcSDoug Anderson goto err_host_allocated; 2884f95f3850SWill Newton 2885f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2886f95f3850SWill Newton dw_mci_init_debugfs(slot); 2887f95f3850SWill Newton #endif 2888f95f3850SWill Newton 2889f95f3850SWill Newton return 0; 2890800d78bfSThomas Abraham 28913cf890fcSDoug Anderson err_host_allocated: 2892800d78bfSThomas Abraham mmc_free_host(mmc); 289351da2240SYuvaraj CD return ret; 2894f95f3850SWill Newton } 2895f95f3850SWill Newton 2896e4a65ef7SJaehoon Chung static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2897f95f3850SWill Newton { 2898f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2899f95f3850SWill Newton mmc_remove_host(slot->mmc); 2900b23475faSJaehoon Chung slot->host->slot = NULL; 2901f95f3850SWill Newton mmc_free_host(slot->mmc); 2902f95f3850SWill Newton } 2903f95f3850SWill Newton 2904f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2905f95f3850SWill Newton { 290669d99fdcSPrabu Thangamuthu int addr_config; 29073fc7eaefSShawn Lin struct device *dev = host->dev; 29083fc7eaefSShawn Lin 29093fc7eaefSShawn Lin /* 29103fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 29113fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 29123fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 29133fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 29143fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 29153fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 29163fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 29173fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 29183fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 29193fc7eaefSShawn Lin */ 29203fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 29213fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 29223fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 29233fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 29243fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 29253fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 29263fc7eaefSShawn Lin } else { 29273fc7eaefSShawn Lin goto no_dma; 29283fc7eaefSShawn Lin } 29293fc7eaefSShawn Lin 29303fc7eaefSShawn Lin /* Determine which DMA interface to use */ 29313fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 29323fc7eaefSShawn Lin /* 29333fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 29343fc7eaefSShawn Lin * IDMAC address bus width 29353fc7eaefSShawn Lin */ 293670692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 293769d99fdcSPrabu Thangamuthu 293869d99fdcSPrabu Thangamuthu if (addr_config == 1) { 293969d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 294069d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 29413fc7eaefSShawn Lin dev_info(host->dev, 29423fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 294369d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 29443fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 29453fc7eaefSShawn Lin DMA_BIT_MASK(64)); 294669d99fdcSPrabu Thangamuthu } else { 294769d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 294869d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 29493fc7eaefSShawn Lin dev_info(host->dev, 29503fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 295169d99fdcSPrabu Thangamuthu } 295269d99fdcSPrabu Thangamuthu 2953f95f3850SWill Newton /* Alloc memory for sg translation */ 2954cc190d4cSShawn Lin host->sg_cpu = dmam_alloc_coherent(host->dev, 2955cc190d4cSShawn Lin DESC_RING_BUF_SZ, 2956f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2957f95f3850SWill Newton if (!host->sg_cpu) { 29583fc7eaefSShawn Lin dev_err(host->dev, 29593fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2960f95f3850SWill Newton __func__); 2961f95f3850SWill Newton goto no_dma; 2962f95f3850SWill Newton } 2963f95f3850SWill Newton 2964f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 296500956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 29663fc7eaefSShawn Lin } else { 29673fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 2968852ff5feSDavid Woods if ((device_property_read_string_array(dev, "dma-names", 2969852ff5feSDavid Woods NULL, 0) < 0) || 2970852ff5feSDavid Woods !device_property_present(dev, "dmas")) { 2971f95f3850SWill Newton goto no_dma; 29723fc7eaefSShawn Lin } 29733fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 29743fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 29753fc7eaefSShawn Lin } 2976f95f3850SWill Newton 2977e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2978e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2979f95f3850SWill Newton if (host->dma_ops->init(host)) { 29800e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 29810e3a22c0SShawn Lin __func__); 2982f95f3850SWill Newton goto no_dma; 2983f95f3850SWill Newton } 2984f95f3850SWill Newton } else { 29854a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2986f95f3850SWill Newton goto no_dma; 2987f95f3850SWill Newton } 2988f95f3850SWill Newton 2989f95f3850SWill Newton return; 2990f95f3850SWill Newton 2991f95f3850SWill Newton no_dma: 29924a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 29933fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2994f95f3850SWill Newton } 2995f95f3850SWill Newton 299637977729SKees Cook static void dw_mci_cmd11_timer(struct timer_list *t) 29975c935165SDoug Anderson { 299837977729SKees Cook struct dw_mci *host = from_timer(host, t, cmd11_timer); 29995c935165SDoug Anderson 3000fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 3001fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 3002fd674198SDoug Anderson return; 3003fd674198SDoug Anderson } 30045c935165SDoug Anderson 30055c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 30065c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 30075c935165SDoug Anderson tasklet_schedule(&host->tasklet); 30085c935165SDoug Anderson } 30095c935165SDoug Anderson 301037977729SKees Cook static void dw_mci_cto_timer(struct timer_list *t) 301103de1921SAddy Ke { 301237977729SKees Cook struct dw_mci *host = from_timer(host, t, cto_timer); 30138892b705SDouglas Anderson unsigned long irqflags; 30148892b705SDouglas Anderson u32 pending; 301503de1921SAddy Ke 30168892b705SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 30178892b705SDouglas Anderson 30188892b705SDouglas Anderson /* 30198892b705SDouglas Anderson * If somehow we have very bad interrupt latency it's remotely possible 30208892b705SDouglas Anderson * that the timer could fire while the interrupt is still pending or 30218892b705SDouglas Anderson * while the interrupt is midway through running. Let's be paranoid 30228892b705SDouglas Anderson * and detect those two cases. Note that this is paranoia is somewhat 30238892b705SDouglas Anderson * justified because in this function we don't actually cancel the 30248892b705SDouglas Anderson * pending command in the controller--we just assume it will never come. 30258892b705SDouglas Anderson */ 30268892b705SDouglas Anderson pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 30278892b705SDouglas Anderson if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 30288892b705SDouglas Anderson /* The interrupt should fire; no need to act but we can warn */ 30298892b705SDouglas Anderson dev_warn(host->dev, "Unexpected interrupt latency\n"); 30308892b705SDouglas Anderson goto exit; 30318892b705SDouglas Anderson } 30328892b705SDouglas Anderson if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 30338892b705SDouglas Anderson /* Presumably interrupt handler couldn't delete the timer */ 30348892b705SDouglas Anderson dev_warn(host->dev, "CTO timeout when already completed\n"); 30358892b705SDouglas Anderson goto exit; 30368892b705SDouglas Anderson } 30378892b705SDouglas Anderson 30388892b705SDouglas Anderson /* 30398892b705SDouglas Anderson * Continued paranoia to make sure we're in the state we expect. 30408892b705SDouglas Anderson * This paranoia isn't really justified but it seems good to be safe. 30418892b705SDouglas Anderson */ 304203de1921SAddy Ke switch (host->state) { 304303de1921SAddy Ke case STATE_SENDING_CMD11: 304403de1921SAddy Ke case STATE_SENDING_CMD: 304503de1921SAddy Ke case STATE_SENDING_STOP: 304603de1921SAddy Ke /* 304703de1921SAddy Ke * If CMD_DONE interrupt does NOT come in sending command 304803de1921SAddy Ke * state, we should notify the driver to terminate current 304903de1921SAddy Ke * transfer and report a command timeout to the core. 305003de1921SAddy Ke */ 305103de1921SAddy Ke host->cmd_status = SDMMC_INT_RTO; 305203de1921SAddy Ke set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 305303de1921SAddy Ke tasklet_schedule(&host->tasklet); 305403de1921SAddy Ke break; 305503de1921SAddy Ke default: 305603de1921SAddy Ke dev_warn(host->dev, "Unexpected command timeout, state %d\n", 305703de1921SAddy Ke host->state); 305803de1921SAddy Ke break; 305903de1921SAddy Ke } 30608892b705SDouglas Anderson 30618892b705SDouglas Anderson exit: 30628892b705SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 306303de1921SAddy Ke } 306403de1921SAddy Ke 306537977729SKees Cook static void dw_mci_dto_timer(struct timer_list *t) 306657e10486SAddy Ke { 306737977729SKees Cook struct dw_mci *host = from_timer(host, t, dto_timer); 306893c23ae3SDouglas Anderson unsigned long irqflags; 306993c23ae3SDouglas Anderson u32 pending; 307057e10486SAddy Ke 307193c23ae3SDouglas Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 307293c23ae3SDouglas Anderson 307393c23ae3SDouglas Anderson /* 307493c23ae3SDouglas Anderson * The DTO timer is much longer than the CTO timer, so it's even less 307593c23ae3SDouglas Anderson * likely that we'll these cases, but it pays to be paranoid. 307693c23ae3SDouglas Anderson */ 307793c23ae3SDouglas Anderson pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 307893c23ae3SDouglas Anderson if (pending & SDMMC_INT_DATA_OVER) { 307993c23ae3SDouglas Anderson /* The interrupt should fire; no need to act but we can warn */ 308093c23ae3SDouglas Anderson dev_warn(host->dev, "Unexpected data interrupt latency\n"); 308193c23ae3SDouglas Anderson goto exit; 308293c23ae3SDouglas Anderson } 308393c23ae3SDouglas Anderson if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 308493c23ae3SDouglas Anderson /* Presumably interrupt handler couldn't delete the timer */ 308593c23ae3SDouglas Anderson dev_warn(host->dev, "DTO timeout when already completed\n"); 308693c23ae3SDouglas Anderson goto exit; 308793c23ae3SDouglas Anderson } 308893c23ae3SDouglas Anderson 308993c23ae3SDouglas Anderson /* 309093c23ae3SDouglas Anderson * Continued paranoia to make sure we're in the state we expect. 309193c23ae3SDouglas Anderson * This paranoia isn't really justified but it seems good to be safe. 309293c23ae3SDouglas Anderson */ 309357e10486SAddy Ke switch (host->state) { 309457e10486SAddy Ke case STATE_SENDING_DATA: 309557e10486SAddy Ke case STATE_DATA_BUSY: 309657e10486SAddy Ke /* 309757e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 309857e10486SAddy Ke * we should notify the driver to terminate current transfer 309957e10486SAddy Ke * and report a data timeout to the core. 310057e10486SAddy Ke */ 310157e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 310257e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 310357e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 310457e10486SAddy Ke tasklet_schedule(&host->tasklet); 310557e10486SAddy Ke break; 310657e10486SAddy Ke default: 310793c23ae3SDouglas Anderson dev_warn(host->dev, "Unexpected data timeout, state %d\n", 310893c23ae3SDouglas Anderson host->state); 310957e10486SAddy Ke break; 311057e10486SAddy Ke } 311193c23ae3SDouglas Anderson 311293c23ae3SDouglas Anderson exit: 311393c23ae3SDouglas Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 311457e10486SAddy Ke } 311557e10486SAddy Ke 3116c91eab4bSThomas Abraham #ifdef CONFIG_OF 3117c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3118c91eab4bSThomas Abraham { 3119c91eab4bSThomas Abraham struct dw_mci_board *pdata; 3120c91eab4bSThomas Abraham struct device *dev = host->dev; 3121e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 3122e8cc37b8SShawn Lin int ret; 31233c6d89eaSDoug Anderson u32 clock_frequency; 3124c91eab4bSThomas Abraham 3125c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3126bf3707eaSBeomho Seo if (!pdata) 3127c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 3128c91eab4bSThomas Abraham 3129d6786fefSGuodong Xu /* find reset controller when exist */ 3130a93d6f31SPhilipp Zabel pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3131d6786fefSGuodong Xu if (IS_ERR(pdata->rstc)) { 3132d6786fefSGuodong Xu if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3133d6786fefSGuodong Xu return ERR_PTR(-EPROBE_DEFER); 3134d6786fefSGuodong Xu } 3135d6786fefSGuodong Xu 3136852ff5feSDavid Woods if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 31370e3a22c0SShawn Lin dev_info(dev, 31380e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 3139c91eab4bSThomas Abraham 3140852ff5feSDavid Woods device_property_read_u32(dev, "card-detect-delay", 3141852ff5feSDavid Woods &pdata->detect_delay_ms); 3142c91eab4bSThomas Abraham 3143852ff5feSDavid Woods device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3144a0361c1aSJun Nie 3145852ff5feSDavid Woods if (device_property_present(dev, "fifo-watermark-aligned")) 3146d6fced83SJun Nie host->wm_aligned = true; 3147d6fced83SJun Nie 3148852ff5feSDavid Woods if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 31493c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 31503c6d89eaSDoug Anderson 3151cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 3152cb27a843SJames Hogan ret = drv_data->parse_dt(host); 3153800d78bfSThomas Abraham if (ret) 3154800d78bfSThomas Abraham return ERR_PTR(ret); 3155800d78bfSThomas Abraham } 3156800d78bfSThomas Abraham 3157c91eab4bSThomas Abraham return pdata; 3158c91eab4bSThomas Abraham } 3159c91eab4bSThomas Abraham 3160c91eab4bSThomas Abraham #else /* CONFIG_OF */ 3161c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3162c91eab4bSThomas Abraham { 3163c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 3164c91eab4bSThomas Abraham } 3165c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 3166c91eab4bSThomas Abraham 3167fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 3168fa0c3283SDoug Anderson { 3169fa0c3283SDoug Anderson unsigned long irqflags; 3170fa0c3283SDoug Anderson u32 temp; 3171fa0c3283SDoug Anderson 3172e8cc37b8SShawn Lin /* 3173e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 3174e8cc37b8SShawn Lin * as well as broken card detection is found. 3175e8cc37b8SShawn Lin */ 3176e47c0b96SJaehoon Chung if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3177e8cc37b8SShawn Lin return; 3178fa0c3283SDoug Anderson 3179e47c0b96SJaehoon Chung if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3180fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 3181fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 3182fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 3183fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 3184fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 3185fa0c3283SDoug Anderson } 318658870241SJaehoon Chung } 3187fa0c3283SDoug Anderson 318862ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 3189f95f3850SWill Newton { 3190e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 319162ca8034SShashidhar Hiremath int width, i, ret = 0; 3192f95f3850SWill Newton u32 fifo_size; 3193f95f3850SWill Newton 3194c91eab4bSThomas Abraham if (!host->pdata) { 3195c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 3196d6786fefSGuodong Xu if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3197d6786fefSGuodong Xu return -EPROBE_DEFER; 3198d6786fefSGuodong Xu } else if (IS_ERR(host->pdata)) { 3199c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 3200c91eab4bSThomas Abraham return -EINVAL; 3201c91eab4bSThomas Abraham } 3202f95f3850SWill Newton } 3203f95f3850SWill Newton 3204780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 3205f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 3206f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 3207f90a0612SThomas Abraham } else { 3208f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 3209f90a0612SThomas Abraham if (ret) { 3210f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 3211f90a0612SThomas Abraham return ret; 3212f90a0612SThomas Abraham } 3213f95f3850SWill Newton } 3214f95f3850SWill Newton 3215780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3216f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 3217f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 32183c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 3219f90a0612SThomas Abraham } else { 3220f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 3221f90a0612SThomas Abraham if (ret) { 3222f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 3223f90a0612SThomas Abraham goto err_clk_biu; 3224f90a0612SThomas Abraham } 3225f90a0612SThomas Abraham 32263c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 32273c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 32283c6d89eaSDoug Anderson if (ret) 32293c6d89eaSDoug Anderson dev_warn(host->dev, 3230612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 32313c6d89eaSDoug Anderson host->pdata->bus_hz); 32323c6d89eaSDoug Anderson } 3233f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 32343c6d89eaSDoug Anderson } 3235f90a0612SThomas Abraham 3236612de4c1SJaehoon Chung if (!host->bus_hz) { 3237612de4c1SJaehoon Chung dev_err(host->dev, 3238612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3239612de4c1SJaehoon Chung ret = -ENODEV; 3240612de4c1SJaehoon Chung goto err_clk_ciu; 3241612de4c1SJaehoon Chung } 3242612de4c1SJaehoon Chung 3243941e372dSliwei if (!IS_ERR(host->pdata->rstc)) { 3244941e372dSliwei reset_control_assert(host->pdata->rstc); 3245941e372dSliwei usleep_range(10, 50); 3246941e372dSliwei reset_control_deassert(host->pdata->rstc); 3247941e372dSliwei } 3248941e372dSliwei 3249002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3250002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3251002f0d5cSYuvaraj Kumar C D if (ret) { 3252002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3253002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3254002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3255002f0d5cSYuvaraj Kumar C D } 3256002f0d5cSYuvaraj Kumar C D } 3257002f0d5cSYuvaraj Kumar C D 325837977729SKees Cook timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 325937977729SKees Cook timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 326037977729SKees Cook timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 326157e10486SAddy Ke 3262f95f3850SWill Newton spin_lock_init(&host->lock); 3263f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3264f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3265f95f3850SWill Newton 3266f95f3850SWill Newton /* 3267f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3268f95f3850SWill Newton * the correct values. 3269f95f3850SWill Newton */ 327070692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3271f95f3850SWill Newton if (!i) { 3272f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3273f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3274f95f3850SWill Newton width = 16; 3275f95f3850SWill Newton host->data_shift = 1; 3276f95f3850SWill Newton } else if (i == 2) { 3277f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3278f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3279f95f3850SWill Newton width = 64; 3280f95f3850SWill Newton host->data_shift = 3; 3281f95f3850SWill Newton } else { 3282f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3283f95f3850SWill Newton WARN((i != 1), 3284f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3285f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3286f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3287f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3288f95f3850SWill Newton width = 32; 3289f95f3850SWill Newton host->data_shift = 2; 3290f95f3850SWill Newton } 3291f95f3850SWill Newton 3292f95f3850SWill Newton /* Reset all blocks */ 32933744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 32943744415cSShawn Lin ret = -ENODEV; 32953744415cSShawn Lin goto err_clk_ciu; 32963744415cSShawn Lin } 3297141a712aSSeungwon Jeon 3298141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3299141a712aSSeungwon Jeon dw_mci_init_dma(host); 3300f95f3850SWill Newton 3301f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3302f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3303f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3304f95f3850SWill Newton 3305f95f3850SWill Newton /* Put in max timeout */ 3306f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3307f95f3850SWill Newton 3308f95f3850SWill Newton /* 3309f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3310f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3311f95f3850SWill Newton */ 3312b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3313b86d8253SJames Hogan /* 3314b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3315b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3316b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3317b86d8253SJames Hogan * should put it in the platform data. 3318b86d8253SJames Hogan */ 3319f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 33208234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3321b86d8253SJames Hogan } else { 3322b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3323b86d8253SJames Hogan } 3324b86d8253SJames Hogan host->fifo_depth = fifo_size; 332552426899SSeungwon Jeon host->fifoth_val = 332652426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3327e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3328f95f3850SWill Newton 3329f95f3850SWill Newton /* disable clock to CIU */ 3330f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3331f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3332f95f3850SWill Newton 333363008768SJames Hogan /* 333463008768SJames Hogan * In 2.40a spec, Data offset is changed. 333563008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 333663008768SJames Hogan */ 333763008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 333863008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 333963008768SJames Hogan 3340a0361c1aSJun Nie if (host->data_addr_override) 3341a0361c1aSJun Nie host->fifo_reg = host->regs + host->data_addr_override; 3342a0361c1aSJun Nie else if (host->verid < DW_MMC_240A) 334376184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 334463008768SJames Hogan else 334576184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 334663008768SJames Hogan 3347f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3348780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3349780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3350f95f3850SWill Newton if (ret) 33516130e7a9SDoug Anderson goto err_dmaunmap; 3352f95f3850SWill Newton 3353d30a8f7bSJaehoon Chung /* 3354fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 33552da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 33562da1d7f2SYuvaraj CD */ 33572da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 33582da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3359fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 33600e3a22c0SShawn Lin /* Enable mci interrupt */ 33610e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 33622da1d7f2SYuvaraj CD 33630e3a22c0SShawn Lin dev_info(host->dev, 33640e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 33652da1d7f2SYuvaraj CD host->irq, width, fifo_size); 33662da1d7f2SYuvaraj CD 3367f95f3850SWill Newton /* We need at least one slot to succeed */ 3368e4a65ef7SJaehoon Chung ret = dw_mci_init_slot(host); 336958870241SJaehoon Chung if (ret) { 33701c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 33716130e7a9SDoug Anderson goto err_dmaunmap; 3372f95f3850SWill Newton } 3373f95f3850SWill Newton 3374b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3375b793f658SDoug Anderson dw_mci_enable_cd(host); 3376b793f658SDoug Anderson 3377f95f3850SWill Newton return 0; 3378f95f3850SWill Newton 3379f95f3850SWill Newton err_dmaunmap: 3380f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3381f95f3850SWill Newton host->dma_ops->exit(host); 3382f90a0612SThomas Abraham 3383d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3384d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3385d6786fefSGuodong Xu 3386f90a0612SThomas Abraham err_clk_ciu: 3387f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3388780f22afSSeungwon Jeon 3389f90a0612SThomas Abraham err_clk_biu: 3390f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3391780f22afSSeungwon Jeon 3392f95f3850SWill Newton return ret; 3393f95f3850SWill Newton } 339462ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3395f95f3850SWill Newton 339662ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3397f95f3850SWill Newton { 3398e4a65ef7SJaehoon Chung dev_dbg(host->dev, "remove slot\n"); 3399b23475faSJaehoon Chung if (host->slot) 3400e4a65ef7SJaehoon Chung dw_mci_cleanup_slot(host->slot); 3401f95f3850SWill Newton 3402048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3403048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3404048fd7e6SPrabu Thangamuthu 3405f95f3850SWill Newton /* disable clock to CIU */ 3406f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3407f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3408f95f3850SWill Newton 3409f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3410f95f3850SWill Newton host->dma_ops->exit(host); 3411f95f3850SWill Newton 3412d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3413d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3414d6786fefSGuodong Xu 3415f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3416f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3417f95f3850SWill Newton } 341862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 341962ca8034SShashidhar Hiremath 342062ca8034SShashidhar Hiremath 3421f95f3850SWill Newton 3422e9ed8835SShawn Lin #ifdef CONFIG_PM 3423ed24e1ffSShawn Lin int dw_mci_runtime_suspend(struct device *dev) 3424f95f3850SWill Newton { 3425ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3426ed24e1ffSShawn Lin 34273fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 34283fc7eaefSShawn Lin host->dma_ops->exit(host); 34293fc7eaefSShawn Lin 3430ed24e1ffSShawn Lin clk_disable_unprepare(host->ciu_clk); 3431ed24e1ffSShawn Lin 343242f989c0SJaehoon Chung if (host->slot && 343342f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 343442f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) 3435ed24e1ffSShawn Lin clk_disable_unprepare(host->biu_clk); 3436ed24e1ffSShawn Lin 3437f95f3850SWill Newton return 0; 3438f95f3850SWill Newton } 3439ed24e1ffSShawn Lin EXPORT_SYMBOL(dw_mci_runtime_suspend); 3440f95f3850SWill Newton 3441ed24e1ffSShawn Lin int dw_mci_runtime_resume(struct device *dev) 3442f95f3850SWill Newton { 3443b23475faSJaehoon Chung int ret = 0; 3444ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3445f95f3850SWill Newton 344642f989c0SJaehoon Chung if (host->slot && 344742f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 344842f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) { 3449ed24e1ffSShawn Lin ret = clk_prepare_enable(host->biu_clk); 3450ed24e1ffSShawn Lin if (ret) 3451e61cf118SJaehoon Chung return ret; 3452e61cf118SJaehoon Chung } 3453e61cf118SJaehoon Chung 3454ed24e1ffSShawn Lin ret = clk_prepare_enable(host->ciu_clk); 3455ed24e1ffSShawn Lin if (ret) 3456df9bcc2bSJoonyoung Shim goto err; 3457df9bcc2bSJoonyoung Shim 3458df9bcc2bSJoonyoung Shim if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3459df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->ciu_clk); 3460df9bcc2bSJoonyoung Shim ret = -ENODEV; 3461df9bcc2bSJoonyoung Shim goto err; 3462df9bcc2bSJoonyoung Shim } 3463ed24e1ffSShawn Lin 34643bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3465141a712aSSeungwon Jeon host->dma_ops->init(host); 3466141a712aSSeungwon Jeon 346752426899SSeungwon Jeon /* 346852426899SSeungwon Jeon * Restore the initial value at FIFOTH register 346952426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 347052426899SSeungwon Jeon */ 3471e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 347252426899SSeungwon Jeon host->prev_blksz = 0; 3473e61cf118SJaehoon Chung 34742eb2944fSDoug Anderson /* Put in max timeout */ 34752eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 34762eb2944fSDoug Anderson 3477e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3478e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3479e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3480fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3481e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3482e61cf118SJaehoon Chung 34830e3a22c0SShawn Lin 3484e47c0b96SJaehoon Chung if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3485e47c0b96SJaehoon Chung dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3486e9748e03SZiyuan Xu 3487e9748e03SZiyuan Xu /* Force setup bus to guarantee available clock output */ 3488e47c0b96SJaehoon Chung dw_mci_setup_bus(host->slot, true); 3489fa0c3283SDoug Anderson 3490fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3491fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3492fa0c3283SDoug Anderson 3493df9bcc2bSJoonyoung Shim return 0; 3494df9bcc2bSJoonyoung Shim 3495df9bcc2bSJoonyoung Shim err: 349642f989c0SJaehoon Chung if (host->slot && 349742f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 349842f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) 3499df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->biu_clk); 3500df9bcc2bSJoonyoung Shim 35011f5c51d7SShawn Lin return ret; 35021f5c51d7SShawn Lin } 3503e9ed8835SShawn Lin EXPORT_SYMBOL(dw_mci_runtime_resume); 3504e9ed8835SShawn Lin #endif /* CONFIG_PM */ 35056fe8890dSJaehoon Chung 3506f95f3850SWill Newton static int __init dw_mci_init(void) 3507f95f3850SWill Newton { 35088e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 350962ca8034SShashidhar Hiremath return 0; 3510f95f3850SWill Newton } 3511f95f3850SWill Newton 3512f95f3850SWill Newton static void __exit dw_mci_exit(void) 3513f95f3850SWill Newton { 3514f95f3850SWill Newton } 3515f95f3850SWill Newton 3516f95f3850SWill Newton module_init(dw_mci_init); 3517f95f3850SWill Newton module_exit(dw_mci_exit); 3518f95f3850SWill Newton 3519f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3520f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3521f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3522f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3523