1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47f95f3850SWill Newton SDMMC_INT_EBE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49f95f3850SWill Newton SDMMC_INT_RESP_ERR) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51f95f3850SWill Newton DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 6569d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6669d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6769d99fdcSPrabu Thangamuthu 6869d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6969d99fdcSPrabu Thangamuthu 7069d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7169d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 726687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 736687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7469d99fdcSPrabu Thangamuthu 7569d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7669d99fdcSPrabu Thangamuthu 7769d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7969d99fdcSPrabu Thangamuthu 8069d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8269d99fdcSPrabu Thangamuthu }; 8369d99fdcSPrabu Thangamuthu 84f95f3850SWill Newton struct idmac_desc { 856687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 86f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 87f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 88f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 89f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 90f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 91f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 92f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 93f95f3850SWill Newton 946687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 95f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 969b7bbe10SShashidhar Hiremath ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 97f95f3850SWill Newton 986687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 99f95f3850SWill Newton 1006687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 101f95f3850SWill Newton }; 102f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 103f95f3850SWill Newton 1043a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 105536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 1060bdbd0e8SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc); 10731bff450SSeungwon Jeon 108f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 109f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 110f95f3850SWill Newton { 111f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 112f95f3850SWill Newton struct mmc_request *mrq; 113f95f3850SWill Newton struct mmc_command *cmd; 114f95f3850SWill Newton struct mmc_command *stop; 115f95f3850SWill Newton struct mmc_data *data; 116f95f3850SWill Newton 117f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 118f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 119f95f3850SWill Newton mrq = slot->mrq; 120f95f3850SWill Newton 121f95f3850SWill Newton if (mrq) { 122f95f3850SWill Newton cmd = mrq->cmd; 123f95f3850SWill Newton data = mrq->data; 124f95f3850SWill Newton stop = mrq->stop; 125f95f3850SWill Newton 126f95f3850SWill Newton if (cmd) 127f95f3850SWill Newton seq_printf(s, 128f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 129f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 130f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 131f95f3850SWill Newton cmd->resp[2], cmd->error); 132f95f3850SWill Newton if (data) 133f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 134f95f3850SWill Newton data->bytes_xfered, data->blocks, 135f95f3850SWill Newton data->blksz, data->flags, data->error); 136f95f3850SWill Newton if (stop) 137f95f3850SWill Newton seq_printf(s, 138f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 139f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 140f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 141f95f3850SWill Newton stop->resp[2], stop->error); 142f95f3850SWill Newton } 143f95f3850SWill Newton 144f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 145f95f3850SWill Newton 146f95f3850SWill Newton return 0; 147f95f3850SWill Newton } 148f95f3850SWill Newton 149f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 150f95f3850SWill Newton { 151f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 152f95f3850SWill Newton } 153f95f3850SWill Newton 154f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 155f95f3850SWill Newton .owner = THIS_MODULE, 156f95f3850SWill Newton .open = dw_mci_req_open, 157f95f3850SWill Newton .read = seq_read, 158f95f3850SWill Newton .llseek = seq_lseek, 159f95f3850SWill Newton .release = single_release, 160f95f3850SWill Newton }; 161f95f3850SWill Newton 162f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 163f95f3850SWill Newton { 164f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 165f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 166f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 167f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 168f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 169f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 170f95f3850SWill Newton 171f95f3850SWill Newton return 0; 172f95f3850SWill Newton } 173f95f3850SWill Newton 174f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 175f95f3850SWill Newton { 176f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 177f95f3850SWill Newton } 178f95f3850SWill Newton 179f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 180f95f3850SWill Newton .owner = THIS_MODULE, 181f95f3850SWill Newton .open = dw_mci_regs_open, 182f95f3850SWill Newton .read = seq_read, 183f95f3850SWill Newton .llseek = seq_lseek, 184f95f3850SWill Newton .release = single_release, 185f95f3850SWill Newton }; 186f95f3850SWill Newton 187f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 188f95f3850SWill Newton { 189f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 190f95f3850SWill Newton struct dw_mci *host = slot->host; 191f95f3850SWill Newton struct dentry *root; 192f95f3850SWill Newton struct dentry *node; 193f95f3850SWill Newton 194f95f3850SWill Newton root = mmc->debugfs_root; 195f95f3850SWill Newton if (!root) 196f95f3850SWill Newton return; 197f95f3850SWill Newton 198f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 199f95f3850SWill Newton &dw_mci_regs_fops); 200f95f3850SWill Newton if (!node) 201f95f3850SWill Newton goto err; 202f95f3850SWill Newton 203f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 204f95f3850SWill Newton &dw_mci_req_fops); 205f95f3850SWill Newton if (!node) 206f95f3850SWill Newton goto err; 207f95f3850SWill Newton 208f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 209f95f3850SWill Newton if (!node) 210f95f3850SWill Newton goto err; 211f95f3850SWill Newton 212f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 213f95f3850SWill Newton (u32 *)&host->pending_events); 214f95f3850SWill Newton if (!node) 215f95f3850SWill Newton goto err; 216f95f3850SWill Newton 217f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 218f95f3850SWill Newton (u32 *)&host->completed_events); 219f95f3850SWill Newton if (!node) 220f95f3850SWill Newton goto err; 221f95f3850SWill Newton 222f95f3850SWill Newton return; 223f95f3850SWill Newton 224f95f3850SWill Newton err: 225f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 226f95f3850SWill Newton } 227f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 228f95f3850SWill Newton 22901730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 23001730558SDoug Anderson 231f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 232f95f3850SWill Newton { 233f95f3850SWill Newton struct mmc_data *data; 234800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23501730558SDoug Anderson struct dw_mci *host = slot->host; 236e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 237f95f3850SWill Newton u32 cmdr; 238f95f3850SWill Newton cmd->error = -EINPROGRESS; 239f95f3850SWill Newton 240f95f3850SWill Newton cmdr = cmd->opcode; 241f95f3850SWill Newton 24290c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24390c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24590c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24690c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 247f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2484a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 249f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 250f95f3850SWill Newton 25101730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25201730558SDoug Anderson u32 clk_en_a; 25301730558SDoug Anderson 25401730558SDoug Anderson /* Special bit makes CMD11 not die */ 25501730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25601730558SDoug Anderson 25701730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25801730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 25901730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 26001730558SDoug Anderson 26101730558SDoug Anderson /* 26201730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26301730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26401730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26501730558SDoug Anderson * voltage change dance. 26601730558SDoug Anderson * 26701730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26801730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 26901730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 27001730558SDoug Anderson * until the voltage change is all done. 27101730558SDoug Anderson */ 27201730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27301730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27401730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27501730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27601730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27701730558SDoug Anderson } 27801730558SDoug Anderson 279f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 280f95f3850SWill Newton /* We expect a response, so set this bit */ 281f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 282f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 283f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 284f95f3850SWill Newton } 285f95f3850SWill Newton 286f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 287f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 288f95f3850SWill Newton 289f95f3850SWill Newton data = cmd->data; 290f95f3850SWill Newton if (data) { 291f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 292f95f3850SWill Newton if (data->flags & MMC_DATA_STREAM) 293f95f3850SWill Newton cmdr |= SDMMC_CMD_STRM_MODE; 294f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 295f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 296f95f3850SWill Newton } 297f95f3850SWill Newton 298cb27a843SJames Hogan if (drv_data && drv_data->prepare_command) 299cb27a843SJames Hogan drv_data->prepare_command(slot->host, &cmdr); 300800d78bfSThomas Abraham 301f95f3850SWill Newton return cmdr; 302f95f3850SWill Newton } 303f95f3850SWill Newton 30490c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30590c2143aSSeungwon Jeon { 30690c2143aSSeungwon Jeon struct mmc_command *stop; 30790c2143aSSeungwon Jeon u32 cmdr; 30890c2143aSSeungwon Jeon 30990c2143aSSeungwon Jeon if (!cmd->data) 31090c2143aSSeungwon Jeon return 0; 31190c2143aSSeungwon Jeon 31290c2143aSSeungwon Jeon stop = &host->stop_abort; 31390c2143aSSeungwon Jeon cmdr = cmd->opcode; 31490c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31590c2143aSSeungwon Jeon 31690c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31790c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31890c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3196c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3206c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3216c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 32290c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 32390c2143aSSeungwon Jeon stop->arg = 0; 32490c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32590c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32690c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32790c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32890c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 32990c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 33090c2143aSSeungwon Jeon } else { 33190c2143aSSeungwon Jeon return 0; 33290c2143aSSeungwon Jeon } 33390c2143aSSeungwon Jeon 33490c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33590c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33690c2143aSSeungwon Jeon 33790c2143aSSeungwon Jeon return cmdr; 33890c2143aSSeungwon Jeon } 33990c2143aSSeungwon Jeon 3400bdbd0e8SDoug Anderson static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 3410bdbd0e8SDoug Anderson { 3420bdbd0e8SDoug Anderson unsigned long timeout = jiffies + msecs_to_jiffies(500); 3430bdbd0e8SDoug Anderson 3440bdbd0e8SDoug Anderson /* 3450bdbd0e8SDoug Anderson * Databook says that before issuing a new data transfer command 3460bdbd0e8SDoug Anderson * we need to check to see if the card is busy. Data transfer commands 3470bdbd0e8SDoug Anderson * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 3480bdbd0e8SDoug Anderson * 3490bdbd0e8SDoug Anderson * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 3500bdbd0e8SDoug Anderson * expected. 3510bdbd0e8SDoug Anderson */ 3520bdbd0e8SDoug Anderson if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 3530bdbd0e8SDoug Anderson !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 3540bdbd0e8SDoug Anderson while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 3550bdbd0e8SDoug Anderson if (time_after(jiffies, timeout)) { 3560bdbd0e8SDoug Anderson /* Command will fail; we'll pass error then */ 3570bdbd0e8SDoug Anderson dev_err(host->dev, "Busy; trying anyway\n"); 3580bdbd0e8SDoug Anderson break; 3590bdbd0e8SDoug Anderson } 3600bdbd0e8SDoug Anderson udelay(10); 3610bdbd0e8SDoug Anderson } 3620bdbd0e8SDoug Anderson } 3630bdbd0e8SDoug Anderson } 3640bdbd0e8SDoug Anderson 365f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 366f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 367f95f3850SWill Newton { 368f95f3850SWill Newton host->cmd = cmd; 3694a90920cSThomas Abraham dev_vdbg(host->dev, 370f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 371f95f3850SWill Newton cmd->arg, cmd_flags); 372f95f3850SWill Newton 373f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 374f95f3850SWill Newton wmb(); 3750bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 376f95f3850SWill Newton 377f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 378f95f3850SWill Newton } 379f95f3850SWill Newton 38090c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 381f95f3850SWill Newton { 38290c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 38390c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 384f95f3850SWill Newton } 385f95f3850SWill Newton 386f95f3850SWill Newton /* DMA interface functions */ 387f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 388f95f3850SWill Newton { 38903e8cb53SJames Hogan if (host->using_dma) { 390f95f3850SWill Newton host->dma_ops->stop(host); 391f95f3850SWill Newton host->dma_ops->cleanup(host); 392aa50f259SSeungwon Jeon } 393aa50f259SSeungwon Jeon 394f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 395f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 396f95f3850SWill Newton } 397f95f3850SWill Newton 3989aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 3999aa51408SSeungwon Jeon { 4009aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4019aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4029aa51408SSeungwon Jeon else 4039aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4049aa51408SSeungwon Jeon } 4059aa51408SSeungwon Jeon 4069beee912SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 407f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 408f95f3850SWill Newton { 409f95f3850SWill Newton struct mmc_data *data = host->data; 410f95f3850SWill Newton 411f95f3850SWill Newton if (data) 4129aa51408SSeungwon Jeon if (!data->host_cookie) 4134a90920cSThomas Abraham dma_unmap_sg(host->dev, 4149aa51408SSeungwon Jeon data->sg, 4159aa51408SSeungwon Jeon data->sg_len, 4169aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 417f95f3850SWill Newton } 418f95f3850SWill Newton 4195ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4205ce9d961SSeungwon Jeon { 4215ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4225ce9d961SSeungwon Jeon /* Software reset of DMA */ 4235ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4245ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4255ce9d961SSeungwon Jeon } 4265ce9d961SSeungwon Jeon 427f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 428f95f3850SWill Newton { 429f95f3850SWill Newton u32 temp; 430f95f3850SWill Newton 431f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 432f95f3850SWill Newton temp = mci_readl(host, CTRL); 433f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 434f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 435f95f3850SWill Newton mci_writel(host, CTRL, temp); 436f95f3850SWill Newton 437f95f3850SWill Newton /* Stop the IDMAC running */ 438f95f3850SWill Newton temp = mci_readl(host, BMOD); 439a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4405ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 441f95f3850SWill Newton mci_writel(host, BMOD, temp); 442f95f3850SWill Newton } 443f95f3850SWill Newton 444f95f3850SWill Newton static void dw_mci_idmac_complete_dma(struct dw_mci *host) 445f95f3850SWill Newton { 446f95f3850SWill Newton struct mmc_data *data = host->data; 447f95f3850SWill Newton 4484a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 449f95f3850SWill Newton 450f95f3850SWill Newton host->dma_ops->cleanup(host); 451f95f3850SWill Newton 452f95f3850SWill Newton /* 453f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 454f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 455f95f3850SWill Newton */ 456f95f3850SWill Newton if (data) { 457f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 458f95f3850SWill Newton tasklet_schedule(&host->tasklet); 459f95f3850SWill Newton } 460f95f3850SWill Newton } 461f95f3850SWill Newton 462f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 463f95f3850SWill Newton unsigned int sg_len) 464f95f3850SWill Newton { 465f95f3850SWill Newton int i; 46669d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 46769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *desc = host->sg_cpu; 46869d99fdcSPrabu Thangamuthu 46969d99fdcSPrabu Thangamuthu for (i = 0; i < sg_len; i++, desc++) { 47069d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 47169d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 47269d99fdcSPrabu Thangamuthu 47369d99fdcSPrabu Thangamuthu /* 47469d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 47569d99fdcSPrabu Thangamuthu * descriptor 47669d99fdcSPrabu Thangamuthu */ 47769d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 47869d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 47969d99fdcSPrabu Thangamuthu /* Buffer length */ 48069d99fdcSPrabu Thangamuthu IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length); 48169d99fdcSPrabu Thangamuthu 48269d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 48369d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 48469d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 48569d99fdcSPrabu Thangamuthu } 48669d99fdcSPrabu Thangamuthu 48769d99fdcSPrabu Thangamuthu /* Set first descriptor */ 48869d99fdcSPrabu Thangamuthu desc = host->sg_cpu; 48969d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_FD; 49069d99fdcSPrabu Thangamuthu 49169d99fdcSPrabu Thangamuthu /* Set last descriptor */ 49269d99fdcSPrabu Thangamuthu desc = host->sg_cpu + (i - 1) * 49369d99fdcSPrabu Thangamuthu sizeof(struct idmac_desc_64addr); 49469d99fdcSPrabu Thangamuthu desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 49569d99fdcSPrabu Thangamuthu desc->des0 |= IDMAC_DES0_LD; 49669d99fdcSPrabu Thangamuthu 49769d99fdcSPrabu Thangamuthu } else { 498f95f3850SWill Newton struct idmac_desc *desc = host->sg_cpu; 499f95f3850SWill Newton 500f95f3850SWill Newton for (i = 0; i < sg_len; i++, desc++) { 501f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 502f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 503f95f3850SWill Newton 50469d99fdcSPrabu Thangamuthu /* 50569d99fdcSPrabu Thangamuthu * Set the OWN bit and disable interrupts for this 50669d99fdcSPrabu Thangamuthu * descriptor 50769d99fdcSPrabu Thangamuthu */ 5086687c42fSBen Dooks desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 5096687c42fSBen Dooks IDMAC_DES0_DIC | IDMAC_DES0_CH); 510f95f3850SWill Newton /* Buffer length */ 511f95f3850SWill Newton IDMAC_SET_BUFFER1_SIZE(desc, length); 512f95f3850SWill Newton 513f95f3850SWill Newton /* Physical address to DMA to/from */ 5146687c42fSBen Dooks desc->des2 = cpu_to_le32(mem_addr); 515f95f3850SWill Newton } 516f95f3850SWill Newton 517f95f3850SWill Newton /* Set first descriptor */ 518f95f3850SWill Newton desc = host->sg_cpu; 5196687c42fSBen Dooks desc->des0 |= cpu_to_le32(IDMAC_DES0_FD); 520f95f3850SWill Newton 521f95f3850SWill Newton /* Set last descriptor */ 522f95f3850SWill Newton desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 5236687c42fSBen Dooks desc->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC)); 5246687c42fSBen Dooks desc->des0 |= cpu_to_le32(IDMAC_DES0_LD); 52569d99fdcSPrabu Thangamuthu } 526f95f3850SWill Newton 527f95f3850SWill Newton wmb(); 528f95f3850SWill Newton } 529f95f3850SWill Newton 530f95f3850SWill Newton static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 531f95f3850SWill Newton { 532f95f3850SWill Newton u32 temp; 533f95f3850SWill Newton 534f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 535f95f3850SWill Newton 536536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 537536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 538536f6b91SSonny Rao dw_mci_idmac_reset(host); 539536f6b91SSonny Rao 540f95f3850SWill Newton /* Select IDMAC interface */ 541f95f3850SWill Newton temp = mci_readl(host, CTRL); 542f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 543f95f3850SWill Newton mci_writel(host, CTRL, temp); 544f95f3850SWill Newton 545f95f3850SWill Newton wmb(); 546f95f3850SWill Newton 547f95f3850SWill Newton /* Enable the IDMAC */ 548f95f3850SWill Newton temp = mci_readl(host, BMOD); 549a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 550f95f3850SWill Newton mci_writel(host, BMOD, temp); 551f95f3850SWill Newton 552f95f3850SWill Newton /* Start it running */ 553f95f3850SWill Newton mci_writel(host, PLDMND, 1); 554f95f3850SWill Newton } 555f95f3850SWill Newton 556f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 557f95f3850SWill Newton { 558897b69e7SSeungwon Jeon int i; 559f95f3850SWill Newton 56069d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 56169d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 56269d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 56369d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 56469d99fdcSPrabu Thangamuthu 56569d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 56669d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 56769d99fdcSPrabu Thangamuthu i++, p++) { 56869d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 56969d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 57069d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 57169d99fdcSPrabu Thangamuthu 57269d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 57369d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 57469d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 57569d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 57669d99fdcSPrabu Thangamuthu p->des1 = 0; 57769d99fdcSPrabu Thangamuthu p->des2 = 0; 57869d99fdcSPrabu Thangamuthu p->des3 = 0; 57969d99fdcSPrabu Thangamuthu } 58069d99fdcSPrabu Thangamuthu 58169d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 58269d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 58369d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 58469d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 58569d99fdcSPrabu Thangamuthu 58669d99fdcSPrabu Thangamuthu } else { 58769d99fdcSPrabu Thangamuthu struct idmac_desc *p; 588f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 589f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 590f95f3850SWill Newton 591f95f3850SWill Newton /* Forward link the descriptor list */ 592f95f3850SWill Newton for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 5936687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 5946687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 595f95f3850SWill Newton 596f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 5976687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 5986687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 59969d99fdcSPrabu Thangamuthu } 600f95f3850SWill Newton 6015ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 602141a712aSSeungwon Jeon 60369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 60469d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 60569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 60669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 60769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 60869d99fdcSPrabu Thangamuthu 60969d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 61069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 61169d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 61269d99fdcSPrabu Thangamuthu 61369d99fdcSPrabu Thangamuthu } else { 614f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 615fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 61669d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 61769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 618f95f3850SWill Newton 619f95f3850SWill Newton /* Set the descriptor base address */ 620f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 62169d99fdcSPrabu Thangamuthu } 62269d99fdcSPrabu Thangamuthu 623f95f3850SWill Newton return 0; 624f95f3850SWill Newton } 625f95f3850SWill Newton 6268e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 627885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 628885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 629885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 630885c3e80SSeungwon Jeon .complete = dw_mci_idmac_complete_dma, 631885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 632885c3e80SSeungwon Jeon }; 633885c3e80SSeungwon Jeon #endif /* CONFIG_MMC_DW_IDMAC */ 634885c3e80SSeungwon Jeon 6359aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 6369aa51408SSeungwon Jeon struct mmc_data *data, 6379aa51408SSeungwon Jeon bool next) 638f95f3850SWill Newton { 639f95f3850SWill Newton struct scatterlist *sg; 6409aa51408SSeungwon Jeon unsigned int i, sg_len; 641f95f3850SWill Newton 6429aa51408SSeungwon Jeon if (!next && data->host_cookie) 6439aa51408SSeungwon Jeon return data->host_cookie; 644f95f3850SWill Newton 645f95f3850SWill Newton /* 646f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 647f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 648f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 649f95f3850SWill Newton */ 650f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 651f95f3850SWill Newton return -EINVAL; 6529aa51408SSeungwon Jeon 653f95f3850SWill Newton if (data->blksz & 3) 654f95f3850SWill Newton return -EINVAL; 655f95f3850SWill Newton 656f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 657f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 658f95f3850SWill Newton return -EINVAL; 659f95f3850SWill Newton } 660f95f3850SWill Newton 6614a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 6629aa51408SSeungwon Jeon data->sg, 6639aa51408SSeungwon Jeon data->sg_len, 6649aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 6659aa51408SSeungwon Jeon if (sg_len == 0) 6669aa51408SSeungwon Jeon return -EINVAL; 6679aa51408SSeungwon Jeon 6689aa51408SSeungwon Jeon if (next) 6699aa51408SSeungwon Jeon data->host_cookie = sg_len; 6709aa51408SSeungwon Jeon 6719aa51408SSeungwon Jeon return sg_len; 6729aa51408SSeungwon Jeon } 6739aa51408SSeungwon Jeon 6749aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 6759aa51408SSeungwon Jeon struct mmc_request *mrq, 6769aa51408SSeungwon Jeon bool is_first_req) 6779aa51408SSeungwon Jeon { 6789aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6799aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6809aa51408SSeungwon Jeon 6819aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 6829aa51408SSeungwon Jeon return; 6839aa51408SSeungwon Jeon 6849aa51408SSeungwon Jeon if (data->host_cookie) { 6859aa51408SSeungwon Jeon data->host_cookie = 0; 6869aa51408SSeungwon Jeon return; 6879aa51408SSeungwon Jeon } 6889aa51408SSeungwon Jeon 6899aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 6909aa51408SSeungwon Jeon data->host_cookie = 0; 6919aa51408SSeungwon Jeon } 6929aa51408SSeungwon Jeon 6939aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 6949aa51408SSeungwon Jeon struct mmc_request *mrq, 6959aa51408SSeungwon Jeon int err) 6969aa51408SSeungwon Jeon { 6979aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 6989aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 6999aa51408SSeungwon Jeon 7009aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 7019aa51408SSeungwon Jeon return; 7029aa51408SSeungwon Jeon 7039aa51408SSeungwon Jeon if (data->host_cookie) 7044a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 7059aa51408SSeungwon Jeon data->sg, 7069aa51408SSeungwon Jeon data->sg_len, 7079aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 7089aa51408SSeungwon Jeon data->host_cookie = 0; 7099aa51408SSeungwon Jeon } 7109aa51408SSeungwon Jeon 71152426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 71252426899SSeungwon Jeon { 71352426899SSeungwon Jeon #ifdef CONFIG_MMC_DW_IDMAC 71452426899SSeungwon Jeon unsigned int blksz = data->blksz; 71552426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 71652426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 71752426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 71852426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 71952426899SSeungwon Jeon int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; 72052426899SSeungwon Jeon 72152426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 72252426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 72352426899SSeungwon Jeon 72452426899SSeungwon Jeon /* 72552426899SSeungwon Jeon * MSIZE is '1', 72652426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 72752426899SSeungwon Jeon */ 72852426899SSeungwon Jeon if (blksz % fifo_width) { 72952426899SSeungwon Jeon msize = 0; 73052426899SSeungwon Jeon rx_wmark = 1; 73152426899SSeungwon Jeon goto done; 73252426899SSeungwon Jeon } 73352426899SSeungwon Jeon 73452426899SSeungwon Jeon do { 73552426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 73652426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 73752426899SSeungwon Jeon msize = idx; 73852426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 73952426899SSeungwon Jeon break; 74052426899SSeungwon Jeon } 74152426899SSeungwon Jeon } while (--idx > 0); 74252426899SSeungwon Jeon /* 74352426899SSeungwon Jeon * If idx is '0', it won't be tried 74452426899SSeungwon Jeon * Thus, initial values are uesed 74552426899SSeungwon Jeon */ 74652426899SSeungwon Jeon done: 74752426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 74852426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 74952426899SSeungwon Jeon #endif 75052426899SSeungwon Jeon } 75152426899SSeungwon Jeon 752f1d2736cSSeungwon Jeon static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 753f1d2736cSSeungwon Jeon { 754f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 755f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 756f1d2736cSSeungwon Jeon u16 thld_size; 757f1d2736cSSeungwon Jeon 758f1d2736cSSeungwon Jeon WARN_ON(!(data->flags & MMC_DATA_READ)); 759f1d2736cSSeungwon Jeon 76066dfd101SJames Hogan /* 76166dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 76266dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 76366dfd101SJames Hogan */ 76466dfd101SJames Hogan if (host->verid < DW_MMC_240A) 76566dfd101SJames Hogan return; 76666dfd101SJames Hogan 767f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 768488b8d63SJaehoon Chung host->timing != MMC_TIMING_MMC_HS400 && 769f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 770f1d2736cSSeungwon Jeon goto disable; 771f1d2736cSSeungwon Jeon 772f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 773f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 774f1d2736cSSeungwon Jeon 775f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 776f1d2736cSSeungwon Jeon goto disable; 777f1d2736cSSeungwon Jeon 778f1d2736cSSeungwon Jeon /* 779f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 780f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 781f1d2736cSSeungwon Jeon * Currently just choose blksz. 782f1d2736cSSeungwon Jeon */ 783f1d2736cSSeungwon Jeon thld_size = blksz; 784f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 785f1d2736cSSeungwon Jeon return; 786f1d2736cSSeungwon Jeon 787f1d2736cSSeungwon Jeon disable: 788f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 789f1d2736cSSeungwon Jeon } 790f1d2736cSSeungwon Jeon 7919aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 7929aa51408SSeungwon Jeon { 793f8c58c11SDoug Anderson unsigned long irqflags; 7949aa51408SSeungwon Jeon int sg_len; 7959aa51408SSeungwon Jeon u32 temp; 7969aa51408SSeungwon Jeon 7979aa51408SSeungwon Jeon host->using_dma = 0; 7989aa51408SSeungwon Jeon 7999aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 8009aa51408SSeungwon Jeon if (!host->use_dma) 8019aa51408SSeungwon Jeon return -ENODEV; 8029aa51408SSeungwon Jeon 8039aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 804a99aa9b9SSeungwon Jeon if (sg_len < 0) { 805a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 8069aa51408SSeungwon Jeon return sg_len; 807a99aa9b9SSeungwon Jeon } 8089aa51408SSeungwon Jeon 80903e8cb53SJames Hogan host->using_dma = 1; 81003e8cb53SJames Hogan 8114a90920cSThomas Abraham dev_vdbg(host->dev, 812f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 813f95f3850SWill Newton (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 814f95f3850SWill Newton sg_len); 815f95f3850SWill Newton 81652426899SSeungwon Jeon /* 81752426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 81852426899SSeungwon Jeon * If current block size is same with previous size, 81952426899SSeungwon Jeon * no need to update fifoth. 82052426899SSeungwon Jeon */ 82152426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 82252426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 82352426899SSeungwon Jeon 824f95f3850SWill Newton /* Enable the DMA interface */ 825f95f3850SWill Newton temp = mci_readl(host, CTRL); 826f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 827f95f3850SWill Newton mci_writel(host, CTRL, temp); 828f95f3850SWill Newton 829f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 830f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 831f95f3850SWill Newton temp = mci_readl(host, INTMASK); 832f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 833f95f3850SWill Newton mci_writel(host, INTMASK, temp); 834f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 835f95f3850SWill Newton 836f95f3850SWill Newton host->dma_ops->start(host, sg_len); 837f95f3850SWill Newton 838f95f3850SWill Newton return 0; 839f95f3850SWill Newton } 840f95f3850SWill Newton 841f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 842f95f3850SWill Newton { 843f8c58c11SDoug Anderson unsigned long irqflags; 844f95f3850SWill Newton u32 temp; 845f95f3850SWill Newton 846f95f3850SWill Newton data->error = -EINPROGRESS; 847f95f3850SWill Newton 848f95f3850SWill Newton WARN_ON(host->data); 849f95f3850SWill Newton host->sg = NULL; 850f95f3850SWill Newton host->data = data; 851f95f3850SWill Newton 852f1d2736cSSeungwon Jeon if (data->flags & MMC_DATA_READ) { 85355c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 854f1d2736cSSeungwon Jeon dw_mci_ctrl_rd_thld(host, data); 855f1d2736cSSeungwon Jeon } else { 85655c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 857f1d2736cSSeungwon Jeon } 85855c5efbcSJames Hogan 859f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 860f9c2a0dcSSeungwon Jeon int flags = SG_MITER_ATOMIC; 861f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 862f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 863f9c2a0dcSSeungwon Jeon else 864f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 865f9c2a0dcSSeungwon Jeon 866f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 867f95f3850SWill Newton host->sg = data->sg; 86834b664a2SJames Hogan host->part_buf_start = 0; 86934b664a2SJames Hogan host->part_buf_count = 0; 870f95f3850SWill Newton 871b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 872f8c58c11SDoug Anderson 873f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 874f95f3850SWill Newton temp = mci_readl(host, INTMASK); 875f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 876f95f3850SWill Newton mci_writel(host, INTMASK, temp); 877f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 878f95f3850SWill Newton 879f95f3850SWill Newton temp = mci_readl(host, CTRL); 880f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 881f95f3850SWill Newton mci_writel(host, CTRL, temp); 88252426899SSeungwon Jeon 88352426899SSeungwon Jeon /* 88452426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 88552426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 88652426899SSeungwon Jeon * prev_blksz should be invalidated. 88752426899SSeungwon Jeon */ 88852426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 88952426899SSeungwon Jeon host->prev_blksz = 0; 89052426899SSeungwon Jeon } else { 89152426899SSeungwon Jeon /* 89252426899SSeungwon Jeon * Keep the current block size. 89352426899SSeungwon Jeon * It will be used to decide whether to update 89452426899SSeungwon Jeon * fifoth register next time. 89552426899SSeungwon Jeon */ 89652426899SSeungwon Jeon host->prev_blksz = data->blksz; 897f95f3850SWill Newton } 898f95f3850SWill Newton } 899f95f3850SWill Newton 900f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 901f95f3850SWill Newton { 902f95f3850SWill Newton struct dw_mci *host = slot->host; 903f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 904f95f3850SWill Newton unsigned int cmd_status = 0; 905f95f3850SWill Newton 906f95f3850SWill Newton mci_writel(host, CMDARG, arg); 907f95f3850SWill Newton wmb(); 9080bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd); 909f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 910f95f3850SWill Newton 911f95f3850SWill Newton while (time_before(jiffies, timeout)) { 912f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 913f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 914f95f3850SWill Newton return; 915f95f3850SWill Newton } 916f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 917f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 918f95f3850SWill Newton cmd, arg, cmd_status); 919f95f3850SWill Newton } 920f95f3850SWill Newton 921ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 922f95f3850SWill Newton { 923f95f3850SWill Newton struct dw_mci *host = slot->host; 924fdf492a1SDoug Anderson unsigned int clock = slot->clock; 925f95f3850SWill Newton u32 div; 9269623b5b9SDoug Anderson u32 clk_en_a; 92701730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 92801730558SDoug Anderson 92901730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 93001730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 93101730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 932f95f3850SWill Newton 933fdf492a1SDoug Anderson if (!clock) { 934fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 93501730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 936fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 937fdf492a1SDoug Anderson div = host->bus_hz / clock; 938fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 939f95f3850SWill Newton /* 940f95f3850SWill Newton * move the + 1 after the divide to prevent 941f95f3850SWill Newton * over-clocking the card. 942f95f3850SWill Newton */ 943e419990bSSeungwon Jeon div += 1; 944e419990bSSeungwon Jeon 945fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 946f95f3850SWill Newton 947fdf492a1SDoug Anderson if ((clock << div) != slot->__clk_old || force_clkinit) 948f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 949fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 950fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 951fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 952fdf492a1SDoug Anderson host->bus_hz, div); 953f95f3850SWill Newton 954f95f3850SWill Newton /* disable clock */ 955f95f3850SWill Newton mci_writel(host, CLKENA, 0); 956f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 957f95f3850SWill Newton 958f95f3850SWill Newton /* inform CIU */ 95901730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 960f95f3850SWill Newton 961f95f3850SWill Newton /* set clock to desired speed */ 962f95f3850SWill Newton mci_writel(host, CLKDIV, div); 963f95f3850SWill Newton 964f95f3850SWill Newton /* inform CIU */ 96501730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 966f95f3850SWill Newton 9679623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 9689623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 969b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 9709623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 9719623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 972f95f3850SWill Newton 973f95f3850SWill Newton /* inform CIU */ 97401730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 975f95f3850SWill Newton 976fdf492a1SDoug Anderson /* keep the clock with reflecting clock dividor */ 977fdf492a1SDoug Anderson slot->__clk_old = clock << div; 978f95f3850SWill Newton } 979f95f3850SWill Newton 980fdf492a1SDoug Anderson host->current_speed = clock; 981fdf492a1SDoug Anderson 982f95f3850SWill Newton /* Set the current slot bus width */ 9831d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 984f95f3850SWill Newton } 985f95f3850SWill Newton 986053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 987053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 988053b3ce6SSeungwon Jeon struct mmc_command *cmd) 989f95f3850SWill Newton { 990f95f3850SWill Newton struct mmc_request *mrq; 991f95f3850SWill Newton struct mmc_data *data; 992f95f3850SWill Newton u32 cmdflags; 993f95f3850SWill Newton 994f95f3850SWill Newton mrq = slot->mrq; 995f95f3850SWill Newton 996f95f3850SWill Newton host->cur_slot = slot; 997f95f3850SWill Newton host->mrq = mrq; 998f95f3850SWill Newton 999f95f3850SWill Newton host->pending_events = 0; 1000f95f3850SWill Newton host->completed_events = 0; 1001e352c813SSeungwon Jeon host->cmd_status = 0; 1002f95f3850SWill Newton host->data_status = 0; 1003e352c813SSeungwon Jeon host->dir_status = 0; 1004f95f3850SWill Newton 1005053b3ce6SSeungwon Jeon data = cmd->data; 1006f95f3850SWill Newton if (data) { 1007f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1008f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1009f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1010f95f3850SWill Newton } 1011f95f3850SWill Newton 1012f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1013f95f3850SWill Newton 1014f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1015f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1016f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1017f95f3850SWill Newton 1018f95f3850SWill Newton if (data) { 1019f95f3850SWill Newton dw_mci_submit_data(host, data); 1020f95f3850SWill Newton wmb(); 1021f95f3850SWill Newton } 1022f95f3850SWill Newton 1023f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1024f95f3850SWill Newton 10255c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 10265c935165SDoug Anderson /* 10275c935165SDoug Anderson * Databook says to fail after 2ms w/ no response; give an 10285c935165SDoug Anderson * extra jiffy just in case we're about to roll over. 10295c935165SDoug Anderson */ 10305c935165SDoug Anderson mod_timer(&host->cmd11_timer, 10315c935165SDoug Anderson jiffies + msecs_to_jiffies(2) + 1); 10325c935165SDoug Anderson } 10335c935165SDoug Anderson 1034f95f3850SWill Newton if (mrq->stop) 1035f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 103690c2143aSSeungwon Jeon else 103790c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1038f95f3850SWill Newton } 1039f95f3850SWill Newton 1040053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1041053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1042053b3ce6SSeungwon Jeon { 1043053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1044053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1045053b3ce6SSeungwon Jeon 1046053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1047053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1048053b3ce6SSeungwon Jeon } 1049053b3ce6SSeungwon Jeon 10507456caaeSJames Hogan /* must be called with host->lock held */ 1051f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1052f95f3850SWill Newton struct mmc_request *mrq) 1053f95f3850SWill Newton { 1054f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1055f95f3850SWill Newton host->state); 1056f95f3850SWill Newton 1057f95f3850SWill Newton slot->mrq = mrq; 1058f95f3850SWill Newton 105901730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 106001730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 106101730558SDoug Anderson "Voltage change didn't complete\n"); 106201730558SDoug Anderson /* 106301730558SDoug Anderson * this case isn't expected to happen, so we can 106401730558SDoug Anderson * either crash here or just try to continue on 106501730558SDoug Anderson * in the closest possible state 106601730558SDoug Anderson */ 106701730558SDoug Anderson host->state = STATE_IDLE; 106801730558SDoug Anderson } 106901730558SDoug Anderson 1070f95f3850SWill Newton if (host->state == STATE_IDLE) { 1071f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1072f95f3850SWill Newton dw_mci_start_request(host, slot); 1073f95f3850SWill Newton } else { 1074f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1075f95f3850SWill Newton } 1076f95f3850SWill Newton } 1077f95f3850SWill Newton 1078f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1079f95f3850SWill Newton { 1080f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1081f95f3850SWill Newton struct dw_mci *host = slot->host; 1082f95f3850SWill Newton 1083f95f3850SWill Newton WARN_ON(slot->mrq); 1084f95f3850SWill Newton 10857456caaeSJames Hogan /* 10867456caaeSJames Hogan * The check for card presence and queueing of the request must be 10877456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 10887456caaeSJames Hogan * request wouldn't fail until another card was inserted. 10897456caaeSJames Hogan */ 10907456caaeSJames Hogan spin_lock_bh(&host->lock); 10917456caaeSJames Hogan 1092f95f3850SWill Newton if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 10937456caaeSJames Hogan spin_unlock_bh(&host->lock); 1094f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1095f95f3850SWill Newton mmc_request_done(mmc, mrq); 1096f95f3850SWill Newton return; 1097f95f3850SWill Newton } 1098f95f3850SWill Newton 1099f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 11007456caaeSJames Hogan 11017456caaeSJames Hogan spin_unlock_bh(&host->lock); 1102f95f3850SWill Newton } 1103f95f3850SWill Newton 1104f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1105f95f3850SWill Newton { 1106f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1107e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 110841babf75SJaehoon Chung u32 regs; 110951da2240SYuvaraj CD int ret; 1110f95f3850SWill Newton 1111f95f3850SWill Newton switch (ios->bus_width) { 1112f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1113f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1114f95f3850SWill Newton break; 1115c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1116c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1117c9b2a06fSJaehoon Chung break; 1118b2f7cb45SJaehoon Chung default: 1119b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1120b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1121f95f3850SWill Newton } 1122f95f3850SWill Newton 112341babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 11243f514291SSeungwon Jeon 11253f514291SSeungwon Jeon /* DDR mode set */ 112680113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 112780113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1128c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 11293f514291SSeungwon Jeon else 1130c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 11313f514291SSeungwon Jeon 113241babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1133f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 113441babf75SJaehoon Chung 1135f95f3850SWill Newton /* 1136f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1137f95f3850SWill Newton * core ios update when finding the minimum. 1138f95f3850SWill Newton */ 1139f95f3850SWill Newton slot->clock = ios->clock; 1140f95f3850SWill Newton 1141cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1142cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1143800d78bfSThomas Abraham 1144f95f3850SWill Newton switch (ios->power_mode) { 1145f95f3850SWill Newton case MMC_POWER_UP: 114651da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 114751da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 114851da2240SYuvaraj CD ios->vdd); 114951da2240SYuvaraj CD if (ret) { 115051da2240SYuvaraj CD dev_err(slot->host->dev, 115151da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 115251da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 115351da2240SYuvaraj CD return; 115451da2240SYuvaraj CD } 115551da2240SYuvaraj CD } 115629d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 115729d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 115829d0d161SDoug Anderson regs |= (1 << slot->id); 115929d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 116029d0d161SDoug Anderson break; 116129d0d161SDoug Anderson case MMC_POWER_ON: 1162d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1163d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 116451da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 116551da2240SYuvaraj CD if (ret < 0) 116651da2240SYuvaraj CD dev_err(slot->host->dev, 1167d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 116851da2240SYuvaraj CD else 116951da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1170d1f1dd86SDoug Anderson 1171d1f1dd86SDoug Anderson } else { 1172d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1173d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1174d1f1dd86SDoug Anderson } 1175d1f1dd86SDoug Anderson 1176d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1177d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1178d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 117951da2240SYuvaraj CD } 1180655babbdSDoug Anderson 1181655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1182655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1183655babbdSDoug Anderson 1184e6f34e2fSJames Hogan break; 1185e6f34e2fSJames Hogan case MMC_POWER_OFF: 1186655babbdSDoug Anderson /* Turn clock off before power goes down */ 1187655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1188655babbdSDoug Anderson 118951da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 119051da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 119151da2240SYuvaraj CD 1192d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 119351da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 119451da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 119551da2240SYuvaraj CD 11964366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 11974366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 11984366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1199f95f3850SWill Newton break; 1200f95f3850SWill Newton default: 1201f95f3850SWill Newton break; 1202f95f3850SWill Newton } 1203655babbdSDoug Anderson 1204655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1205655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1206f95f3850SWill Newton } 1207f95f3850SWill Newton 120801730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 120901730558SDoug Anderson { 121001730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 121101730558SDoug Anderson u32 status; 121201730558SDoug Anderson 121301730558SDoug Anderson /* 121401730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 121501730558SDoug Anderson * (the data lines) are 0000 121601730558SDoug Anderson */ 121701730558SDoug Anderson status = mci_readl(slot->host, STATUS); 121801730558SDoug Anderson 121901730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 122001730558SDoug Anderson } 122101730558SDoug Anderson 122201730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 122301730558SDoug Anderson { 122401730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 122501730558SDoug Anderson struct dw_mci *host = slot->host; 122601730558SDoug Anderson u32 uhs; 122701730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 122801730558SDoug Anderson int min_uv, max_uv; 122901730558SDoug Anderson int ret; 123001730558SDoug Anderson 123101730558SDoug Anderson /* 123201730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 123301730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 123401730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 123501730558SDoug Anderson */ 123601730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 123701730558SDoug Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 123801730558SDoug Anderson min_uv = 2700000; 123901730558SDoug Anderson max_uv = 3600000; 124001730558SDoug Anderson uhs &= ~v18; 124101730558SDoug Anderson } else { 124201730558SDoug Anderson min_uv = 1700000; 124301730558SDoug Anderson max_uv = 1950000; 124401730558SDoug Anderson uhs |= v18; 124501730558SDoug Anderson } 124601730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 124701730558SDoug Anderson ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 124801730558SDoug Anderson 124901730558SDoug Anderson if (ret) { 1250b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 125101730558SDoug Anderson "Regulator set error %d: %d - %d\n", 125201730558SDoug Anderson ret, min_uv, max_uv); 125301730558SDoug Anderson return ret; 125401730558SDoug Anderson } 125501730558SDoug Anderson } 125601730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 125701730558SDoug Anderson 125801730558SDoug Anderson return 0; 125901730558SDoug Anderson } 126001730558SDoug Anderson 1261f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1262f95f3850SWill Newton { 1263f95f3850SWill Newton int read_only; 1264f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 12659795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1266f95f3850SWill Newton 1267f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 126826375b5cSJaehoon Chung if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) || 126926375b5cSJaehoon Chung (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)) 1270b4967aa5SThomas Abraham read_only = 0; 12719795a846SJaehoon Chung else if (!IS_ERR_VALUE(gpio_ro)) 12729795a846SJaehoon Chung read_only = gpio_ro; 1273f95f3850SWill Newton else 1274f95f3850SWill Newton read_only = 1275f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1276f95f3850SWill Newton 1277f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1278f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1279f95f3850SWill Newton 1280f95f3850SWill Newton return read_only; 1281f95f3850SWill Newton } 1282f95f3850SWill Newton 1283f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1284f95f3850SWill Newton { 1285f95f3850SWill Newton int present; 1286f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1287f95f3850SWill Newton struct dw_mci_board *brd = slot->host->pdata; 12887cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 12897cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1290f95f3850SWill Newton 1291f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1292fc3d7720SJaehoon Chung if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 1293fc3d7720SJaehoon Chung present = 1; 1294bf626e55SZhangfei Gao else if (!IS_ERR_VALUE(gpio_cd)) 12957cf347bdSZhangfei Gao present = gpio_cd; 1296f95f3850SWill Newton else 1297f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1298f95f3850SWill Newton == 0 ? 1 : 0; 1299f95f3850SWill Newton 13007cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1301bf626e55SZhangfei Gao if (present) { 1302bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1303f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1304bf626e55SZhangfei Gao } else { 1305bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1306f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1307bf626e55SZhangfei Gao } 13087cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1309f95f3850SWill Newton 1310f95f3850SWill Newton return present; 1311f95f3850SWill Newton } 1312f95f3850SWill Newton 1313b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1314b24c8b26SDoug Anderson { 1315b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1316b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1317b24c8b26SDoug Anderson 13189623b5b9SDoug Anderson /* 13199623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 13209623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 13219623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 13229623b5b9SDoug Anderson */ 1323b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 13249623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1325b24c8b26SDoug Anderson u32 clk_en_a_old; 1326b24c8b26SDoug Anderson u32 clk_en_a; 13279623b5b9SDoug Anderson 1328b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 13299623b5b9SDoug Anderson 1330b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1331b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1332b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1333b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1334b24c8b26SDoug Anderson } else { 1335b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1336b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1337b24c8b26SDoug Anderson } 1338b24c8b26SDoug Anderson 1339b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1340b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 13419623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 13429623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 13439623b5b9SDoug Anderson } 13449623b5b9SDoug Anderson } 1345b24c8b26SDoug Anderson } 13469623b5b9SDoug Anderson 13471a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 13481a5c8e1fSShashidhar Hiremath { 13491a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 13501a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1351f8c58c11SDoug Anderson unsigned long irqflags; 13521a5c8e1fSShashidhar Hiremath u32 int_mask; 13531a5c8e1fSShashidhar Hiremath 1354f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1355f8c58c11SDoug Anderson 13561a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 13571a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1358b24c8b26SDoug Anderson if (enb) 1359b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1360b24c8b26SDoug Anderson else 1361b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1362b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1363f8c58c11SDoug Anderson 1364f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13651a5c8e1fSShashidhar Hiremath } 13661a5c8e1fSShashidhar Hiremath 13670976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 13680976f16dSSeungwon Jeon { 13690976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 13700976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 13710976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 13720976f16dSSeungwon Jeon int err = -ENOSYS; 13730976f16dSSeungwon Jeon 13740976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 13756c2c6506SUlf Hansson err = drv_data->execute_tuning(slot); 13760976f16dSSeungwon Jeon return err; 13770976f16dSSeungwon Jeon } 13780976f16dSSeungwon Jeon 1379c22f5e1bSWu Fengguang static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 138080113132SSeungwon Jeon { 138180113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 138280113132SSeungwon Jeon struct dw_mci *host = slot->host; 138380113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 138480113132SSeungwon Jeon 138580113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 138680113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 138780113132SSeungwon Jeon 138880113132SSeungwon Jeon return 0; 138980113132SSeungwon Jeon } 139080113132SSeungwon Jeon 1391f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1392f95f3850SWill Newton .request = dw_mci_request, 13939aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 13949aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1395f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1396f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1397f95f3850SWill Newton .get_cd = dw_mci_get_cd, 13981a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 13990976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 140001730558SDoug Anderson .card_busy = dw_mci_card_busy, 140101730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1402b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 140380113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1404f95f3850SWill Newton }; 1405f95f3850SWill Newton 1406f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1407f95f3850SWill Newton __releases(&host->lock) 1408f95f3850SWill Newton __acquires(&host->lock) 1409f95f3850SWill Newton { 1410f95f3850SWill Newton struct dw_mci_slot *slot; 1411f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1412f95f3850SWill Newton 1413f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1414f95f3850SWill Newton 1415f95f3850SWill Newton host->cur_slot->mrq = NULL; 1416f95f3850SWill Newton host->mrq = NULL; 1417f95f3850SWill Newton if (!list_empty(&host->queue)) { 1418f95f3850SWill Newton slot = list_entry(host->queue.next, 1419f95f3850SWill Newton struct dw_mci_slot, queue_node); 1420f95f3850SWill Newton list_del(&slot->queue_node); 14214a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1422f95f3850SWill Newton mmc_hostname(slot->mmc)); 1423f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1424f95f3850SWill Newton dw_mci_start_request(host, slot); 1425f95f3850SWill Newton } else { 14264a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 142701730558SDoug Anderson 142801730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 142901730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 143001730558SDoug Anderson else 1431f95f3850SWill Newton host->state = STATE_IDLE; 1432f95f3850SWill Newton } 1433f95f3850SWill Newton 1434f95f3850SWill Newton spin_unlock(&host->lock); 1435f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1436f95f3850SWill Newton spin_lock(&host->lock); 1437f95f3850SWill Newton } 1438f95f3850SWill Newton 1439e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1440f95f3850SWill Newton { 1441f95f3850SWill Newton u32 status = host->cmd_status; 1442f95f3850SWill Newton 1443f95f3850SWill Newton host->cmd_status = 0; 1444f95f3850SWill Newton 1445f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1446f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1447f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1448f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1449f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1450f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1451f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1452f95f3850SWill Newton } else { 1453f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1454f95f3850SWill Newton cmd->resp[1] = 0; 1455f95f3850SWill Newton cmd->resp[2] = 0; 1456f95f3850SWill Newton cmd->resp[3] = 0; 1457f95f3850SWill Newton } 1458f95f3850SWill Newton } 1459f95f3850SWill Newton 1460f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1461f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1462f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1463f95f3850SWill Newton cmd->error = -EILSEQ; 1464f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1465f95f3850SWill Newton cmd->error = -EIO; 1466f95f3850SWill Newton else 1467f95f3850SWill Newton cmd->error = 0; 1468f95f3850SWill Newton 1469f95f3850SWill Newton if (cmd->error) { 1470f95f3850SWill Newton /* newer ip versions need a delay between retries */ 1471f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1472f95f3850SWill Newton mdelay(20); 1473f95f3850SWill Newton } 1474e352c813SSeungwon Jeon 1475e352c813SSeungwon Jeon return cmd->error; 1476e352c813SSeungwon Jeon } 1477e352c813SSeungwon Jeon 1478e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1479e352c813SSeungwon Jeon { 148031bff450SSeungwon Jeon u32 status = host->data_status; 1481e352c813SSeungwon Jeon 1482e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1483e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1484e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1485e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1486e352c813SSeungwon Jeon data->error = -EILSEQ; 1487e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1488e352c813SSeungwon Jeon if (host->dir_status == 1489e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1490e352c813SSeungwon Jeon /* 1491e352c813SSeungwon Jeon * No data CRC status was returned. 1492e352c813SSeungwon Jeon * The number of bytes transferred 1493e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1494e352c813SSeungwon Jeon */ 1495e352c813SSeungwon Jeon data->bytes_xfered = 0; 1496e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1497e352c813SSeungwon Jeon } else if (host->dir_status == 1498e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1499e352c813SSeungwon Jeon data->error = -EIO; 1500e352c813SSeungwon Jeon } 1501e352c813SSeungwon Jeon } else { 1502e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1503e352c813SSeungwon Jeon data->error = -EIO; 1504e352c813SSeungwon Jeon } 1505e352c813SSeungwon Jeon 1506e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1507e352c813SSeungwon Jeon 1508e352c813SSeungwon Jeon /* 1509e352c813SSeungwon Jeon * After an error, there may be data lingering 151031bff450SSeungwon Jeon * in the FIFO 1511e352c813SSeungwon Jeon */ 15123a33a94cSSonny Rao dw_mci_reset(host); 1513e352c813SSeungwon Jeon } else { 1514e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1515e352c813SSeungwon Jeon data->error = 0; 1516e352c813SSeungwon Jeon } 1517e352c813SSeungwon Jeon 1518e352c813SSeungwon Jeon return data->error; 1519f95f3850SWill Newton } 1520f95f3850SWill Newton 1521f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1522f95f3850SWill Newton { 1523f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1524f95f3850SWill Newton struct mmc_data *data; 1525f95f3850SWill Newton struct mmc_command *cmd; 1526e352c813SSeungwon Jeon struct mmc_request *mrq; 1527f95f3850SWill Newton enum dw_mci_state state; 1528f95f3850SWill Newton enum dw_mci_state prev_state; 1529e352c813SSeungwon Jeon unsigned int err; 1530f95f3850SWill Newton 1531f95f3850SWill Newton spin_lock(&host->lock); 1532f95f3850SWill Newton 1533f95f3850SWill Newton state = host->state; 1534f95f3850SWill Newton data = host->data; 1535e352c813SSeungwon Jeon mrq = host->mrq; 1536f95f3850SWill Newton 1537f95f3850SWill Newton do { 1538f95f3850SWill Newton prev_state = state; 1539f95f3850SWill Newton 1540f95f3850SWill Newton switch (state) { 1541f95f3850SWill Newton case STATE_IDLE: 154201730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1543f95f3850SWill Newton break; 1544f95f3850SWill Newton 154501730558SDoug Anderson case STATE_SENDING_CMD11: 1546f95f3850SWill Newton case STATE_SENDING_CMD: 1547f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1548f95f3850SWill Newton &host->pending_events)) 1549f95f3850SWill Newton break; 1550f95f3850SWill Newton 1551f95f3850SWill Newton cmd = host->cmd; 1552f95f3850SWill Newton host->cmd = NULL; 1553f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1554e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1555e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1556053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1557053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1558e352c813SSeungwon Jeon mrq->cmd); 1559053b3ce6SSeungwon Jeon goto unlock; 1560053b3ce6SSeungwon Jeon } 1561053b3ce6SSeungwon Jeon 1562e352c813SSeungwon Jeon if (cmd->data && err) { 156371abb133SSeungwon Jeon dw_mci_stop_dma(host); 156490c2143aSSeungwon Jeon send_stop_abort(host, data); 156571abb133SSeungwon Jeon state = STATE_SENDING_STOP; 156671abb133SSeungwon Jeon break; 156771abb133SSeungwon Jeon } 156871abb133SSeungwon Jeon 1569e352c813SSeungwon Jeon if (!cmd->data || err) { 1570e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1571f95f3850SWill Newton goto unlock; 1572f95f3850SWill Newton } 1573f95f3850SWill Newton 1574f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1575f95f3850SWill Newton /* fall through */ 1576f95f3850SWill Newton 1577f95f3850SWill Newton case STATE_SENDING_DATA: 15782aa35465SDoug Anderson /* 15792aa35465SDoug Anderson * We could get a data error and never a transfer 15802aa35465SDoug Anderson * complete so we'd better check for it here. 15812aa35465SDoug Anderson * 15822aa35465SDoug Anderson * Note that we don't really care if we also got a 15832aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 15842aa35465SDoug Anderson * abort won't hurt. 15852aa35465SDoug Anderson */ 1586f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1587f95f3850SWill Newton &host->pending_events)) { 1588f95f3850SWill Newton dw_mci_stop_dma(host); 1589bdb9a90bSaddy ke if (data->stop || 1590bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1591bdb9a90bSaddy ke SDMMC_INT_EBE))) 159290c2143aSSeungwon Jeon send_stop_abort(host, data); 1593f95f3850SWill Newton state = STATE_DATA_ERROR; 1594f95f3850SWill Newton break; 1595f95f3850SWill Newton } 1596f95f3850SWill Newton 1597f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1598f95f3850SWill Newton &host->pending_events)) 1599f95f3850SWill Newton break; 1600f95f3850SWill Newton 1601f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 16022aa35465SDoug Anderson 16032aa35465SDoug Anderson /* 16042aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 16052aa35465SDoug Anderson * before the transfer completed. This might not have 16062aa35465SDoug Anderson * been caught by the check above because the interrupt 16072aa35465SDoug Anderson * could have gone off between the previous check and 16082aa35465SDoug Anderson * the check for transfer complete. 16092aa35465SDoug Anderson * 16102aa35465SDoug Anderson * Technically this ought not be needed assuming we 16112aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 16122aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 16132aa35465SDoug Anderson * 16142aa35465SDoug Anderson * This has the advantage of sending the stop command. 16152aa35465SDoug Anderson */ 16162aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 16172aa35465SDoug Anderson &host->pending_events)) { 16182aa35465SDoug Anderson dw_mci_stop_dma(host); 1619bdb9a90bSaddy ke if (data->stop || 1620bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1621bdb9a90bSaddy ke SDMMC_INT_EBE))) 16222aa35465SDoug Anderson send_stop_abort(host, data); 16232aa35465SDoug Anderson state = STATE_DATA_ERROR; 16242aa35465SDoug Anderson break; 16252aa35465SDoug Anderson } 1626f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 16272aa35465SDoug Anderson 1628f95f3850SWill Newton /* fall through */ 1629f95f3850SWill Newton 1630f95f3850SWill Newton case STATE_DATA_BUSY: 1631f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1632f95f3850SWill Newton &host->pending_events)) 1633f95f3850SWill Newton break; 1634f95f3850SWill Newton 1635f95f3850SWill Newton host->data = NULL; 1636f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1637e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1638f95f3850SWill Newton 1639e352c813SSeungwon Jeon if (!err) { 1640e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 164117c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1642053b3ce6SSeungwon Jeon data->stop->error = 0; 1643e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1644053b3ce6SSeungwon Jeon goto unlock; 1645053b3ce6SSeungwon Jeon } 1646053b3ce6SSeungwon Jeon 164790c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1648e352c813SSeungwon Jeon if (data->stop) 164990c2143aSSeungwon Jeon send_stop_abort(host, data); 16502aa35465SDoug Anderson } else { 16512aa35465SDoug Anderson /* 16522aa35465SDoug Anderson * If we don't have a command complete now we'll 16532aa35465SDoug Anderson * never get one since we just reset everything; 16542aa35465SDoug Anderson * better end the request. 16552aa35465SDoug Anderson * 16562aa35465SDoug Anderson * If we do have a command complete we'll fall 16572aa35465SDoug Anderson * through to the SENDING_STOP command and 16582aa35465SDoug Anderson * everything will be peachy keen. 16592aa35465SDoug Anderson */ 16602aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 16612aa35465SDoug Anderson &host->pending_events)) { 16622aa35465SDoug Anderson host->cmd = NULL; 16632aa35465SDoug Anderson dw_mci_request_end(host, mrq); 16642aa35465SDoug Anderson goto unlock; 16652aa35465SDoug Anderson } 166690c2143aSSeungwon Jeon } 1667e352c813SSeungwon Jeon 1668e352c813SSeungwon Jeon /* 1669e352c813SSeungwon Jeon * If err has non-zero, 1670e352c813SSeungwon Jeon * stop-abort command has been already issued. 1671e352c813SSeungwon Jeon */ 1672e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1673e352c813SSeungwon Jeon 1674f95f3850SWill Newton /* fall through */ 1675f95f3850SWill Newton 1676f95f3850SWill Newton case STATE_SENDING_STOP: 1677f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1678f95f3850SWill Newton &host->pending_events)) 1679f95f3850SWill Newton break; 1680f95f3850SWill Newton 168171abb133SSeungwon Jeon /* CMD error in data command */ 168231bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 16833a33a94cSSonny Rao dw_mci_reset(host); 168471abb133SSeungwon Jeon 1685f95f3850SWill Newton host->cmd = NULL; 168671abb133SSeungwon Jeon host->data = NULL; 168790c2143aSSeungwon Jeon 1688e352c813SSeungwon Jeon if (mrq->stop) 1689e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 169090c2143aSSeungwon Jeon else 169190c2143aSSeungwon Jeon host->cmd_status = 0; 169290c2143aSSeungwon Jeon 1693e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1694f95f3850SWill Newton goto unlock; 1695f95f3850SWill Newton 1696f95f3850SWill Newton case STATE_DATA_ERROR: 1697f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1698f95f3850SWill Newton &host->pending_events)) 1699f95f3850SWill Newton break; 1700f95f3850SWill Newton 1701f95f3850SWill Newton state = STATE_DATA_BUSY; 1702f95f3850SWill Newton break; 1703f95f3850SWill Newton } 1704f95f3850SWill Newton } while (state != prev_state); 1705f95f3850SWill Newton 1706f95f3850SWill Newton host->state = state; 1707f95f3850SWill Newton unlock: 1708f95f3850SWill Newton spin_unlock(&host->lock); 1709f95f3850SWill Newton 1710f95f3850SWill Newton } 1711f95f3850SWill Newton 171234b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 171334b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 171434b664a2SJames Hogan { 171534b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 171634b664a2SJames Hogan host->part_buf_count = cnt; 171734b664a2SJames Hogan } 171834b664a2SJames Hogan 171934b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 172034b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 172134b664a2SJames Hogan { 172234b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 172334b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 172434b664a2SJames Hogan host->part_buf_count += cnt; 172534b664a2SJames Hogan return cnt; 172634b664a2SJames Hogan } 172734b664a2SJames Hogan 172834b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 172934b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 173034b664a2SJames Hogan { 173134b664a2SJames Hogan cnt = min(cnt, (int)host->part_buf_count); 173234b664a2SJames Hogan if (cnt) { 173334b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 173434b664a2SJames Hogan cnt); 173534b664a2SJames Hogan host->part_buf_count -= cnt; 173634b664a2SJames Hogan host->part_buf_start += cnt; 173734b664a2SJames Hogan } 173834b664a2SJames Hogan return cnt; 173934b664a2SJames Hogan } 174034b664a2SJames Hogan 174134b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 174234b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 174334b664a2SJames Hogan { 174434b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 174534b664a2SJames Hogan host->part_buf_start = cnt; 174634b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 174734b664a2SJames Hogan } 174834b664a2SJames Hogan 1749f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1750f95f3850SWill Newton { 1751cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1752cfbeb59cSMarkos Chandras int init_cnt = cnt; 1753cfbeb59cSMarkos Chandras 175434b664a2SJames Hogan /* try and push anything in the part_buf */ 175534b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 175634b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 175734b664a2SJames Hogan buf += len; 175834b664a2SJames Hogan cnt -= len; 1759cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 1760*76184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 176134b664a2SJames Hogan host->part_buf_count = 0; 176234b664a2SJames Hogan } 176334b664a2SJames Hogan } 176434b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 176534b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 176634b664a2SJames Hogan while (cnt >= 2) { 176734b664a2SJames Hogan u16 aligned_buf[64]; 176834b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 176934b664a2SJames Hogan int items = len >> 1; 177034b664a2SJames Hogan int i; 177134b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 177234b664a2SJames Hogan memcpy(aligned_buf, buf, len); 177334b664a2SJames Hogan buf += len; 177434b664a2SJames Hogan cnt -= len; 177534b664a2SJames Hogan /* push data from aligned buffer into fifo */ 177634b664a2SJames Hogan for (i = 0; i < items; ++i) 1777*76184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 177834b664a2SJames Hogan } 177934b664a2SJames Hogan } else 178034b664a2SJames Hogan #endif 178134b664a2SJames Hogan { 178234b664a2SJames Hogan u16 *pdata = buf; 178334b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 1784*76184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 178534b664a2SJames Hogan buf = pdata; 178634b664a2SJames Hogan } 178734b664a2SJames Hogan /* put anything remaining in the part_buf */ 178834b664a2SJames Hogan if (cnt) { 178934b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1790cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1791cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1792cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 1793*76184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 1794f95f3850SWill Newton } 1795f95f3850SWill Newton } 1796f95f3850SWill Newton 1797f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1798f95f3850SWill Newton { 179934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 180034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 180134b664a2SJames Hogan while (cnt >= 2) { 180234b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 180334b664a2SJames Hogan u16 aligned_buf[64]; 180434b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 180534b664a2SJames Hogan int items = len >> 1; 180634b664a2SJames Hogan int i; 180734b664a2SJames Hogan for (i = 0; i < items; ++i) 1808*76184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 180934b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 181034b664a2SJames Hogan memcpy(buf, aligned_buf, len); 181134b664a2SJames Hogan buf += len; 181234b664a2SJames Hogan cnt -= len; 181334b664a2SJames Hogan } 181434b664a2SJames Hogan } else 181534b664a2SJames Hogan #endif 181634b664a2SJames Hogan { 181734b664a2SJames Hogan u16 *pdata = buf; 181834b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 1819*76184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 182034b664a2SJames Hogan buf = pdata; 182134b664a2SJames Hogan } 182234b664a2SJames Hogan if (cnt) { 1823*76184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 182434b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1825f95f3850SWill Newton } 1826f95f3850SWill Newton } 1827f95f3850SWill Newton 1828f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1829f95f3850SWill Newton { 1830cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1831cfbeb59cSMarkos Chandras int init_cnt = cnt; 1832cfbeb59cSMarkos Chandras 183334b664a2SJames Hogan /* try and push anything in the part_buf */ 183434b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 183534b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 183634b664a2SJames Hogan buf += len; 183734b664a2SJames Hogan cnt -= len; 1838cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 1839*76184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 184034b664a2SJames Hogan host->part_buf_count = 0; 184134b664a2SJames Hogan } 184234b664a2SJames Hogan } 184334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 184434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 184534b664a2SJames Hogan while (cnt >= 4) { 184634b664a2SJames Hogan u32 aligned_buf[32]; 184734b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 184834b664a2SJames Hogan int items = len >> 2; 184934b664a2SJames Hogan int i; 185034b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 185134b664a2SJames Hogan memcpy(aligned_buf, buf, len); 185234b664a2SJames Hogan buf += len; 185334b664a2SJames Hogan cnt -= len; 185434b664a2SJames Hogan /* push data from aligned buffer into fifo */ 185534b664a2SJames Hogan for (i = 0; i < items; ++i) 1856*76184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 185734b664a2SJames Hogan } 185834b664a2SJames Hogan } else 185934b664a2SJames Hogan #endif 186034b664a2SJames Hogan { 186134b664a2SJames Hogan u32 *pdata = buf; 186234b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 1863*76184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 186434b664a2SJames Hogan buf = pdata; 186534b664a2SJames Hogan } 186634b664a2SJames Hogan /* put anything remaining in the part_buf */ 186734b664a2SJames Hogan if (cnt) { 186834b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1869cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1870cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1871cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 1872*76184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 1873f95f3850SWill Newton } 1874f95f3850SWill Newton } 1875f95f3850SWill Newton 1876f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1877f95f3850SWill Newton { 187834b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 187934b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 188034b664a2SJames Hogan while (cnt >= 4) { 188134b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 188234b664a2SJames Hogan u32 aligned_buf[32]; 188334b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 188434b664a2SJames Hogan int items = len >> 2; 188534b664a2SJames Hogan int i; 188634b664a2SJames Hogan for (i = 0; i < items; ++i) 1887*76184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 188834b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 188934b664a2SJames Hogan memcpy(buf, aligned_buf, len); 189034b664a2SJames Hogan buf += len; 189134b664a2SJames Hogan cnt -= len; 189234b664a2SJames Hogan } 189334b664a2SJames Hogan } else 189434b664a2SJames Hogan #endif 189534b664a2SJames Hogan { 189634b664a2SJames Hogan u32 *pdata = buf; 189734b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 1898*76184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 189934b664a2SJames Hogan buf = pdata; 190034b664a2SJames Hogan } 190134b664a2SJames Hogan if (cnt) { 1902*76184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 190334b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 1904f95f3850SWill Newton } 1905f95f3850SWill Newton } 1906f95f3850SWill Newton 1907f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1908f95f3850SWill Newton { 1909cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1910cfbeb59cSMarkos Chandras int init_cnt = cnt; 1911cfbeb59cSMarkos Chandras 191234b664a2SJames Hogan /* try and push anything in the part_buf */ 191334b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 191434b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 191534b664a2SJames Hogan buf += len; 191634b664a2SJames Hogan cnt -= len; 1917c09fbd74SSeungwon Jeon 1918cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 1919*76184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 192034b664a2SJames Hogan host->part_buf_count = 0; 192134b664a2SJames Hogan } 192234b664a2SJames Hogan } 192334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 192434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 192534b664a2SJames Hogan while (cnt >= 8) { 192634b664a2SJames Hogan u64 aligned_buf[16]; 192734b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 192834b664a2SJames Hogan int items = len >> 3; 192934b664a2SJames Hogan int i; 193034b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 193134b664a2SJames Hogan memcpy(aligned_buf, buf, len); 193234b664a2SJames Hogan buf += len; 193334b664a2SJames Hogan cnt -= len; 193434b664a2SJames Hogan /* push data from aligned buffer into fifo */ 193534b664a2SJames Hogan for (i = 0; i < items; ++i) 1936*76184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 193734b664a2SJames Hogan } 193834b664a2SJames Hogan } else 193934b664a2SJames Hogan #endif 194034b664a2SJames Hogan { 194134b664a2SJames Hogan u64 *pdata = buf; 194234b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 1943*76184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 194434b664a2SJames Hogan buf = pdata; 194534b664a2SJames Hogan } 194634b664a2SJames Hogan /* put anything remaining in the part_buf */ 194734b664a2SJames Hogan if (cnt) { 194834b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 1949cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 1950cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 1951cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 1952*76184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 1953f95f3850SWill Newton } 1954f95f3850SWill Newton } 1955f95f3850SWill Newton 1956f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1957f95f3850SWill Newton { 195834b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 195934b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 196034b664a2SJames Hogan while (cnt >= 8) { 196134b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 196234b664a2SJames Hogan u64 aligned_buf[16]; 196334b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 196434b664a2SJames Hogan int items = len >> 3; 196534b664a2SJames Hogan int i; 196634b664a2SJames Hogan for (i = 0; i < items; ++i) 1967*76184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 1968*76184ac1SBen Dooks 196934b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 197034b664a2SJames Hogan memcpy(buf, aligned_buf, len); 197134b664a2SJames Hogan buf += len; 197234b664a2SJames Hogan cnt -= len; 1973f95f3850SWill Newton } 197434b664a2SJames Hogan } else 197534b664a2SJames Hogan #endif 197634b664a2SJames Hogan { 197734b664a2SJames Hogan u64 *pdata = buf; 197834b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 1979*76184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 198034b664a2SJames Hogan buf = pdata; 198134b664a2SJames Hogan } 198234b664a2SJames Hogan if (cnt) { 1983*76184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 198434b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 198534b664a2SJames Hogan } 198634b664a2SJames Hogan } 198734b664a2SJames Hogan 198834b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 198934b664a2SJames Hogan { 199034b664a2SJames Hogan int len; 199134b664a2SJames Hogan 199234b664a2SJames Hogan /* get remaining partial bytes */ 199334b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 199434b664a2SJames Hogan if (unlikely(len == cnt)) 199534b664a2SJames Hogan return; 199634b664a2SJames Hogan buf += len; 199734b664a2SJames Hogan cnt -= len; 199834b664a2SJames Hogan 199934b664a2SJames Hogan /* get the rest of the data */ 200034b664a2SJames Hogan host->pull_data(host, buf, cnt); 2001f95f3850SWill Newton } 2002f95f3850SWill Newton 200387a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2004f95f3850SWill Newton { 2005f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2006f9c2a0dcSSeungwon Jeon void *buf; 2007f9c2a0dcSSeungwon Jeon unsigned int offset; 2008f95f3850SWill Newton struct mmc_data *data = host->data; 2009f95f3850SWill Newton int shift = host->data_shift; 2010f95f3850SWill Newton u32 status; 20113e4b0d8bSMarkos Chandras unsigned int len; 2012f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2013f95f3850SWill Newton 2014f95f3850SWill Newton do { 2015f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2016f9c2a0dcSSeungwon Jeon goto done; 2017f95f3850SWill Newton 20184225fc85SImre Deak host->sg = sg_miter->piter.sg; 2019f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2020f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2021f9c2a0dcSSeungwon Jeon offset = 0; 2022f9c2a0dcSSeungwon Jeon 2023f9c2a0dcSSeungwon Jeon do { 2024f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2025f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2026f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2027f9c2a0dcSSeungwon Jeon if (!len) 2028f9c2a0dcSSeungwon Jeon break; 2029f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 20303e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2031f95f3850SWill Newton offset += len; 2032f9c2a0dcSSeungwon Jeon remain -= len; 2033f9c2a0dcSSeungwon Jeon } while (remain); 2034f95f3850SWill Newton 2035e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2036f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2037f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 203887a74d39SKyoungil Kim /* if the RXDR is ready read again */ 203987a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 204087a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2041f9c2a0dcSSeungwon Jeon 2042f9c2a0dcSSeungwon Jeon if (!remain) { 2043f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2044f9c2a0dcSSeungwon Jeon goto done; 2045f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2046f9c2a0dcSSeungwon Jeon } 2047f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2048f95f3850SWill Newton return; 2049f95f3850SWill Newton 2050f95f3850SWill Newton done: 2051f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2052f9c2a0dcSSeungwon Jeon host->sg = NULL; 2053f95f3850SWill Newton smp_wmb(); 2054f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2055f95f3850SWill Newton } 2056f95f3850SWill Newton 2057f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2058f95f3850SWill Newton { 2059f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2060f9c2a0dcSSeungwon Jeon void *buf; 2061f9c2a0dcSSeungwon Jeon unsigned int offset; 2062f95f3850SWill Newton struct mmc_data *data = host->data; 2063f95f3850SWill Newton int shift = host->data_shift; 2064f95f3850SWill Newton u32 status; 20653e4b0d8bSMarkos Chandras unsigned int len; 2066f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2067f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2068f95f3850SWill Newton 2069f95f3850SWill Newton do { 2070f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2071f9c2a0dcSSeungwon Jeon goto done; 2072f95f3850SWill Newton 20734225fc85SImre Deak host->sg = sg_miter->piter.sg; 2074f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2075f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2076f9c2a0dcSSeungwon Jeon offset = 0; 2077f9c2a0dcSSeungwon Jeon 2078f9c2a0dcSSeungwon Jeon do { 2079f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2080f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2081f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2082f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2083f9c2a0dcSSeungwon Jeon if (!len) 2084f9c2a0dcSSeungwon Jeon break; 2085f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 20863e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2087f95f3850SWill Newton offset += len; 2088f9c2a0dcSSeungwon Jeon remain -= len; 2089f9c2a0dcSSeungwon Jeon } while (remain); 2090f95f3850SWill Newton 2091e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2092f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2093f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2094f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2095f9c2a0dcSSeungwon Jeon 2096f9c2a0dcSSeungwon Jeon if (!remain) { 2097f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2098f9c2a0dcSSeungwon Jeon goto done; 2099f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2100f9c2a0dcSSeungwon Jeon } 2101f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2102f95f3850SWill Newton return; 2103f95f3850SWill Newton 2104f95f3850SWill Newton done: 2105f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2106f9c2a0dcSSeungwon Jeon host->sg = NULL; 2107f95f3850SWill Newton smp_wmb(); 2108f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2109f95f3850SWill Newton } 2110f95f3850SWill Newton 2111f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2112f95f3850SWill Newton { 2113f95f3850SWill Newton if (!host->cmd_status) 2114f95f3850SWill Newton host->cmd_status = status; 2115f95f3850SWill Newton 2116f95f3850SWill Newton smp_wmb(); 2117f95f3850SWill Newton 2118f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2119f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2120f95f3850SWill Newton } 2121f95f3850SWill Newton 21226130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 21236130e7a9SDoug Anderson { 21246130e7a9SDoug Anderson int i; 21256130e7a9SDoug Anderson 21266130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 21276130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 21286130e7a9SDoug Anderson 21296130e7a9SDoug Anderson if (!slot) 21306130e7a9SDoug Anderson continue; 21316130e7a9SDoug Anderson 21326130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 21336130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 21346130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 21356130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 21366130e7a9SDoug Anderson } 21376130e7a9SDoug Anderson } 21386130e7a9SDoug Anderson 2139f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2140f95f3850SWill Newton { 2141f95f3850SWill Newton struct dw_mci *host = dev_id; 2142182c9081SSeungwon Jeon u32 pending; 21431a5c8e1fSShashidhar Hiremath int i; 2144f95f3850SWill Newton 2145f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2146f95f3850SWill Newton 2147f95f3850SWill Newton /* 2148f95f3850SWill Newton * DTO fix - version 2.10a and below, and only if internal DMA 2149f95f3850SWill Newton * is configured. 2150f95f3850SWill Newton */ 2151f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2152f95f3850SWill Newton if (!pending && 2153f95f3850SWill Newton ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2154f95f3850SWill Newton pending |= SDMMC_INT_DATA_OVER; 2155f95f3850SWill Newton } 2156f95f3850SWill Newton 2157476d79f1SDoug Anderson if (pending) { 215801730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 215901730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 216001730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 21615c935165SDoug Anderson del_timer(&host->cmd11_timer); 21625c935165SDoug Anderson 216301730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 216401730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 216501730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 216601730558SDoug Anderson } 216701730558SDoug Anderson 2168f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2169f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2170182c9081SSeungwon Jeon host->cmd_status = pending; 2171f95f3850SWill Newton smp_wmb(); 2172f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2173f95f3850SWill Newton } 2174f95f3850SWill Newton 2175f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2176f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2177f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2178182c9081SSeungwon Jeon host->data_status = pending; 2179f95f3850SWill Newton smp_wmb(); 2180f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2181f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2182f95f3850SWill Newton } 2183f95f3850SWill Newton 2184f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 2185f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2186f95f3850SWill Newton if (!host->data_status) 2187182c9081SSeungwon Jeon host->data_status = pending; 2188f95f3850SWill Newton smp_wmb(); 2189f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2190f95f3850SWill Newton if (host->sg != NULL) 219187a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2192f95f3850SWill Newton } 2193f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2194f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2195f95f3850SWill Newton } 2196f95f3850SWill Newton 2197f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2198f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2199b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 220087a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2201f95f3850SWill Newton } 2202f95f3850SWill Newton 2203f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2204f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2205b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2206f95f3850SWill Newton dw_mci_write_data_pio(host); 2207f95f3850SWill Newton } 2208f95f3850SWill Newton 2209f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2210f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2211182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2212f95f3850SWill Newton } 2213f95f3850SWill Newton 2214f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2215f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 22166130e7a9SDoug Anderson dw_mci_handle_cd(host); 2217f95f3850SWill Newton } 2218f95f3850SWill Newton 22191a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 22201a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 22211a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2222ed2540efSDoug Anderson 2223ed2540efSDoug Anderson if (!slot) 2224ed2540efSDoug Anderson continue; 2225ed2540efSDoug Anderson 222676756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 222776756234SAddy Ke mci_writel(host, RINTSTS, 222876756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 22291a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 22301a5c8e1fSShashidhar Hiremath } 22311a5c8e1fSShashidhar Hiremath } 22321a5c8e1fSShashidhar Hiremath 22331fb5f68aSMarkos Chandras } 2234f95f3850SWill Newton 2235f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2236f95f3850SWill Newton /* Handle DMA interrupts */ 223769d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 223869d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 223969d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 224069d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 224169d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 224269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 224369d99fdcSPrabu Thangamuthu host->dma_ops->complete(host); 224469d99fdcSPrabu Thangamuthu } 224569d99fdcSPrabu Thangamuthu } else { 2246f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2247f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 224869d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 224969d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2250f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2251f95f3850SWill Newton host->dma_ops->complete(host); 2252f95f3850SWill Newton } 225369d99fdcSPrabu Thangamuthu } 2254f95f3850SWill Newton #endif 2255f95f3850SWill Newton 2256f95f3850SWill Newton return IRQ_HANDLED; 2257f95f3850SWill Newton } 2258f95f3850SWill Newton 2259c91eab4bSThomas Abraham #ifdef CONFIG_OF 2260c91eab4bSThomas Abraham /* given a slot id, find out the device node representing that slot */ 2261c91eab4bSThomas Abraham static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 2262c91eab4bSThomas Abraham { 2263c91eab4bSThomas Abraham struct device_node *np; 2264c91eab4bSThomas Abraham const __be32 *addr; 2265c91eab4bSThomas Abraham int len; 2266c91eab4bSThomas Abraham 2267c91eab4bSThomas Abraham if (!dev || !dev->of_node) 2268c91eab4bSThomas Abraham return NULL; 2269c91eab4bSThomas Abraham 2270c91eab4bSThomas Abraham for_each_child_of_node(dev->of_node, np) { 2271c91eab4bSThomas Abraham addr = of_get_property(np, "reg", &len); 2272c91eab4bSThomas Abraham if (!addr || (len < sizeof(int))) 2273c91eab4bSThomas Abraham continue; 2274c91eab4bSThomas Abraham if (be32_to_cpup(addr) == slot) 2275c91eab4bSThomas Abraham return np; 2276c91eab4bSThomas Abraham } 2277c91eab4bSThomas Abraham return NULL; 2278c91eab4bSThomas Abraham } 2279c91eab4bSThomas Abraham 2280a70aaa64SDoug Anderson static struct dw_mci_of_slot_quirks { 2281a70aaa64SDoug Anderson char *quirk; 2282a70aaa64SDoug Anderson int id; 2283a70aaa64SDoug Anderson } of_slot_quirks[] = { 2284a70aaa64SDoug Anderson { 2285a70aaa64SDoug Anderson .quirk = "disable-wp", 2286a70aaa64SDoug Anderson .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, 2287a70aaa64SDoug Anderson }, 2288a70aaa64SDoug Anderson }; 2289a70aaa64SDoug Anderson 2290a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2291a70aaa64SDoug Anderson { 2292a70aaa64SDoug Anderson struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 2293a70aaa64SDoug Anderson int quirks = 0; 2294a70aaa64SDoug Anderson int idx; 2295a70aaa64SDoug Anderson 2296a70aaa64SDoug Anderson /* get quirks */ 2297a70aaa64SDoug Anderson for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) 229826375b5cSJaehoon Chung if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) { 229926375b5cSJaehoon Chung dev_warn(dev, "Slot quirk %s is deprecated\n", 230026375b5cSJaehoon Chung of_slot_quirks[idx].quirk); 2301a70aaa64SDoug Anderson quirks |= of_slot_quirks[idx].id; 230226375b5cSJaehoon Chung } 2303a70aaa64SDoug Anderson 2304a70aaa64SDoug Anderson return quirks; 2305a70aaa64SDoug Anderson } 2306c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2307a70aaa64SDoug Anderson static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 2308a70aaa64SDoug Anderson { 2309a70aaa64SDoug Anderson return 0; 2310a70aaa64SDoug Anderson } 2311c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2312c91eab4bSThomas Abraham 231336c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2314f95f3850SWill Newton { 2315f95f3850SWill Newton struct mmc_host *mmc; 2316f95f3850SWill Newton struct dw_mci_slot *slot; 2317e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2318800d78bfSThomas Abraham int ctrl_id, ret; 23191f44a2a5SSeungwon Jeon u32 freq[2]; 2320f95f3850SWill Newton 23214a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2322f95f3850SWill Newton if (!mmc) 2323f95f3850SWill Newton return -ENOMEM; 2324f95f3850SWill Newton 2325f95f3850SWill Newton slot = mmc_priv(mmc); 2326f95f3850SWill Newton slot->id = id; 232776756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2328f95f3850SWill Newton slot->mmc = mmc; 2329f95f3850SWill Newton slot->host = host; 2330c91eab4bSThomas Abraham host->slot[id] = slot; 2331f95f3850SWill Newton 2332a70aaa64SDoug Anderson slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 2333a70aaa64SDoug Anderson 2334f95f3850SWill Newton mmc->ops = &dw_mci_ops; 23351f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 23361f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 23371f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 23381f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 23391f44a2a5SSeungwon Jeon } else { 23401f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 23411f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 23421f44a2a5SSeungwon Jeon } 2343f95f3850SWill Newton 234451da2240SYuvaraj CD /*if there are external regulators, get them*/ 234551da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 234651da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 23473cf890fcSDoug Anderson goto err_host_allocated; 234851da2240SYuvaraj CD 234951da2240SYuvaraj CD if (!mmc->ocr_avail) 2350f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2351f95f3850SWill Newton 2352fc3d7720SJaehoon Chung if (host->pdata->caps) 2353fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2354fc3d7720SJaehoon Chung 2355ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2356ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2357ab269128SAbhilash Kesavan 2358800d78bfSThomas Abraham if (host->dev->of_node) { 2359800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2360800d78bfSThomas Abraham if (ctrl_id < 0) 2361800d78bfSThomas Abraham ctrl_id = 0; 2362800d78bfSThomas Abraham } else { 2363800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2364800d78bfSThomas Abraham } 2365cb27a843SJames Hogan if (drv_data && drv_data->caps) 2366cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2367800d78bfSThomas Abraham 23684f408cc6SSeungwon Jeon if (host->pdata->caps2) 23694f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 23704f408cc6SSeungwon Jeon 23713cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 23723cf890fcSDoug Anderson if (ret) 23733cf890fcSDoug Anderson goto err_host_allocated; 2374f95f3850SWill Newton 2375f95f3850SWill Newton if (host->pdata->blk_settings) { 2376f95f3850SWill Newton mmc->max_segs = host->pdata->blk_settings->max_segs; 2377f95f3850SWill Newton mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 2378f95f3850SWill Newton mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 2379f95f3850SWill Newton mmc->max_req_size = host->pdata->blk_settings->max_req_size; 2380f95f3850SWill Newton mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 2381f95f3850SWill Newton } else { 2382f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 2383a39e5746SJaehoon Chung #ifdef CONFIG_MMC_DW_IDMAC 2384a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2385a39e5746SJaehoon Chung mmc->max_blk_size = 65536; 2386a39e5746SJaehoon Chung mmc->max_seg_size = 0x1000; 23871a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 23881a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 2389a39e5746SJaehoon Chung #else 2390f95f3850SWill Newton mmc->max_segs = 64; 2391f95f3850SWill Newton mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2392f95f3850SWill Newton mmc->max_blk_count = 512; 2393f95f3850SWill Newton mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2394f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2395f95f3850SWill Newton #endif /* CONFIG_MMC_DW_IDMAC */ 2396a39e5746SJaehoon Chung } 2397f95f3850SWill Newton 2398ae0eb348SJaehoon Chung if (dw_mci_get_cd(mmc)) 2399ae0eb348SJaehoon Chung set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2400ae0eb348SJaehoon Chung else 2401ae0eb348SJaehoon Chung clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2402ae0eb348SJaehoon Chung 24030cea529dSJaehoon Chung ret = mmc_add_host(mmc); 24040cea529dSJaehoon Chung if (ret) 24053cf890fcSDoug Anderson goto err_host_allocated; 2406f95f3850SWill Newton 2407f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2408f95f3850SWill Newton dw_mci_init_debugfs(slot); 2409f95f3850SWill Newton #endif 2410f95f3850SWill Newton 2411f95f3850SWill Newton return 0; 2412800d78bfSThomas Abraham 24133cf890fcSDoug Anderson err_host_allocated: 2414800d78bfSThomas Abraham mmc_free_host(mmc); 241551da2240SYuvaraj CD return ret; 2416f95f3850SWill Newton } 2417f95f3850SWill Newton 2418f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2419f95f3850SWill Newton { 2420f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2421f95f3850SWill Newton mmc_remove_host(slot->mmc); 2422f95f3850SWill Newton slot->host->slot[id] = NULL; 2423f95f3850SWill Newton mmc_free_host(slot->mmc); 2424f95f3850SWill Newton } 2425f95f3850SWill Newton 2426f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2427f95f3850SWill Newton { 242869d99fdcSPrabu Thangamuthu int addr_config; 242969d99fdcSPrabu Thangamuthu /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ 243069d99fdcSPrabu Thangamuthu addr_config = (mci_readl(host, HCON) >> 27) & 0x01; 243169d99fdcSPrabu Thangamuthu 243269d99fdcSPrabu Thangamuthu if (addr_config == 1) { 243369d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 243469d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 243569d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); 243669d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 243769d99fdcSPrabu Thangamuthu dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); 243869d99fdcSPrabu Thangamuthu } else { 243969d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 244069d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 244169d99fdcSPrabu Thangamuthu dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); 244269d99fdcSPrabu Thangamuthu } 244369d99fdcSPrabu Thangamuthu 2444f95f3850SWill Newton /* Alloc memory for sg translation */ 2445780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2446f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2447f95f3850SWill Newton if (!host->sg_cpu) { 24484a90920cSThomas Abraham dev_err(host->dev, "%s: could not alloc DMA memory\n", 2449f95f3850SWill Newton __func__); 2450f95f3850SWill Newton goto no_dma; 2451f95f3850SWill Newton } 2452f95f3850SWill Newton 2453f95f3850SWill Newton /* Determine which DMA interface to use */ 2454f95f3850SWill Newton #ifdef CONFIG_MMC_DW_IDMAC 2455f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 245600956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 2457f95f3850SWill Newton #endif 2458f95f3850SWill Newton 2459f95f3850SWill Newton if (!host->dma_ops) 2460f95f3850SWill Newton goto no_dma; 2461f95f3850SWill Newton 2462e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2463e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2464f95f3850SWill Newton if (host->dma_ops->init(host)) { 24654a90920cSThomas Abraham dev_err(host->dev, "%s: Unable to initialize " 2466f95f3850SWill Newton "DMA Controller.\n", __func__); 2467f95f3850SWill Newton goto no_dma; 2468f95f3850SWill Newton } 2469f95f3850SWill Newton } else { 24704a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2471f95f3850SWill Newton goto no_dma; 2472f95f3850SWill Newton } 2473f95f3850SWill Newton 2474f95f3850SWill Newton host->use_dma = 1; 2475f95f3850SWill Newton return; 2476f95f3850SWill Newton 2477f95f3850SWill Newton no_dma: 24784a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 2479f95f3850SWill Newton host->use_dma = 0; 2480f95f3850SWill Newton return; 2481f95f3850SWill Newton } 2482f95f3850SWill Newton 248331bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2484f95f3850SWill Newton { 2485f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 248631bff450SSeungwon Jeon u32 ctrl; 2487f95f3850SWill Newton 248831bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 248931bff450SSeungwon Jeon ctrl |= reset; 249031bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2491f95f3850SWill Newton 2492f95f3850SWill Newton /* wait till resets clear */ 2493f95f3850SWill Newton do { 2494f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 249531bff450SSeungwon Jeon if (!(ctrl & reset)) 2496f95f3850SWill Newton return true; 2497f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2498f95f3850SWill Newton 249931bff450SSeungwon Jeon dev_err(host->dev, 250031bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 250131bff450SSeungwon Jeon ctrl & reset); 2502f95f3850SWill Newton 2503f95f3850SWill Newton return false; 2504f95f3850SWill Newton } 2505f95f3850SWill Newton 25063a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 250731bff450SSeungwon Jeon { 25083a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 25093a33a94cSSonny Rao bool ret = false; 25103a33a94cSSonny Rao 251131bff450SSeungwon Jeon /* 251231bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 251331bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 251431bff450SSeungwon Jeon */ 251531bff450SSeungwon Jeon if (host->sg) { 251631bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 251731bff450SSeungwon Jeon host->sg = NULL; 251831bff450SSeungwon Jeon } 251931bff450SSeungwon Jeon 25203a33a94cSSonny Rao if (host->use_dma) 25213a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 25223a33a94cSSonny Rao 25233a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 25243a33a94cSSonny Rao /* 25253a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 25263a33a94cSSonny Rao * interrupts. 25273a33a94cSSonny Rao */ 25283a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 25293a33a94cSSonny Rao 25303a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 25313a33a94cSSonny Rao if (host->use_dma) { 25323a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 25333a33a94cSSonny Rao u32 status; 25343a33a94cSSonny Rao do { 25353a33a94cSSonny Rao status = mci_readl(host, STATUS); 25363a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 25373a33a94cSSonny Rao break; 25383a33a94cSSonny Rao cpu_relax(); 25393a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 25403a33a94cSSonny Rao 25413a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 25423a33a94cSSonny Rao dev_err(host->dev, 25433a33a94cSSonny Rao "%s: Timeout waiting for dma_req to " 25443a33a94cSSonny Rao "clear during reset\n", __func__); 25453a33a94cSSonny Rao goto ciu_out; 254631bff450SSeungwon Jeon } 254731bff450SSeungwon Jeon 25483a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 25493a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 25503a33a94cSSonny Rao goto ciu_out; 25513a33a94cSSonny Rao } 25523a33a94cSSonny Rao } else { 25533a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 25543a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 25553a33a94cSSonny Rao dev_err(host->dev, "%s: fifo/dma reset bits didn't " 25563a33a94cSSonny Rao "clear but ciu was reset, doing clock update\n", 25573a33a94cSSonny Rao __func__); 25583a33a94cSSonny Rao goto ciu_out; 25593a33a94cSSonny Rao } 25603a33a94cSSonny Rao } 25613a33a94cSSonny Rao 25623a33a94cSSonny Rao #if IS_ENABLED(CONFIG_MMC_DW_IDMAC) 25633a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 25643a33a94cSSonny Rao dw_mci_idmac_reset(host); 25653a33a94cSSonny Rao #endif 25663a33a94cSSonny Rao 25673a33a94cSSonny Rao ret = true; 25683a33a94cSSonny Rao 25693a33a94cSSonny Rao ciu_out: 25703a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 25713a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 25723a33a94cSSonny Rao 25733a33a94cSSonny Rao return ret; 257431bff450SSeungwon Jeon } 257531bff450SSeungwon Jeon 25765c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 25775c935165SDoug Anderson { 25785c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 25795c935165SDoug Anderson 25805c935165SDoug Anderson if (host->state != STATE_SENDING_CMD11) 25815c935165SDoug Anderson dev_info(host->dev, "Unexpected CMD11 timeout\n"); 25825c935165SDoug Anderson 25835c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 25845c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 25855c935165SDoug Anderson tasklet_schedule(&host->tasklet); 25865c935165SDoug Anderson } 25875c935165SDoug Anderson 2588c91eab4bSThomas Abraham #ifdef CONFIG_OF 2589c91eab4bSThomas Abraham static struct dw_mci_of_quirks { 2590c91eab4bSThomas Abraham char *quirk; 2591c91eab4bSThomas Abraham int id; 2592c91eab4bSThomas Abraham } of_quirks[] = { 2593c91eab4bSThomas Abraham { 2594c91eab4bSThomas Abraham .quirk = "broken-cd", 2595c91eab4bSThomas Abraham .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 259626375b5cSJaehoon Chung }, { 259726375b5cSJaehoon Chung .quirk = "disable-wp", 259826375b5cSJaehoon Chung .id = DW_MCI_QUIRK_NO_WRITE_PROTECT, 2599c91eab4bSThomas Abraham }, 2600c91eab4bSThomas Abraham }; 2601c91eab4bSThomas Abraham 2602c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2603c91eab4bSThomas Abraham { 2604c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2605c91eab4bSThomas Abraham struct device *dev = host->dev; 2606c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2607e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2608800d78bfSThomas Abraham int idx, ret; 26093c6d89eaSDoug Anderson u32 clock_frequency; 2610c91eab4bSThomas Abraham 2611c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2612bf3707eaSBeomho Seo if (!pdata) 2613c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2614c91eab4bSThomas Abraham 2615c91eab4bSThomas Abraham /* find out number of slots supported */ 2616c91eab4bSThomas Abraham if (of_property_read_u32(dev->of_node, "num-slots", 2617c91eab4bSThomas Abraham &pdata->num_slots)) { 2618c91eab4bSThomas Abraham dev_info(dev, "num-slots property not found, " 2619c91eab4bSThomas Abraham "assuming 1 slot is available\n"); 2620c91eab4bSThomas Abraham pdata->num_slots = 1; 2621c91eab4bSThomas Abraham } 2622c91eab4bSThomas Abraham 2623c91eab4bSThomas Abraham /* get quirks */ 2624c91eab4bSThomas Abraham for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2625c91eab4bSThomas Abraham if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2626c91eab4bSThomas Abraham pdata->quirks |= of_quirks[idx].id; 2627c91eab4bSThomas Abraham 2628c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2629c91eab4bSThomas Abraham dev_info(dev, "fifo-depth property not found, using " 2630c91eab4bSThomas Abraham "value of FIFOTH register as default\n"); 2631c91eab4bSThomas Abraham 2632c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2633c91eab4bSThomas Abraham 26343c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 26353c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 26363c6d89eaSDoug Anderson 2637cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2638cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2639800d78bfSThomas Abraham if (ret) 2640800d78bfSThomas Abraham return ERR_PTR(ret); 2641800d78bfSThomas Abraham } 2642800d78bfSThomas Abraham 264310b49841SSeungwon Jeon if (of_find_property(np, "supports-highspeed", NULL)) 264410b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 264510b49841SSeungwon Jeon 2646c91eab4bSThomas Abraham return pdata; 2647c91eab4bSThomas Abraham } 2648c91eab4bSThomas Abraham 2649c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2650c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2651c91eab4bSThomas Abraham { 2652c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2653c91eab4bSThomas Abraham } 2654c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2655c91eab4bSThomas Abraham 2656fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2657fa0c3283SDoug Anderson { 2658fa0c3283SDoug Anderson struct dw_mci_board *brd = host->pdata; 2659fa0c3283SDoug Anderson unsigned long irqflags; 2660fa0c3283SDoug Anderson u32 temp; 2661fa0c3283SDoug Anderson int i; 2662fa0c3283SDoug Anderson 2663fa0c3283SDoug Anderson /* No need for CD if broken card detection */ 2664fa0c3283SDoug Anderson if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 2665fa0c3283SDoug Anderson return; 2666fa0c3283SDoug Anderson 2667fa0c3283SDoug Anderson /* No need for CD if all slots have a non-error GPIO */ 2668fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 2669fa0c3283SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 2670fa0c3283SDoug Anderson 2671fa0c3283SDoug Anderson if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) 2672fa0c3283SDoug Anderson break; 2673fa0c3283SDoug Anderson } 2674fa0c3283SDoug Anderson if (i == host->num_slots) 2675fa0c3283SDoug Anderson return; 2676fa0c3283SDoug Anderson 2677fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 2678fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 2679fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 2680fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 2681fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2682fa0c3283SDoug Anderson } 2683fa0c3283SDoug Anderson 268462ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2685f95f3850SWill Newton { 2686e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 268762ca8034SShashidhar Hiremath int width, i, ret = 0; 2688f95f3850SWill Newton u32 fifo_size; 26891c2215b7SThomas Abraham int init_slots = 0; 2690f95f3850SWill Newton 2691c91eab4bSThomas Abraham if (!host->pdata) { 2692c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2693c91eab4bSThomas Abraham if (IS_ERR(host->pdata)) { 2694c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2695c91eab4bSThomas Abraham return -EINVAL; 2696c91eab4bSThomas Abraham } 2697f95f3850SWill Newton } 2698f95f3850SWill Newton 2699907abd51SJaehoon Chung if (host->pdata->num_slots > 1) { 27004a90920cSThomas Abraham dev_err(host->dev, 2701907abd51SJaehoon Chung "Platform data must supply num_slots.\n"); 270262ca8034SShashidhar Hiremath return -ENODEV; 2703f95f3850SWill Newton } 2704f95f3850SWill Newton 2705780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2706f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2707f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2708f90a0612SThomas Abraham } else { 2709f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2710f90a0612SThomas Abraham if (ret) { 2711f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2712f90a0612SThomas Abraham return ret; 2713f90a0612SThomas Abraham } 2714f95f3850SWill Newton } 2715f95f3850SWill Newton 2716780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2717f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2718f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 27193c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2720f90a0612SThomas Abraham } else { 2721f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2722f90a0612SThomas Abraham if (ret) { 2723f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2724f90a0612SThomas Abraham goto err_clk_biu; 2725f90a0612SThomas Abraham } 2726f90a0612SThomas Abraham 27273c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 27283c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 27293c6d89eaSDoug Anderson if (ret) 27303c6d89eaSDoug Anderson dev_warn(host->dev, 2731612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 27323c6d89eaSDoug Anderson host->pdata->bus_hz); 27333c6d89eaSDoug Anderson } 2734f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 27353c6d89eaSDoug Anderson } 2736f90a0612SThomas Abraham 2737612de4c1SJaehoon Chung if (!host->bus_hz) { 2738612de4c1SJaehoon Chung dev_err(host->dev, 2739612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 2740612de4c1SJaehoon Chung ret = -ENODEV; 2741612de4c1SJaehoon Chung goto err_clk_ciu; 2742612de4c1SJaehoon Chung } 2743612de4c1SJaehoon Chung 2744002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 2745002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 2746002f0d5cSYuvaraj Kumar C D if (ret) { 2747002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 2748002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 2749002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 2750002f0d5cSYuvaraj Kumar C D } 2751002f0d5cSYuvaraj Kumar C D } 2752002f0d5cSYuvaraj Kumar C D 2753cb27a843SJames Hogan if (drv_data && drv_data->setup_clock) { 2754cb27a843SJames Hogan ret = drv_data->setup_clock(host); 2755800d78bfSThomas Abraham if (ret) { 2756800d78bfSThomas Abraham dev_err(host->dev, 2757800d78bfSThomas Abraham "implementation specific clock setup failed\n"); 2758800d78bfSThomas Abraham goto err_clk_ciu; 2759800d78bfSThomas Abraham } 2760800d78bfSThomas Abraham } 2761800d78bfSThomas Abraham 27625c935165SDoug Anderson setup_timer(&host->cmd11_timer, 27635c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 27645c935165SDoug Anderson 276562ca8034SShashidhar Hiremath host->quirks = host->pdata->quirks; 2766f95f3850SWill Newton 2767f95f3850SWill Newton spin_lock_init(&host->lock); 2768f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 2769f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 2770f95f3850SWill Newton 2771f95f3850SWill Newton /* 2772f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 2773f95f3850SWill Newton * the correct values. 2774f95f3850SWill Newton */ 2775f95f3850SWill Newton i = (mci_readl(host, HCON) >> 7) & 0x7; 2776f95f3850SWill Newton if (!i) { 2777f95f3850SWill Newton host->push_data = dw_mci_push_data16; 2778f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 2779f95f3850SWill Newton width = 16; 2780f95f3850SWill Newton host->data_shift = 1; 2781f95f3850SWill Newton } else if (i == 2) { 2782f95f3850SWill Newton host->push_data = dw_mci_push_data64; 2783f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 2784f95f3850SWill Newton width = 64; 2785f95f3850SWill Newton host->data_shift = 3; 2786f95f3850SWill Newton } else { 2787f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 2788f95f3850SWill Newton WARN((i != 1), 2789f95f3850SWill Newton "HCON reports a reserved host data width!\n" 2790f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 2791f95f3850SWill Newton host->push_data = dw_mci_push_data32; 2792f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 2793f95f3850SWill Newton width = 32; 2794f95f3850SWill Newton host->data_shift = 2; 2795f95f3850SWill Newton } 2796f95f3850SWill Newton 2797f95f3850SWill Newton /* Reset all blocks */ 27983a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 2799141a712aSSeungwon Jeon return -ENODEV; 2800141a712aSSeungwon Jeon 2801141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 2802141a712aSSeungwon Jeon dw_mci_init_dma(host); 2803f95f3850SWill Newton 2804f95f3850SWill Newton /* Clear the interrupts for the host controller */ 2805f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2806f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2807f95f3850SWill Newton 2808f95f3850SWill Newton /* Put in max timeout */ 2809f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 2810f95f3850SWill Newton 2811f95f3850SWill Newton /* 2812f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2813f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 2814f95f3850SWill Newton */ 2815b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 2816b86d8253SJames Hogan /* 2817b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2818b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 2819b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 2820b86d8253SJames Hogan * should put it in the platform data. 2821b86d8253SJames Hogan */ 2822f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 28238234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2824b86d8253SJames Hogan } else { 2825b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 2826b86d8253SJames Hogan } 2827b86d8253SJames Hogan host->fifo_depth = fifo_size; 282852426899SSeungwon Jeon host->fifoth_val = 282952426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 2830e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 2831f95f3850SWill Newton 2832f95f3850SWill Newton /* disable clock to CIU */ 2833f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2834f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2835f95f3850SWill Newton 283663008768SJames Hogan /* 283763008768SJames Hogan * In 2.40a spec, Data offset is changed. 283863008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 283963008768SJames Hogan */ 284063008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 284163008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 284263008768SJames Hogan 284363008768SJames Hogan if (host->verid < DW_MMC_240A) 2844*76184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 284563008768SJames Hogan else 2846*76184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 284763008768SJames Hogan 2848f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2849780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2850780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 2851f95f3850SWill Newton if (ret) 28526130e7a9SDoug Anderson goto err_dmaunmap; 2853f95f3850SWill Newton 2854f95f3850SWill Newton if (host->pdata->num_slots) 2855f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 2856f95f3850SWill Newton else 2857f95f3850SWill Newton host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2858f95f3850SWill Newton 28592da1d7f2SYuvaraj CD /* 2860fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 28612da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 28622da1d7f2SYuvaraj CD */ 28632da1d7f2SYuvaraj CD mci_writel(host, RINTSTS, 0xFFFFFFFF); 28642da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 28652da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2866fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 28672da1d7f2SYuvaraj CD mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 28682da1d7f2SYuvaraj CD 28692da1d7f2SYuvaraj CD dev_info(host->dev, "DW MMC controller at irq %d, " 28702da1d7f2SYuvaraj CD "%d bit host data width, " 28712da1d7f2SYuvaraj CD "%u deep fifo\n", 28722da1d7f2SYuvaraj CD host->irq, width, fifo_size); 28732da1d7f2SYuvaraj CD 2874f95f3850SWill Newton /* We need at least one slot to succeed */ 2875f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2876f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 28771c2215b7SThomas Abraham if (ret) 28781c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 28791c2215b7SThomas Abraham else 28801c2215b7SThomas Abraham init_slots++; 2881f95f3850SWill Newton } 28821c2215b7SThomas Abraham 28831c2215b7SThomas Abraham if (init_slots) { 28841c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 28851c2215b7SThomas Abraham } else { 28861c2215b7SThomas Abraham dev_dbg(host->dev, "attempted to initialize %d slots, " 28871c2215b7SThomas Abraham "but failed on all\n", host->num_slots); 28886130e7a9SDoug Anderson goto err_dmaunmap; 2889f95f3850SWill Newton } 2890f95f3850SWill Newton 2891b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 2892b793f658SDoug Anderson dw_mci_enable_cd(host); 2893b793f658SDoug Anderson 2894f95f3850SWill Newton if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 28954a90920cSThomas Abraham dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2896f95f3850SWill Newton 2897f95f3850SWill Newton return 0; 2898f95f3850SWill Newton 2899f95f3850SWill Newton err_dmaunmap: 2900f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2901f95f3850SWill Newton host->dma_ops->exit(host); 2902f90a0612SThomas Abraham 2903f90a0612SThomas Abraham err_clk_ciu: 2904780f22afSSeungwon Jeon if (!IS_ERR(host->ciu_clk)) 2905f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2906780f22afSSeungwon Jeon 2907f90a0612SThomas Abraham err_clk_biu: 2908780f22afSSeungwon Jeon if (!IS_ERR(host->biu_clk)) 2909f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2910780f22afSSeungwon Jeon 2911f95f3850SWill Newton return ret; 2912f95f3850SWill Newton } 291362ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 2914f95f3850SWill Newton 291562ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 2916f95f3850SWill Newton { 2917f95f3850SWill Newton int i; 2918f95f3850SWill Newton 2919f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 2920f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2921f95f3850SWill Newton 2922f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 29234a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 2924f95f3850SWill Newton if (host->slot[i]) 2925f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 2926f95f3850SWill Newton } 2927f95f3850SWill Newton 2928f95f3850SWill Newton /* disable clock to CIU */ 2929f95f3850SWill Newton mci_writel(host, CLKENA, 0); 2930f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 2931f95f3850SWill Newton 2932f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 2933f95f3850SWill Newton host->dma_ops->exit(host); 2934f95f3850SWill Newton 2935f90a0612SThomas Abraham if (!IS_ERR(host->ciu_clk)) 2936f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 2937780f22afSSeungwon Jeon 2938f90a0612SThomas Abraham if (!IS_ERR(host->biu_clk)) 2939f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 2940f95f3850SWill Newton } 294162ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 294262ca8034SShashidhar Hiremath 294362ca8034SShashidhar Hiremath 2944f95f3850SWill Newton 29456fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 2946f95f3850SWill Newton /* 2947f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 2948f95f3850SWill Newton */ 294962ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 2950f95f3850SWill Newton { 2951f95f3850SWill Newton return 0; 2952f95f3850SWill Newton } 295362ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 2954f95f3850SWill Newton 295562ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 2956f95f3850SWill Newton { 2957f95f3850SWill Newton int i, ret; 2958f95f3850SWill Newton 29593a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 2960e61cf118SJaehoon Chung ret = -ENODEV; 2961e61cf118SJaehoon Chung return ret; 2962e61cf118SJaehoon Chung } 2963e61cf118SJaehoon Chung 29643bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 2965141a712aSSeungwon Jeon host->dma_ops->init(host); 2966141a712aSSeungwon Jeon 296752426899SSeungwon Jeon /* 296852426899SSeungwon Jeon * Restore the initial value at FIFOTH register 296952426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 297052426899SSeungwon Jeon */ 2971e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 297252426899SSeungwon Jeon host->prev_blksz = 0; 2973e61cf118SJaehoon Chung 29742eb2944fSDoug Anderson /* Put in max timeout */ 29752eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 29762eb2944fSDoug Anderson 2977e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 2978e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2979e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2980fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 2981e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2982e61cf118SJaehoon Chung 2983f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 2984f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 2985f95f3850SWill Newton if (!slot) 2986f95f3850SWill Newton continue; 2987ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 2988ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 2989ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 2990ab269128SAbhilash Kesavan } 2991f95f3850SWill Newton } 2992fa0c3283SDoug Anderson 2993fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 2994fa0c3283SDoug Anderson dw_mci_enable_cd(host); 2995fa0c3283SDoug Anderson 2996f95f3850SWill Newton return 0; 2997f95f3850SWill Newton } 299862ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 29996fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 30006fe8890dSJaehoon Chung 3001f95f3850SWill Newton static int __init dw_mci_init(void) 3002f95f3850SWill Newton { 30038e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 300462ca8034SShashidhar Hiremath return 0; 3005f95f3850SWill Newton } 3006f95f3850SWill Newton 3007f95f3850SWill Newton static void __exit dw_mci_exit(void) 3008f95f3850SWill Newton { 3009f95f3850SWill Newton } 3010f95f3850SWill Newton 3011f95f3850SWill Newton module_init(dw_mci_init); 3012f95f3850SWill Newton module_exit(dw_mci_exit); 3013f95f3850SWill Newton 3014f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3015f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3016f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3017f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3018