1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22b6d2d81cSShawn Lin #include <linux/iopoll.h> 23f95f3850SWill Newton #include <linux/ioport.h> 24f95f3850SWill Newton #include <linux/module.h> 25f95f3850SWill Newton #include <linux/platform_device.h> 26a6db2c86SDouglas Anderson #include <linux/pm_runtime.h> 27f95f3850SWill Newton #include <linux/seq_file.h> 28f95f3850SWill Newton #include <linux/slab.h> 29f95f3850SWill Newton #include <linux/stat.h> 30f95f3850SWill Newton #include <linux/delay.h> 31f95f3850SWill Newton #include <linux/irq.h> 32b24c8b26SDoug Anderson #include <linux/mmc/card.h> 33f95f3850SWill Newton #include <linux/mmc/host.h> 34f95f3850SWill Newton #include <linux/mmc/mmc.h> 3501730558SDoug Anderson #include <linux/mmc/sd.h> 3690c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 37f95f3850SWill Newton #include <linux/bitops.h> 38c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 39c91eab4bSThomas Abraham #include <linux/of.h> 4055a6ceb2SDoug Anderson #include <linux/of_gpio.h> 41bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 42f95f3850SWill Newton 43f95f3850SWill Newton #include "dw_mmc.h" 44f95f3850SWill Newton 45f95f3850SWill Newton /* Common flag combinations */ 463f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 487a3c5677SDoug Anderson SDMMC_INT_EBE | SDMMC_INT_HLE) 49f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 507a3c5677SDoug Anderson SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 527a3c5677SDoug Anderson DW_MCI_CMD_ERROR_FLAGS) 53f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 54f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 55f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 56f95f3850SWill Newton 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 5872e83577SJaehoon Chung #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 591f44a2a5SSeungwon Jeon 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 65cc190d4cSShawn Lin #define DESC_RING_BUF_SZ PAGE_SIZE 66cc190d4cSShawn Lin 6769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6869d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 69b6d2d81cSShawn Lin #define IDMAC_OWN_CLR64(x) \ 70b6d2d81cSShawn Lin !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 7169d99fdcSPrabu Thangamuthu 7269d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7569d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 766687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 776687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 8069d99fdcSPrabu Thangamuthu 8169d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 8269d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 8369d99fdcSPrabu Thangamuthu 8469d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8569d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8669d99fdcSPrabu Thangamuthu }; 8769d99fdcSPrabu Thangamuthu 88f95f3850SWill Newton struct idmac_desc { 896687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 90f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 91f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 92f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 93f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 94f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 95f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 96f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 97f95f3850SWill Newton 986687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 99f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100e5306c3aSBen Dooks ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101f95f3850SWill Newton 1026687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 103f95f3850SWill Newton 1046687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 105f95f3850SWill Newton }; 1065959b32eSAlexey Brodkin 1075959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1085959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 109f95f3850SWill Newton 110f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 111f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 112f95f3850SWill Newton { 113f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 114f95f3850SWill Newton struct mmc_request *mrq; 115f95f3850SWill Newton struct mmc_command *cmd; 116f95f3850SWill Newton struct mmc_command *stop; 117f95f3850SWill Newton struct mmc_data *data; 118f95f3850SWill Newton 119f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 120f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 121f95f3850SWill Newton mrq = slot->mrq; 122f95f3850SWill Newton 123f95f3850SWill Newton if (mrq) { 124f95f3850SWill Newton cmd = mrq->cmd; 125f95f3850SWill Newton data = mrq->data; 126f95f3850SWill Newton stop = mrq->stop; 127f95f3850SWill Newton 128f95f3850SWill Newton if (cmd) 129f95f3850SWill Newton seq_printf(s, 130f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 132f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 133f95f3850SWill Newton cmd->resp[2], cmd->error); 134f95f3850SWill Newton if (data) 135f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136f95f3850SWill Newton data->bytes_xfered, data->blocks, 137f95f3850SWill Newton data->blksz, data->flags, data->error); 138f95f3850SWill Newton if (stop) 139f95f3850SWill Newton seq_printf(s, 140f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 142f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 143f95f3850SWill Newton stop->resp[2], stop->error); 144f95f3850SWill Newton } 145f95f3850SWill Newton 146f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 147f95f3850SWill Newton 148f95f3850SWill Newton return 0; 149f95f3850SWill Newton } 150f95f3850SWill Newton 151f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 152f95f3850SWill Newton { 153f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 154f95f3850SWill Newton } 155f95f3850SWill Newton 156f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 157f95f3850SWill Newton .owner = THIS_MODULE, 158f95f3850SWill Newton .open = dw_mci_req_open, 159f95f3850SWill Newton .read = seq_read, 160f95f3850SWill Newton .llseek = seq_lseek, 161f95f3850SWill Newton .release = single_release, 162f95f3850SWill Newton }; 163f95f3850SWill Newton 164f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 165f95f3850SWill Newton { 16621657ebdSJaehoon Chung struct dw_mci *host = s->private; 16721657ebdSJaehoon Chung 16821657ebdSJaehoon Chung seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 16921657ebdSJaehoon Chung seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 17021657ebdSJaehoon Chung seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 17121657ebdSJaehoon Chung seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 17221657ebdSJaehoon Chung seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 17321657ebdSJaehoon Chung seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 174f95f3850SWill Newton 175f95f3850SWill Newton return 0; 176f95f3850SWill Newton } 177f95f3850SWill Newton 178f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 179f95f3850SWill Newton { 180f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 181f95f3850SWill Newton } 182f95f3850SWill Newton 183f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 184f95f3850SWill Newton .owner = THIS_MODULE, 185f95f3850SWill Newton .open = dw_mci_regs_open, 186f95f3850SWill Newton .read = seq_read, 187f95f3850SWill Newton .llseek = seq_lseek, 188f95f3850SWill Newton .release = single_release, 189f95f3850SWill Newton }; 190f95f3850SWill Newton 191f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 192f95f3850SWill Newton { 193f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 194f95f3850SWill Newton struct dw_mci *host = slot->host; 195f95f3850SWill Newton struct dentry *root; 196f95f3850SWill Newton struct dentry *node; 197f95f3850SWill Newton 198f95f3850SWill Newton root = mmc->debugfs_root; 199f95f3850SWill Newton if (!root) 200f95f3850SWill Newton return; 201f95f3850SWill Newton 202f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 203f95f3850SWill Newton &dw_mci_regs_fops); 204f95f3850SWill Newton if (!node) 205f95f3850SWill Newton goto err; 206f95f3850SWill Newton 207f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 208f95f3850SWill Newton &dw_mci_req_fops); 209f95f3850SWill Newton if (!node) 210f95f3850SWill Newton goto err; 211f95f3850SWill Newton 212f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 213f95f3850SWill Newton if (!node) 214f95f3850SWill Newton goto err; 215f95f3850SWill Newton 216f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 217f95f3850SWill Newton (u32 *)&host->pending_events); 218f95f3850SWill Newton if (!node) 219f95f3850SWill Newton goto err; 220f95f3850SWill Newton 221f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 222f95f3850SWill Newton (u32 *)&host->completed_events); 223f95f3850SWill Newton if (!node) 224f95f3850SWill Newton goto err; 225f95f3850SWill Newton 226f95f3850SWill Newton return; 227f95f3850SWill Newton 228f95f3850SWill Newton err: 229f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 230f95f3850SWill Newton } 231f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 232f95f3850SWill Newton 2338e6db1f6SShawn Lin static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2348e6db1f6SShawn Lin { 2358e6db1f6SShawn Lin u32 ctrl; 2368e6db1f6SShawn Lin 2378e6db1f6SShawn Lin ctrl = mci_readl(host, CTRL); 2388e6db1f6SShawn Lin ctrl |= reset; 2398e6db1f6SShawn Lin mci_writel(host, CTRL, ctrl); 2408e6db1f6SShawn Lin 2418e6db1f6SShawn Lin /* wait till resets clear */ 2428e6db1f6SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 2438e6db1f6SShawn Lin !(ctrl & reset), 2448e6db1f6SShawn Lin 1, 500 * USEC_PER_MSEC)) { 2458e6db1f6SShawn Lin dev_err(host->dev, 2468e6db1f6SShawn Lin "Timeout resetting block (ctrl reset %#x)\n", 2478e6db1f6SShawn Lin ctrl & reset); 2488e6db1f6SShawn Lin return false; 2498e6db1f6SShawn Lin } 2508e6db1f6SShawn Lin 2518e6db1f6SShawn Lin return true; 2528e6db1f6SShawn Lin } 25301730558SDoug Anderson 254*4dba18deSShawn Lin static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 255*4dba18deSShawn Lin { 256*4dba18deSShawn Lin u32 status; 257*4dba18deSShawn Lin 258*4dba18deSShawn Lin /* 259*4dba18deSShawn Lin * Databook says that before issuing a new data transfer command 260*4dba18deSShawn Lin * we need to check to see if the card is busy. Data transfer commands 261*4dba18deSShawn Lin * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 262*4dba18deSShawn Lin * 263*4dba18deSShawn Lin * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 264*4dba18deSShawn Lin * expected. 265*4dba18deSShawn Lin */ 266*4dba18deSShawn Lin if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 267*4dba18deSShawn Lin !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 268*4dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 269*4dba18deSShawn Lin status, 270*4dba18deSShawn Lin !(status & SDMMC_STATUS_BUSY), 271*4dba18deSShawn Lin 10, 500 * USEC_PER_MSEC)) 272*4dba18deSShawn Lin dev_err(host->dev, "Busy; trying anyway\n"); 273*4dba18deSShawn Lin } 274*4dba18deSShawn Lin } 275*4dba18deSShawn Lin 276*4dba18deSShawn Lin static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 277*4dba18deSShawn Lin { 278*4dba18deSShawn Lin struct dw_mci *host = slot->host; 279*4dba18deSShawn Lin unsigned int cmd_status = 0; 280*4dba18deSShawn Lin 281*4dba18deSShawn Lin mci_writel(host, CMDARG, arg); 282*4dba18deSShawn Lin wmb(); /* drain writebuffer */ 283*4dba18deSShawn Lin dw_mci_wait_while_busy(host, cmd); 284*4dba18deSShawn Lin mci_writel(host, CMD, SDMMC_CMD_START | cmd); 285*4dba18deSShawn Lin 286*4dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 287*4dba18deSShawn Lin !(cmd_status & SDMMC_CMD_START), 288*4dba18deSShawn Lin 1, 500 * USEC_PER_MSEC)) 289*4dba18deSShawn Lin dev_err(&slot->mmc->class_dev, 290*4dba18deSShawn Lin "Timeout sending command (cmd %#x arg %#x status %#x)\n", 291*4dba18deSShawn Lin cmd, arg, cmd_status); 292*4dba18deSShawn Lin } 293*4dba18deSShawn Lin 294f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 295f95f3850SWill Newton { 296800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 29701730558SDoug Anderson struct dw_mci *host = slot->host; 298f95f3850SWill Newton u32 cmdr; 299f95f3850SWill Newton 3000e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 301f95f3850SWill Newton cmdr = cmd->opcode; 302f95f3850SWill Newton 30390c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 30490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 30590c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 30690c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 30790c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 308f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 3094a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 310f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 311f95f3850SWill Newton 31201730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 31301730558SDoug Anderson u32 clk_en_a; 31401730558SDoug Anderson 31501730558SDoug Anderson /* Special bit makes CMD11 not die */ 31601730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 31701730558SDoug Anderson 31801730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 31901730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 32001730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 32101730558SDoug Anderson 32201730558SDoug Anderson /* 32301730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 32401730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 32501730558SDoug Anderson * since stopping the clock is a specific part of the UHS 32601730558SDoug Anderson * voltage change dance. 32701730558SDoug Anderson * 32801730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 32901730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 33001730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 33101730558SDoug Anderson * until the voltage change is all done. 33201730558SDoug Anderson */ 33301730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 33401730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 33501730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 33601730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 33701730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 33801730558SDoug Anderson } 33901730558SDoug Anderson 340f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 341f95f3850SWill Newton /* We expect a response, so set this bit */ 342f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 343f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 344f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 345f95f3850SWill Newton } 346f95f3850SWill Newton 347f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 348f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 349f95f3850SWill Newton 3500349c085SJaehoon Chung if (cmd->data) { 351f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 3520349c085SJaehoon Chung if (cmd->data->flags & MMC_DATA_WRITE) 353f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 354f95f3850SWill Newton } 355f95f3850SWill Newton 356aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 357aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 358800d78bfSThomas Abraham 359f95f3850SWill Newton return cmdr; 360f95f3850SWill Newton } 361f95f3850SWill Newton 36290c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 36390c2143aSSeungwon Jeon { 36490c2143aSSeungwon Jeon struct mmc_command *stop; 36590c2143aSSeungwon Jeon u32 cmdr; 36690c2143aSSeungwon Jeon 36790c2143aSSeungwon Jeon if (!cmd->data) 36890c2143aSSeungwon Jeon return 0; 36990c2143aSSeungwon Jeon 37090c2143aSSeungwon Jeon stop = &host->stop_abort; 37190c2143aSSeungwon Jeon cmdr = cmd->opcode; 37290c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 37390c2143aSSeungwon Jeon 37490c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 37590c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 37690c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3776c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3786c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3796c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 38090c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 38190c2143aSSeungwon Jeon stop->arg = 0; 38290c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 38390c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 38490c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 38590c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 38690c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 38790c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 38890c2143aSSeungwon Jeon } else { 38990c2143aSSeungwon Jeon return 0; 39090c2143aSSeungwon Jeon } 39190c2143aSSeungwon Jeon 39290c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 39390c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 39490c2143aSSeungwon Jeon 3958c005b40SJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags)) 3968c005b40SJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 3978c005b40SJaehoon Chung 39890c2143aSSeungwon Jeon return cmdr; 39990c2143aSSeungwon Jeon } 40090c2143aSSeungwon Jeon 401f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 402f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 403f95f3850SWill Newton { 404f95f3850SWill Newton host->cmd = cmd; 4054a90920cSThomas Abraham dev_vdbg(host->dev, 406f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 407f95f3850SWill Newton cmd->arg, cmd_flags); 408f95f3850SWill Newton 409f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 4100e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 4110bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 412f95f3850SWill Newton 413f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 414f95f3850SWill Newton } 415f95f3850SWill Newton 41690c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 417f95f3850SWill Newton { 418e13c3c08SJaehoon Chung struct mmc_command *stop = &host->stop_abort; 4190e3a22c0SShawn Lin 42090c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 421f95f3850SWill Newton } 422f95f3850SWill Newton 423f95f3850SWill Newton /* DMA interface functions */ 424f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 425f95f3850SWill Newton { 42603e8cb53SJames Hogan if (host->using_dma) { 427f95f3850SWill Newton host->dma_ops->stop(host); 428f95f3850SWill Newton host->dma_ops->cleanup(host); 429aa50f259SSeungwon Jeon } 430aa50f259SSeungwon Jeon 431f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 432f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 433f95f3850SWill Newton } 434f95f3850SWill Newton 4359aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 4369aa51408SSeungwon Jeon { 4379aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4389aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4399aa51408SSeungwon Jeon else 4409aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4419aa51408SSeungwon Jeon } 4429aa51408SSeungwon Jeon 443f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 444f95f3850SWill Newton { 445f95f3850SWill Newton struct mmc_data *data = host->data; 446f95f3850SWill Newton 447a4cc7eb4SJaehoon Chung if (data && data->host_cookie == COOKIE_MAPPED) { 4484a90920cSThomas Abraham dma_unmap_sg(host->dev, 4499aa51408SSeungwon Jeon data->sg, 4509aa51408SSeungwon Jeon data->sg_len, 4519aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 452a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 453a4cc7eb4SJaehoon Chung } 454f95f3850SWill Newton } 455f95f3850SWill Newton 4565ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4575ce9d961SSeungwon Jeon { 4585ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4595ce9d961SSeungwon Jeon /* Software reset of DMA */ 4605ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4615ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4625ce9d961SSeungwon Jeon } 4635ce9d961SSeungwon Jeon 464f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 465f95f3850SWill Newton { 466f95f3850SWill Newton u32 temp; 467f95f3850SWill Newton 468f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 469f95f3850SWill Newton temp = mci_readl(host, CTRL); 470f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 471f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 472f95f3850SWill Newton mci_writel(host, CTRL, temp); 473f95f3850SWill Newton 474f95f3850SWill Newton /* Stop the IDMAC running */ 475f95f3850SWill Newton temp = mci_readl(host, BMOD); 476a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4775ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 478f95f3850SWill Newton mci_writel(host, BMOD, temp); 479f95f3850SWill Newton } 480f95f3850SWill Newton 4813fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 482f95f3850SWill Newton { 4833fc7eaefSShawn Lin struct dw_mci *host = arg; 484f95f3850SWill Newton struct mmc_data *data = host->data; 485f95f3850SWill Newton 4864a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 487f95f3850SWill Newton 4883fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 4893fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 4903fc7eaefSShawn Lin /* Invalidate cache after read */ 4913fc7eaefSShawn Lin dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 4923fc7eaefSShawn Lin data->sg, 4933fc7eaefSShawn Lin data->sg_len, 4943fc7eaefSShawn Lin DMA_FROM_DEVICE); 4953fc7eaefSShawn Lin 496f95f3850SWill Newton host->dma_ops->cleanup(host); 497f95f3850SWill Newton 498f95f3850SWill Newton /* 499f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 500f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 501f95f3850SWill Newton */ 502f95f3850SWill Newton if (data) { 503f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 504f95f3850SWill Newton tasklet_schedule(&host->tasklet); 505f95f3850SWill Newton } 506f95f3850SWill Newton } 507f95f3850SWill Newton 508f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 509f95f3850SWill Newton { 510897b69e7SSeungwon Jeon int i; 511f95f3850SWill Newton 51269d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 51369d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 51469d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 515cc190d4cSShawn Lin host->ring_size = 516cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 51769d99fdcSPrabu Thangamuthu 51869d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 51969d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 52069d99fdcSPrabu Thangamuthu i++, p++) { 52169d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 52269d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 52369d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 52469d99fdcSPrabu Thangamuthu 52569d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 52669d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 52769d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 52869d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 52969d99fdcSPrabu Thangamuthu p->des1 = 0; 53069d99fdcSPrabu Thangamuthu p->des2 = 0; 53169d99fdcSPrabu Thangamuthu p->des3 = 0; 53269d99fdcSPrabu Thangamuthu } 53369d99fdcSPrabu Thangamuthu 53469d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 53569d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 53669d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 53769d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 53869d99fdcSPrabu Thangamuthu 53969d99fdcSPrabu Thangamuthu } else { 54069d99fdcSPrabu Thangamuthu struct idmac_desc *p; 541f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 542cc190d4cSShawn Lin host->ring_size = 543cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 544f95f3850SWill Newton 545f95f3850SWill Newton /* Forward link the descriptor list */ 5460e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 5470e3a22c0SShawn Lin i < host->ring_size - 1; 5480e3a22c0SShawn Lin i++, p++) { 5496687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 5506687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 5514b244724SZhangfei Gao p->des1 = 0; 5524b244724SZhangfei Gao } 553f95f3850SWill Newton 554f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 5556687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 5566687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 55769d99fdcSPrabu Thangamuthu } 558f95f3850SWill Newton 5595ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 560141a712aSSeungwon Jeon 56169d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 56269d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 56369d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 56469d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 56569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 56669d99fdcSPrabu Thangamuthu 56769d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 56869d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 56969d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 57069d99fdcSPrabu Thangamuthu 57169d99fdcSPrabu Thangamuthu } else { 572f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 573fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 57469d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 57569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 576f95f3850SWill Newton 577f95f3850SWill Newton /* Set the descriptor base address */ 578f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 57969d99fdcSPrabu Thangamuthu } 58069d99fdcSPrabu Thangamuthu 581f95f3850SWill Newton return 0; 582f95f3850SWill Newton } 583f95f3850SWill Newton 5843b2a067bSShawn Lin static inline int dw_mci_prepare_desc64(struct dw_mci *host, 5853b2a067bSShawn Lin struct mmc_data *data, 5863b2a067bSShawn Lin unsigned int sg_len) 5873b2a067bSShawn Lin { 5883b2a067bSShawn Lin unsigned int desc_len; 5893b2a067bSShawn Lin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 590b6d2d81cSShawn Lin u32 val; 5913b2a067bSShawn Lin int i; 5923b2a067bSShawn Lin 5933b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 5943b2a067bSShawn Lin 5953b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 5963b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 5973b2a067bSShawn Lin 5983b2a067bSShawn Lin u64 mem_addr = sg_dma_address(&data->sg[i]); 5993b2a067bSShawn Lin 6003b2a067bSShawn Lin for ( ; length ; desc++) { 6013b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6023b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6033b2a067bSShawn Lin 6043b2a067bSShawn Lin length -= desc_len; 6053b2a067bSShawn Lin 6063b2a067bSShawn Lin /* 6073b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6083b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6093b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6103b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6113b2a067bSShawn Lin */ 612b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 613b6d2d81cSShawn Lin !(val & IDMAC_DES0_OWN), 614b6d2d81cSShawn Lin 10, 100 * USEC_PER_MSEC)) 6153b2a067bSShawn Lin goto err_own_bit; 6163b2a067bSShawn Lin 6173b2a067bSShawn Lin /* 6183b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6193b2a067bSShawn Lin * for this descriptor 6203b2a067bSShawn Lin */ 6213b2a067bSShawn Lin desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 6223b2a067bSShawn Lin IDMAC_DES0_CH; 6233b2a067bSShawn Lin 6243b2a067bSShawn Lin /* Buffer length */ 6253b2a067bSShawn Lin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 6263b2a067bSShawn Lin 6273b2a067bSShawn Lin /* Physical address to DMA to/from */ 6283b2a067bSShawn Lin desc->des4 = mem_addr & 0xffffffff; 6293b2a067bSShawn Lin desc->des5 = mem_addr >> 32; 6303b2a067bSShawn Lin 6313b2a067bSShawn Lin /* Update physical address for the next desc */ 6323b2a067bSShawn Lin mem_addr += desc_len; 6333b2a067bSShawn Lin 6343b2a067bSShawn Lin /* Save pointer to the last descriptor */ 6353b2a067bSShawn Lin desc_last = desc; 6363b2a067bSShawn Lin } 6373b2a067bSShawn Lin } 6383b2a067bSShawn Lin 6393b2a067bSShawn Lin /* Set first descriptor */ 6403b2a067bSShawn Lin desc_first->des0 |= IDMAC_DES0_FD; 6413b2a067bSShawn Lin 6423b2a067bSShawn Lin /* Set last descriptor */ 6433b2a067bSShawn Lin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 6443b2a067bSShawn Lin desc_last->des0 |= IDMAC_DES0_LD; 6453b2a067bSShawn Lin 6463b2a067bSShawn Lin return 0; 6473b2a067bSShawn Lin err_own_bit: 6483b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 64926be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 650cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 6513b2a067bSShawn Lin dw_mci_idmac_init(host); 6523b2a067bSShawn Lin return -EINVAL; 6533b2a067bSShawn Lin } 6543b2a067bSShawn Lin 6553b2a067bSShawn Lin 6563b2a067bSShawn Lin static inline int dw_mci_prepare_desc32(struct dw_mci *host, 6573b2a067bSShawn Lin struct mmc_data *data, 6583b2a067bSShawn Lin unsigned int sg_len) 6593b2a067bSShawn Lin { 6603b2a067bSShawn Lin unsigned int desc_len; 6613b2a067bSShawn Lin struct idmac_desc *desc_first, *desc_last, *desc; 662b6d2d81cSShawn Lin u32 val; 6633b2a067bSShawn Lin int i; 6643b2a067bSShawn Lin 6653b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6663b2a067bSShawn Lin 6673b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6683b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6693b2a067bSShawn Lin 6703b2a067bSShawn Lin u32 mem_addr = sg_dma_address(&data->sg[i]); 6713b2a067bSShawn Lin 6723b2a067bSShawn Lin for ( ; length ; desc++) { 6733b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6743b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6753b2a067bSShawn Lin 6763b2a067bSShawn Lin length -= desc_len; 6773b2a067bSShawn Lin 6783b2a067bSShawn Lin /* 6793b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6803b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6813b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6823b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6833b2a067bSShawn Lin */ 684b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 685b6d2d81cSShawn Lin IDMAC_OWN_CLR64(val), 686b6d2d81cSShawn Lin 10, 687b6d2d81cSShawn Lin 100 * USEC_PER_MSEC)) 6883b2a067bSShawn Lin goto err_own_bit; 6893b2a067bSShawn Lin 6903b2a067bSShawn Lin /* 6913b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6923b2a067bSShawn Lin * for this descriptor 6933b2a067bSShawn Lin */ 6943b2a067bSShawn Lin desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 6953b2a067bSShawn Lin IDMAC_DES0_DIC | 6963b2a067bSShawn Lin IDMAC_DES0_CH); 6973b2a067bSShawn Lin 6983b2a067bSShawn Lin /* Buffer length */ 6993b2a067bSShawn Lin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 7003b2a067bSShawn Lin 7013b2a067bSShawn Lin /* Physical address to DMA to/from */ 7023b2a067bSShawn Lin desc->des2 = cpu_to_le32(mem_addr); 7033b2a067bSShawn Lin 7043b2a067bSShawn Lin /* Update physical address for the next desc */ 7053b2a067bSShawn Lin mem_addr += desc_len; 7063b2a067bSShawn Lin 7073b2a067bSShawn Lin /* Save pointer to the last descriptor */ 7083b2a067bSShawn Lin desc_last = desc; 7093b2a067bSShawn Lin } 7103b2a067bSShawn Lin } 7113b2a067bSShawn Lin 7123b2a067bSShawn Lin /* Set first descriptor */ 7133b2a067bSShawn Lin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 7143b2a067bSShawn Lin 7153b2a067bSShawn Lin /* Set last descriptor */ 7163b2a067bSShawn Lin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 7173b2a067bSShawn Lin IDMAC_DES0_DIC)); 7183b2a067bSShawn Lin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 7193b2a067bSShawn Lin 7203b2a067bSShawn Lin return 0; 7213b2a067bSShawn Lin err_own_bit: 7223b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 72326be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 724cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 7253b2a067bSShawn Lin dw_mci_idmac_init(host); 7263b2a067bSShawn Lin return -EINVAL; 7273b2a067bSShawn Lin } 7283b2a067bSShawn Lin 7293b2a067bSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 7303b2a067bSShawn Lin { 7313b2a067bSShawn Lin u32 temp; 7323b2a067bSShawn Lin int ret; 7333b2a067bSShawn Lin 7343b2a067bSShawn Lin if (host->dma_64bit_address == 1) 7353b2a067bSShawn Lin ret = dw_mci_prepare_desc64(host, host->data, sg_len); 7363b2a067bSShawn Lin else 7373b2a067bSShawn Lin ret = dw_mci_prepare_desc32(host, host->data, sg_len); 7383b2a067bSShawn Lin 7393b2a067bSShawn Lin if (ret) 7403b2a067bSShawn Lin goto out; 7413b2a067bSShawn Lin 7423b2a067bSShawn Lin /* drain writebuffer */ 7433b2a067bSShawn Lin wmb(); 7443b2a067bSShawn Lin 7453b2a067bSShawn Lin /* Make sure to reset DMA in case we did PIO before this */ 7463b2a067bSShawn Lin dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 7473b2a067bSShawn Lin dw_mci_idmac_reset(host); 7483b2a067bSShawn Lin 7493b2a067bSShawn Lin /* Select IDMAC interface */ 7503b2a067bSShawn Lin temp = mci_readl(host, CTRL); 7513b2a067bSShawn Lin temp |= SDMMC_CTRL_USE_IDMAC; 7523b2a067bSShawn Lin mci_writel(host, CTRL, temp); 7533b2a067bSShawn Lin 7543b2a067bSShawn Lin /* drain writebuffer */ 7553b2a067bSShawn Lin wmb(); 7563b2a067bSShawn Lin 7573b2a067bSShawn Lin /* Enable the IDMAC */ 7583b2a067bSShawn Lin temp = mci_readl(host, BMOD); 7593b2a067bSShawn Lin temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 7603b2a067bSShawn Lin mci_writel(host, BMOD, temp); 7613b2a067bSShawn Lin 7623b2a067bSShawn Lin /* Start it running */ 7633b2a067bSShawn Lin mci_writel(host, PLDMND, 1); 7643b2a067bSShawn Lin 7653b2a067bSShawn Lin out: 7663b2a067bSShawn Lin return ret; 7673b2a067bSShawn Lin } 7683b2a067bSShawn Lin 7698e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 770885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 771885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 772885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 7733fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 774885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 775885c3e80SSeungwon Jeon }; 7763fc7eaefSShawn Lin 7773fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 7783fc7eaefSShawn Lin { 779ab925a31SShawn Lin dmaengine_terminate_async(host->dms->ch); 7803fc7eaefSShawn Lin } 7813fc7eaefSShawn Lin 7823fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 7833fc7eaefSShawn Lin unsigned int sg_len) 7843fc7eaefSShawn Lin { 7853fc7eaefSShawn Lin struct dma_slave_config cfg; 7863fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 7873fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 7883fc7eaefSShawn Lin const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 7893fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 7903fc7eaefSShawn Lin u32 fifoth_val; 7913fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 7923fc7eaefSShawn Lin int ret = 0; 7933fc7eaefSShawn Lin 7943fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 795260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 7963fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 7973fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7983fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7993fc7eaefSShawn Lin 8003fc7eaefSShawn Lin /* Match burst msize with external dma config */ 8013fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 8023fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 8033fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 8043fc7eaefSShawn Lin 8053fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 8063fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 8073fc7eaefSShawn Lin else 8083fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 8093fc7eaefSShawn Lin 8103fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 8113fc7eaefSShawn Lin if (ret) { 8123fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 8133fc7eaefSShawn Lin return -EBUSY; 8143fc7eaefSShawn Lin } 8153fc7eaefSShawn Lin 8163fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 8173fc7eaefSShawn Lin sg_len, cfg.direction, 8183fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 8193fc7eaefSShawn Lin if (!desc) { 8203fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 8213fc7eaefSShawn Lin return -EBUSY; 8223fc7eaefSShawn Lin } 8233fc7eaefSShawn Lin 8243fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 8253fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 8263fc7eaefSShawn Lin desc->callback_param = (void *)host; 8273fc7eaefSShawn Lin dmaengine_submit(desc); 8283fc7eaefSShawn Lin 8293fc7eaefSShawn Lin /* Flush cache before write */ 8303fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 8313fc7eaefSShawn Lin dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 8323fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 8333fc7eaefSShawn Lin 8343fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 8353fc7eaefSShawn Lin 8363fc7eaefSShawn Lin return 0; 8373fc7eaefSShawn Lin } 8383fc7eaefSShawn Lin 8393fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 8403fc7eaefSShawn Lin { 8413fc7eaefSShawn Lin /* Request external dma channel */ 8423fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 8433fc7eaefSShawn Lin if (!host->dms) 8443fc7eaefSShawn Lin return -ENOMEM; 8453fc7eaefSShawn Lin 8463fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 8473fc7eaefSShawn Lin if (!host->dms->ch) { 8484539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 8493fc7eaefSShawn Lin kfree(host->dms); 8503fc7eaefSShawn Lin host->dms = NULL; 8513fc7eaefSShawn Lin return -ENXIO; 8523fc7eaefSShawn Lin } 8533fc7eaefSShawn Lin 8543fc7eaefSShawn Lin return 0; 8553fc7eaefSShawn Lin } 8563fc7eaefSShawn Lin 8573fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 8583fc7eaefSShawn Lin { 8593fc7eaefSShawn Lin if (host->dms) { 8603fc7eaefSShawn Lin if (host->dms->ch) { 8613fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 8623fc7eaefSShawn Lin host->dms->ch = NULL; 8633fc7eaefSShawn Lin } 8643fc7eaefSShawn Lin kfree(host->dms); 8653fc7eaefSShawn Lin host->dms = NULL; 8663fc7eaefSShawn Lin } 8673fc7eaefSShawn Lin } 8683fc7eaefSShawn Lin 8693fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 8703fc7eaefSShawn Lin .init = dw_mci_edmac_init, 8713fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 8723fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 8733fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 8743fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 8753fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 8763fc7eaefSShawn Lin }; 877885c3e80SSeungwon Jeon 8789aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 8799aa51408SSeungwon Jeon struct mmc_data *data, 880a4cc7eb4SJaehoon Chung int cookie) 881f95f3850SWill Newton { 882f95f3850SWill Newton struct scatterlist *sg; 8839aa51408SSeungwon Jeon unsigned int i, sg_len; 884f95f3850SWill Newton 885a4cc7eb4SJaehoon Chung if (data->host_cookie == COOKIE_PRE_MAPPED) 886a4cc7eb4SJaehoon Chung return data->sg_len; 887f95f3850SWill Newton 888f95f3850SWill Newton /* 889f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 890f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 891f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 892f95f3850SWill Newton */ 893f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 894f95f3850SWill Newton return -EINVAL; 8959aa51408SSeungwon Jeon 896f95f3850SWill Newton if (data->blksz & 3) 897f95f3850SWill Newton return -EINVAL; 898f95f3850SWill Newton 899f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 900f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 901f95f3850SWill Newton return -EINVAL; 902f95f3850SWill Newton } 903f95f3850SWill Newton 9044a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 9059aa51408SSeungwon Jeon data->sg, 9069aa51408SSeungwon Jeon data->sg_len, 9079aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 9089aa51408SSeungwon Jeon if (sg_len == 0) 9099aa51408SSeungwon Jeon return -EINVAL; 9109aa51408SSeungwon Jeon 911a4cc7eb4SJaehoon Chung data->host_cookie = cookie; 9129aa51408SSeungwon Jeon 9139aa51408SSeungwon Jeon return sg_len; 9149aa51408SSeungwon Jeon } 9159aa51408SSeungwon Jeon 9169aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 917d3c6aac3SLinus Walleij struct mmc_request *mrq) 9189aa51408SSeungwon Jeon { 9199aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9209aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9219aa51408SSeungwon Jeon 9229aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9239aa51408SSeungwon Jeon return; 9249aa51408SSeungwon Jeon 925a4cc7eb4SJaehoon Chung /* This data might be unmapped at this time */ 926a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9279aa51408SSeungwon Jeon 928a4cc7eb4SJaehoon Chung if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 929a4cc7eb4SJaehoon Chung COOKIE_PRE_MAPPED) < 0) 930a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9319aa51408SSeungwon Jeon } 9329aa51408SSeungwon Jeon 9339aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 9349aa51408SSeungwon Jeon struct mmc_request *mrq, 9359aa51408SSeungwon Jeon int err) 9369aa51408SSeungwon Jeon { 9379aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9389aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9399aa51408SSeungwon Jeon 9409aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9419aa51408SSeungwon Jeon return; 9429aa51408SSeungwon Jeon 943a4cc7eb4SJaehoon Chung if (data->host_cookie != COOKIE_UNMAPPED) 9444a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 9459aa51408SSeungwon Jeon data->sg, 9469aa51408SSeungwon Jeon data->sg_len, 9479aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 948a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9499aa51408SSeungwon Jeon } 9509aa51408SSeungwon Jeon 951671fa142SShawn Lin static int dw_mci_get_cd(struct mmc_host *mmc) 952671fa142SShawn Lin { 953671fa142SShawn Lin int present; 954671fa142SShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 955671fa142SShawn Lin struct dw_mci *host = slot->host; 956671fa142SShawn Lin int gpio_cd = mmc_gpio_get_cd(mmc); 957671fa142SShawn Lin 958671fa142SShawn Lin /* Use platform get_cd function, else try onboard card detect */ 959671fa142SShawn Lin if (((mmc->caps & MMC_CAP_NEEDS_POLL) 960671fa142SShawn Lin || !mmc_card_is_removable(mmc))) { 961671fa142SShawn Lin present = 1; 962671fa142SShawn Lin 963671fa142SShawn Lin if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 964671fa142SShawn Lin if (mmc->caps & MMC_CAP_NEEDS_POLL) { 965671fa142SShawn Lin dev_info(&mmc->class_dev, 966671fa142SShawn Lin "card is polling.\n"); 967671fa142SShawn Lin } else { 968671fa142SShawn Lin dev_info(&mmc->class_dev, 969671fa142SShawn Lin "card is non-removable.\n"); 970671fa142SShawn Lin } 971671fa142SShawn Lin set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 972671fa142SShawn Lin } 973671fa142SShawn Lin 974671fa142SShawn Lin return present; 975671fa142SShawn Lin } else if (gpio_cd >= 0) 976671fa142SShawn Lin present = gpio_cd; 977671fa142SShawn Lin else 978671fa142SShawn Lin present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 979671fa142SShawn Lin == 0 ? 1 : 0; 980671fa142SShawn Lin 981671fa142SShawn Lin spin_lock_bh(&host->lock); 982671fa142SShawn Lin if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 983671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is present\n"); 984671fa142SShawn Lin else if (!present && 985671fa142SShawn Lin !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 986671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is not present\n"); 987671fa142SShawn Lin spin_unlock_bh(&host->lock); 988671fa142SShawn Lin 989671fa142SShawn Lin return present; 990671fa142SShawn Lin } 991671fa142SShawn Lin 99252426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 99352426899SSeungwon Jeon { 99452426899SSeungwon Jeon unsigned int blksz = data->blksz; 99552426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 99652426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 99752426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 99852426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 9990e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 100052426899SSeungwon Jeon 10013fc7eaefSShawn Lin /* pio should ship this scenario */ 10023fc7eaefSShawn Lin if (!host->use_dma) 10033fc7eaefSShawn Lin return; 10043fc7eaefSShawn Lin 100552426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 100652426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 100752426899SSeungwon Jeon 100852426899SSeungwon Jeon /* 100952426899SSeungwon Jeon * MSIZE is '1', 101052426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 101152426899SSeungwon Jeon */ 101220753569SShawn Lin if (blksz % fifo_width) 101352426899SSeungwon Jeon goto done; 101452426899SSeungwon Jeon 101552426899SSeungwon Jeon do { 101652426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 101752426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 101852426899SSeungwon Jeon msize = idx; 101952426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 102052426899SSeungwon Jeon break; 102152426899SSeungwon Jeon } 102252426899SSeungwon Jeon } while (--idx > 0); 102352426899SSeungwon Jeon /* 102452426899SSeungwon Jeon * If idx is '0', it won't be tried 102552426899SSeungwon Jeon * Thus, initial values are uesed 102652426899SSeungwon Jeon */ 102752426899SSeungwon Jeon done: 102852426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 102952426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 103052426899SSeungwon Jeon } 103152426899SSeungwon Jeon 10327e4bf1bcSJaehoon Chung static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1033f1d2736cSSeungwon Jeon { 1034f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 1035f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 1036f1d2736cSSeungwon Jeon u16 thld_size; 10377e4bf1bcSJaehoon Chung u8 enable; 1038f1d2736cSSeungwon Jeon 103966dfd101SJames Hogan /* 104066dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 104166dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 104266dfd101SJames Hogan */ 10437e4bf1bcSJaehoon Chung if (host->verid < DW_MMC_240A || 10447e4bf1bcSJaehoon Chung (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 104566dfd101SJames Hogan return; 104666dfd101SJames Hogan 10477e4bf1bcSJaehoon Chung /* 10487e4bf1bcSJaehoon Chung * Card write Threshold is introduced since 2.80a 10497e4bf1bcSJaehoon Chung * It's used when HS400 mode is enabled. 10507e4bf1bcSJaehoon Chung */ 10517e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE && 10527e4bf1bcSJaehoon Chung !(host->timing != MMC_TIMING_MMC_HS400)) 10537e4bf1bcSJaehoon Chung return; 10547e4bf1bcSJaehoon Chung 10557e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE) 10567e4bf1bcSJaehoon Chung enable = SDMMC_CARD_WR_THR_EN; 10577e4bf1bcSJaehoon Chung else 10587e4bf1bcSJaehoon Chung enable = SDMMC_CARD_RD_THR_EN; 10597e4bf1bcSJaehoon Chung 1060f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 1061f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 1062f1d2736cSSeungwon Jeon goto disable; 1063f1d2736cSSeungwon Jeon 1064f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 1065f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 1066f1d2736cSSeungwon Jeon 1067f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 1068f1d2736cSSeungwon Jeon goto disable; 1069f1d2736cSSeungwon Jeon 1070f1d2736cSSeungwon Jeon /* 1071f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1072f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1073f1d2736cSSeungwon Jeon * Currently just choose blksz. 1074f1d2736cSSeungwon Jeon */ 1075f1d2736cSSeungwon Jeon thld_size = blksz; 10767e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1077f1d2736cSSeungwon Jeon return; 1078f1d2736cSSeungwon Jeon 1079f1d2736cSSeungwon Jeon disable: 10807e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, 0); 1081f1d2736cSSeungwon Jeon } 1082f1d2736cSSeungwon Jeon 10839aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 10849aa51408SSeungwon Jeon { 1085f8c58c11SDoug Anderson unsigned long irqflags; 10869aa51408SSeungwon Jeon int sg_len; 10879aa51408SSeungwon Jeon u32 temp; 10889aa51408SSeungwon Jeon 10899aa51408SSeungwon Jeon host->using_dma = 0; 10909aa51408SSeungwon Jeon 10919aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 10929aa51408SSeungwon Jeon if (!host->use_dma) 10939aa51408SSeungwon Jeon return -ENODEV; 10949aa51408SSeungwon Jeon 1095a4cc7eb4SJaehoon Chung sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1096a99aa9b9SSeungwon Jeon if (sg_len < 0) { 1097a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 10989aa51408SSeungwon Jeon return sg_len; 1099a99aa9b9SSeungwon Jeon } 11009aa51408SSeungwon Jeon 110103e8cb53SJames Hogan host->using_dma = 1; 110203e8cb53SJames Hogan 11033fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 11044a90920cSThomas Abraham dev_vdbg(host->dev, 1105f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 11063fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 11073fc7eaefSShawn Lin (unsigned long)host->sg_dma, 1108f95f3850SWill Newton sg_len); 1109f95f3850SWill Newton 111052426899SSeungwon Jeon /* 111152426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 111252426899SSeungwon Jeon * If current block size is same with previous size, 111352426899SSeungwon Jeon * no need to update fifoth. 111452426899SSeungwon Jeon */ 111552426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 111652426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 111752426899SSeungwon Jeon 1118f95f3850SWill Newton /* Enable the DMA interface */ 1119f95f3850SWill Newton temp = mci_readl(host, CTRL); 1120f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 1121f95f3850SWill Newton mci_writel(host, CTRL, temp); 1122f95f3850SWill Newton 1123f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 1124f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1125f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1126f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1127f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1128f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1129f95f3850SWill Newton 11303fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 1131647f80a1SJaehoon Chung host->dma_ops->stop(host); 1132d12d0cb1SShawn Lin /* We can't do DMA, try PIO for this one */ 1133d12d0cb1SShawn Lin dev_dbg(host->dev, 1134d12d0cb1SShawn Lin "%s: fall back to PIO mode for current transfer\n", 1135d12d0cb1SShawn Lin __func__); 11363fc7eaefSShawn Lin return -ENODEV; 11373fc7eaefSShawn Lin } 1138f95f3850SWill Newton 1139f95f3850SWill Newton return 0; 1140f95f3850SWill Newton } 1141f95f3850SWill Newton 1142f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1143f95f3850SWill Newton { 1144f8c58c11SDoug Anderson unsigned long irqflags; 11450e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1146f95f3850SWill Newton u32 temp; 1147f95f3850SWill Newton 1148f95f3850SWill Newton data->error = -EINPROGRESS; 1149f95f3850SWill Newton 1150f95f3850SWill Newton WARN_ON(host->data); 1151f95f3850SWill Newton host->sg = NULL; 1152f95f3850SWill Newton host->data = data; 1153f95f3850SWill Newton 11547e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_READ) 115555c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 11567e4bf1bcSJaehoon Chung else 115755c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 11587e4bf1bcSJaehoon Chung 11597e4bf1bcSJaehoon Chung dw_mci_ctrl_thld(host, data); 116055c5efbcSJames Hogan 1161f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1162f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1163f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1164f9c2a0dcSSeungwon Jeon else 1165f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1166f9c2a0dcSSeungwon Jeon 1167f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1168f95f3850SWill Newton host->sg = data->sg; 116934b664a2SJames Hogan host->part_buf_start = 0; 117034b664a2SJames Hogan host->part_buf_count = 0; 1171f95f3850SWill Newton 1172b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1173f8c58c11SDoug Anderson 1174f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1175f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1176f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1177f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1178f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1179f95f3850SWill Newton 1180f95f3850SWill Newton temp = mci_readl(host, CTRL); 1181f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1182f95f3850SWill Newton mci_writel(host, CTRL, temp); 118352426899SSeungwon Jeon 118452426899SSeungwon Jeon /* 1185d6fced83SJun Nie * Use the initial fifoth_val for PIO mode. If wm_algined 1186d6fced83SJun Nie * is set, we set watermark same as data size. 118752426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 118852426899SSeungwon Jeon * prev_blksz should be invalidated. 118952426899SSeungwon Jeon */ 1190d6fced83SJun Nie if (host->wm_aligned) 1191d6fced83SJun Nie dw_mci_adjust_fifoth(host, data); 1192d6fced83SJun Nie else 119352426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 119452426899SSeungwon Jeon host->prev_blksz = 0; 119552426899SSeungwon Jeon } else { 119652426899SSeungwon Jeon /* 119752426899SSeungwon Jeon * Keep the current block size. 119852426899SSeungwon Jeon * It will be used to decide whether to update 119952426899SSeungwon Jeon * fifoth register next time. 120052426899SSeungwon Jeon */ 120152426899SSeungwon Jeon host->prev_blksz = data->blksz; 1202f95f3850SWill Newton } 1203f95f3850SWill Newton } 1204f95f3850SWill Newton 1205ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1206f95f3850SWill Newton { 1207f95f3850SWill Newton struct dw_mci *host = slot->host; 1208fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1209f95f3850SWill Newton u32 div; 12109623b5b9SDoug Anderson u32 clk_en_a; 121101730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 121201730558SDoug Anderson 121301730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 121401730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 121501730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1216f95f3850SWill Newton 1217fdf492a1SDoug Anderson if (!clock) { 1218fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 121901730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1220fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1221fdf492a1SDoug Anderson div = host->bus_hz / clock; 1222fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1223f95f3850SWill Newton /* 1224f95f3850SWill Newton * move the + 1 after the divide to prevent 1225f95f3850SWill Newton * over-clocking the card. 1226f95f3850SWill Newton */ 1227e419990bSSeungwon Jeon div += 1; 1228e419990bSSeungwon Jeon 1229fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1230f95f3850SWill Newton 1231e6cd7a8eSJaehoon Chung if ((clock != slot->__clk_old && 1232e6cd7a8eSJaehoon Chung !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1233e6cd7a8eSJaehoon Chung force_clkinit) { 1234ce69e2feSShawn Lin /* Silent the verbose log if calling from PM context */ 1235ce69e2feSShawn Lin if (!force_clkinit) 1236f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1237fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1238fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1239fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1240fdf492a1SDoug Anderson host->bus_hz, div); 1241f95f3850SWill Newton 1242e6cd7a8eSJaehoon Chung /* 1243e6cd7a8eSJaehoon Chung * If card is polling, display the message only 1244e6cd7a8eSJaehoon Chung * one time at boot time. 1245e6cd7a8eSJaehoon Chung */ 1246e6cd7a8eSJaehoon Chung if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1247e6cd7a8eSJaehoon Chung slot->mmc->f_min == clock) 1248e6cd7a8eSJaehoon Chung set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1249e6cd7a8eSJaehoon Chung } 1250e6cd7a8eSJaehoon Chung 1251f95f3850SWill Newton /* disable clock */ 1252f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1253f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1254f95f3850SWill Newton 1255f95f3850SWill Newton /* inform CIU */ 125601730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1257f95f3850SWill Newton 1258f95f3850SWill Newton /* set clock to desired speed */ 1259f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1260f95f3850SWill Newton 1261f95f3850SWill Newton /* inform CIU */ 126201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1263f95f3850SWill Newton 12649623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 12659623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1266b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 12679623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 12689623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1269f95f3850SWill Newton 1270f95f3850SWill Newton /* inform CIU */ 127101730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1272005d675aSJaehoon Chung 1273005d675aSJaehoon Chung /* keep the last clock value that was requested from core */ 1274005d675aSJaehoon Chung slot->__clk_old = clock; 1275f95f3850SWill Newton } 1276f95f3850SWill Newton 1277fdf492a1SDoug Anderson host->current_speed = clock; 1278fdf492a1SDoug Anderson 1279f95f3850SWill Newton /* Set the current slot bus width */ 12801d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1281f95f3850SWill Newton } 1282f95f3850SWill Newton 1283053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1284053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1285053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1286f95f3850SWill Newton { 1287f95f3850SWill Newton struct mmc_request *mrq; 1288f95f3850SWill Newton struct mmc_data *data; 1289f95f3850SWill Newton u32 cmdflags; 1290f95f3850SWill Newton 1291f95f3850SWill Newton mrq = slot->mrq; 1292f95f3850SWill Newton 1293f95f3850SWill Newton host->cur_slot = slot; 1294f95f3850SWill Newton host->mrq = mrq; 1295f95f3850SWill Newton 1296f95f3850SWill Newton host->pending_events = 0; 1297f95f3850SWill Newton host->completed_events = 0; 1298e352c813SSeungwon Jeon host->cmd_status = 0; 1299f95f3850SWill Newton host->data_status = 0; 1300e352c813SSeungwon Jeon host->dir_status = 0; 1301f95f3850SWill Newton 1302053b3ce6SSeungwon Jeon data = cmd->data; 1303f95f3850SWill Newton if (data) { 1304f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1305f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1306f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1307f95f3850SWill Newton } 1308f95f3850SWill Newton 1309f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1310f95f3850SWill Newton 1311f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1312f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1313f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1314f95f3850SWill Newton 1315f95f3850SWill Newton if (data) { 1316f95f3850SWill Newton dw_mci_submit_data(host, data); 13170e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1318f95f3850SWill Newton } 1319f95f3850SWill Newton 1320f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1321f95f3850SWill Newton 13225c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 132349ba0302SDoug Anderson unsigned long irqflags; 132449ba0302SDoug Anderson 13255c935165SDoug Anderson /* 13268886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 13278886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 13288886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 13298886a6fdSDoug Anderson * is just about to roll over. 133049ba0302SDoug Anderson * 133149ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 133249ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 133349ba0302SDoug Anderson * already ran so we don't want the timeout). 13345c935165SDoug Anderson */ 133549ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 133649ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 13375c935165SDoug Anderson mod_timer(&host->cmd11_timer, 13388886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 133949ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13405c935165SDoug Anderson } 13415c935165SDoug Anderson 134290c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1343f95f3850SWill Newton } 1344f95f3850SWill Newton 1345053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1346053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1347053b3ce6SSeungwon Jeon { 1348053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1349053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1350053b3ce6SSeungwon Jeon 1351053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1352053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1353053b3ce6SSeungwon Jeon } 1354053b3ce6SSeungwon Jeon 13557456caaeSJames Hogan /* must be called with host->lock held */ 1356f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1357f95f3850SWill Newton struct mmc_request *mrq) 1358f95f3850SWill Newton { 1359f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1360f95f3850SWill Newton host->state); 1361f95f3850SWill Newton 1362f95f3850SWill Newton slot->mrq = mrq; 1363f95f3850SWill Newton 136401730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 136501730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 136601730558SDoug Anderson "Voltage change didn't complete\n"); 136701730558SDoug Anderson /* 136801730558SDoug Anderson * this case isn't expected to happen, so we can 136901730558SDoug Anderson * either crash here or just try to continue on 137001730558SDoug Anderson * in the closest possible state 137101730558SDoug Anderson */ 137201730558SDoug Anderson host->state = STATE_IDLE; 137301730558SDoug Anderson } 137401730558SDoug Anderson 1375f95f3850SWill Newton if (host->state == STATE_IDLE) { 1376f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1377f95f3850SWill Newton dw_mci_start_request(host, slot); 1378f95f3850SWill Newton } else { 1379f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1380f95f3850SWill Newton } 1381f95f3850SWill Newton } 1382f95f3850SWill Newton 1383f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1384f95f3850SWill Newton { 1385f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1386f95f3850SWill Newton struct dw_mci *host = slot->host; 1387f95f3850SWill Newton 1388f95f3850SWill Newton WARN_ON(slot->mrq); 1389f95f3850SWill Newton 13907456caaeSJames Hogan /* 13917456caaeSJames Hogan * The check for card presence and queueing of the request must be 13927456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 13937456caaeSJames Hogan * request wouldn't fail until another card was inserted. 13947456caaeSJames Hogan */ 13957456caaeSJames Hogan 139656f6911cSShawn Lin if (!dw_mci_get_cd(mmc)) { 1397f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1398f95f3850SWill Newton mmc_request_done(mmc, mrq); 1399f95f3850SWill Newton return; 1400f95f3850SWill Newton } 1401f95f3850SWill Newton 140256f6911cSShawn Lin spin_lock_bh(&host->lock); 140356f6911cSShawn Lin 1404f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 14057456caaeSJames Hogan 14067456caaeSJames Hogan spin_unlock_bh(&host->lock); 1407f95f3850SWill Newton } 1408f95f3850SWill Newton 1409f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1410f95f3850SWill Newton { 1411f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1412e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 141341babf75SJaehoon Chung u32 regs; 141451da2240SYuvaraj CD int ret; 1415f95f3850SWill Newton 1416f95f3850SWill Newton switch (ios->bus_width) { 1417f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1418f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1419f95f3850SWill Newton break; 1420c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1421c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1422c9b2a06fSJaehoon Chung break; 1423b2f7cb45SJaehoon Chung default: 1424b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1425b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1426f95f3850SWill Newton } 1427f95f3850SWill Newton 142841babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 14293f514291SSeungwon Jeon 14303f514291SSeungwon Jeon /* DDR mode set */ 143180113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 14327cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 143380113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1434c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 14353f514291SSeungwon Jeon else 1436c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 14373f514291SSeungwon Jeon 143841babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1439f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 144041babf75SJaehoon Chung 1441f95f3850SWill Newton /* 1442f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1443f95f3850SWill Newton * core ios update when finding the minimum. 1444f95f3850SWill Newton */ 1445f95f3850SWill Newton slot->clock = ios->clock; 1446f95f3850SWill Newton 1447cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1448cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1449800d78bfSThomas Abraham 1450f95f3850SWill Newton switch (ios->power_mode) { 1451f95f3850SWill Newton case MMC_POWER_UP: 145251da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 145351da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 145451da2240SYuvaraj CD ios->vdd); 145551da2240SYuvaraj CD if (ret) { 145651da2240SYuvaraj CD dev_err(slot->host->dev, 145751da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 145851da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 145951da2240SYuvaraj CD return; 146051da2240SYuvaraj CD } 146151da2240SYuvaraj CD } 146229d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 146329d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 146429d0d161SDoug Anderson regs |= (1 << slot->id); 146529d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 146629d0d161SDoug Anderson break; 146729d0d161SDoug Anderson case MMC_POWER_ON: 1468d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1469d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 147051da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 147151da2240SYuvaraj CD if (ret < 0) 147251da2240SYuvaraj CD dev_err(slot->host->dev, 1473d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 147451da2240SYuvaraj CD else 147551da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1476d1f1dd86SDoug Anderson 1477d1f1dd86SDoug Anderson } else { 1478d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1479d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1480d1f1dd86SDoug Anderson } 1481d1f1dd86SDoug Anderson 1482d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1483d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1484d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 148551da2240SYuvaraj CD } 1486655babbdSDoug Anderson 1487655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1488655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1489655babbdSDoug Anderson 1490e6f34e2fSJames Hogan break; 1491e6f34e2fSJames Hogan case MMC_POWER_OFF: 1492655babbdSDoug Anderson /* Turn clock off before power goes down */ 1493655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1494655babbdSDoug Anderson 149551da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 149651da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 149751da2240SYuvaraj CD 1498d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 149951da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 150051da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 150151da2240SYuvaraj CD 15024366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 15034366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 15044366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1505f95f3850SWill Newton break; 1506f95f3850SWill Newton default: 1507f95f3850SWill Newton break; 1508f95f3850SWill Newton } 1509655babbdSDoug Anderson 1510655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1511655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1512f95f3850SWill Newton } 1513f95f3850SWill Newton 151401730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 151501730558SDoug Anderson { 151601730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 151701730558SDoug Anderson u32 status; 151801730558SDoug Anderson 151901730558SDoug Anderson /* 152001730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 152101730558SDoug Anderson * (the data lines) are 0000 152201730558SDoug Anderson */ 152301730558SDoug Anderson status = mci_readl(slot->host, STATUS); 152401730558SDoug Anderson 152501730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 152601730558SDoug Anderson } 152701730558SDoug Anderson 152801730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 152901730558SDoug Anderson { 153001730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 153101730558SDoug Anderson struct dw_mci *host = slot->host; 15328f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 153301730558SDoug Anderson u32 uhs; 153401730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 153501730558SDoug Anderson int ret; 153601730558SDoug Anderson 15378f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 15388f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 15398f7849c4SZhangfei Gao 154001730558SDoug Anderson /* 154101730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 154201730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 154301730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 154401730558SDoug Anderson */ 154501730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1546e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 154701730558SDoug Anderson uhs &= ~v18; 1548e0848f5dSDouglas Anderson else 154901730558SDoug Anderson uhs |= v18; 1550e0848f5dSDouglas Anderson 155101730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1552e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 155301730558SDoug Anderson 155401730558SDoug Anderson if (ret) { 1555b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1556e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1557e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 155801730558SDoug Anderson return ret; 155901730558SDoug Anderson } 156001730558SDoug Anderson } 156101730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 156201730558SDoug Anderson 156301730558SDoug Anderson return 0; 156401730558SDoug Anderson } 156501730558SDoug Anderson 1566f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1567f95f3850SWill Newton { 1568f95f3850SWill Newton int read_only; 1569f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 15709795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1571f95f3850SWill Newton 1572f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1573287980e4SArnd Bergmann if (gpio_ro >= 0) 15749795a846SJaehoon Chung read_only = gpio_ro; 1575f95f3850SWill Newton else 1576f95f3850SWill Newton read_only = 1577f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1578f95f3850SWill Newton 1579f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1580f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1581f95f3850SWill Newton 1582f95f3850SWill Newton return read_only; 1583f95f3850SWill Newton } 1584f95f3850SWill Newton 1585935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1586935a665eSShawn Lin { 1587935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1588935a665eSShawn Lin struct dw_mci *host = slot->host; 1589935a665eSShawn Lin int reset; 1590935a665eSShawn Lin 1591935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1592935a665eSShawn Lin dw_mci_idmac_reset(host); 1593935a665eSShawn Lin 1594935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1595935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1596935a665eSShawn Lin return; 1597935a665eSShawn Lin 1598935a665eSShawn Lin /* 1599935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1600935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1601935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1602935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1603935a665eSShawn Lin */ 1604935a665eSShawn Lin reset = mci_readl(host, RST_N); 1605935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1606935a665eSShawn Lin mci_writel(host, RST_N, reset); 1607935a665eSShawn Lin usleep_range(1, 2); 1608935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1609935a665eSShawn Lin mci_writel(host, RST_N, reset); 1610935a665eSShawn Lin usleep_range(200, 300); 1611935a665eSShawn Lin } 1612935a665eSShawn Lin 1613b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1614b24c8b26SDoug Anderson { 1615b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1616b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1617b24c8b26SDoug Anderson 16189623b5b9SDoug Anderson /* 16199623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 16209623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 16219623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 16229623b5b9SDoug Anderson */ 1623b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 16249623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1625b24c8b26SDoug Anderson u32 clk_en_a_old; 1626b24c8b26SDoug Anderson u32 clk_en_a; 16279623b5b9SDoug Anderson 1628b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 16299623b5b9SDoug Anderson 1630b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1631b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1632a6db2c86SDouglas Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) { 1633a6db2c86SDouglas Anderson pm_runtime_get_noresume(mmc->parent); 1634b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1635a6db2c86SDouglas Anderson } 1636b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1637b24c8b26SDoug Anderson } else { 1638a6db2c86SDouglas Anderson if (test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) { 1639a6db2c86SDouglas Anderson pm_runtime_put_noidle(mmc->parent); 1640b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1641a6db2c86SDouglas Anderson } 1642b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1643b24c8b26SDoug Anderson } 1644b24c8b26SDoug Anderson 1645b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1646b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 16479623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 16489623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 16499623b5b9SDoug Anderson } 16509623b5b9SDoug Anderson } 1651b24c8b26SDoug Anderson } 16529623b5b9SDoug Anderson 16531a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 16541a5c8e1fSShashidhar Hiremath { 16551a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 16561a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1657f8c58c11SDoug Anderson unsigned long irqflags; 16581a5c8e1fSShashidhar Hiremath u32 int_mask; 16591a5c8e1fSShashidhar Hiremath 1660f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1661f8c58c11SDoug Anderson 16621a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 16631a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1664b24c8b26SDoug Anderson if (enb) 1665b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1666b24c8b26SDoug Anderson else 1667b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1668b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1669f8c58c11SDoug Anderson 1670f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 16711a5c8e1fSShashidhar Hiremath } 16721a5c8e1fSShashidhar Hiremath 16730976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 16740976f16dSSeungwon Jeon { 16750976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 16760976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 16770976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 16780e3a22c0SShawn Lin int err = -EINVAL; 16790976f16dSSeungwon Jeon 16800976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 16819979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 16820976f16dSSeungwon Jeon return err; 16830976f16dSSeungwon Jeon } 16840976f16dSSeungwon Jeon 16850e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 16860e3a22c0SShawn Lin struct mmc_ios *ios) 168780113132SSeungwon Jeon { 168880113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 168980113132SSeungwon Jeon struct dw_mci *host = slot->host; 169080113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 169180113132SSeungwon Jeon 169280113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 169380113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 169480113132SSeungwon Jeon 169580113132SSeungwon Jeon return 0; 169680113132SSeungwon Jeon } 169780113132SSeungwon Jeon 16984e7392b2SShawn Lin static bool dw_mci_reset(struct dw_mci *host) 16994e7392b2SShawn Lin { 17004e7392b2SShawn Lin u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 17014e7392b2SShawn Lin bool ret = false; 17024e7392b2SShawn Lin 17034e7392b2SShawn Lin /* 17044e7392b2SShawn Lin * Resetting generates a block interrupt, hence setting 17054e7392b2SShawn Lin * the scatter-gather pointer to NULL. 17064e7392b2SShawn Lin */ 17074e7392b2SShawn Lin if (host->sg) { 17084e7392b2SShawn Lin sg_miter_stop(&host->sg_miter); 17094e7392b2SShawn Lin host->sg = NULL; 17104e7392b2SShawn Lin } 17114e7392b2SShawn Lin 17124e7392b2SShawn Lin if (host->use_dma) 17134e7392b2SShawn Lin flags |= SDMMC_CTRL_DMA_RESET; 17144e7392b2SShawn Lin 17154e7392b2SShawn Lin if (dw_mci_ctrl_reset(host, flags)) { 17164e7392b2SShawn Lin /* 17174e7392b2SShawn Lin * In all cases we clear the RAWINTS register to clear any 17184e7392b2SShawn Lin * interrupts. 17194e7392b2SShawn Lin */ 17204e7392b2SShawn Lin mci_writel(host, RINTSTS, 0xFFFFFFFF); 17214e7392b2SShawn Lin 17224e7392b2SShawn Lin /* if using dma we wait for dma_req to clear */ 17234e7392b2SShawn Lin if (host->use_dma) { 17244e7392b2SShawn Lin u32 status; 17254e7392b2SShawn Lin 17264e7392b2SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 17274e7392b2SShawn Lin status, 17284e7392b2SShawn Lin !(status & SDMMC_STATUS_DMA_REQ), 17294e7392b2SShawn Lin 1, 500 * USEC_PER_MSEC)) { 17304e7392b2SShawn Lin dev_err(host->dev, 17314e7392b2SShawn Lin "%s: Timeout waiting for dma_req to clear during reset\n", 17324e7392b2SShawn Lin __func__); 17334e7392b2SShawn Lin goto ciu_out; 17344e7392b2SShawn Lin } 17354e7392b2SShawn Lin 17364e7392b2SShawn Lin /* when using DMA next we reset the fifo again */ 17374e7392b2SShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 17384e7392b2SShawn Lin goto ciu_out; 17394e7392b2SShawn Lin } 17404e7392b2SShawn Lin } else { 17414e7392b2SShawn Lin /* if the controller reset bit did clear, then set clock regs */ 17424e7392b2SShawn Lin if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 17434e7392b2SShawn Lin dev_err(host->dev, 17444e7392b2SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 17454e7392b2SShawn Lin __func__); 17464e7392b2SShawn Lin goto ciu_out; 17474e7392b2SShawn Lin } 17484e7392b2SShawn Lin } 17494e7392b2SShawn Lin 17504e7392b2SShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 17514e7392b2SShawn Lin /* It is also recommended that we reset and reprogram idmac */ 17524e7392b2SShawn Lin dw_mci_idmac_reset(host); 17534e7392b2SShawn Lin 17544e7392b2SShawn Lin ret = true; 17554e7392b2SShawn Lin 17564e7392b2SShawn Lin ciu_out: 17574e7392b2SShawn Lin /* After a CTRL reset we need to have CIU set clock registers */ 17584e7392b2SShawn Lin mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 17594e7392b2SShawn Lin 17604e7392b2SShawn Lin return ret; 17614e7392b2SShawn Lin } 17624e7392b2SShawn Lin 1763f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1764f95f3850SWill Newton .request = dw_mci_request, 17659aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 17669aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1767f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1768f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1769f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1770935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 17711a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 17720976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 177301730558SDoug Anderson .card_busy = dw_mci_card_busy, 177401730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1775b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 177680113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1777f95f3850SWill Newton }; 1778f95f3850SWill Newton 1779f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1780f95f3850SWill Newton __releases(&host->lock) 1781f95f3850SWill Newton __acquires(&host->lock) 1782f95f3850SWill Newton { 1783f95f3850SWill Newton struct dw_mci_slot *slot; 1784f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1785f95f3850SWill Newton 1786f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1787f95f3850SWill Newton 1788f95f3850SWill Newton host->cur_slot->mrq = NULL; 1789f95f3850SWill Newton host->mrq = NULL; 1790f95f3850SWill Newton if (!list_empty(&host->queue)) { 1791f95f3850SWill Newton slot = list_entry(host->queue.next, 1792f95f3850SWill Newton struct dw_mci_slot, queue_node); 1793f95f3850SWill Newton list_del(&slot->queue_node); 17944a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1795f95f3850SWill Newton mmc_hostname(slot->mmc)); 1796f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1797f95f3850SWill Newton dw_mci_start_request(host, slot); 1798f95f3850SWill Newton } else { 17994a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 180001730558SDoug Anderson 180101730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 180201730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 180301730558SDoug Anderson else 1804f95f3850SWill Newton host->state = STATE_IDLE; 1805f95f3850SWill Newton } 1806f95f3850SWill Newton 1807f95f3850SWill Newton spin_unlock(&host->lock); 1808f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1809f95f3850SWill Newton spin_lock(&host->lock); 1810f95f3850SWill Newton } 1811f95f3850SWill Newton 1812e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1813f95f3850SWill Newton { 1814f95f3850SWill Newton u32 status = host->cmd_status; 1815f95f3850SWill Newton 1816f95f3850SWill Newton host->cmd_status = 0; 1817f95f3850SWill Newton 1818f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1819f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1820f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1821f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1822f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1823f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1824f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1825f95f3850SWill Newton } else { 1826f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1827f95f3850SWill Newton cmd->resp[1] = 0; 1828f95f3850SWill Newton cmd->resp[2] = 0; 1829f95f3850SWill Newton cmd->resp[3] = 0; 1830f95f3850SWill Newton } 1831f95f3850SWill Newton } 1832f95f3850SWill Newton 1833f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1834f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1835f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1836f95f3850SWill Newton cmd->error = -EILSEQ; 1837f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1838f95f3850SWill Newton cmd->error = -EIO; 1839f95f3850SWill Newton else 1840f95f3850SWill Newton cmd->error = 0; 1841f95f3850SWill Newton 1842e352c813SSeungwon Jeon return cmd->error; 1843e352c813SSeungwon Jeon } 1844e352c813SSeungwon Jeon 1845e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1846e352c813SSeungwon Jeon { 184731bff450SSeungwon Jeon u32 status = host->data_status; 1848e352c813SSeungwon Jeon 1849e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1850e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1851e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1852e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1853e352c813SSeungwon Jeon data->error = -EILSEQ; 1854e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1855e352c813SSeungwon Jeon if (host->dir_status == 1856e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1857e352c813SSeungwon Jeon /* 1858e352c813SSeungwon Jeon * No data CRC status was returned. 1859e352c813SSeungwon Jeon * The number of bytes transferred 1860e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1861e352c813SSeungwon Jeon */ 1862e352c813SSeungwon Jeon data->bytes_xfered = 0; 1863e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1864e352c813SSeungwon Jeon } else if (host->dir_status == 1865e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1866e7a1dec1SShawn Lin data->error = -EILSEQ; 1867e352c813SSeungwon Jeon } 1868e352c813SSeungwon Jeon } else { 1869e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1870e7a1dec1SShawn Lin data->error = -EILSEQ; 1871e352c813SSeungwon Jeon } 1872e352c813SSeungwon Jeon 1873e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1874e352c813SSeungwon Jeon 1875e352c813SSeungwon Jeon /* 1876e352c813SSeungwon Jeon * After an error, there may be data lingering 187731bff450SSeungwon Jeon * in the FIFO 1878e352c813SSeungwon Jeon */ 18793a33a94cSSonny Rao dw_mci_reset(host); 1880e352c813SSeungwon Jeon } else { 1881e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1882e352c813SSeungwon Jeon data->error = 0; 1883e352c813SSeungwon Jeon } 1884e352c813SSeungwon Jeon 1885e352c813SSeungwon Jeon return data->error; 1886f95f3850SWill Newton } 1887f95f3850SWill Newton 188857e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 188957e10486SAddy Ke { 189057e10486SAddy Ke unsigned int drto_clks; 189157e10486SAddy Ke unsigned int drto_ms; 189257e10486SAddy Ke 189357e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 189457e10486SAddy Ke drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 189557e10486SAddy Ke 189657e10486SAddy Ke /* add a bit spare time */ 189757e10486SAddy Ke drto_ms += 10; 189857e10486SAddy Ke 189957e10486SAddy Ke mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 190057e10486SAddy Ke } 190157e10486SAddy Ke 1902f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1903f95f3850SWill Newton { 1904f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1905f95f3850SWill Newton struct mmc_data *data; 1906f95f3850SWill Newton struct mmc_command *cmd; 1907e352c813SSeungwon Jeon struct mmc_request *mrq; 1908f95f3850SWill Newton enum dw_mci_state state; 1909f95f3850SWill Newton enum dw_mci_state prev_state; 1910e352c813SSeungwon Jeon unsigned int err; 1911f95f3850SWill Newton 1912f95f3850SWill Newton spin_lock(&host->lock); 1913f95f3850SWill Newton 1914f95f3850SWill Newton state = host->state; 1915f95f3850SWill Newton data = host->data; 1916e352c813SSeungwon Jeon mrq = host->mrq; 1917f95f3850SWill Newton 1918f95f3850SWill Newton do { 1919f95f3850SWill Newton prev_state = state; 1920f95f3850SWill Newton 1921f95f3850SWill Newton switch (state) { 1922f95f3850SWill Newton case STATE_IDLE: 192301730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1924f95f3850SWill Newton break; 1925f95f3850SWill Newton 192601730558SDoug Anderson case STATE_SENDING_CMD11: 1927f95f3850SWill Newton case STATE_SENDING_CMD: 1928f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1929f95f3850SWill Newton &host->pending_events)) 1930f95f3850SWill Newton break; 1931f95f3850SWill Newton 1932f95f3850SWill Newton cmd = host->cmd; 1933f95f3850SWill Newton host->cmd = NULL; 1934f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1935e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1936e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1937053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1938053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1939e352c813SSeungwon Jeon mrq->cmd); 1940053b3ce6SSeungwon Jeon goto unlock; 1941053b3ce6SSeungwon Jeon } 1942053b3ce6SSeungwon Jeon 1943e352c813SSeungwon Jeon if (cmd->data && err) { 194446d17952SDoug Anderson /* 194546d17952SDoug Anderson * During UHS tuning sequence, sending the stop 194646d17952SDoug Anderson * command after the response CRC error would 194746d17952SDoug Anderson * throw the system into a confused state 194846d17952SDoug Anderson * causing all future tuning phases to report 194946d17952SDoug Anderson * failure. 195046d17952SDoug Anderson * 195146d17952SDoug Anderson * In such case controller will move into a data 195246d17952SDoug Anderson * transfer state after a response error or 195346d17952SDoug Anderson * response CRC error. Let's let that finish 195446d17952SDoug Anderson * before trying to send a stop, so we'll go to 195546d17952SDoug Anderson * STATE_SENDING_DATA. 195646d17952SDoug Anderson * 195746d17952SDoug Anderson * Although letting the data transfer take place 195846d17952SDoug Anderson * will waste a bit of time (we already know 195946d17952SDoug Anderson * the command was bad), it can't cause any 196046d17952SDoug Anderson * errors since it's possible it would have 196146d17952SDoug Anderson * taken place anyway if this tasklet got 196246d17952SDoug Anderson * delayed. Allowing the transfer to take place 196346d17952SDoug Anderson * avoids races and keeps things simple. 196446d17952SDoug Anderson */ 196546d17952SDoug Anderson if ((err != -ETIMEDOUT) && 196646d17952SDoug Anderson (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 196746d17952SDoug Anderson state = STATE_SENDING_DATA; 196846d17952SDoug Anderson continue; 196946d17952SDoug Anderson } 197046d17952SDoug Anderson 197171abb133SSeungwon Jeon dw_mci_stop_dma(host); 197290c2143aSSeungwon Jeon send_stop_abort(host, data); 197371abb133SSeungwon Jeon state = STATE_SENDING_STOP; 197471abb133SSeungwon Jeon break; 197571abb133SSeungwon Jeon } 197671abb133SSeungwon Jeon 1977e352c813SSeungwon Jeon if (!cmd->data || err) { 1978e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1979f95f3850SWill Newton goto unlock; 1980f95f3850SWill Newton } 1981f95f3850SWill Newton 1982f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1983f95f3850SWill Newton /* fall through */ 1984f95f3850SWill Newton 1985f95f3850SWill Newton case STATE_SENDING_DATA: 19862aa35465SDoug Anderson /* 19872aa35465SDoug Anderson * We could get a data error and never a transfer 19882aa35465SDoug Anderson * complete so we'd better check for it here. 19892aa35465SDoug Anderson * 19902aa35465SDoug Anderson * Note that we don't really care if we also got a 19912aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 19922aa35465SDoug Anderson * abort won't hurt. 19932aa35465SDoug Anderson */ 1994f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1995f95f3850SWill Newton &host->pending_events)) { 1996f95f3850SWill Newton dw_mci_stop_dma(host); 1997e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 1998bdb9a90bSaddy ke SDMMC_INT_EBE))) 199990c2143aSSeungwon Jeon send_stop_abort(host, data); 2000f95f3850SWill Newton state = STATE_DATA_ERROR; 2001f95f3850SWill Newton break; 2002f95f3850SWill Newton } 2003f95f3850SWill Newton 2004f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 200557e10486SAddy Ke &host->pending_events)) { 200657e10486SAddy Ke /* 200757e10486SAddy Ke * If all data-related interrupts don't come 200857e10486SAddy Ke * within the given time in reading data state. 200957e10486SAddy Ke */ 201016a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 201157e10486SAddy Ke dw_mci_set_drto(host); 2012f95f3850SWill Newton break; 201357e10486SAddy Ke } 2014f95f3850SWill Newton 2015f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 20162aa35465SDoug Anderson 20172aa35465SDoug Anderson /* 20182aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 20192aa35465SDoug Anderson * before the transfer completed. This might not have 20202aa35465SDoug Anderson * been caught by the check above because the interrupt 20212aa35465SDoug Anderson * could have gone off between the previous check and 20222aa35465SDoug Anderson * the check for transfer complete. 20232aa35465SDoug Anderson * 20242aa35465SDoug Anderson * Technically this ought not be needed assuming we 20252aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 20262aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 20272aa35465SDoug Anderson * 20282aa35465SDoug Anderson * This has the advantage of sending the stop command. 20292aa35465SDoug Anderson */ 20302aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 20312aa35465SDoug Anderson &host->pending_events)) { 20322aa35465SDoug Anderson dw_mci_stop_dma(host); 2033e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2034bdb9a90bSaddy ke SDMMC_INT_EBE))) 20352aa35465SDoug Anderson send_stop_abort(host, data); 20362aa35465SDoug Anderson state = STATE_DATA_ERROR; 20372aa35465SDoug Anderson break; 20382aa35465SDoug Anderson } 2039f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 20402aa35465SDoug Anderson 2041f95f3850SWill Newton /* fall through */ 2042f95f3850SWill Newton 2043f95f3850SWill Newton case STATE_DATA_BUSY: 2044f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 204557e10486SAddy Ke &host->pending_events)) { 204657e10486SAddy Ke /* 204757e10486SAddy Ke * If data error interrupt comes but data over 204857e10486SAddy Ke * interrupt doesn't come within the given time. 204957e10486SAddy Ke * in reading data state. 205057e10486SAddy Ke */ 205116a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 205257e10486SAddy Ke dw_mci_set_drto(host); 2053f95f3850SWill Newton break; 205457e10486SAddy Ke } 2055f95f3850SWill Newton 2056f95f3850SWill Newton host->data = NULL; 2057f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2058e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 2059f95f3850SWill Newton 2060e352c813SSeungwon Jeon if (!err) { 2061e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 206217c8bc85SSachin Kamat if (mrq->sbc && data->stop) 2063053b3ce6SSeungwon Jeon data->stop->error = 0; 2064e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2065053b3ce6SSeungwon Jeon goto unlock; 2066053b3ce6SSeungwon Jeon } 2067053b3ce6SSeungwon Jeon 206890c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 2069e352c813SSeungwon Jeon if (data->stop) 207090c2143aSSeungwon Jeon send_stop_abort(host, data); 20712aa35465SDoug Anderson } else { 20722aa35465SDoug Anderson /* 20732aa35465SDoug Anderson * If we don't have a command complete now we'll 20742aa35465SDoug Anderson * never get one since we just reset everything; 20752aa35465SDoug Anderson * better end the request. 20762aa35465SDoug Anderson * 20772aa35465SDoug Anderson * If we do have a command complete we'll fall 20782aa35465SDoug Anderson * through to the SENDING_STOP command and 20792aa35465SDoug Anderson * everything will be peachy keen. 20802aa35465SDoug Anderson */ 20812aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 20822aa35465SDoug Anderson &host->pending_events)) { 20832aa35465SDoug Anderson host->cmd = NULL; 20842aa35465SDoug Anderson dw_mci_request_end(host, mrq); 20852aa35465SDoug Anderson goto unlock; 20862aa35465SDoug Anderson } 208790c2143aSSeungwon Jeon } 2088e352c813SSeungwon Jeon 2089e352c813SSeungwon Jeon /* 2090e352c813SSeungwon Jeon * If err has non-zero, 2091e352c813SSeungwon Jeon * stop-abort command has been already issued. 2092e352c813SSeungwon Jeon */ 2093e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 2094e352c813SSeungwon Jeon 2095f95f3850SWill Newton /* fall through */ 2096f95f3850SWill Newton 2097f95f3850SWill Newton case STATE_SENDING_STOP: 2098f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 2099f95f3850SWill Newton &host->pending_events)) 2100f95f3850SWill Newton break; 2101f95f3850SWill Newton 210271abb133SSeungwon Jeon /* CMD error in data command */ 210331bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 21043a33a94cSSonny Rao dw_mci_reset(host); 210571abb133SSeungwon Jeon 2106f95f3850SWill Newton host->cmd = NULL; 210771abb133SSeungwon Jeon host->data = NULL; 210890c2143aSSeungwon Jeon 2109e13c3c08SJaehoon Chung if (!mrq->sbc && mrq->stop) 2110e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 211190c2143aSSeungwon Jeon else 211290c2143aSSeungwon Jeon host->cmd_status = 0; 211390c2143aSSeungwon Jeon 2114e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2115f95f3850SWill Newton goto unlock; 2116f95f3850SWill Newton 2117f95f3850SWill Newton case STATE_DATA_ERROR: 2118f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2119f95f3850SWill Newton &host->pending_events)) 2120f95f3850SWill Newton break; 2121f95f3850SWill Newton 2122f95f3850SWill Newton state = STATE_DATA_BUSY; 2123f95f3850SWill Newton break; 2124f95f3850SWill Newton } 2125f95f3850SWill Newton } while (state != prev_state); 2126f95f3850SWill Newton 2127f95f3850SWill Newton host->state = state; 2128f95f3850SWill Newton unlock: 2129f95f3850SWill Newton spin_unlock(&host->lock); 2130f95f3850SWill Newton 2131f95f3850SWill Newton } 2132f95f3850SWill Newton 213334b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 213434b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 213534b664a2SJames Hogan { 213634b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 213734b664a2SJames Hogan host->part_buf_count = cnt; 213834b664a2SJames Hogan } 213934b664a2SJames Hogan 214034b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 214134b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 214234b664a2SJames Hogan { 214334b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 214434b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 214534b664a2SJames Hogan host->part_buf_count += cnt; 214634b664a2SJames Hogan return cnt; 214734b664a2SJames Hogan } 214834b664a2SJames Hogan 214934b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 215034b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 215134b664a2SJames Hogan { 21520e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 215334b664a2SJames Hogan if (cnt) { 215434b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 215534b664a2SJames Hogan cnt); 215634b664a2SJames Hogan host->part_buf_count -= cnt; 215734b664a2SJames Hogan host->part_buf_start += cnt; 215834b664a2SJames Hogan } 215934b664a2SJames Hogan return cnt; 216034b664a2SJames Hogan } 216134b664a2SJames Hogan 216234b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 216334b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 216434b664a2SJames Hogan { 216534b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 216634b664a2SJames Hogan host->part_buf_start = cnt; 216734b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 216834b664a2SJames Hogan } 216934b664a2SJames Hogan 2170f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2171f95f3850SWill Newton { 2172cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2173cfbeb59cSMarkos Chandras int init_cnt = cnt; 2174cfbeb59cSMarkos Chandras 217534b664a2SJames Hogan /* try and push anything in the part_buf */ 217634b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 217734b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 21780e3a22c0SShawn Lin 217934b664a2SJames Hogan buf += len; 218034b664a2SJames Hogan cnt -= len; 2181cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 218276184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 218334b664a2SJames Hogan host->part_buf_count = 0; 218434b664a2SJames Hogan } 218534b664a2SJames Hogan } 218634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 218734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 218834b664a2SJames Hogan while (cnt >= 2) { 218934b664a2SJames Hogan u16 aligned_buf[64]; 219034b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 219134b664a2SJames Hogan int items = len >> 1; 219234b664a2SJames Hogan int i; 219334b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 219434b664a2SJames Hogan memcpy(aligned_buf, buf, len); 219534b664a2SJames Hogan buf += len; 219634b664a2SJames Hogan cnt -= len; 219734b664a2SJames Hogan /* push data from aligned buffer into fifo */ 219834b664a2SJames Hogan for (i = 0; i < items; ++i) 219976184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 220034b664a2SJames Hogan } 220134b664a2SJames Hogan } else 220234b664a2SJames Hogan #endif 220334b664a2SJames Hogan { 220434b664a2SJames Hogan u16 *pdata = buf; 22050e3a22c0SShawn Lin 220634b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 220776184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 220834b664a2SJames Hogan buf = pdata; 220934b664a2SJames Hogan } 221034b664a2SJames Hogan /* put anything remaining in the part_buf */ 221134b664a2SJames Hogan if (cnt) { 221234b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2213cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2214cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2215cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 221676184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2217f95f3850SWill Newton } 2218f95f3850SWill Newton } 2219f95f3850SWill Newton 2220f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2221f95f3850SWill Newton { 222234b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 222334b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 222434b664a2SJames Hogan while (cnt >= 2) { 222534b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 222634b664a2SJames Hogan u16 aligned_buf[64]; 222734b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 222834b664a2SJames Hogan int items = len >> 1; 222934b664a2SJames Hogan int i; 22300e3a22c0SShawn Lin 223134b664a2SJames Hogan for (i = 0; i < items; ++i) 223276184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 223334b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 223434b664a2SJames Hogan memcpy(buf, aligned_buf, len); 223534b664a2SJames Hogan buf += len; 223634b664a2SJames Hogan cnt -= len; 223734b664a2SJames Hogan } 223834b664a2SJames Hogan } else 223934b664a2SJames Hogan #endif 224034b664a2SJames Hogan { 224134b664a2SJames Hogan u16 *pdata = buf; 22420e3a22c0SShawn Lin 224334b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 224476184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 224534b664a2SJames Hogan buf = pdata; 224634b664a2SJames Hogan } 224734b664a2SJames Hogan if (cnt) { 224876184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 224934b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2250f95f3850SWill Newton } 2251f95f3850SWill Newton } 2252f95f3850SWill Newton 2253f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2254f95f3850SWill Newton { 2255cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2256cfbeb59cSMarkos Chandras int init_cnt = cnt; 2257cfbeb59cSMarkos Chandras 225834b664a2SJames Hogan /* try and push anything in the part_buf */ 225934b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 226034b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 22610e3a22c0SShawn Lin 226234b664a2SJames Hogan buf += len; 226334b664a2SJames Hogan cnt -= len; 2264cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 226576184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 226634b664a2SJames Hogan host->part_buf_count = 0; 226734b664a2SJames Hogan } 226834b664a2SJames Hogan } 226934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 227034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 227134b664a2SJames Hogan while (cnt >= 4) { 227234b664a2SJames Hogan u32 aligned_buf[32]; 227334b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 227434b664a2SJames Hogan int items = len >> 2; 227534b664a2SJames Hogan int i; 227634b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 227734b664a2SJames Hogan memcpy(aligned_buf, buf, len); 227834b664a2SJames Hogan buf += len; 227934b664a2SJames Hogan cnt -= len; 228034b664a2SJames Hogan /* push data from aligned buffer into fifo */ 228134b664a2SJames Hogan for (i = 0; i < items; ++i) 228276184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 228334b664a2SJames Hogan } 228434b664a2SJames Hogan } else 228534b664a2SJames Hogan #endif 228634b664a2SJames Hogan { 228734b664a2SJames Hogan u32 *pdata = buf; 22880e3a22c0SShawn Lin 228934b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 229076184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 229134b664a2SJames Hogan buf = pdata; 229234b664a2SJames Hogan } 229334b664a2SJames Hogan /* put anything remaining in the part_buf */ 229434b664a2SJames Hogan if (cnt) { 229534b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2296cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2297cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2298cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 229976184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2300f95f3850SWill Newton } 2301f95f3850SWill Newton } 2302f95f3850SWill Newton 2303f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2304f95f3850SWill Newton { 230534b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 230634b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 230734b664a2SJames Hogan while (cnt >= 4) { 230834b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 230934b664a2SJames Hogan u32 aligned_buf[32]; 231034b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 231134b664a2SJames Hogan int items = len >> 2; 231234b664a2SJames Hogan int i; 23130e3a22c0SShawn Lin 231434b664a2SJames Hogan for (i = 0; i < items; ++i) 231576184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 231634b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 231734b664a2SJames Hogan memcpy(buf, aligned_buf, len); 231834b664a2SJames Hogan buf += len; 231934b664a2SJames Hogan cnt -= len; 232034b664a2SJames Hogan } 232134b664a2SJames Hogan } else 232234b664a2SJames Hogan #endif 232334b664a2SJames Hogan { 232434b664a2SJames Hogan u32 *pdata = buf; 23250e3a22c0SShawn Lin 232634b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 232776184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 232834b664a2SJames Hogan buf = pdata; 232934b664a2SJames Hogan } 233034b664a2SJames Hogan if (cnt) { 233176184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 233234b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2333f95f3850SWill Newton } 2334f95f3850SWill Newton } 2335f95f3850SWill Newton 2336f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2337f95f3850SWill Newton { 2338cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2339cfbeb59cSMarkos Chandras int init_cnt = cnt; 2340cfbeb59cSMarkos Chandras 234134b664a2SJames Hogan /* try and push anything in the part_buf */ 234234b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 234334b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 23440e3a22c0SShawn Lin 234534b664a2SJames Hogan buf += len; 234634b664a2SJames Hogan cnt -= len; 2347c09fbd74SSeungwon Jeon 2348cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 234976184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 235034b664a2SJames Hogan host->part_buf_count = 0; 235134b664a2SJames Hogan } 235234b664a2SJames Hogan } 235334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 235434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 235534b664a2SJames Hogan while (cnt >= 8) { 235634b664a2SJames Hogan u64 aligned_buf[16]; 235734b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 235834b664a2SJames Hogan int items = len >> 3; 235934b664a2SJames Hogan int i; 236034b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 236134b664a2SJames Hogan memcpy(aligned_buf, buf, len); 236234b664a2SJames Hogan buf += len; 236334b664a2SJames Hogan cnt -= len; 236434b664a2SJames Hogan /* push data from aligned buffer into fifo */ 236534b664a2SJames Hogan for (i = 0; i < items; ++i) 236676184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 236734b664a2SJames Hogan } 236834b664a2SJames Hogan } else 236934b664a2SJames Hogan #endif 237034b664a2SJames Hogan { 237134b664a2SJames Hogan u64 *pdata = buf; 23720e3a22c0SShawn Lin 237334b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 237476184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 237534b664a2SJames Hogan buf = pdata; 237634b664a2SJames Hogan } 237734b664a2SJames Hogan /* put anything remaining in the part_buf */ 237834b664a2SJames Hogan if (cnt) { 237934b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2380cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2381cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2382cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 238376184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2384f95f3850SWill Newton } 2385f95f3850SWill Newton } 2386f95f3850SWill Newton 2387f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2388f95f3850SWill Newton { 238934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 239034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 239134b664a2SJames Hogan while (cnt >= 8) { 239234b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 239334b664a2SJames Hogan u64 aligned_buf[16]; 239434b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 239534b664a2SJames Hogan int items = len >> 3; 239634b664a2SJames Hogan int i; 23970e3a22c0SShawn Lin 239834b664a2SJames Hogan for (i = 0; i < items; ++i) 239976184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 240076184ac1SBen Dooks 240134b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 240234b664a2SJames Hogan memcpy(buf, aligned_buf, len); 240334b664a2SJames Hogan buf += len; 240434b664a2SJames Hogan cnt -= len; 2405f95f3850SWill Newton } 240634b664a2SJames Hogan } else 240734b664a2SJames Hogan #endif 240834b664a2SJames Hogan { 240934b664a2SJames Hogan u64 *pdata = buf; 24100e3a22c0SShawn Lin 241134b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 241276184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 241334b664a2SJames Hogan buf = pdata; 241434b664a2SJames Hogan } 241534b664a2SJames Hogan if (cnt) { 241676184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 241734b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 241834b664a2SJames Hogan } 241934b664a2SJames Hogan } 242034b664a2SJames Hogan 242134b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 242234b664a2SJames Hogan { 242334b664a2SJames Hogan int len; 242434b664a2SJames Hogan 242534b664a2SJames Hogan /* get remaining partial bytes */ 242634b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 242734b664a2SJames Hogan if (unlikely(len == cnt)) 242834b664a2SJames Hogan return; 242934b664a2SJames Hogan buf += len; 243034b664a2SJames Hogan cnt -= len; 243134b664a2SJames Hogan 243234b664a2SJames Hogan /* get the rest of the data */ 243334b664a2SJames Hogan host->pull_data(host, buf, cnt); 2434f95f3850SWill Newton } 2435f95f3850SWill Newton 243687a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2437f95f3850SWill Newton { 2438f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2439f9c2a0dcSSeungwon Jeon void *buf; 2440f9c2a0dcSSeungwon Jeon unsigned int offset; 2441f95f3850SWill Newton struct mmc_data *data = host->data; 2442f95f3850SWill Newton int shift = host->data_shift; 2443f95f3850SWill Newton u32 status; 24443e4b0d8bSMarkos Chandras unsigned int len; 2445f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2446f95f3850SWill Newton 2447f95f3850SWill Newton do { 2448f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2449f9c2a0dcSSeungwon Jeon goto done; 2450f95f3850SWill Newton 24514225fc85SImre Deak host->sg = sg_miter->piter.sg; 2452f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2453f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2454f9c2a0dcSSeungwon Jeon offset = 0; 2455f9c2a0dcSSeungwon Jeon 2456f9c2a0dcSSeungwon Jeon do { 2457f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2458f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2459f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2460f9c2a0dcSSeungwon Jeon if (!len) 2461f9c2a0dcSSeungwon Jeon break; 2462f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 24633e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2464f95f3850SWill Newton offset += len; 2465f9c2a0dcSSeungwon Jeon remain -= len; 2466f9c2a0dcSSeungwon Jeon } while (remain); 2467f95f3850SWill Newton 2468e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2469f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2470f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 247187a74d39SKyoungil Kim /* if the RXDR is ready read again */ 247287a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 247387a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2474f9c2a0dcSSeungwon Jeon 2475f9c2a0dcSSeungwon Jeon if (!remain) { 2476f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2477f9c2a0dcSSeungwon Jeon goto done; 2478f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2479f9c2a0dcSSeungwon Jeon } 2480f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2481f95f3850SWill Newton return; 2482f95f3850SWill Newton 2483f95f3850SWill Newton done: 2484f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2485f9c2a0dcSSeungwon Jeon host->sg = NULL; 24860e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2487f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2488f95f3850SWill Newton } 2489f95f3850SWill Newton 2490f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2491f95f3850SWill Newton { 2492f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2493f9c2a0dcSSeungwon Jeon void *buf; 2494f9c2a0dcSSeungwon Jeon unsigned int offset; 2495f95f3850SWill Newton struct mmc_data *data = host->data; 2496f95f3850SWill Newton int shift = host->data_shift; 2497f95f3850SWill Newton u32 status; 24983e4b0d8bSMarkos Chandras unsigned int len; 2499f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2500f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2501f95f3850SWill Newton 2502f95f3850SWill Newton do { 2503f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2504f9c2a0dcSSeungwon Jeon goto done; 2505f95f3850SWill Newton 25064225fc85SImre Deak host->sg = sg_miter->piter.sg; 2507f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2508f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2509f9c2a0dcSSeungwon Jeon offset = 0; 2510f9c2a0dcSSeungwon Jeon 2511f9c2a0dcSSeungwon Jeon do { 2512f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2513f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2514f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2515f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2516f9c2a0dcSSeungwon Jeon if (!len) 2517f9c2a0dcSSeungwon Jeon break; 2518f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 25193e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2520f95f3850SWill Newton offset += len; 2521f9c2a0dcSSeungwon Jeon remain -= len; 2522f9c2a0dcSSeungwon Jeon } while (remain); 2523f95f3850SWill Newton 2524e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2525f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2526f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2527f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2528f9c2a0dcSSeungwon Jeon 2529f9c2a0dcSSeungwon Jeon if (!remain) { 2530f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2531f9c2a0dcSSeungwon Jeon goto done; 2532f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2533f9c2a0dcSSeungwon Jeon } 2534f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2535f95f3850SWill Newton return; 2536f95f3850SWill Newton 2537f95f3850SWill Newton done: 2538f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2539f9c2a0dcSSeungwon Jeon host->sg = NULL; 25400e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2541f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2542f95f3850SWill Newton } 2543f95f3850SWill Newton 2544f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2545f95f3850SWill Newton { 2546f95f3850SWill Newton if (!host->cmd_status) 2547f95f3850SWill Newton host->cmd_status = status; 2548f95f3850SWill Newton 25490e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2550f95f3850SWill Newton 2551f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2552f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2553f95f3850SWill Newton } 2554f95f3850SWill Newton 25556130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 25566130e7a9SDoug Anderson { 25576130e7a9SDoug Anderson int i; 25586130e7a9SDoug Anderson 25596130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 25606130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 25616130e7a9SDoug Anderson 25626130e7a9SDoug Anderson if (!slot) 25636130e7a9SDoug Anderson continue; 25646130e7a9SDoug Anderson 25656130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 25666130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 25676130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 25686130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 25696130e7a9SDoug Anderson } 25706130e7a9SDoug Anderson } 25716130e7a9SDoug Anderson 2572f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2573f95f3850SWill Newton { 2574f95f3850SWill Newton struct dw_mci *host = dev_id; 2575182c9081SSeungwon Jeon u32 pending; 25761a5c8e1fSShashidhar Hiremath int i; 2577f95f3850SWill Newton 2578f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2579f95f3850SWill Newton 2580476d79f1SDoug Anderson if (pending) { 258101730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 258201730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 258301730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 258449ba0302SDoug Anderson unsigned long irqflags; 25855c935165SDoug Anderson 258601730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 258701730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 258849ba0302SDoug Anderson 258949ba0302SDoug Anderson /* 259049ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 259149ba0302SDoug Anderson * off after the lock is released, so safe to delete. 259249ba0302SDoug Anderson */ 259349ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 259401730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 259549ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 259649ba0302SDoug Anderson 259749ba0302SDoug Anderson del_timer(&host->cmd11_timer); 259801730558SDoug Anderson } 259901730558SDoug Anderson 2600f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2601f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2602182c9081SSeungwon Jeon host->cmd_status = pending; 26030e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2604f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2605f95f3850SWill Newton } 2606f95f3850SWill Newton 2607f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2608f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2609f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2610182c9081SSeungwon Jeon host->data_status = pending; 26110e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2612f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2613f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2614f95f3850SWill Newton } 2615f95f3850SWill Newton 2616f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 261757e10486SAddy Ke del_timer(&host->dto_timer); 261857e10486SAddy Ke 2619f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2620f95f3850SWill Newton if (!host->data_status) 2621182c9081SSeungwon Jeon host->data_status = pending; 26220e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2623f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2624f95f3850SWill Newton if (host->sg != NULL) 262587a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2626f95f3850SWill Newton } 2627f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2628f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2629f95f3850SWill Newton } 2630f95f3850SWill Newton 2631f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2632f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2633b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 263487a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2635f95f3850SWill Newton } 2636f95f3850SWill Newton 2637f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2638f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2639b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2640f95f3850SWill Newton dw_mci_write_data_pio(host); 2641f95f3850SWill Newton } 2642f95f3850SWill Newton 2643f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2644f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2645182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2646f95f3850SWill Newton } 2647f95f3850SWill Newton 2648f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2649f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 26506130e7a9SDoug Anderson dw_mci_handle_cd(host); 2651f95f3850SWill Newton } 2652f95f3850SWill Newton 26531a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 26541a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 26551a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2656ed2540efSDoug Anderson 2657ed2540efSDoug Anderson if (!slot) 2658ed2540efSDoug Anderson continue; 2659ed2540efSDoug Anderson 266076756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 266176756234SAddy Ke mci_writel(host, RINTSTS, 266276756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 26631a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 26641a5c8e1fSShashidhar Hiremath } 26651a5c8e1fSShashidhar Hiremath } 26661a5c8e1fSShashidhar Hiremath 26671fb5f68aSMarkos Chandras } 2668f95f3850SWill Newton 26693fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 26703fc7eaefSShawn Lin return IRQ_HANDLED; 26713fc7eaefSShawn Lin 26723fc7eaefSShawn Lin /* Handle IDMA interrupts */ 267369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 267469d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 267569d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 267669d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 267769d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 267869d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2679faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 26803fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 268169d99fdcSPrabu Thangamuthu } 268269d99fdcSPrabu Thangamuthu } else { 2683f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2684f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 268569d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 268669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2687f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2688faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 26893fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2690f95f3850SWill Newton } 269169d99fdcSPrabu Thangamuthu } 2692f95f3850SWill Newton 2693f95f3850SWill Newton return IRQ_HANDLED; 2694f95f3850SWill Newton } 2695f95f3850SWill Newton 269636c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2697f95f3850SWill Newton { 2698f95f3850SWill Newton struct mmc_host *mmc; 2699f95f3850SWill Newton struct dw_mci_slot *slot; 2700e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2701800d78bfSThomas Abraham int ctrl_id, ret; 27021f44a2a5SSeungwon Jeon u32 freq[2]; 2703f95f3850SWill Newton 27044a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2705f95f3850SWill Newton if (!mmc) 2706f95f3850SWill Newton return -ENOMEM; 2707f95f3850SWill Newton 2708f95f3850SWill Newton slot = mmc_priv(mmc); 2709f95f3850SWill Newton slot->id = id; 271076756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2711f95f3850SWill Newton slot->mmc = mmc; 2712f95f3850SWill Newton slot->host = host; 2713c91eab4bSThomas Abraham host->slot[id] = slot; 2714f95f3850SWill Newton 2715f95f3850SWill Newton mmc->ops = &dw_mci_ops; 27161f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 27171f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 27181f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 27191f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 27201f44a2a5SSeungwon Jeon } else { 2721b023030fSJaehoon Chung dev_info(host->dev, 2722b023030fSJaehoon Chung "'clock-freq-min-max' property was deprecated.\n"); 27231f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 27241f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 27251f44a2a5SSeungwon Jeon } 2726f95f3850SWill Newton 272751da2240SYuvaraj CD /*if there are external regulators, get them*/ 272851da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 272951da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 27303cf890fcSDoug Anderson goto err_host_allocated; 273151da2240SYuvaraj CD 273251da2240SYuvaraj CD if (!mmc->ocr_avail) 2733f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2734f95f3850SWill Newton 2735fc3d7720SJaehoon Chung if (host->pdata->caps) 2736fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2737fc3d7720SJaehoon Chung 27386024e166SJaehoon Chung /* 27396024e166SJaehoon Chung * Support MMC_CAP_ERASE by default. 27406024e166SJaehoon Chung * It needs to use trim/discard/erase commands. 27416024e166SJaehoon Chung */ 27426024e166SJaehoon Chung mmc->caps |= MMC_CAP_ERASE; 27436024e166SJaehoon Chung 2744ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2745ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2746ab269128SAbhilash Kesavan 2747800d78bfSThomas Abraham if (host->dev->of_node) { 2748800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2749800d78bfSThomas Abraham if (ctrl_id < 0) 2750800d78bfSThomas Abraham ctrl_id = 0; 2751800d78bfSThomas Abraham } else { 2752800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2753800d78bfSThomas Abraham } 2754cb27a843SJames Hogan if (drv_data && drv_data->caps) 2755cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2756800d78bfSThomas Abraham 27574f408cc6SSeungwon Jeon if (host->pdata->caps2) 27584f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 27594f408cc6SSeungwon Jeon 27603cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 27613cf890fcSDoug Anderson if (ret) 27623cf890fcSDoug Anderson goto err_host_allocated; 2763f95f3850SWill Newton 2764f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 27653fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2766a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2767225faf87SJaehoon Chung mmc->max_blk_size = 65535; 2768575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 27691a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 27701a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 27713fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 27723fc7eaefSShawn Lin mmc->max_segs = 64; 2773225faf87SJaehoon Chung mmc->max_blk_size = 65535; 27743fc7eaefSShawn Lin mmc->max_blk_count = 65535; 27753fc7eaefSShawn Lin mmc->max_req_size = 27763fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 27773fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2778575c319dSHeiko Stuebner } else { 27793fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2780f95f3850SWill Newton mmc->max_segs = 64; 2781225faf87SJaehoon Chung mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2782f95f3850SWill Newton mmc->max_blk_count = 512; 2783575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2784575c319dSHeiko Stuebner mmc->max_blk_count; 2785f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2786575c319dSHeiko Stuebner } 2787f95f3850SWill Newton 2788c0834a58SShawn Lin dw_mci_get_cd(mmc); 2789ae0eb348SJaehoon Chung 27900cea529dSJaehoon Chung ret = mmc_add_host(mmc); 27910cea529dSJaehoon Chung if (ret) 27923cf890fcSDoug Anderson goto err_host_allocated; 2793f95f3850SWill Newton 2794f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2795f95f3850SWill Newton dw_mci_init_debugfs(slot); 2796f95f3850SWill Newton #endif 2797f95f3850SWill Newton 2798f95f3850SWill Newton return 0; 2799800d78bfSThomas Abraham 28003cf890fcSDoug Anderson err_host_allocated: 2801800d78bfSThomas Abraham mmc_free_host(mmc); 280251da2240SYuvaraj CD return ret; 2803f95f3850SWill Newton } 2804f95f3850SWill Newton 2805f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2806f95f3850SWill Newton { 2807f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2808f95f3850SWill Newton mmc_remove_host(slot->mmc); 2809f95f3850SWill Newton slot->host->slot[id] = NULL; 2810f95f3850SWill Newton mmc_free_host(slot->mmc); 2811f95f3850SWill Newton } 2812f95f3850SWill Newton 2813f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2814f95f3850SWill Newton { 281569d99fdcSPrabu Thangamuthu int addr_config; 28163fc7eaefSShawn Lin struct device *dev = host->dev; 28173fc7eaefSShawn Lin struct device_node *np = dev->of_node; 28183fc7eaefSShawn Lin 28193fc7eaefSShawn Lin /* 28203fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 28213fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 28223fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 28233fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 28243fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 28253fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 28263fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 28273fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 28283fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 28293fc7eaefSShawn Lin */ 28303fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 28313fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 28323fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 28333fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 28343fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 28353fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 28363fc7eaefSShawn Lin } else { 28373fc7eaefSShawn Lin goto no_dma; 28383fc7eaefSShawn Lin } 28393fc7eaefSShawn Lin 28403fc7eaefSShawn Lin /* Determine which DMA interface to use */ 28413fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 28423fc7eaefSShawn Lin /* 28433fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 28443fc7eaefSShawn Lin * IDMAC address bus width 28453fc7eaefSShawn Lin */ 284670692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 284769d99fdcSPrabu Thangamuthu 284869d99fdcSPrabu Thangamuthu if (addr_config == 1) { 284969d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 285069d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 28513fc7eaefSShawn Lin dev_info(host->dev, 28523fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 285369d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 28543fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 28553fc7eaefSShawn Lin DMA_BIT_MASK(64)); 285669d99fdcSPrabu Thangamuthu } else { 285769d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 285869d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 28593fc7eaefSShawn Lin dev_info(host->dev, 28603fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 286169d99fdcSPrabu Thangamuthu } 286269d99fdcSPrabu Thangamuthu 2863f95f3850SWill Newton /* Alloc memory for sg translation */ 2864cc190d4cSShawn Lin host->sg_cpu = dmam_alloc_coherent(host->dev, 2865cc190d4cSShawn Lin DESC_RING_BUF_SZ, 2866f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2867f95f3850SWill Newton if (!host->sg_cpu) { 28683fc7eaefSShawn Lin dev_err(host->dev, 28693fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2870f95f3850SWill Newton __func__); 2871f95f3850SWill Newton goto no_dma; 2872f95f3850SWill Newton } 2873f95f3850SWill Newton 2874f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 287500956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 28763fc7eaefSShawn Lin } else { 28773fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 28783fc7eaefSShawn Lin if ((of_property_count_strings(np, "dma-names") < 0) || 28793fc7eaefSShawn Lin (!of_find_property(np, "dmas", NULL))) { 2880f95f3850SWill Newton goto no_dma; 28813fc7eaefSShawn Lin } 28823fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 28833fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 28843fc7eaefSShawn Lin } 2885f95f3850SWill Newton 2886e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2887e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2888f95f3850SWill Newton if (host->dma_ops->init(host)) { 28890e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 28900e3a22c0SShawn Lin __func__); 2891f95f3850SWill Newton goto no_dma; 2892f95f3850SWill Newton } 2893f95f3850SWill Newton } else { 28944a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2895f95f3850SWill Newton goto no_dma; 2896f95f3850SWill Newton } 2897f95f3850SWill Newton 2898f95f3850SWill Newton return; 2899f95f3850SWill Newton 2900f95f3850SWill Newton no_dma: 29014a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 29023fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2903f95f3850SWill Newton } 2904f95f3850SWill Newton 29055c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 29065c935165SDoug Anderson { 29075c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 29085c935165SDoug Anderson 2909fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 2910fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2911fd674198SDoug Anderson return; 2912fd674198SDoug Anderson } 29135c935165SDoug Anderson 29145c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 29155c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 29165c935165SDoug Anderson tasklet_schedule(&host->tasklet); 29175c935165SDoug Anderson } 29185c935165SDoug Anderson 291957e10486SAddy Ke static void dw_mci_dto_timer(unsigned long arg) 292057e10486SAddy Ke { 292157e10486SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 292257e10486SAddy Ke 292357e10486SAddy Ke switch (host->state) { 292457e10486SAddy Ke case STATE_SENDING_DATA: 292557e10486SAddy Ke case STATE_DATA_BUSY: 292657e10486SAddy Ke /* 292757e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 292857e10486SAddy Ke * we should notify the driver to terminate current transfer 292957e10486SAddy Ke * and report a data timeout to the core. 293057e10486SAddy Ke */ 293157e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 293257e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 293357e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 293457e10486SAddy Ke tasklet_schedule(&host->tasklet); 293557e10486SAddy Ke break; 293657e10486SAddy Ke default: 293757e10486SAddy Ke break; 293857e10486SAddy Ke } 293957e10486SAddy Ke } 294057e10486SAddy Ke 2941c91eab4bSThomas Abraham #ifdef CONFIG_OF 2942c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2943c91eab4bSThomas Abraham { 2944c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2945c91eab4bSThomas Abraham struct device *dev = host->dev; 2946c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2947e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2948e8cc37b8SShawn Lin int ret; 29493c6d89eaSDoug Anderson u32 clock_frequency; 2950c91eab4bSThomas Abraham 2951c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2952bf3707eaSBeomho Seo if (!pdata) 2953c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2954c91eab4bSThomas Abraham 2955d6786fefSGuodong Xu /* find reset controller when exist */ 29563a667e3fSJaehoon Chung pdata->rstc = devm_reset_control_get_optional(dev, "reset"); 2957d6786fefSGuodong Xu if (IS_ERR(pdata->rstc)) { 2958d6786fefSGuodong Xu if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 2959d6786fefSGuodong Xu return ERR_PTR(-EPROBE_DEFER); 2960d6786fefSGuodong Xu } 2961d6786fefSGuodong Xu 2962c91eab4bSThomas Abraham /* find out number of slots supported */ 29638a629d26SShawn Lin of_property_read_u32(np, "num-slots", &pdata->num_slots); 2964c91eab4bSThomas Abraham 2965c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 29660e3a22c0SShawn Lin dev_info(dev, 29670e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 2968c91eab4bSThomas Abraham 2969c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2970c91eab4bSThomas Abraham 2971a0361c1aSJun Nie of_property_read_u32(np, "data-addr", &host->data_addr_override); 2972a0361c1aSJun Nie 2973d6fced83SJun Nie if (of_get_property(np, "fifo-watermark-aligned", NULL)) 2974d6fced83SJun Nie host->wm_aligned = true; 2975d6fced83SJun Nie 29763c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 29773c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 29783c6d89eaSDoug Anderson 2979cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2980cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2981800d78bfSThomas Abraham if (ret) 2982800d78bfSThomas Abraham return ERR_PTR(ret); 2983800d78bfSThomas Abraham } 2984800d78bfSThomas Abraham 2985c91eab4bSThomas Abraham return pdata; 2986c91eab4bSThomas Abraham } 2987c91eab4bSThomas Abraham 2988c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2989c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2990c91eab4bSThomas Abraham { 2991c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2992c91eab4bSThomas Abraham } 2993c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2994c91eab4bSThomas Abraham 2995fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2996fa0c3283SDoug Anderson { 2997fa0c3283SDoug Anderson unsigned long irqflags; 2998fa0c3283SDoug Anderson u32 temp; 2999fa0c3283SDoug Anderson int i; 3000e8cc37b8SShawn Lin struct dw_mci_slot *slot; 3001fa0c3283SDoug Anderson 3002e8cc37b8SShawn Lin /* 3003e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 3004e8cc37b8SShawn Lin * as well as broken card detection is found. 3005e8cc37b8SShawn Lin */ 3006fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 3007e8cc37b8SShawn Lin slot = host->slot[i]; 3008e8cc37b8SShawn Lin if (slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3009e8cc37b8SShawn Lin return; 3010fa0c3283SDoug Anderson 3011287980e4SArnd Bergmann if (mmc_gpio_get_cd(slot->mmc) < 0) 3012fa0c3283SDoug Anderson break; 3013fa0c3283SDoug Anderson } 3014fa0c3283SDoug Anderson if (i == host->num_slots) 3015fa0c3283SDoug Anderson return; 3016fa0c3283SDoug Anderson 3017fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 3018fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 3019fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 3020fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 3021fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 3022fa0c3283SDoug Anderson } 3023fa0c3283SDoug Anderson 302462ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 3025f95f3850SWill Newton { 3026e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 302762ca8034SShashidhar Hiremath int width, i, ret = 0; 3028f95f3850SWill Newton u32 fifo_size; 30291c2215b7SThomas Abraham int init_slots = 0; 3030f95f3850SWill Newton 3031c91eab4bSThomas Abraham if (!host->pdata) { 3032c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 3033d6786fefSGuodong Xu if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3034d6786fefSGuodong Xu return -EPROBE_DEFER; 3035d6786fefSGuodong Xu } else if (IS_ERR(host->pdata)) { 3036c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 3037c91eab4bSThomas Abraham return -EINVAL; 3038c91eab4bSThomas Abraham } 3039f95f3850SWill Newton } 3040f95f3850SWill Newton 3041780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 3042f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 3043f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 3044f90a0612SThomas Abraham } else { 3045f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 3046f90a0612SThomas Abraham if (ret) { 3047f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 3048f90a0612SThomas Abraham return ret; 3049f90a0612SThomas Abraham } 3050f95f3850SWill Newton } 3051f95f3850SWill Newton 3052780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3053f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 3054f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 30553c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 3056f90a0612SThomas Abraham } else { 3057f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 3058f90a0612SThomas Abraham if (ret) { 3059f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 3060f90a0612SThomas Abraham goto err_clk_biu; 3061f90a0612SThomas Abraham } 3062f90a0612SThomas Abraham 30633c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 30643c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 30653c6d89eaSDoug Anderson if (ret) 30663c6d89eaSDoug Anderson dev_warn(host->dev, 3067612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 30683c6d89eaSDoug Anderson host->pdata->bus_hz); 30693c6d89eaSDoug Anderson } 3070f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 30713c6d89eaSDoug Anderson } 3072f90a0612SThomas Abraham 3073612de4c1SJaehoon Chung if (!host->bus_hz) { 3074612de4c1SJaehoon Chung dev_err(host->dev, 3075612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3076612de4c1SJaehoon Chung ret = -ENODEV; 3077612de4c1SJaehoon Chung goto err_clk_ciu; 3078612de4c1SJaehoon Chung } 3079612de4c1SJaehoon Chung 3080002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3081002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3082002f0d5cSYuvaraj Kumar C D if (ret) { 3083002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3084002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3085002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3086002f0d5cSYuvaraj Kumar C D } 3087002f0d5cSYuvaraj Kumar C D } 3088002f0d5cSYuvaraj Kumar C D 3089d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) { 3090d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3091d6786fefSGuodong Xu usleep_range(10, 50); 3092d6786fefSGuodong Xu reset_control_deassert(host->pdata->rstc); 3093d6786fefSGuodong Xu } 3094d6786fefSGuodong Xu 30955c935165SDoug Anderson setup_timer(&host->cmd11_timer, 30965c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 30975c935165SDoug Anderson 309857e10486SAddy Ke setup_timer(&host->dto_timer, 309957e10486SAddy Ke dw_mci_dto_timer, (unsigned long)host); 310057e10486SAddy Ke 3101f95f3850SWill Newton spin_lock_init(&host->lock); 3102f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3103f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3104f95f3850SWill Newton 3105f95f3850SWill Newton /* 3106f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3107f95f3850SWill Newton * the correct values. 3108f95f3850SWill Newton */ 310970692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3110f95f3850SWill Newton if (!i) { 3111f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3112f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3113f95f3850SWill Newton width = 16; 3114f95f3850SWill Newton host->data_shift = 1; 3115f95f3850SWill Newton } else if (i == 2) { 3116f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3117f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3118f95f3850SWill Newton width = 64; 3119f95f3850SWill Newton host->data_shift = 3; 3120f95f3850SWill Newton } else { 3121f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3122f95f3850SWill Newton WARN((i != 1), 3123f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3124f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3125f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3126f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3127f95f3850SWill Newton width = 32; 3128f95f3850SWill Newton host->data_shift = 2; 3129f95f3850SWill Newton } 3130f95f3850SWill Newton 3131f95f3850SWill Newton /* Reset all blocks */ 31323744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 31333744415cSShawn Lin ret = -ENODEV; 31343744415cSShawn Lin goto err_clk_ciu; 31353744415cSShawn Lin } 3136141a712aSSeungwon Jeon 3137141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3138141a712aSSeungwon Jeon dw_mci_init_dma(host); 3139f95f3850SWill Newton 3140f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3141f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3142f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3143f95f3850SWill Newton 3144f95f3850SWill Newton /* Put in max timeout */ 3145f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3146f95f3850SWill Newton 3147f95f3850SWill Newton /* 3148f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3149f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3150f95f3850SWill Newton */ 3151b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3152b86d8253SJames Hogan /* 3153b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3154b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3155b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3156b86d8253SJames Hogan * should put it in the platform data. 3157b86d8253SJames Hogan */ 3158f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 31598234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3160b86d8253SJames Hogan } else { 3161b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3162b86d8253SJames Hogan } 3163b86d8253SJames Hogan host->fifo_depth = fifo_size; 316452426899SSeungwon Jeon host->fifoth_val = 316552426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3166e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3167f95f3850SWill Newton 3168f95f3850SWill Newton /* disable clock to CIU */ 3169f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3170f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3171f95f3850SWill Newton 317263008768SJames Hogan /* 317363008768SJames Hogan * In 2.40a spec, Data offset is changed. 317463008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 317563008768SJames Hogan */ 317663008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 317763008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 317863008768SJames Hogan 3179a0361c1aSJun Nie if (host->data_addr_override) 3180a0361c1aSJun Nie host->fifo_reg = host->regs + host->data_addr_override; 3181a0361c1aSJun Nie else if (host->verid < DW_MMC_240A) 318276184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 318363008768SJames Hogan else 318476184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 318563008768SJames Hogan 3186f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3187780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3188780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3189f95f3850SWill Newton if (ret) 31906130e7a9SDoug Anderson goto err_dmaunmap; 3191f95f3850SWill Newton 3192f95f3850SWill Newton if (host->pdata->num_slots) 3193f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 3194f95f3850SWill Newton else 31958a629d26SShawn Lin host->num_slots = 1; 31968a629d26SShawn Lin 31978a629d26SShawn Lin if (host->num_slots < 1 || 31988a629d26SShawn Lin host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) { 31998a629d26SShawn Lin dev_err(host->dev, 32008a629d26SShawn Lin "Platform data must supply correct num_slots.\n"); 32018a629d26SShawn Lin ret = -ENODEV; 32028a629d26SShawn Lin goto err_clk_ciu; 32038a629d26SShawn Lin } 3204f95f3850SWill Newton 32052da1d7f2SYuvaraj CD /* 3206fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 32072da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 32082da1d7f2SYuvaraj CD */ 32092da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 32102da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3211fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 32120e3a22c0SShawn Lin /* Enable mci interrupt */ 32130e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 32142da1d7f2SYuvaraj CD 32150e3a22c0SShawn Lin dev_info(host->dev, 32160e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 32172da1d7f2SYuvaraj CD host->irq, width, fifo_size); 32182da1d7f2SYuvaraj CD 3219f95f3850SWill Newton /* We need at least one slot to succeed */ 3220f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3221f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 32221c2215b7SThomas Abraham if (ret) 32231c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 32241c2215b7SThomas Abraham else 32251c2215b7SThomas Abraham init_slots++; 3226f95f3850SWill Newton } 32271c2215b7SThomas Abraham 32281c2215b7SThomas Abraham if (init_slots) { 32291c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 32301c2215b7SThomas Abraham } else { 32310e3a22c0SShawn Lin dev_dbg(host->dev, 32320e3a22c0SShawn Lin "attempted to initialize %d slots, but failed on all\n", 32330e3a22c0SShawn Lin host->num_slots); 32346130e7a9SDoug Anderson goto err_dmaunmap; 3235f95f3850SWill Newton } 3236f95f3850SWill Newton 3237b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3238b793f658SDoug Anderson dw_mci_enable_cd(host); 3239b793f658SDoug Anderson 3240f95f3850SWill Newton return 0; 3241f95f3850SWill Newton 3242f95f3850SWill Newton err_dmaunmap: 3243f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3244f95f3850SWill Newton host->dma_ops->exit(host); 3245f90a0612SThomas Abraham 3246d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3247d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3248d6786fefSGuodong Xu 3249f90a0612SThomas Abraham err_clk_ciu: 3250f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3251780f22afSSeungwon Jeon 3252f90a0612SThomas Abraham err_clk_biu: 3253f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3254780f22afSSeungwon Jeon 3255f95f3850SWill Newton return ret; 3256f95f3850SWill Newton } 325762ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3258f95f3850SWill Newton 325962ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3260f95f3850SWill Newton { 3261f95f3850SWill Newton int i; 3262f95f3850SWill Newton 3263f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 32644a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 3265f95f3850SWill Newton if (host->slot[i]) 3266f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 3267f95f3850SWill Newton } 3268f95f3850SWill Newton 3269048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3270048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3271048fd7e6SPrabu Thangamuthu 3272f95f3850SWill Newton /* disable clock to CIU */ 3273f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3274f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3275f95f3850SWill Newton 3276f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3277f95f3850SWill Newton host->dma_ops->exit(host); 3278f95f3850SWill Newton 3279d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3280d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3281d6786fefSGuodong Xu 3282f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3283f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3284f95f3850SWill Newton } 328562ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 328662ca8034SShashidhar Hiremath 328762ca8034SShashidhar Hiremath 3288f95f3850SWill Newton 3289e9ed8835SShawn Lin #ifdef CONFIG_PM 3290ed24e1ffSShawn Lin int dw_mci_runtime_suspend(struct device *dev) 3291f95f3850SWill Newton { 3292ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3293ed24e1ffSShawn Lin 32943fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 32953fc7eaefSShawn Lin host->dma_ops->exit(host); 32963fc7eaefSShawn Lin 3297ed24e1ffSShawn Lin clk_disable_unprepare(host->ciu_clk); 3298ed24e1ffSShawn Lin 3299ed24e1ffSShawn Lin if (host->cur_slot && 3300ed24e1ffSShawn Lin (mmc_can_gpio_cd(host->cur_slot->mmc) || 3301ed24e1ffSShawn Lin !mmc_card_is_removable(host->cur_slot->mmc))) 3302ed24e1ffSShawn Lin clk_disable_unprepare(host->biu_clk); 3303ed24e1ffSShawn Lin 3304f95f3850SWill Newton return 0; 3305f95f3850SWill Newton } 3306ed24e1ffSShawn Lin EXPORT_SYMBOL(dw_mci_runtime_suspend); 3307f95f3850SWill Newton 3308ed24e1ffSShawn Lin int dw_mci_runtime_resume(struct device *dev) 3309f95f3850SWill Newton { 3310ed24e1ffSShawn Lin int i, ret = 0; 3311ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3312f95f3850SWill Newton 3313ed24e1ffSShawn Lin if (host->cur_slot && 3314ed24e1ffSShawn Lin (mmc_can_gpio_cd(host->cur_slot->mmc) || 3315ed24e1ffSShawn Lin !mmc_card_is_removable(host->cur_slot->mmc))) { 3316ed24e1ffSShawn Lin ret = clk_prepare_enable(host->biu_clk); 3317ed24e1ffSShawn Lin if (ret) 3318e61cf118SJaehoon Chung return ret; 3319e61cf118SJaehoon Chung } 3320e61cf118SJaehoon Chung 3321ed24e1ffSShawn Lin ret = clk_prepare_enable(host->ciu_clk); 3322ed24e1ffSShawn Lin if (ret) 3323df9bcc2bSJoonyoung Shim goto err; 3324df9bcc2bSJoonyoung Shim 3325df9bcc2bSJoonyoung Shim if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3326df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->ciu_clk); 3327df9bcc2bSJoonyoung Shim ret = -ENODEV; 3328df9bcc2bSJoonyoung Shim goto err; 3329df9bcc2bSJoonyoung Shim } 3330ed24e1ffSShawn Lin 33313bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3332141a712aSSeungwon Jeon host->dma_ops->init(host); 3333141a712aSSeungwon Jeon 333452426899SSeungwon Jeon /* 333552426899SSeungwon Jeon * Restore the initial value at FIFOTH register 333652426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 333752426899SSeungwon Jeon */ 3338e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 333952426899SSeungwon Jeon host->prev_blksz = 0; 3340e61cf118SJaehoon Chung 33412eb2944fSDoug Anderson /* Put in max timeout */ 33422eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 33432eb2944fSDoug Anderson 3344e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3345e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3346e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3347fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3348e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3349e61cf118SJaehoon Chung 3350f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3351f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 33520e3a22c0SShawn Lin 3353f95f3850SWill Newton if (!slot) 3354f95f3850SWill Newton continue; 3355e9748e03SZiyuan Xu if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3356ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3357e9748e03SZiyuan Xu 3358e9748e03SZiyuan Xu /* Force setup bus to guarantee available clock output */ 3359ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 3360ab269128SAbhilash Kesavan } 3361fa0c3283SDoug Anderson 3362fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3363fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3364fa0c3283SDoug Anderson 3365df9bcc2bSJoonyoung Shim return 0; 3366df9bcc2bSJoonyoung Shim 3367df9bcc2bSJoonyoung Shim err: 3368df9bcc2bSJoonyoung Shim if (host->cur_slot && 3369df9bcc2bSJoonyoung Shim (mmc_can_gpio_cd(host->cur_slot->mmc) || 3370df9bcc2bSJoonyoung Shim !mmc_card_is_removable(host->cur_slot->mmc))) 3371df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->biu_clk); 3372df9bcc2bSJoonyoung Shim 33731f5c51d7SShawn Lin return ret; 33741f5c51d7SShawn Lin } 3375e9ed8835SShawn Lin EXPORT_SYMBOL(dw_mci_runtime_resume); 3376e9ed8835SShawn Lin #endif /* CONFIG_PM */ 33776fe8890dSJaehoon Chung 3378f95f3850SWill Newton static int __init dw_mci_init(void) 3379f95f3850SWill Newton { 33808e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 338162ca8034SShashidhar Hiremath return 0; 3382f95f3850SWill Newton } 3383f95f3850SWill Newton 3384f95f3850SWill Newton static void __exit dw_mci_exit(void) 3385f95f3850SWill Newton { 3386f95f3850SWill Newton } 3387f95f3850SWill Newton 3388f95f3850SWill Newton module_init(dw_mci_init); 3389f95f3850SWill Newton module_exit(dw_mci_exit); 3390f95f3850SWill Newton 3391f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3392f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3393f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3394f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3395