1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22f95f3850SWill Newton #include <linux/ioport.h> 23f95f3850SWill Newton #include <linux/module.h> 24f95f3850SWill Newton #include <linux/platform_device.h> 25f95f3850SWill Newton #include <linux/seq_file.h> 26f95f3850SWill Newton #include <linux/slab.h> 27f95f3850SWill Newton #include <linux/stat.h> 28f95f3850SWill Newton #include <linux/delay.h> 29f95f3850SWill Newton #include <linux/irq.h> 30b24c8b26SDoug Anderson #include <linux/mmc/card.h> 31f95f3850SWill Newton #include <linux/mmc/host.h> 32f95f3850SWill Newton #include <linux/mmc/mmc.h> 3301730558SDoug Anderson #include <linux/mmc/sd.h> 3490c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 35f95f3850SWill Newton #include <linux/mmc/dw_mmc.h> 36f95f3850SWill Newton #include <linux/bitops.h> 37c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 38c91eab4bSThomas Abraham #include <linux/of.h> 3955a6ceb2SDoug Anderson #include <linux/of_gpio.h> 40bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 41f95f3850SWill Newton 42f95f3850SWill Newton #include "dw_mmc.h" 43f95f3850SWill Newton 44f95f3850SWill Newton /* Common flag combinations */ 453f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47f95f3850SWill Newton SDMMC_INT_EBE) 48f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49f95f3850SWill Newton SDMMC_INT_RESP_ERR) 50f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51f95f3850SWill Newton DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 53f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 54f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 55f95f3850SWill Newton 561f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 581f44a2a5SSeungwon Jeon 59fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 60fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 63fc79a4d6SJoonyoung Shim 6469d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6569d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 6669d99fdcSPrabu Thangamuthu 6769d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 6869d99fdcSPrabu Thangamuthu 6969d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7069d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 716687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 726687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 7569d99fdcSPrabu Thangamuthu 7669d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 7769d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8069d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8169d99fdcSPrabu Thangamuthu }; 8269d99fdcSPrabu Thangamuthu 83f95f3850SWill Newton struct idmac_desc { 846687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 85f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 86f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 87f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 88f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 89f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 90f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 91f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 92f95f3850SWill Newton 936687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 94f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 959b7bbe10SShashidhar Hiremath ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 96f95f3850SWill Newton 976687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 98f95f3850SWill Newton 996687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 100f95f3850SWill Newton }; 1015959b32eSAlexey Brodkin 1025959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1035959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 104f95f3850SWill Newton 1053a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host); 106536f6b91SSonny Rao static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 1070bdbd0e8SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc); 10831bff450SSeungwon Jeon 109f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 110f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 111f95f3850SWill Newton { 112f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 113f95f3850SWill Newton struct mmc_request *mrq; 114f95f3850SWill Newton struct mmc_command *cmd; 115f95f3850SWill Newton struct mmc_command *stop; 116f95f3850SWill Newton struct mmc_data *data; 117f95f3850SWill Newton 118f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 119f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 120f95f3850SWill Newton mrq = slot->mrq; 121f95f3850SWill Newton 122f95f3850SWill Newton if (mrq) { 123f95f3850SWill Newton cmd = mrq->cmd; 124f95f3850SWill Newton data = mrq->data; 125f95f3850SWill Newton stop = mrq->stop; 126f95f3850SWill Newton 127f95f3850SWill Newton if (cmd) 128f95f3850SWill Newton seq_printf(s, 129f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 130f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 131f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 132f95f3850SWill Newton cmd->resp[2], cmd->error); 133f95f3850SWill Newton if (data) 134f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 135f95f3850SWill Newton data->bytes_xfered, data->blocks, 136f95f3850SWill Newton data->blksz, data->flags, data->error); 137f95f3850SWill Newton if (stop) 138f95f3850SWill Newton seq_printf(s, 139f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 140f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 141f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 142f95f3850SWill Newton stop->resp[2], stop->error); 143f95f3850SWill Newton } 144f95f3850SWill Newton 145f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 146f95f3850SWill Newton 147f95f3850SWill Newton return 0; 148f95f3850SWill Newton } 149f95f3850SWill Newton 150f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 151f95f3850SWill Newton { 152f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 153f95f3850SWill Newton } 154f95f3850SWill Newton 155f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 156f95f3850SWill Newton .owner = THIS_MODULE, 157f95f3850SWill Newton .open = dw_mci_req_open, 158f95f3850SWill Newton .read = seq_read, 159f95f3850SWill Newton .llseek = seq_lseek, 160f95f3850SWill Newton .release = single_release, 161f95f3850SWill Newton }; 162f95f3850SWill Newton 163f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 164f95f3850SWill Newton { 165f95f3850SWill Newton seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 166f95f3850SWill Newton seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 167f95f3850SWill Newton seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 168f95f3850SWill Newton seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 169f95f3850SWill Newton seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 170f95f3850SWill Newton seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 171f95f3850SWill Newton 172f95f3850SWill Newton return 0; 173f95f3850SWill Newton } 174f95f3850SWill Newton 175f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 176f95f3850SWill Newton { 177f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 178f95f3850SWill Newton } 179f95f3850SWill Newton 180f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 181f95f3850SWill Newton .owner = THIS_MODULE, 182f95f3850SWill Newton .open = dw_mci_regs_open, 183f95f3850SWill Newton .read = seq_read, 184f95f3850SWill Newton .llseek = seq_lseek, 185f95f3850SWill Newton .release = single_release, 186f95f3850SWill Newton }; 187f95f3850SWill Newton 188f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 189f95f3850SWill Newton { 190f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 191f95f3850SWill Newton struct dw_mci *host = slot->host; 192f95f3850SWill Newton struct dentry *root; 193f95f3850SWill Newton struct dentry *node; 194f95f3850SWill Newton 195f95f3850SWill Newton root = mmc->debugfs_root; 196f95f3850SWill Newton if (!root) 197f95f3850SWill Newton return; 198f95f3850SWill Newton 199f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 200f95f3850SWill Newton &dw_mci_regs_fops); 201f95f3850SWill Newton if (!node) 202f95f3850SWill Newton goto err; 203f95f3850SWill Newton 204f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 205f95f3850SWill Newton &dw_mci_req_fops); 206f95f3850SWill Newton if (!node) 207f95f3850SWill Newton goto err; 208f95f3850SWill Newton 209f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 210f95f3850SWill Newton if (!node) 211f95f3850SWill Newton goto err; 212f95f3850SWill Newton 213f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 214f95f3850SWill Newton (u32 *)&host->pending_events); 215f95f3850SWill Newton if (!node) 216f95f3850SWill Newton goto err; 217f95f3850SWill Newton 218f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 219f95f3850SWill Newton (u32 *)&host->completed_events); 220f95f3850SWill Newton if (!node) 221f95f3850SWill Newton goto err; 222f95f3850SWill Newton 223f95f3850SWill Newton return; 224f95f3850SWill Newton 225f95f3850SWill Newton err: 226f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 227f95f3850SWill Newton } 228f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 229f95f3850SWill Newton 23001730558SDoug Anderson static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 23101730558SDoug Anderson 232f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 233f95f3850SWill Newton { 234f95f3850SWill Newton struct mmc_data *data; 235800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 23601730558SDoug Anderson struct dw_mci *host = slot->host; 237f95f3850SWill Newton u32 cmdr; 238f95f3850SWill Newton 2390e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 240f95f3850SWill Newton cmdr = cmd->opcode; 241f95f3850SWill Newton 24290c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 24390c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 24490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 24590c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 24690c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 247f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 2484a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 249f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 250f95f3850SWill Newton 25101730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 25201730558SDoug Anderson u32 clk_en_a; 25301730558SDoug Anderson 25401730558SDoug Anderson /* Special bit makes CMD11 not die */ 25501730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 25601730558SDoug Anderson 25701730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 25801730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 25901730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 26001730558SDoug Anderson 26101730558SDoug Anderson /* 26201730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 26301730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 26401730558SDoug Anderson * since stopping the clock is a specific part of the UHS 26501730558SDoug Anderson * voltage change dance. 26601730558SDoug Anderson * 26701730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 26801730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 26901730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 27001730558SDoug Anderson * until the voltage change is all done. 27101730558SDoug Anderson */ 27201730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 27301730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 27401730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 27501730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 27601730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 27701730558SDoug Anderson } 27801730558SDoug Anderson 279f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 280f95f3850SWill Newton /* We expect a response, so set this bit */ 281f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 282f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 283f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 284f95f3850SWill Newton } 285f95f3850SWill Newton 286f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 287f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 288f95f3850SWill Newton 289f95f3850SWill Newton data = cmd->data; 290f95f3850SWill Newton if (data) { 291f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 292f95f3850SWill Newton if (data->flags & MMC_DATA_WRITE) 293f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 294f95f3850SWill Newton } 295f95f3850SWill Newton 296aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 297aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 298800d78bfSThomas Abraham 299f95f3850SWill Newton return cmdr; 300f95f3850SWill Newton } 301f95f3850SWill Newton 30290c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 30390c2143aSSeungwon Jeon { 30490c2143aSSeungwon Jeon struct mmc_command *stop; 30590c2143aSSeungwon Jeon u32 cmdr; 30690c2143aSSeungwon Jeon 30790c2143aSSeungwon Jeon if (!cmd->data) 30890c2143aSSeungwon Jeon return 0; 30990c2143aSSeungwon Jeon 31090c2143aSSeungwon Jeon stop = &host->stop_abort; 31190c2143aSSeungwon Jeon cmdr = cmd->opcode; 31290c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 31390c2143aSSeungwon Jeon 31490c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 31590c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 31690c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3176c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3186c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3196c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 32090c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 32190c2143aSSeungwon Jeon stop->arg = 0; 32290c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 32390c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 32490c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 32590c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 32690c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 32790c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 32890c2143aSSeungwon Jeon } else { 32990c2143aSSeungwon Jeon return 0; 33090c2143aSSeungwon Jeon } 33190c2143aSSeungwon Jeon 33290c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 33390c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 33490c2143aSSeungwon Jeon 33590c2143aSSeungwon Jeon return cmdr; 33690c2143aSSeungwon Jeon } 33790c2143aSSeungwon Jeon 3380bdbd0e8SDoug Anderson static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 3390bdbd0e8SDoug Anderson { 3400bdbd0e8SDoug Anderson unsigned long timeout = jiffies + msecs_to_jiffies(500); 3410bdbd0e8SDoug Anderson 3420bdbd0e8SDoug Anderson /* 3430bdbd0e8SDoug Anderson * Databook says that before issuing a new data transfer command 3440bdbd0e8SDoug Anderson * we need to check to see if the card is busy. Data transfer commands 3450bdbd0e8SDoug Anderson * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 3460bdbd0e8SDoug Anderson * 3470bdbd0e8SDoug Anderson * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 3480bdbd0e8SDoug Anderson * expected. 3490bdbd0e8SDoug Anderson */ 3500bdbd0e8SDoug Anderson if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 3510bdbd0e8SDoug Anderson !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 3520bdbd0e8SDoug Anderson while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 3530bdbd0e8SDoug Anderson if (time_after(jiffies, timeout)) { 3540bdbd0e8SDoug Anderson /* Command will fail; we'll pass error then */ 3550bdbd0e8SDoug Anderson dev_err(host->dev, "Busy; trying anyway\n"); 3560bdbd0e8SDoug Anderson break; 3570bdbd0e8SDoug Anderson } 3580bdbd0e8SDoug Anderson udelay(10); 3590bdbd0e8SDoug Anderson } 3600bdbd0e8SDoug Anderson } 3610bdbd0e8SDoug Anderson } 3620bdbd0e8SDoug Anderson 363f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 364f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 365f95f3850SWill Newton { 366f95f3850SWill Newton host->cmd = cmd; 3674a90920cSThomas Abraham dev_vdbg(host->dev, 368f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 369f95f3850SWill Newton cmd->arg, cmd_flags); 370f95f3850SWill Newton 371f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 3720e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 3730bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 374f95f3850SWill Newton 375f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 376f95f3850SWill Newton } 377f95f3850SWill Newton 37890c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 379f95f3850SWill Newton { 38090c2143aSSeungwon Jeon struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 3810e3a22c0SShawn Lin 38290c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 383f95f3850SWill Newton } 384f95f3850SWill Newton 385f95f3850SWill Newton /* DMA interface functions */ 386f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 387f95f3850SWill Newton { 38803e8cb53SJames Hogan if (host->using_dma) { 389f95f3850SWill Newton host->dma_ops->stop(host); 390f95f3850SWill Newton host->dma_ops->cleanup(host); 391aa50f259SSeungwon Jeon } 392aa50f259SSeungwon Jeon 393f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 394f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 395f95f3850SWill Newton } 396f95f3850SWill Newton 3979aa51408SSeungwon Jeon static int dw_mci_get_dma_dir(struct mmc_data *data) 3989aa51408SSeungwon Jeon { 3999aa51408SSeungwon Jeon if (data->flags & MMC_DATA_WRITE) 4009aa51408SSeungwon Jeon return DMA_TO_DEVICE; 4019aa51408SSeungwon Jeon else 4029aa51408SSeungwon Jeon return DMA_FROM_DEVICE; 4039aa51408SSeungwon Jeon } 4049aa51408SSeungwon Jeon 405f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 406f95f3850SWill Newton { 407f95f3850SWill Newton struct mmc_data *data = host->data; 408f95f3850SWill Newton 409f95f3850SWill Newton if (data) 4109aa51408SSeungwon Jeon if (!data->host_cookie) 4114a90920cSThomas Abraham dma_unmap_sg(host->dev, 4129aa51408SSeungwon Jeon data->sg, 4139aa51408SSeungwon Jeon data->sg_len, 4149aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 415f95f3850SWill Newton } 416f95f3850SWill Newton 4175ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4185ce9d961SSeungwon Jeon { 4195ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4205ce9d961SSeungwon Jeon /* Software reset of DMA */ 4215ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4225ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4235ce9d961SSeungwon Jeon } 4245ce9d961SSeungwon Jeon 425f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 426f95f3850SWill Newton { 427f95f3850SWill Newton u32 temp; 428f95f3850SWill Newton 429f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 430f95f3850SWill Newton temp = mci_readl(host, CTRL); 431f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 432f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 433f95f3850SWill Newton mci_writel(host, CTRL, temp); 434f95f3850SWill Newton 435f95f3850SWill Newton /* Stop the IDMAC running */ 436f95f3850SWill Newton temp = mci_readl(host, BMOD); 437a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4385ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 439f95f3850SWill Newton mci_writel(host, BMOD, temp); 440f95f3850SWill Newton } 441f95f3850SWill Newton 4423fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 443f95f3850SWill Newton { 4443fc7eaefSShawn Lin struct dw_mci *host = arg; 445f95f3850SWill Newton struct mmc_data *data = host->data; 446f95f3850SWill Newton 4474a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 448f95f3850SWill Newton 4493fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 4503fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 4513fc7eaefSShawn Lin /* Invalidate cache after read */ 4523fc7eaefSShawn Lin dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 4533fc7eaefSShawn Lin data->sg, 4543fc7eaefSShawn Lin data->sg_len, 4553fc7eaefSShawn Lin DMA_FROM_DEVICE); 4563fc7eaefSShawn Lin 457f95f3850SWill Newton host->dma_ops->cleanup(host); 458f95f3850SWill Newton 459f95f3850SWill Newton /* 460f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 461f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 462f95f3850SWill Newton */ 463f95f3850SWill Newton if (data) { 464f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 465f95f3850SWill Newton tasklet_schedule(&host->tasklet); 466f95f3850SWill Newton } 467f95f3850SWill Newton } 468f95f3850SWill Newton 469f95f3850SWill Newton static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 470f95f3850SWill Newton unsigned int sg_len) 471f95f3850SWill Newton { 4725959b32eSAlexey Brodkin unsigned int desc_len; 473f95f3850SWill Newton int i; 4740e3a22c0SShawn Lin 47569d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 4765959b32eSAlexey Brodkin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 47769d99fdcSPrabu Thangamuthu 4785959b32eSAlexey Brodkin desc_first = desc_last = desc = host->sg_cpu; 4795959b32eSAlexey Brodkin 4805959b32eSAlexey Brodkin for (i = 0; i < sg_len; i++) { 48169d99fdcSPrabu Thangamuthu unsigned int length = sg_dma_len(&data->sg[i]); 4820e3a22c0SShawn Lin 48369d99fdcSPrabu Thangamuthu u64 mem_addr = sg_dma_address(&data->sg[i]); 48469d99fdcSPrabu Thangamuthu 4855959b32eSAlexey Brodkin for ( ; length ; desc++) { 4865959b32eSAlexey Brodkin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 4875959b32eSAlexey Brodkin length : DW_MCI_DESC_DATA_LENGTH; 4885959b32eSAlexey Brodkin 4895959b32eSAlexey Brodkin length -= desc_len; 4905959b32eSAlexey Brodkin 49169d99fdcSPrabu Thangamuthu /* 4925959b32eSAlexey Brodkin * Set the OWN bit and disable interrupts 4935959b32eSAlexey Brodkin * for this descriptor 49469d99fdcSPrabu Thangamuthu */ 49569d99fdcSPrabu Thangamuthu desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 49669d99fdcSPrabu Thangamuthu IDMAC_DES0_CH; 4975959b32eSAlexey Brodkin 49869d99fdcSPrabu Thangamuthu /* Buffer length */ 4995959b32eSAlexey Brodkin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 50069d99fdcSPrabu Thangamuthu 50169d99fdcSPrabu Thangamuthu /* Physical address to DMA to/from */ 50269d99fdcSPrabu Thangamuthu desc->des4 = mem_addr & 0xffffffff; 50369d99fdcSPrabu Thangamuthu desc->des5 = mem_addr >> 32; 5045959b32eSAlexey Brodkin 5055959b32eSAlexey Brodkin /* Update physical address for the next desc */ 5065959b32eSAlexey Brodkin mem_addr += desc_len; 5075959b32eSAlexey Brodkin 5085959b32eSAlexey Brodkin /* Save pointer to the last descriptor */ 5095959b32eSAlexey Brodkin desc_last = desc; 5105959b32eSAlexey Brodkin } 51169d99fdcSPrabu Thangamuthu } 51269d99fdcSPrabu Thangamuthu 51369d99fdcSPrabu Thangamuthu /* Set first descriptor */ 5145959b32eSAlexey Brodkin desc_first->des0 |= IDMAC_DES0_FD; 51569d99fdcSPrabu Thangamuthu 51669d99fdcSPrabu Thangamuthu /* Set last descriptor */ 5175959b32eSAlexey Brodkin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 5185959b32eSAlexey Brodkin desc_last->des0 |= IDMAC_DES0_LD; 51969d99fdcSPrabu Thangamuthu 52069d99fdcSPrabu Thangamuthu } else { 5215959b32eSAlexey Brodkin struct idmac_desc *desc_first, *desc_last, *desc; 522f95f3850SWill Newton 5235959b32eSAlexey Brodkin desc_first = desc_last = desc = host->sg_cpu; 5245959b32eSAlexey Brodkin 5255959b32eSAlexey Brodkin for (i = 0; i < sg_len; i++) { 526f95f3850SWill Newton unsigned int length = sg_dma_len(&data->sg[i]); 5270e3a22c0SShawn Lin 528f95f3850SWill Newton u32 mem_addr = sg_dma_address(&data->sg[i]); 529f95f3850SWill Newton 5305959b32eSAlexey Brodkin for ( ; length ; desc++) { 5315959b32eSAlexey Brodkin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 5325959b32eSAlexey Brodkin length : DW_MCI_DESC_DATA_LENGTH; 5335959b32eSAlexey Brodkin 5345959b32eSAlexey Brodkin length -= desc_len; 5355959b32eSAlexey Brodkin 53669d99fdcSPrabu Thangamuthu /* 5375959b32eSAlexey Brodkin * Set the OWN bit and disable interrupts 5385959b32eSAlexey Brodkin * for this descriptor 53969d99fdcSPrabu Thangamuthu */ 5406687c42fSBen Dooks desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 5415959b32eSAlexey Brodkin IDMAC_DES0_DIC | 5425959b32eSAlexey Brodkin IDMAC_DES0_CH); 5435959b32eSAlexey Brodkin 544f95f3850SWill Newton /* Buffer length */ 5455959b32eSAlexey Brodkin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 546f95f3850SWill Newton 547f95f3850SWill Newton /* Physical address to DMA to/from */ 5486687c42fSBen Dooks desc->des2 = cpu_to_le32(mem_addr); 5495959b32eSAlexey Brodkin 5505959b32eSAlexey Brodkin /* Update physical address for the next desc */ 5515959b32eSAlexey Brodkin mem_addr += desc_len; 5525959b32eSAlexey Brodkin 5535959b32eSAlexey Brodkin /* Save pointer to the last descriptor */ 5545959b32eSAlexey Brodkin desc_last = desc; 5555959b32eSAlexey Brodkin } 556f95f3850SWill Newton } 557f95f3850SWill Newton 558f95f3850SWill Newton /* Set first descriptor */ 5595959b32eSAlexey Brodkin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 560f95f3850SWill Newton 561f95f3850SWill Newton /* Set last descriptor */ 5625959b32eSAlexey Brodkin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 5635959b32eSAlexey Brodkin IDMAC_DES0_DIC)); 5645959b32eSAlexey Brodkin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 56569d99fdcSPrabu Thangamuthu } 566f95f3850SWill Newton 5670e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 568f95f3850SWill Newton } 569f95f3850SWill Newton 5703fc7eaefSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 571f95f3850SWill Newton { 572f95f3850SWill Newton u32 temp; 573f95f3850SWill Newton 574f95f3850SWill Newton dw_mci_translate_sglist(host, host->data, sg_len); 575f95f3850SWill Newton 576536f6b91SSonny Rao /* Make sure to reset DMA in case we did PIO before this */ 577536f6b91SSonny Rao dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 578536f6b91SSonny Rao dw_mci_idmac_reset(host); 579536f6b91SSonny Rao 580f95f3850SWill Newton /* Select IDMAC interface */ 581f95f3850SWill Newton temp = mci_readl(host, CTRL); 582f95f3850SWill Newton temp |= SDMMC_CTRL_USE_IDMAC; 583f95f3850SWill Newton mci_writel(host, CTRL, temp); 584f95f3850SWill Newton 5850e3a22c0SShawn Lin /* drain writebuffer */ 586f95f3850SWill Newton wmb(); 587f95f3850SWill Newton 588f95f3850SWill Newton /* Enable the IDMAC */ 589f95f3850SWill Newton temp = mci_readl(host, BMOD); 590a5289a43SJaehoon Chung temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 591f95f3850SWill Newton mci_writel(host, BMOD, temp); 592f95f3850SWill Newton 593f95f3850SWill Newton /* Start it running */ 594f95f3850SWill Newton mci_writel(host, PLDMND, 1); 5953fc7eaefSShawn Lin 5963fc7eaefSShawn Lin return 0; 597f95f3850SWill Newton } 598f95f3850SWill Newton 599f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 600f95f3850SWill Newton { 601897b69e7SSeungwon Jeon int i; 602f95f3850SWill Newton 60369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 60469d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 60569d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 60669d99fdcSPrabu Thangamuthu host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 60769d99fdcSPrabu Thangamuthu 60869d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 60969d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 61069d99fdcSPrabu Thangamuthu i++, p++) { 61169d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 61269d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 61369d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 61469d99fdcSPrabu Thangamuthu 61569d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 61669d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 61769d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 61869d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 61969d99fdcSPrabu Thangamuthu p->des1 = 0; 62069d99fdcSPrabu Thangamuthu p->des2 = 0; 62169d99fdcSPrabu Thangamuthu p->des3 = 0; 62269d99fdcSPrabu Thangamuthu } 62369d99fdcSPrabu Thangamuthu 62469d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 62569d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 62669d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 62769d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 62869d99fdcSPrabu Thangamuthu 62969d99fdcSPrabu Thangamuthu } else { 63069d99fdcSPrabu Thangamuthu struct idmac_desc *p; 631f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 632f95f3850SWill Newton host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 633f95f3850SWill Newton 634f95f3850SWill Newton /* Forward link the descriptor list */ 6350e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 6360e3a22c0SShawn Lin i < host->ring_size - 1; 6370e3a22c0SShawn Lin i++, p++) { 6386687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 6396687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 6404b244724SZhangfei Gao p->des1 = 0; 6414b244724SZhangfei Gao } 642f95f3850SWill Newton 643f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 6446687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 6456687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 64669d99fdcSPrabu Thangamuthu } 647f95f3850SWill Newton 6485ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 649141a712aSSeungwon Jeon 65069d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 65169d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 65269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 65369d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 65469d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 65569d99fdcSPrabu Thangamuthu 65669d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 65769d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 65869d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 65969d99fdcSPrabu Thangamuthu 66069d99fdcSPrabu Thangamuthu } else { 661f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 662fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 66369d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 66469d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 665f95f3850SWill Newton 666f95f3850SWill Newton /* Set the descriptor base address */ 667f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 66869d99fdcSPrabu Thangamuthu } 66969d99fdcSPrabu Thangamuthu 670f95f3850SWill Newton return 0; 671f95f3850SWill Newton } 672f95f3850SWill Newton 6738e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 674885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 675885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 676885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 6773fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 678885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 679885c3e80SSeungwon Jeon }; 6803fc7eaefSShawn Lin 6813fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 6823fc7eaefSShawn Lin { 6833fc7eaefSShawn Lin dmaengine_terminate_all(host->dms->ch); 6843fc7eaefSShawn Lin } 6853fc7eaefSShawn Lin 6863fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 6873fc7eaefSShawn Lin unsigned int sg_len) 6883fc7eaefSShawn Lin { 6893fc7eaefSShawn Lin struct dma_slave_config cfg; 6903fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 6913fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 6923fc7eaefSShawn Lin const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 6933fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 6943fc7eaefSShawn Lin u32 fifoth_val; 6953fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 6963fc7eaefSShawn Lin int ret = 0; 6973fc7eaefSShawn Lin 6983fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 699260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 7003fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 7013fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7023fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 7033fc7eaefSShawn Lin 7043fc7eaefSShawn Lin /* Match burst msize with external dma config */ 7053fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 7063fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 7073fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 7083fc7eaefSShawn Lin 7093fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7103fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 7113fc7eaefSShawn Lin else 7123fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 7133fc7eaefSShawn Lin 7143fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 7153fc7eaefSShawn Lin if (ret) { 7163fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 7173fc7eaefSShawn Lin return -EBUSY; 7183fc7eaefSShawn Lin } 7193fc7eaefSShawn Lin 7203fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 7213fc7eaefSShawn Lin sg_len, cfg.direction, 7223fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 7233fc7eaefSShawn Lin if (!desc) { 7243fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 7253fc7eaefSShawn Lin return -EBUSY; 7263fc7eaefSShawn Lin } 7273fc7eaefSShawn Lin 7283fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 7293fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 7303fc7eaefSShawn Lin desc->callback_param = (void *)host; 7313fc7eaefSShawn Lin dmaengine_submit(desc); 7323fc7eaefSShawn Lin 7333fc7eaefSShawn Lin /* Flush cache before write */ 7343fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 7353fc7eaefSShawn Lin dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 7363fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 7373fc7eaefSShawn Lin 7383fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 7393fc7eaefSShawn Lin 7403fc7eaefSShawn Lin return 0; 7413fc7eaefSShawn Lin } 7423fc7eaefSShawn Lin 7433fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 7443fc7eaefSShawn Lin { 7453fc7eaefSShawn Lin /* Request external dma channel */ 7463fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 7473fc7eaefSShawn Lin if (!host->dms) 7483fc7eaefSShawn Lin return -ENOMEM; 7493fc7eaefSShawn Lin 7503fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 7513fc7eaefSShawn Lin if (!host->dms->ch) { 7524539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 7533fc7eaefSShawn Lin kfree(host->dms); 7543fc7eaefSShawn Lin host->dms = NULL; 7553fc7eaefSShawn Lin return -ENXIO; 7563fc7eaefSShawn Lin } 7573fc7eaefSShawn Lin 7583fc7eaefSShawn Lin return 0; 7593fc7eaefSShawn Lin } 7603fc7eaefSShawn Lin 7613fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 7623fc7eaefSShawn Lin { 7633fc7eaefSShawn Lin if (host->dms) { 7643fc7eaefSShawn Lin if (host->dms->ch) { 7653fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 7663fc7eaefSShawn Lin host->dms->ch = NULL; 7673fc7eaefSShawn Lin } 7683fc7eaefSShawn Lin kfree(host->dms); 7693fc7eaefSShawn Lin host->dms = NULL; 7703fc7eaefSShawn Lin } 7713fc7eaefSShawn Lin } 7723fc7eaefSShawn Lin 7733fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 7743fc7eaefSShawn Lin .init = dw_mci_edmac_init, 7753fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 7763fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 7773fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 7783fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 7793fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 7803fc7eaefSShawn Lin }; 781885c3e80SSeungwon Jeon 7829aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 7839aa51408SSeungwon Jeon struct mmc_data *data, 7849aa51408SSeungwon Jeon bool next) 785f95f3850SWill Newton { 786f95f3850SWill Newton struct scatterlist *sg; 7879aa51408SSeungwon Jeon unsigned int i, sg_len; 788f95f3850SWill Newton 7899aa51408SSeungwon Jeon if (!next && data->host_cookie) 7909aa51408SSeungwon Jeon return data->host_cookie; 791f95f3850SWill Newton 792f95f3850SWill Newton /* 793f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 794f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 795f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 796f95f3850SWill Newton */ 797f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 798f95f3850SWill Newton return -EINVAL; 7999aa51408SSeungwon Jeon 800f95f3850SWill Newton if (data->blksz & 3) 801f95f3850SWill Newton return -EINVAL; 802f95f3850SWill Newton 803f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 804f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 805f95f3850SWill Newton return -EINVAL; 806f95f3850SWill Newton } 807f95f3850SWill Newton 8084a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 8099aa51408SSeungwon Jeon data->sg, 8109aa51408SSeungwon Jeon data->sg_len, 8119aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 8129aa51408SSeungwon Jeon if (sg_len == 0) 8139aa51408SSeungwon Jeon return -EINVAL; 8149aa51408SSeungwon Jeon 8159aa51408SSeungwon Jeon if (next) 8169aa51408SSeungwon Jeon data->host_cookie = sg_len; 8179aa51408SSeungwon Jeon 8189aa51408SSeungwon Jeon return sg_len; 8199aa51408SSeungwon Jeon } 8209aa51408SSeungwon Jeon 8219aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 8229aa51408SSeungwon Jeon struct mmc_request *mrq, 8239aa51408SSeungwon Jeon bool is_first_req) 8249aa51408SSeungwon Jeon { 8259aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 8269aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 8279aa51408SSeungwon Jeon 8289aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 8299aa51408SSeungwon Jeon return; 8309aa51408SSeungwon Jeon 8319aa51408SSeungwon Jeon if (data->host_cookie) { 8329aa51408SSeungwon Jeon data->host_cookie = 0; 8339aa51408SSeungwon Jeon return; 8349aa51408SSeungwon Jeon } 8359aa51408SSeungwon Jeon 8369aa51408SSeungwon Jeon if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 8379aa51408SSeungwon Jeon data->host_cookie = 0; 8389aa51408SSeungwon Jeon } 8399aa51408SSeungwon Jeon 8409aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 8419aa51408SSeungwon Jeon struct mmc_request *mrq, 8429aa51408SSeungwon Jeon int err) 8439aa51408SSeungwon Jeon { 8449aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 8459aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 8469aa51408SSeungwon Jeon 8479aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 8489aa51408SSeungwon Jeon return; 8499aa51408SSeungwon Jeon 8509aa51408SSeungwon Jeon if (data->host_cookie) 8514a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 8529aa51408SSeungwon Jeon data->sg, 8539aa51408SSeungwon Jeon data->sg_len, 8549aa51408SSeungwon Jeon dw_mci_get_dma_dir(data)); 8559aa51408SSeungwon Jeon data->host_cookie = 0; 8569aa51408SSeungwon Jeon } 8579aa51408SSeungwon Jeon 85852426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 85952426899SSeungwon Jeon { 86052426899SSeungwon Jeon unsigned int blksz = data->blksz; 86152426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 86252426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 86352426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 86452426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 8650e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 86652426899SSeungwon Jeon 8673fc7eaefSShawn Lin /* pio should ship this scenario */ 8683fc7eaefSShawn Lin if (!host->use_dma) 8693fc7eaefSShawn Lin return; 8703fc7eaefSShawn Lin 87152426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 87252426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 87352426899SSeungwon Jeon 87452426899SSeungwon Jeon /* 87552426899SSeungwon Jeon * MSIZE is '1', 87652426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 87752426899SSeungwon Jeon */ 87852426899SSeungwon Jeon if (blksz % fifo_width) { 87952426899SSeungwon Jeon msize = 0; 88052426899SSeungwon Jeon rx_wmark = 1; 88152426899SSeungwon Jeon goto done; 88252426899SSeungwon Jeon } 88352426899SSeungwon Jeon 88452426899SSeungwon Jeon do { 88552426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 88652426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 88752426899SSeungwon Jeon msize = idx; 88852426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 88952426899SSeungwon Jeon break; 89052426899SSeungwon Jeon } 89152426899SSeungwon Jeon } while (--idx > 0); 89252426899SSeungwon Jeon /* 89352426899SSeungwon Jeon * If idx is '0', it won't be tried 89452426899SSeungwon Jeon * Thus, initial values are uesed 89552426899SSeungwon Jeon */ 89652426899SSeungwon Jeon done: 89752426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 89852426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 89952426899SSeungwon Jeon } 90052426899SSeungwon Jeon 901f1d2736cSSeungwon Jeon static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 902f1d2736cSSeungwon Jeon { 903f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 904f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 905f1d2736cSSeungwon Jeon u16 thld_size; 906f1d2736cSSeungwon Jeon 907f1d2736cSSeungwon Jeon WARN_ON(!(data->flags & MMC_DATA_READ)); 908f1d2736cSSeungwon Jeon 90966dfd101SJames Hogan /* 91066dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 91166dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 91266dfd101SJames Hogan */ 91366dfd101SJames Hogan if (host->verid < DW_MMC_240A) 91466dfd101SJames Hogan return; 91566dfd101SJames Hogan 916f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 917488b8d63SJaehoon Chung host->timing != MMC_TIMING_MMC_HS400 && 918f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 919f1d2736cSSeungwon Jeon goto disable; 920f1d2736cSSeungwon Jeon 921f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 922f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 923f1d2736cSSeungwon Jeon 924f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 925f1d2736cSSeungwon Jeon goto disable; 926f1d2736cSSeungwon Jeon 927f1d2736cSSeungwon Jeon /* 928f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 929f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 930f1d2736cSSeungwon Jeon * Currently just choose blksz. 931f1d2736cSSeungwon Jeon */ 932f1d2736cSSeungwon Jeon thld_size = blksz; 933f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 934f1d2736cSSeungwon Jeon return; 935f1d2736cSSeungwon Jeon 936f1d2736cSSeungwon Jeon disable: 937f1d2736cSSeungwon Jeon mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 938f1d2736cSSeungwon Jeon } 939f1d2736cSSeungwon Jeon 9409aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 9419aa51408SSeungwon Jeon { 942f8c58c11SDoug Anderson unsigned long irqflags; 9439aa51408SSeungwon Jeon int sg_len; 9449aa51408SSeungwon Jeon u32 temp; 9459aa51408SSeungwon Jeon 9469aa51408SSeungwon Jeon host->using_dma = 0; 9479aa51408SSeungwon Jeon 9489aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 9499aa51408SSeungwon Jeon if (!host->use_dma) 9509aa51408SSeungwon Jeon return -ENODEV; 9519aa51408SSeungwon Jeon 9529aa51408SSeungwon Jeon sg_len = dw_mci_pre_dma_transfer(host, data, 0); 953a99aa9b9SSeungwon Jeon if (sg_len < 0) { 954a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 9559aa51408SSeungwon Jeon return sg_len; 956a99aa9b9SSeungwon Jeon } 9579aa51408SSeungwon Jeon 95803e8cb53SJames Hogan host->using_dma = 1; 95903e8cb53SJames Hogan 9603fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 9614a90920cSThomas Abraham dev_vdbg(host->dev, 962f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 9633fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 9643fc7eaefSShawn Lin (unsigned long)host->sg_dma, 965f95f3850SWill Newton sg_len); 966f95f3850SWill Newton 96752426899SSeungwon Jeon /* 96852426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 96952426899SSeungwon Jeon * If current block size is same with previous size, 97052426899SSeungwon Jeon * no need to update fifoth. 97152426899SSeungwon Jeon */ 97252426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 97352426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 97452426899SSeungwon Jeon 975f95f3850SWill Newton /* Enable the DMA interface */ 976f95f3850SWill Newton temp = mci_readl(host, CTRL); 977f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 978f95f3850SWill Newton mci_writel(host, CTRL, temp); 979f95f3850SWill Newton 980f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 981f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 982f95f3850SWill Newton temp = mci_readl(host, INTMASK); 983f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 984f95f3850SWill Newton mci_writel(host, INTMASK, temp); 985f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 986f95f3850SWill Newton 9873fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 9883fc7eaefSShawn Lin /* We can't do DMA */ 9893fc7eaefSShawn Lin dev_err(host->dev, "%s: failed to start DMA.\n", __func__); 9903fc7eaefSShawn Lin return -ENODEV; 9913fc7eaefSShawn Lin } 992f95f3850SWill Newton 993f95f3850SWill Newton return 0; 994f95f3850SWill Newton } 995f95f3850SWill Newton 996f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 997f95f3850SWill Newton { 998f8c58c11SDoug Anderson unsigned long irqflags; 9990e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1000f95f3850SWill Newton u32 temp; 1001f95f3850SWill Newton 1002f95f3850SWill Newton data->error = -EINPROGRESS; 1003f95f3850SWill Newton 1004f95f3850SWill Newton WARN_ON(host->data); 1005f95f3850SWill Newton host->sg = NULL; 1006f95f3850SWill Newton host->data = data; 1007f95f3850SWill Newton 1008f1d2736cSSeungwon Jeon if (data->flags & MMC_DATA_READ) { 100955c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 1010f1d2736cSSeungwon Jeon dw_mci_ctrl_rd_thld(host, data); 1011f1d2736cSSeungwon Jeon } else { 101255c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 1013f1d2736cSSeungwon Jeon } 101455c5efbcSJames Hogan 1015f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1016f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1017f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1018f9c2a0dcSSeungwon Jeon else 1019f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1020f9c2a0dcSSeungwon Jeon 1021f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1022f95f3850SWill Newton host->sg = data->sg; 102334b664a2SJames Hogan host->part_buf_start = 0; 102434b664a2SJames Hogan host->part_buf_count = 0; 1025f95f3850SWill Newton 1026b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1027f8c58c11SDoug Anderson 1028f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1029f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1030f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1031f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1032f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1033f95f3850SWill Newton 1034f95f3850SWill Newton temp = mci_readl(host, CTRL); 1035f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1036f95f3850SWill Newton mci_writel(host, CTRL, temp); 103752426899SSeungwon Jeon 103852426899SSeungwon Jeon /* 103952426899SSeungwon Jeon * Use the initial fifoth_val for PIO mode. 104052426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 104152426899SSeungwon Jeon * prev_blksz should be invalidated. 104252426899SSeungwon Jeon */ 104352426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 104452426899SSeungwon Jeon host->prev_blksz = 0; 104552426899SSeungwon Jeon } else { 104652426899SSeungwon Jeon /* 104752426899SSeungwon Jeon * Keep the current block size. 104852426899SSeungwon Jeon * It will be used to decide whether to update 104952426899SSeungwon Jeon * fifoth register next time. 105052426899SSeungwon Jeon */ 105152426899SSeungwon Jeon host->prev_blksz = data->blksz; 1052f95f3850SWill Newton } 1053f95f3850SWill Newton } 1054f95f3850SWill Newton 1055f95f3850SWill Newton static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 1056f95f3850SWill Newton { 1057f95f3850SWill Newton struct dw_mci *host = slot->host; 1058f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 1059f95f3850SWill Newton unsigned int cmd_status = 0; 1060f95f3850SWill Newton 1061f95f3850SWill Newton mci_writel(host, CMDARG, arg); 10620e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 10630bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd); 1064f95f3850SWill Newton mci_writel(host, CMD, SDMMC_CMD_START | cmd); 1065f95f3850SWill Newton 1066f95f3850SWill Newton while (time_before(jiffies, timeout)) { 1067f95f3850SWill Newton cmd_status = mci_readl(host, CMD); 1068f95f3850SWill Newton if (!(cmd_status & SDMMC_CMD_START)) 1069f95f3850SWill Newton return; 1070f95f3850SWill Newton } 1071f95f3850SWill Newton dev_err(&slot->mmc->class_dev, 1072f95f3850SWill Newton "Timeout sending command (cmd %#x arg %#x status %#x)\n", 1073f95f3850SWill Newton cmd, arg, cmd_status); 1074f95f3850SWill Newton } 1075f95f3850SWill Newton 1076ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1077f95f3850SWill Newton { 1078f95f3850SWill Newton struct dw_mci *host = slot->host; 1079fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1080f95f3850SWill Newton u32 div; 10819623b5b9SDoug Anderson u32 clk_en_a; 108201730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 108301730558SDoug Anderson 108401730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 108501730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 108601730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1087f95f3850SWill Newton 1088fdf492a1SDoug Anderson if (!clock) { 1089fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 109001730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1091fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1092fdf492a1SDoug Anderson div = host->bus_hz / clock; 1093fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1094f95f3850SWill Newton /* 1095f95f3850SWill Newton * move the + 1 after the divide to prevent 1096f95f3850SWill Newton * over-clocking the card. 1097f95f3850SWill Newton */ 1098e419990bSSeungwon Jeon div += 1; 1099e419990bSSeungwon Jeon 1100fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1101f95f3850SWill Newton 1102fdf492a1SDoug Anderson if ((clock << div) != slot->__clk_old || force_clkinit) 1103f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1104fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1105fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1106fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1107fdf492a1SDoug Anderson host->bus_hz, div); 1108f95f3850SWill Newton 1109f95f3850SWill Newton /* disable clock */ 1110f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1111f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1112f95f3850SWill Newton 1113f95f3850SWill Newton /* inform CIU */ 111401730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1115f95f3850SWill Newton 1116f95f3850SWill Newton /* set clock to desired speed */ 1117f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1118f95f3850SWill Newton 1119f95f3850SWill Newton /* inform CIU */ 112001730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1121f95f3850SWill Newton 11229623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 11239623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1124b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 11259623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 11269623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1127f95f3850SWill Newton 1128f95f3850SWill Newton /* inform CIU */ 112901730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1130f95f3850SWill Newton 1131fdf492a1SDoug Anderson /* keep the clock with reflecting clock dividor */ 1132fdf492a1SDoug Anderson slot->__clk_old = clock << div; 1133f95f3850SWill Newton } 1134f95f3850SWill Newton 1135fdf492a1SDoug Anderson host->current_speed = clock; 1136fdf492a1SDoug Anderson 1137f95f3850SWill Newton /* Set the current slot bus width */ 11381d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1139f95f3850SWill Newton } 1140f95f3850SWill Newton 1141053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1142053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1143053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1144f95f3850SWill Newton { 1145f95f3850SWill Newton struct mmc_request *mrq; 1146f95f3850SWill Newton struct mmc_data *data; 1147f95f3850SWill Newton u32 cmdflags; 1148f95f3850SWill Newton 1149f95f3850SWill Newton mrq = slot->mrq; 1150f95f3850SWill Newton 1151f95f3850SWill Newton host->cur_slot = slot; 1152f95f3850SWill Newton host->mrq = mrq; 1153f95f3850SWill Newton 1154f95f3850SWill Newton host->pending_events = 0; 1155f95f3850SWill Newton host->completed_events = 0; 1156e352c813SSeungwon Jeon host->cmd_status = 0; 1157f95f3850SWill Newton host->data_status = 0; 1158e352c813SSeungwon Jeon host->dir_status = 0; 1159f95f3850SWill Newton 1160053b3ce6SSeungwon Jeon data = cmd->data; 1161f95f3850SWill Newton if (data) { 1162f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1163f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1164f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1165f95f3850SWill Newton } 1166f95f3850SWill Newton 1167f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1168f95f3850SWill Newton 1169f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1170f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1171f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1172f95f3850SWill Newton 1173f95f3850SWill Newton if (data) { 1174f95f3850SWill Newton dw_mci_submit_data(host, data); 11750e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1176f95f3850SWill Newton } 1177f95f3850SWill Newton 1178f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1179f95f3850SWill Newton 11805c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 118149ba0302SDoug Anderson unsigned long irqflags; 118249ba0302SDoug Anderson 11835c935165SDoug Anderson /* 11848886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 11858886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 11868886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 11878886a6fdSDoug Anderson * is just about to roll over. 118849ba0302SDoug Anderson * 118949ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 119049ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 119149ba0302SDoug Anderson * already ran so we don't want the timeout). 11925c935165SDoug Anderson */ 119349ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 119449ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 11955c935165SDoug Anderson mod_timer(&host->cmd11_timer, 11968886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 119749ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 11985c935165SDoug Anderson } 11995c935165SDoug Anderson 1200f95f3850SWill Newton if (mrq->stop) 1201f95f3850SWill Newton host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 120290c2143aSSeungwon Jeon else 120390c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1204f95f3850SWill Newton } 1205f95f3850SWill Newton 1206053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1207053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1208053b3ce6SSeungwon Jeon { 1209053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1210053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1211053b3ce6SSeungwon Jeon 1212053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1213053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1214053b3ce6SSeungwon Jeon } 1215053b3ce6SSeungwon Jeon 12167456caaeSJames Hogan /* must be called with host->lock held */ 1217f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1218f95f3850SWill Newton struct mmc_request *mrq) 1219f95f3850SWill Newton { 1220f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1221f95f3850SWill Newton host->state); 1222f95f3850SWill Newton 1223f95f3850SWill Newton slot->mrq = mrq; 1224f95f3850SWill Newton 122501730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 122601730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 122701730558SDoug Anderson "Voltage change didn't complete\n"); 122801730558SDoug Anderson /* 122901730558SDoug Anderson * this case isn't expected to happen, so we can 123001730558SDoug Anderson * either crash here or just try to continue on 123101730558SDoug Anderson * in the closest possible state 123201730558SDoug Anderson */ 123301730558SDoug Anderson host->state = STATE_IDLE; 123401730558SDoug Anderson } 123501730558SDoug Anderson 1236f95f3850SWill Newton if (host->state == STATE_IDLE) { 1237f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1238f95f3850SWill Newton dw_mci_start_request(host, slot); 1239f95f3850SWill Newton } else { 1240f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1241f95f3850SWill Newton } 1242f95f3850SWill Newton } 1243f95f3850SWill Newton 1244f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1245f95f3850SWill Newton { 1246f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1247f95f3850SWill Newton struct dw_mci *host = slot->host; 1248f95f3850SWill Newton 1249f95f3850SWill Newton WARN_ON(slot->mrq); 1250f95f3850SWill Newton 12517456caaeSJames Hogan /* 12527456caaeSJames Hogan * The check for card presence and queueing of the request must be 12537456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 12547456caaeSJames Hogan * request wouldn't fail until another card was inserted. 12557456caaeSJames Hogan */ 12567456caaeSJames Hogan spin_lock_bh(&host->lock); 12577456caaeSJames Hogan 1258f95f3850SWill Newton if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 12597456caaeSJames Hogan spin_unlock_bh(&host->lock); 1260f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1261f95f3850SWill Newton mmc_request_done(mmc, mrq); 1262f95f3850SWill Newton return; 1263f95f3850SWill Newton } 1264f95f3850SWill Newton 1265f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 12667456caaeSJames Hogan 12677456caaeSJames Hogan spin_unlock_bh(&host->lock); 1268f95f3850SWill Newton } 1269f95f3850SWill Newton 1270f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1271f95f3850SWill Newton { 1272f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1273e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 127441babf75SJaehoon Chung u32 regs; 127551da2240SYuvaraj CD int ret; 1276f95f3850SWill Newton 1277f95f3850SWill Newton switch (ios->bus_width) { 1278f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1279f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1280f95f3850SWill Newton break; 1281c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1282c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1283c9b2a06fSJaehoon Chung break; 1284b2f7cb45SJaehoon Chung default: 1285b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1286b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1287f95f3850SWill Newton } 1288f95f3850SWill Newton 128941babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 12903f514291SSeungwon Jeon 12913f514291SSeungwon Jeon /* DDR mode set */ 129280113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 12937cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 129480113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1295c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 12963f514291SSeungwon Jeon else 1297c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 12983f514291SSeungwon Jeon 129941babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1300f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 130141babf75SJaehoon Chung 1302f95f3850SWill Newton /* 1303f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1304f95f3850SWill Newton * core ios update when finding the minimum. 1305f95f3850SWill Newton */ 1306f95f3850SWill Newton slot->clock = ios->clock; 1307f95f3850SWill Newton 1308cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1309cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1310800d78bfSThomas Abraham 1311f95f3850SWill Newton switch (ios->power_mode) { 1312f95f3850SWill Newton case MMC_POWER_UP: 131351da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 131451da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 131551da2240SYuvaraj CD ios->vdd); 131651da2240SYuvaraj CD if (ret) { 131751da2240SYuvaraj CD dev_err(slot->host->dev, 131851da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 131951da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 132051da2240SYuvaraj CD return; 132151da2240SYuvaraj CD } 132251da2240SYuvaraj CD } 132329d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 132429d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 132529d0d161SDoug Anderson regs |= (1 << slot->id); 132629d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 132729d0d161SDoug Anderson break; 132829d0d161SDoug Anderson case MMC_POWER_ON: 1329d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1330d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 133151da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 133251da2240SYuvaraj CD if (ret < 0) 133351da2240SYuvaraj CD dev_err(slot->host->dev, 1334d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 133551da2240SYuvaraj CD else 133651da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1337d1f1dd86SDoug Anderson 1338d1f1dd86SDoug Anderson } else { 1339d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1340d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1341d1f1dd86SDoug Anderson } 1342d1f1dd86SDoug Anderson 1343d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1344d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1345d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 134651da2240SYuvaraj CD } 1347655babbdSDoug Anderson 1348655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1349655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1350655babbdSDoug Anderson 1351e6f34e2fSJames Hogan break; 1352e6f34e2fSJames Hogan case MMC_POWER_OFF: 1353655babbdSDoug Anderson /* Turn clock off before power goes down */ 1354655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1355655babbdSDoug Anderson 135651da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 135751da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 135851da2240SYuvaraj CD 1359d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 136051da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 136151da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 136251da2240SYuvaraj CD 13634366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 13644366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 13654366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1366f95f3850SWill Newton break; 1367f95f3850SWill Newton default: 1368f95f3850SWill Newton break; 1369f95f3850SWill Newton } 1370655babbdSDoug Anderson 1371655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1372655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1373f95f3850SWill Newton } 1374f95f3850SWill Newton 137501730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 137601730558SDoug Anderson { 137701730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 137801730558SDoug Anderson u32 status; 137901730558SDoug Anderson 138001730558SDoug Anderson /* 138101730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 138201730558SDoug Anderson * (the data lines) are 0000 138301730558SDoug Anderson */ 138401730558SDoug Anderson status = mci_readl(slot->host, STATUS); 138501730558SDoug Anderson 138601730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 138701730558SDoug Anderson } 138801730558SDoug Anderson 138901730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 139001730558SDoug Anderson { 139101730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 139201730558SDoug Anderson struct dw_mci *host = slot->host; 13938f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 139401730558SDoug Anderson u32 uhs; 139501730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 139601730558SDoug Anderson int ret; 139701730558SDoug Anderson 13988f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 13998f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 14008f7849c4SZhangfei Gao 140101730558SDoug Anderson /* 140201730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 140301730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 140401730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 140501730558SDoug Anderson */ 140601730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1407e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 140801730558SDoug Anderson uhs &= ~v18; 1409e0848f5dSDouglas Anderson else 141001730558SDoug Anderson uhs |= v18; 1411e0848f5dSDouglas Anderson 141201730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1413e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 141401730558SDoug Anderson 141501730558SDoug Anderson if (ret) { 1416b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1417e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1418e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 141901730558SDoug Anderson return ret; 142001730558SDoug Anderson } 142101730558SDoug Anderson } 142201730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 142301730558SDoug Anderson 142401730558SDoug Anderson return 0; 142501730558SDoug Anderson } 142601730558SDoug Anderson 1427f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1428f95f3850SWill Newton { 1429f95f3850SWill Newton int read_only; 1430f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 14319795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1432f95f3850SWill Newton 1433f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1434eff8f2f5SLars-Peter Clausen if (!IS_ERR_VALUE(gpio_ro)) 14359795a846SJaehoon Chung read_only = gpio_ro; 1436f95f3850SWill Newton else 1437f95f3850SWill Newton read_only = 1438f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1439f95f3850SWill Newton 1440f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1441f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1442f95f3850SWill Newton 1443f95f3850SWill Newton return read_only; 1444f95f3850SWill Newton } 1445f95f3850SWill Newton 1446f95f3850SWill Newton static int dw_mci_get_cd(struct mmc_host *mmc) 1447f95f3850SWill Newton { 1448f95f3850SWill Newton int present; 1449f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 14507cf347bdSZhangfei Gao struct dw_mci *host = slot->host; 14517cf347bdSZhangfei Gao int gpio_cd = mmc_gpio_get_cd(mmc); 1452f95f3850SWill Newton 1453f95f3850SWill Newton /* Use platform get_cd function, else try onboard card detect */ 1454e8cc37b8SShawn Lin if ((mmc->caps & MMC_CAP_NEEDS_POLL) || 14554de3bf66SZhangfei Gao (mmc->caps & MMC_CAP_NONREMOVABLE)) 1456fc3d7720SJaehoon Chung present = 1; 1457bf626e55SZhangfei Gao else if (!IS_ERR_VALUE(gpio_cd)) 14587cf347bdSZhangfei Gao present = gpio_cd; 1459f95f3850SWill Newton else 1460f95f3850SWill Newton present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1461f95f3850SWill Newton == 0 ? 1 : 0; 1462f95f3850SWill Newton 14637cf347bdSZhangfei Gao spin_lock_bh(&host->lock); 1464bf626e55SZhangfei Gao if (present) { 1465bf626e55SZhangfei Gao set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1466f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is present\n"); 1467bf626e55SZhangfei Gao } else { 1468bf626e55SZhangfei Gao clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1469f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is not present\n"); 1470bf626e55SZhangfei Gao } 14717cf347bdSZhangfei Gao spin_unlock_bh(&host->lock); 1472f95f3850SWill Newton 1473f95f3850SWill Newton return present; 1474f95f3850SWill Newton } 1475f95f3850SWill Newton 1476935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1477935a665eSShawn Lin { 1478935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1479935a665eSShawn Lin struct dw_mci *host = slot->host; 1480935a665eSShawn Lin int reset; 1481935a665eSShawn Lin 1482935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1483935a665eSShawn Lin dw_mci_idmac_reset(host); 1484935a665eSShawn Lin 1485935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1486935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1487935a665eSShawn Lin return; 1488935a665eSShawn Lin 1489935a665eSShawn Lin /* 1490935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1491935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1492935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1493935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1494935a665eSShawn Lin */ 1495935a665eSShawn Lin reset = mci_readl(host, RST_N); 1496935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1497935a665eSShawn Lin mci_writel(host, RST_N, reset); 1498935a665eSShawn Lin usleep_range(1, 2); 1499935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1500935a665eSShawn Lin mci_writel(host, RST_N, reset); 1501935a665eSShawn Lin usleep_range(200, 300); 1502935a665eSShawn Lin } 1503935a665eSShawn Lin 1504b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1505b24c8b26SDoug Anderson { 1506b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1507b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1508b24c8b26SDoug Anderson 15099623b5b9SDoug Anderson /* 15109623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 15119623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 15129623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 15139623b5b9SDoug Anderson */ 1514b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 15159623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1516b24c8b26SDoug Anderson u32 clk_en_a_old; 1517b24c8b26SDoug Anderson u32 clk_en_a; 15189623b5b9SDoug Anderson 1519b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 15209623b5b9SDoug Anderson 1521b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1522b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1523b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1524b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1525b24c8b26SDoug Anderson } else { 1526b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1527b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1528b24c8b26SDoug Anderson } 1529b24c8b26SDoug Anderson 1530b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1531b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 15329623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 15339623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 15349623b5b9SDoug Anderson } 15359623b5b9SDoug Anderson } 1536b24c8b26SDoug Anderson } 15379623b5b9SDoug Anderson 15381a5c8e1fSShashidhar Hiremath static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 15391a5c8e1fSShashidhar Hiremath { 15401a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = mmc_priv(mmc); 15411a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1542f8c58c11SDoug Anderson unsigned long irqflags; 15431a5c8e1fSShashidhar Hiremath u32 int_mask; 15441a5c8e1fSShashidhar Hiremath 1545f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1546f8c58c11SDoug Anderson 15471a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 15481a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1549b24c8b26SDoug Anderson if (enb) 1550b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1551b24c8b26SDoug Anderson else 1552b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1553b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1554f8c58c11SDoug Anderson 1555f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 15561a5c8e1fSShashidhar Hiremath } 15571a5c8e1fSShashidhar Hiremath 15580976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 15590976f16dSSeungwon Jeon { 15600976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 15610976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 15620976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 15630e3a22c0SShawn Lin int err = -EINVAL; 15640976f16dSSeungwon Jeon 15650976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 15669979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 15670976f16dSSeungwon Jeon return err; 15680976f16dSSeungwon Jeon } 15690976f16dSSeungwon Jeon 15700e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 15710e3a22c0SShawn Lin struct mmc_ios *ios) 157280113132SSeungwon Jeon { 157380113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 157480113132SSeungwon Jeon struct dw_mci *host = slot->host; 157580113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 157680113132SSeungwon Jeon 157780113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 157880113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 157980113132SSeungwon Jeon 158080113132SSeungwon Jeon return 0; 158180113132SSeungwon Jeon } 158280113132SSeungwon Jeon 1583f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1584f95f3850SWill Newton .request = dw_mci_request, 15859aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 15869aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1587f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1588f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1589f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1590935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 15911a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 15920976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 159301730558SDoug Anderson .card_busy = dw_mci_card_busy, 159401730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1595b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 159680113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1597f95f3850SWill Newton }; 1598f95f3850SWill Newton 1599f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1600f95f3850SWill Newton __releases(&host->lock) 1601f95f3850SWill Newton __acquires(&host->lock) 1602f95f3850SWill Newton { 1603f95f3850SWill Newton struct dw_mci_slot *slot; 1604f95f3850SWill Newton struct mmc_host *prev_mmc = host->cur_slot->mmc; 1605f95f3850SWill Newton 1606f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1607f95f3850SWill Newton 1608f95f3850SWill Newton host->cur_slot->mrq = NULL; 1609f95f3850SWill Newton host->mrq = NULL; 1610f95f3850SWill Newton if (!list_empty(&host->queue)) { 1611f95f3850SWill Newton slot = list_entry(host->queue.next, 1612f95f3850SWill Newton struct dw_mci_slot, queue_node); 1613f95f3850SWill Newton list_del(&slot->queue_node); 16144a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1615f95f3850SWill Newton mmc_hostname(slot->mmc)); 1616f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1617f95f3850SWill Newton dw_mci_start_request(host, slot); 1618f95f3850SWill Newton } else { 16194a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 162001730558SDoug Anderson 162101730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 162201730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 162301730558SDoug Anderson else 1624f95f3850SWill Newton host->state = STATE_IDLE; 1625f95f3850SWill Newton } 1626f95f3850SWill Newton 1627f95f3850SWill Newton spin_unlock(&host->lock); 1628f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1629f95f3850SWill Newton spin_lock(&host->lock); 1630f95f3850SWill Newton } 1631f95f3850SWill Newton 1632e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1633f95f3850SWill Newton { 1634f95f3850SWill Newton u32 status = host->cmd_status; 1635f95f3850SWill Newton 1636f95f3850SWill Newton host->cmd_status = 0; 1637f95f3850SWill Newton 1638f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1639f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1640f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1641f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1642f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1643f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1644f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1645f95f3850SWill Newton } else { 1646f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1647f95f3850SWill Newton cmd->resp[1] = 0; 1648f95f3850SWill Newton cmd->resp[2] = 0; 1649f95f3850SWill Newton cmd->resp[3] = 0; 1650f95f3850SWill Newton } 1651f95f3850SWill Newton } 1652f95f3850SWill Newton 1653f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1654f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1655f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1656f95f3850SWill Newton cmd->error = -EILSEQ; 1657f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1658f95f3850SWill Newton cmd->error = -EIO; 1659f95f3850SWill Newton else 1660f95f3850SWill Newton cmd->error = 0; 1661f95f3850SWill Newton 1662e352c813SSeungwon Jeon return cmd->error; 1663e352c813SSeungwon Jeon } 1664e352c813SSeungwon Jeon 1665e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1666e352c813SSeungwon Jeon { 166731bff450SSeungwon Jeon u32 status = host->data_status; 1668e352c813SSeungwon Jeon 1669e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1670e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1671e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1672e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1673e352c813SSeungwon Jeon data->error = -EILSEQ; 1674e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1675e352c813SSeungwon Jeon if (host->dir_status == 1676e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1677e352c813SSeungwon Jeon /* 1678e352c813SSeungwon Jeon * No data CRC status was returned. 1679e352c813SSeungwon Jeon * The number of bytes transferred 1680e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1681e352c813SSeungwon Jeon */ 1682e352c813SSeungwon Jeon data->bytes_xfered = 0; 1683e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1684e352c813SSeungwon Jeon } else if (host->dir_status == 1685e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1686e352c813SSeungwon Jeon data->error = -EIO; 1687e352c813SSeungwon Jeon } 1688e352c813SSeungwon Jeon } else { 1689e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1690e352c813SSeungwon Jeon data->error = -EIO; 1691e352c813SSeungwon Jeon } 1692e352c813SSeungwon Jeon 1693e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1694e352c813SSeungwon Jeon 1695e352c813SSeungwon Jeon /* 1696e352c813SSeungwon Jeon * After an error, there may be data lingering 169731bff450SSeungwon Jeon * in the FIFO 1698e352c813SSeungwon Jeon */ 16993a33a94cSSonny Rao dw_mci_reset(host); 1700e352c813SSeungwon Jeon } else { 1701e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1702e352c813SSeungwon Jeon data->error = 0; 1703e352c813SSeungwon Jeon } 1704e352c813SSeungwon Jeon 1705e352c813SSeungwon Jeon return data->error; 1706f95f3850SWill Newton } 1707f95f3850SWill Newton 170857e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 170957e10486SAddy Ke { 171057e10486SAddy Ke unsigned int drto_clks; 171157e10486SAddy Ke unsigned int drto_ms; 171257e10486SAddy Ke 171357e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 171457e10486SAddy Ke drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 171557e10486SAddy Ke 171657e10486SAddy Ke /* add a bit spare time */ 171757e10486SAddy Ke drto_ms += 10; 171857e10486SAddy Ke 171957e10486SAddy Ke mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 172057e10486SAddy Ke } 172157e10486SAddy Ke 1722f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1723f95f3850SWill Newton { 1724f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1725f95f3850SWill Newton struct mmc_data *data; 1726f95f3850SWill Newton struct mmc_command *cmd; 1727e352c813SSeungwon Jeon struct mmc_request *mrq; 1728f95f3850SWill Newton enum dw_mci_state state; 1729f95f3850SWill Newton enum dw_mci_state prev_state; 1730e352c813SSeungwon Jeon unsigned int err; 1731f95f3850SWill Newton 1732f95f3850SWill Newton spin_lock(&host->lock); 1733f95f3850SWill Newton 1734f95f3850SWill Newton state = host->state; 1735f95f3850SWill Newton data = host->data; 1736e352c813SSeungwon Jeon mrq = host->mrq; 1737f95f3850SWill Newton 1738f95f3850SWill Newton do { 1739f95f3850SWill Newton prev_state = state; 1740f95f3850SWill Newton 1741f95f3850SWill Newton switch (state) { 1742f95f3850SWill Newton case STATE_IDLE: 174301730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1744f95f3850SWill Newton break; 1745f95f3850SWill Newton 174601730558SDoug Anderson case STATE_SENDING_CMD11: 1747f95f3850SWill Newton case STATE_SENDING_CMD: 1748f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1749f95f3850SWill Newton &host->pending_events)) 1750f95f3850SWill Newton break; 1751f95f3850SWill Newton 1752f95f3850SWill Newton cmd = host->cmd; 1753f95f3850SWill Newton host->cmd = NULL; 1754f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1755e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1756e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1757053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 1758053b3ce6SSeungwon Jeon __dw_mci_start_request(host, host->cur_slot, 1759e352c813SSeungwon Jeon mrq->cmd); 1760053b3ce6SSeungwon Jeon goto unlock; 1761053b3ce6SSeungwon Jeon } 1762053b3ce6SSeungwon Jeon 1763e352c813SSeungwon Jeon if (cmd->data && err) { 176471abb133SSeungwon Jeon dw_mci_stop_dma(host); 176590c2143aSSeungwon Jeon send_stop_abort(host, data); 176671abb133SSeungwon Jeon state = STATE_SENDING_STOP; 176771abb133SSeungwon Jeon break; 176871abb133SSeungwon Jeon } 176971abb133SSeungwon Jeon 1770e352c813SSeungwon Jeon if (!cmd->data || err) { 1771e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1772f95f3850SWill Newton goto unlock; 1773f95f3850SWill Newton } 1774f95f3850SWill Newton 1775f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 1776f95f3850SWill Newton /* fall through */ 1777f95f3850SWill Newton 1778f95f3850SWill Newton case STATE_SENDING_DATA: 17792aa35465SDoug Anderson /* 17802aa35465SDoug Anderson * We could get a data error and never a transfer 17812aa35465SDoug Anderson * complete so we'd better check for it here. 17822aa35465SDoug Anderson * 17832aa35465SDoug Anderson * Note that we don't really care if we also got a 17842aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 17852aa35465SDoug Anderson * abort won't hurt. 17862aa35465SDoug Anderson */ 1787f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 1788f95f3850SWill Newton &host->pending_events)) { 1789f95f3850SWill Newton dw_mci_stop_dma(host); 1790bdb9a90bSaddy ke if (data->stop || 1791bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1792bdb9a90bSaddy ke SDMMC_INT_EBE))) 179390c2143aSSeungwon Jeon send_stop_abort(host, data); 1794f95f3850SWill Newton state = STATE_DATA_ERROR; 1795f95f3850SWill Newton break; 1796f95f3850SWill Newton } 1797f95f3850SWill Newton 1798f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 179957e10486SAddy Ke &host->pending_events)) { 180057e10486SAddy Ke /* 180157e10486SAddy Ke * If all data-related interrupts don't come 180257e10486SAddy Ke * within the given time in reading data state. 180357e10486SAddy Ke */ 180457e10486SAddy Ke if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 180557e10486SAddy Ke (host->dir_status == DW_MCI_RECV_STATUS)) 180657e10486SAddy Ke dw_mci_set_drto(host); 1807f95f3850SWill Newton break; 180857e10486SAddy Ke } 1809f95f3850SWill Newton 1810f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 18112aa35465SDoug Anderson 18122aa35465SDoug Anderson /* 18132aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 18142aa35465SDoug Anderson * before the transfer completed. This might not have 18152aa35465SDoug Anderson * been caught by the check above because the interrupt 18162aa35465SDoug Anderson * could have gone off between the previous check and 18172aa35465SDoug Anderson * the check for transfer complete. 18182aa35465SDoug Anderson * 18192aa35465SDoug Anderson * Technically this ought not be needed assuming we 18202aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 18212aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 18222aa35465SDoug Anderson * 18232aa35465SDoug Anderson * This has the advantage of sending the stop command. 18242aa35465SDoug Anderson */ 18252aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 18262aa35465SDoug Anderson &host->pending_events)) { 18272aa35465SDoug Anderson dw_mci_stop_dma(host); 1828bdb9a90bSaddy ke if (data->stop || 1829bdb9a90bSaddy ke !(host->data_status & (SDMMC_INT_DRTO | 1830bdb9a90bSaddy ke SDMMC_INT_EBE))) 18312aa35465SDoug Anderson send_stop_abort(host, data); 18322aa35465SDoug Anderson state = STATE_DATA_ERROR; 18332aa35465SDoug Anderson break; 18342aa35465SDoug Anderson } 1835f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 18362aa35465SDoug Anderson 1837f95f3850SWill Newton /* fall through */ 1838f95f3850SWill Newton 1839f95f3850SWill Newton case STATE_DATA_BUSY: 1840f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 184157e10486SAddy Ke &host->pending_events)) { 184257e10486SAddy Ke /* 184357e10486SAddy Ke * If data error interrupt comes but data over 184457e10486SAddy Ke * interrupt doesn't come within the given time. 184557e10486SAddy Ke * in reading data state. 184657e10486SAddy Ke */ 184757e10486SAddy Ke if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 184857e10486SAddy Ke (host->dir_status == DW_MCI_RECV_STATUS)) 184957e10486SAddy Ke dw_mci_set_drto(host); 1850f95f3850SWill Newton break; 185157e10486SAddy Ke } 1852f95f3850SWill Newton 1853f95f3850SWill Newton host->data = NULL; 1854f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1855e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 1856f95f3850SWill Newton 1857e352c813SSeungwon Jeon if (!err) { 1858e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 185917c8bc85SSachin Kamat if (mrq->sbc && data->stop) 1860053b3ce6SSeungwon Jeon data->stop->error = 0; 1861e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1862053b3ce6SSeungwon Jeon goto unlock; 1863053b3ce6SSeungwon Jeon } 1864053b3ce6SSeungwon Jeon 186590c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 1866e352c813SSeungwon Jeon if (data->stop) 186790c2143aSSeungwon Jeon send_stop_abort(host, data); 18682aa35465SDoug Anderson } else { 18692aa35465SDoug Anderson /* 18702aa35465SDoug Anderson * If we don't have a command complete now we'll 18712aa35465SDoug Anderson * never get one since we just reset everything; 18722aa35465SDoug Anderson * better end the request. 18732aa35465SDoug Anderson * 18742aa35465SDoug Anderson * If we do have a command complete we'll fall 18752aa35465SDoug Anderson * through to the SENDING_STOP command and 18762aa35465SDoug Anderson * everything will be peachy keen. 18772aa35465SDoug Anderson */ 18782aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 18792aa35465SDoug Anderson &host->pending_events)) { 18802aa35465SDoug Anderson host->cmd = NULL; 18812aa35465SDoug Anderson dw_mci_request_end(host, mrq); 18822aa35465SDoug Anderson goto unlock; 18832aa35465SDoug Anderson } 188490c2143aSSeungwon Jeon } 1885e352c813SSeungwon Jeon 1886e352c813SSeungwon Jeon /* 1887e352c813SSeungwon Jeon * If err has non-zero, 1888e352c813SSeungwon Jeon * stop-abort command has been already issued. 1889e352c813SSeungwon Jeon */ 1890e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 1891e352c813SSeungwon Jeon 1892f95f3850SWill Newton /* fall through */ 1893f95f3850SWill Newton 1894f95f3850SWill Newton case STATE_SENDING_STOP: 1895f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1896f95f3850SWill Newton &host->pending_events)) 1897f95f3850SWill Newton break; 1898f95f3850SWill Newton 189971abb133SSeungwon Jeon /* CMD error in data command */ 190031bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 19013a33a94cSSonny Rao dw_mci_reset(host); 190271abb133SSeungwon Jeon 1903f95f3850SWill Newton host->cmd = NULL; 190471abb133SSeungwon Jeon host->data = NULL; 190590c2143aSSeungwon Jeon 1906e352c813SSeungwon Jeon if (mrq->stop) 1907e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 190890c2143aSSeungwon Jeon else 190990c2143aSSeungwon Jeon host->cmd_status = 0; 191090c2143aSSeungwon Jeon 1911e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 1912f95f3850SWill Newton goto unlock; 1913f95f3850SWill Newton 1914f95f3850SWill Newton case STATE_DATA_ERROR: 1915f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1916f95f3850SWill Newton &host->pending_events)) 1917f95f3850SWill Newton break; 1918f95f3850SWill Newton 1919f95f3850SWill Newton state = STATE_DATA_BUSY; 1920f95f3850SWill Newton break; 1921f95f3850SWill Newton } 1922f95f3850SWill Newton } while (state != prev_state); 1923f95f3850SWill Newton 1924f95f3850SWill Newton host->state = state; 1925f95f3850SWill Newton unlock: 1926f95f3850SWill Newton spin_unlock(&host->lock); 1927f95f3850SWill Newton 1928f95f3850SWill Newton } 1929f95f3850SWill Newton 193034b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 193134b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 193234b664a2SJames Hogan { 193334b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 193434b664a2SJames Hogan host->part_buf_count = cnt; 193534b664a2SJames Hogan } 193634b664a2SJames Hogan 193734b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 193834b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 193934b664a2SJames Hogan { 194034b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 194134b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 194234b664a2SJames Hogan host->part_buf_count += cnt; 194334b664a2SJames Hogan return cnt; 194434b664a2SJames Hogan } 194534b664a2SJames Hogan 194634b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 194734b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 194834b664a2SJames Hogan { 19490e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 195034b664a2SJames Hogan if (cnt) { 195134b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 195234b664a2SJames Hogan cnt); 195334b664a2SJames Hogan host->part_buf_count -= cnt; 195434b664a2SJames Hogan host->part_buf_start += cnt; 195534b664a2SJames Hogan } 195634b664a2SJames Hogan return cnt; 195734b664a2SJames Hogan } 195834b664a2SJames Hogan 195934b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 196034b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 196134b664a2SJames Hogan { 196234b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 196334b664a2SJames Hogan host->part_buf_start = cnt; 196434b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 196534b664a2SJames Hogan } 196634b664a2SJames Hogan 1967f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1968f95f3850SWill Newton { 1969cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 1970cfbeb59cSMarkos Chandras int init_cnt = cnt; 1971cfbeb59cSMarkos Chandras 197234b664a2SJames Hogan /* try and push anything in the part_buf */ 197334b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 197434b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 19750e3a22c0SShawn Lin 197634b664a2SJames Hogan buf += len; 197734b664a2SJames Hogan cnt -= len; 1978cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 197976184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 198034b664a2SJames Hogan host->part_buf_count = 0; 198134b664a2SJames Hogan } 198234b664a2SJames Hogan } 198334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 198434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 198534b664a2SJames Hogan while (cnt >= 2) { 198634b664a2SJames Hogan u16 aligned_buf[64]; 198734b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 198834b664a2SJames Hogan int items = len >> 1; 198934b664a2SJames Hogan int i; 199034b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 199134b664a2SJames Hogan memcpy(aligned_buf, buf, len); 199234b664a2SJames Hogan buf += len; 199334b664a2SJames Hogan cnt -= len; 199434b664a2SJames Hogan /* push data from aligned buffer into fifo */ 199534b664a2SJames Hogan for (i = 0; i < items; ++i) 199676184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 199734b664a2SJames Hogan } 199834b664a2SJames Hogan } else 199934b664a2SJames Hogan #endif 200034b664a2SJames Hogan { 200134b664a2SJames Hogan u16 *pdata = buf; 20020e3a22c0SShawn Lin 200334b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 200476184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 200534b664a2SJames Hogan buf = pdata; 200634b664a2SJames Hogan } 200734b664a2SJames Hogan /* put anything remaining in the part_buf */ 200834b664a2SJames Hogan if (cnt) { 200934b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2010cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2011cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2012cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 201376184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2014f95f3850SWill Newton } 2015f95f3850SWill Newton } 2016f95f3850SWill Newton 2017f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2018f95f3850SWill Newton { 201934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 202034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 202134b664a2SJames Hogan while (cnt >= 2) { 202234b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 202334b664a2SJames Hogan u16 aligned_buf[64]; 202434b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 202534b664a2SJames Hogan int items = len >> 1; 202634b664a2SJames Hogan int i; 20270e3a22c0SShawn Lin 202834b664a2SJames Hogan for (i = 0; i < items; ++i) 202976184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 203034b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 203134b664a2SJames Hogan memcpy(buf, aligned_buf, len); 203234b664a2SJames Hogan buf += len; 203334b664a2SJames Hogan cnt -= len; 203434b664a2SJames Hogan } 203534b664a2SJames Hogan } else 203634b664a2SJames Hogan #endif 203734b664a2SJames Hogan { 203834b664a2SJames Hogan u16 *pdata = buf; 20390e3a22c0SShawn Lin 204034b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 204176184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 204234b664a2SJames Hogan buf = pdata; 204334b664a2SJames Hogan } 204434b664a2SJames Hogan if (cnt) { 204576184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 204634b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2047f95f3850SWill Newton } 2048f95f3850SWill Newton } 2049f95f3850SWill Newton 2050f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2051f95f3850SWill Newton { 2052cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2053cfbeb59cSMarkos Chandras int init_cnt = cnt; 2054cfbeb59cSMarkos Chandras 205534b664a2SJames Hogan /* try and push anything in the part_buf */ 205634b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 205734b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 20580e3a22c0SShawn Lin 205934b664a2SJames Hogan buf += len; 206034b664a2SJames Hogan cnt -= len; 2061cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 206276184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 206334b664a2SJames Hogan host->part_buf_count = 0; 206434b664a2SJames Hogan } 206534b664a2SJames Hogan } 206634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 206734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 206834b664a2SJames Hogan while (cnt >= 4) { 206934b664a2SJames Hogan u32 aligned_buf[32]; 207034b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 207134b664a2SJames Hogan int items = len >> 2; 207234b664a2SJames Hogan int i; 207334b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 207434b664a2SJames Hogan memcpy(aligned_buf, buf, len); 207534b664a2SJames Hogan buf += len; 207634b664a2SJames Hogan cnt -= len; 207734b664a2SJames Hogan /* push data from aligned buffer into fifo */ 207834b664a2SJames Hogan for (i = 0; i < items; ++i) 207976184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 208034b664a2SJames Hogan } 208134b664a2SJames Hogan } else 208234b664a2SJames Hogan #endif 208334b664a2SJames Hogan { 208434b664a2SJames Hogan u32 *pdata = buf; 20850e3a22c0SShawn Lin 208634b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 208776184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 208834b664a2SJames Hogan buf = pdata; 208934b664a2SJames Hogan } 209034b664a2SJames Hogan /* put anything remaining in the part_buf */ 209134b664a2SJames Hogan if (cnt) { 209234b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2093cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2094cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2095cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 209676184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2097f95f3850SWill Newton } 2098f95f3850SWill Newton } 2099f95f3850SWill Newton 2100f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2101f95f3850SWill Newton { 210234b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 210334b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 210434b664a2SJames Hogan while (cnt >= 4) { 210534b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 210634b664a2SJames Hogan u32 aligned_buf[32]; 210734b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 210834b664a2SJames Hogan int items = len >> 2; 210934b664a2SJames Hogan int i; 21100e3a22c0SShawn Lin 211134b664a2SJames Hogan for (i = 0; i < items; ++i) 211276184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 211334b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 211434b664a2SJames Hogan memcpy(buf, aligned_buf, len); 211534b664a2SJames Hogan buf += len; 211634b664a2SJames Hogan cnt -= len; 211734b664a2SJames Hogan } 211834b664a2SJames Hogan } else 211934b664a2SJames Hogan #endif 212034b664a2SJames Hogan { 212134b664a2SJames Hogan u32 *pdata = buf; 21220e3a22c0SShawn Lin 212334b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 212476184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 212534b664a2SJames Hogan buf = pdata; 212634b664a2SJames Hogan } 212734b664a2SJames Hogan if (cnt) { 212876184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 212934b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2130f95f3850SWill Newton } 2131f95f3850SWill Newton } 2132f95f3850SWill Newton 2133f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2134f95f3850SWill Newton { 2135cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2136cfbeb59cSMarkos Chandras int init_cnt = cnt; 2137cfbeb59cSMarkos Chandras 213834b664a2SJames Hogan /* try and push anything in the part_buf */ 213934b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 214034b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 21410e3a22c0SShawn Lin 214234b664a2SJames Hogan buf += len; 214334b664a2SJames Hogan cnt -= len; 2144c09fbd74SSeungwon Jeon 2145cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 214676184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 214734b664a2SJames Hogan host->part_buf_count = 0; 214834b664a2SJames Hogan } 214934b664a2SJames Hogan } 215034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 215134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 215234b664a2SJames Hogan while (cnt >= 8) { 215334b664a2SJames Hogan u64 aligned_buf[16]; 215434b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 215534b664a2SJames Hogan int items = len >> 3; 215634b664a2SJames Hogan int i; 215734b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 215834b664a2SJames Hogan memcpy(aligned_buf, buf, len); 215934b664a2SJames Hogan buf += len; 216034b664a2SJames Hogan cnt -= len; 216134b664a2SJames Hogan /* push data from aligned buffer into fifo */ 216234b664a2SJames Hogan for (i = 0; i < items; ++i) 216376184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 216434b664a2SJames Hogan } 216534b664a2SJames Hogan } else 216634b664a2SJames Hogan #endif 216734b664a2SJames Hogan { 216834b664a2SJames Hogan u64 *pdata = buf; 21690e3a22c0SShawn Lin 217034b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 217176184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 217234b664a2SJames Hogan buf = pdata; 217334b664a2SJames Hogan } 217434b664a2SJames Hogan /* put anything remaining in the part_buf */ 217534b664a2SJames Hogan if (cnt) { 217634b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2177cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2178cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2179cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 218076184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2181f95f3850SWill Newton } 2182f95f3850SWill Newton } 2183f95f3850SWill Newton 2184f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2185f95f3850SWill Newton { 218634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 218734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 218834b664a2SJames Hogan while (cnt >= 8) { 218934b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 219034b664a2SJames Hogan u64 aligned_buf[16]; 219134b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 219234b664a2SJames Hogan int items = len >> 3; 219334b664a2SJames Hogan int i; 21940e3a22c0SShawn Lin 219534b664a2SJames Hogan for (i = 0; i < items; ++i) 219676184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 219776184ac1SBen Dooks 219834b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 219934b664a2SJames Hogan memcpy(buf, aligned_buf, len); 220034b664a2SJames Hogan buf += len; 220134b664a2SJames Hogan cnt -= len; 2202f95f3850SWill Newton } 220334b664a2SJames Hogan } else 220434b664a2SJames Hogan #endif 220534b664a2SJames Hogan { 220634b664a2SJames Hogan u64 *pdata = buf; 22070e3a22c0SShawn Lin 220834b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 220976184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 221034b664a2SJames Hogan buf = pdata; 221134b664a2SJames Hogan } 221234b664a2SJames Hogan if (cnt) { 221376184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 221434b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 221534b664a2SJames Hogan } 221634b664a2SJames Hogan } 221734b664a2SJames Hogan 221834b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 221934b664a2SJames Hogan { 222034b664a2SJames Hogan int len; 222134b664a2SJames Hogan 222234b664a2SJames Hogan /* get remaining partial bytes */ 222334b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 222434b664a2SJames Hogan if (unlikely(len == cnt)) 222534b664a2SJames Hogan return; 222634b664a2SJames Hogan buf += len; 222734b664a2SJames Hogan cnt -= len; 222834b664a2SJames Hogan 222934b664a2SJames Hogan /* get the rest of the data */ 223034b664a2SJames Hogan host->pull_data(host, buf, cnt); 2231f95f3850SWill Newton } 2232f95f3850SWill Newton 223387a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2234f95f3850SWill Newton { 2235f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2236f9c2a0dcSSeungwon Jeon void *buf; 2237f9c2a0dcSSeungwon Jeon unsigned int offset; 2238f95f3850SWill Newton struct mmc_data *data = host->data; 2239f95f3850SWill Newton int shift = host->data_shift; 2240f95f3850SWill Newton u32 status; 22413e4b0d8bSMarkos Chandras unsigned int len; 2242f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2243f95f3850SWill Newton 2244f95f3850SWill Newton do { 2245f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2246f9c2a0dcSSeungwon Jeon goto done; 2247f95f3850SWill Newton 22484225fc85SImre Deak host->sg = sg_miter->piter.sg; 2249f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2250f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2251f9c2a0dcSSeungwon Jeon offset = 0; 2252f9c2a0dcSSeungwon Jeon 2253f9c2a0dcSSeungwon Jeon do { 2254f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2255f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2256f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2257f9c2a0dcSSeungwon Jeon if (!len) 2258f9c2a0dcSSeungwon Jeon break; 2259f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 22603e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2261f95f3850SWill Newton offset += len; 2262f9c2a0dcSSeungwon Jeon remain -= len; 2263f9c2a0dcSSeungwon Jeon } while (remain); 2264f95f3850SWill Newton 2265e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2266f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2267f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 226887a74d39SKyoungil Kim /* if the RXDR is ready read again */ 226987a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 227087a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2271f9c2a0dcSSeungwon Jeon 2272f9c2a0dcSSeungwon Jeon if (!remain) { 2273f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2274f9c2a0dcSSeungwon Jeon goto done; 2275f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2276f9c2a0dcSSeungwon Jeon } 2277f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2278f95f3850SWill Newton return; 2279f95f3850SWill Newton 2280f95f3850SWill Newton done: 2281f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2282f9c2a0dcSSeungwon Jeon host->sg = NULL; 22830e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2284f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2285f95f3850SWill Newton } 2286f95f3850SWill Newton 2287f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2288f95f3850SWill Newton { 2289f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2290f9c2a0dcSSeungwon Jeon void *buf; 2291f9c2a0dcSSeungwon Jeon unsigned int offset; 2292f95f3850SWill Newton struct mmc_data *data = host->data; 2293f95f3850SWill Newton int shift = host->data_shift; 2294f95f3850SWill Newton u32 status; 22953e4b0d8bSMarkos Chandras unsigned int len; 2296f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2297f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2298f95f3850SWill Newton 2299f95f3850SWill Newton do { 2300f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2301f9c2a0dcSSeungwon Jeon goto done; 2302f95f3850SWill Newton 23034225fc85SImre Deak host->sg = sg_miter->piter.sg; 2304f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2305f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2306f9c2a0dcSSeungwon Jeon offset = 0; 2307f9c2a0dcSSeungwon Jeon 2308f9c2a0dcSSeungwon Jeon do { 2309f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2310f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2311f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2312f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2313f9c2a0dcSSeungwon Jeon if (!len) 2314f9c2a0dcSSeungwon Jeon break; 2315f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 23163e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2317f95f3850SWill Newton offset += len; 2318f9c2a0dcSSeungwon Jeon remain -= len; 2319f9c2a0dcSSeungwon Jeon } while (remain); 2320f95f3850SWill Newton 2321e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2322f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2323f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2324f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2325f9c2a0dcSSeungwon Jeon 2326f9c2a0dcSSeungwon Jeon if (!remain) { 2327f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2328f9c2a0dcSSeungwon Jeon goto done; 2329f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2330f9c2a0dcSSeungwon Jeon } 2331f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2332f95f3850SWill Newton return; 2333f95f3850SWill Newton 2334f95f3850SWill Newton done: 2335f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2336f9c2a0dcSSeungwon Jeon host->sg = NULL; 23370e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2338f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2339f95f3850SWill Newton } 2340f95f3850SWill Newton 2341f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2342f95f3850SWill Newton { 2343f95f3850SWill Newton if (!host->cmd_status) 2344f95f3850SWill Newton host->cmd_status = status; 2345f95f3850SWill Newton 23460e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2347f95f3850SWill Newton 2348f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2349f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2350f95f3850SWill Newton } 2351f95f3850SWill Newton 23526130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 23536130e7a9SDoug Anderson { 23546130e7a9SDoug Anderson int i; 23556130e7a9SDoug Anderson 23566130e7a9SDoug Anderson for (i = 0; i < host->num_slots; i++) { 23576130e7a9SDoug Anderson struct dw_mci_slot *slot = host->slot[i]; 23586130e7a9SDoug Anderson 23596130e7a9SDoug Anderson if (!slot) 23606130e7a9SDoug Anderson continue; 23616130e7a9SDoug Anderson 23626130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 23636130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 23646130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 23656130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 23666130e7a9SDoug Anderson } 23676130e7a9SDoug Anderson } 23686130e7a9SDoug Anderson 2369f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2370f95f3850SWill Newton { 2371f95f3850SWill Newton struct dw_mci *host = dev_id; 2372182c9081SSeungwon Jeon u32 pending; 23731a5c8e1fSShashidhar Hiremath int i; 2374f95f3850SWill Newton 2375f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2376f95f3850SWill Newton 2377476d79f1SDoug Anderson if (pending) { 237801730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 237901730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 238001730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 238149ba0302SDoug Anderson unsigned long irqflags; 23825c935165SDoug Anderson 238301730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 238401730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 238549ba0302SDoug Anderson 238649ba0302SDoug Anderson /* 238749ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 238849ba0302SDoug Anderson * off after the lock is released, so safe to delete. 238949ba0302SDoug Anderson */ 239049ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 239101730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 239249ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 239349ba0302SDoug Anderson 239449ba0302SDoug Anderson del_timer(&host->cmd11_timer); 239501730558SDoug Anderson } 239601730558SDoug Anderson 2397f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2398f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2399182c9081SSeungwon Jeon host->cmd_status = pending; 24000e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2401f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2402f95f3850SWill Newton } 2403f95f3850SWill Newton 2404f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2405f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2406f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2407182c9081SSeungwon Jeon host->data_status = pending; 24080e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2409f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2410f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2411f95f3850SWill Newton } 2412f95f3850SWill Newton 2413f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 241457e10486SAddy Ke if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO) 241557e10486SAddy Ke del_timer(&host->dto_timer); 241657e10486SAddy Ke 2417f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2418f95f3850SWill Newton if (!host->data_status) 2419182c9081SSeungwon Jeon host->data_status = pending; 24200e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2421f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2422f95f3850SWill Newton if (host->sg != NULL) 242387a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2424f95f3850SWill Newton } 2425f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2426f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2427f95f3850SWill Newton } 2428f95f3850SWill Newton 2429f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2430f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2431b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 243287a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2433f95f3850SWill Newton } 2434f95f3850SWill Newton 2435f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2436f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2437b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2438f95f3850SWill Newton dw_mci_write_data_pio(host); 2439f95f3850SWill Newton } 2440f95f3850SWill Newton 2441f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2442f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2443182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2444f95f3850SWill Newton } 2445f95f3850SWill Newton 2446f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2447f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 24486130e7a9SDoug Anderson dw_mci_handle_cd(host); 2449f95f3850SWill Newton } 2450f95f3850SWill Newton 24511a5c8e1fSShashidhar Hiremath /* Handle SDIO Interrupts */ 24521a5c8e1fSShashidhar Hiremath for (i = 0; i < host->num_slots; i++) { 24531a5c8e1fSShashidhar Hiremath struct dw_mci_slot *slot = host->slot[i]; 2454ed2540efSDoug Anderson 2455ed2540efSDoug Anderson if (!slot) 2456ed2540efSDoug Anderson continue; 2457ed2540efSDoug Anderson 245876756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 245976756234SAddy Ke mci_writel(host, RINTSTS, 246076756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 24611a5c8e1fSShashidhar Hiremath mmc_signal_sdio_irq(slot->mmc); 24621a5c8e1fSShashidhar Hiremath } 24631a5c8e1fSShashidhar Hiremath } 24641a5c8e1fSShashidhar Hiremath 24651fb5f68aSMarkos Chandras } 2466f95f3850SWill Newton 24673fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 24683fc7eaefSShawn Lin return IRQ_HANDLED; 24693fc7eaefSShawn Lin 24703fc7eaefSShawn Lin /* Handle IDMA interrupts */ 247169d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 247269d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 247369d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 247469d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 247569d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 247669d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 24773fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 247869d99fdcSPrabu Thangamuthu } 247969d99fdcSPrabu Thangamuthu } else { 2480f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2481f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 248269d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 248369d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2484f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 24853fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2486f95f3850SWill Newton } 248769d99fdcSPrabu Thangamuthu } 2488f95f3850SWill Newton 2489f95f3850SWill Newton return IRQ_HANDLED; 2490f95f3850SWill Newton } 2491f95f3850SWill Newton 2492c91eab4bSThomas Abraham #ifdef CONFIG_OF 2493eff8f2f5SLars-Peter Clausen /* given a slot, find out the device node representing that slot */ 2494eff8f2f5SLars-Peter Clausen static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot) 2495c91eab4bSThomas Abraham { 2496eff8f2f5SLars-Peter Clausen struct device *dev = slot->mmc->parent; 2497c91eab4bSThomas Abraham struct device_node *np; 2498c91eab4bSThomas Abraham const __be32 *addr; 2499c91eab4bSThomas Abraham int len; 2500c91eab4bSThomas Abraham 2501c91eab4bSThomas Abraham if (!dev || !dev->of_node) 2502c91eab4bSThomas Abraham return NULL; 2503c91eab4bSThomas Abraham 2504c91eab4bSThomas Abraham for_each_child_of_node(dev->of_node, np) { 2505c91eab4bSThomas Abraham addr = of_get_property(np, "reg", &len); 2506c91eab4bSThomas Abraham if (!addr || (len < sizeof(int))) 2507c91eab4bSThomas Abraham continue; 2508eff8f2f5SLars-Peter Clausen if (be32_to_cpup(addr) == slot->id) 2509c91eab4bSThomas Abraham return np; 2510c91eab4bSThomas Abraham } 2511c91eab4bSThomas Abraham return NULL; 2512c91eab4bSThomas Abraham } 2513c91eab4bSThomas Abraham 2514eff8f2f5SLars-Peter Clausen static void dw_mci_slot_of_parse(struct dw_mci_slot *slot) 2515a70aaa64SDoug Anderson { 2516eff8f2f5SLars-Peter Clausen struct device_node *np = dw_mci_of_find_slot_node(slot); 2517a70aaa64SDoug Anderson 2518eff8f2f5SLars-Peter Clausen if (!np) 2519eff8f2f5SLars-Peter Clausen return; 2520a70aaa64SDoug Anderson 2521eff8f2f5SLars-Peter Clausen if (of_property_read_bool(np, "disable-wp")) { 2522eff8f2f5SLars-Peter Clausen slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; 2523eff8f2f5SLars-Peter Clausen dev_warn(slot->mmc->parent, 2524eff8f2f5SLars-Peter Clausen "Slot quirk 'disable-wp' is deprecated\n"); 252526375b5cSJaehoon Chung } 2526a70aaa64SDoug Anderson } 2527c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2528eff8f2f5SLars-Peter Clausen static void dw_mci_slot_of_parse(struct dw_mci_slot *slot) 2529a70aaa64SDoug Anderson { 2530a70aaa64SDoug Anderson } 2531c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2532c91eab4bSThomas Abraham 253336c179a9SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2534f95f3850SWill Newton { 2535f95f3850SWill Newton struct mmc_host *mmc; 2536f95f3850SWill Newton struct dw_mci_slot *slot; 2537e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2538800d78bfSThomas Abraham int ctrl_id, ret; 25391f44a2a5SSeungwon Jeon u32 freq[2]; 2540f95f3850SWill Newton 25414a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2542f95f3850SWill Newton if (!mmc) 2543f95f3850SWill Newton return -ENOMEM; 2544f95f3850SWill Newton 2545f95f3850SWill Newton slot = mmc_priv(mmc); 2546f95f3850SWill Newton slot->id = id; 254776756234SAddy Ke slot->sdio_id = host->sdio_id0 + id; 2548f95f3850SWill Newton slot->mmc = mmc; 2549f95f3850SWill Newton slot->host = host; 2550c91eab4bSThomas Abraham host->slot[id] = slot; 2551f95f3850SWill Newton 2552f95f3850SWill Newton mmc->ops = &dw_mci_ops; 25531f44a2a5SSeungwon Jeon if (of_property_read_u32_array(host->dev->of_node, 25541f44a2a5SSeungwon Jeon "clock-freq-min-max", freq, 2)) { 25551f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 25561f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 25571f44a2a5SSeungwon Jeon } else { 25581f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 25591f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 25601f44a2a5SSeungwon Jeon } 2561f95f3850SWill Newton 256251da2240SYuvaraj CD /*if there are external regulators, get them*/ 256351da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 256451da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 25653cf890fcSDoug Anderson goto err_host_allocated; 256651da2240SYuvaraj CD 256751da2240SYuvaraj CD if (!mmc->ocr_avail) 2568f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2569f95f3850SWill Newton 2570fc3d7720SJaehoon Chung if (host->pdata->caps) 2571fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2572fc3d7720SJaehoon Chung 2573ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2574ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2575ab269128SAbhilash Kesavan 2576800d78bfSThomas Abraham if (host->dev->of_node) { 2577800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2578800d78bfSThomas Abraham if (ctrl_id < 0) 2579800d78bfSThomas Abraham ctrl_id = 0; 2580800d78bfSThomas Abraham } else { 2581800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2582800d78bfSThomas Abraham } 2583cb27a843SJames Hogan if (drv_data && drv_data->caps) 2584cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2585800d78bfSThomas Abraham 25864f408cc6SSeungwon Jeon if (host->pdata->caps2) 25874f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 25884f408cc6SSeungwon Jeon 2589eff8f2f5SLars-Peter Clausen dw_mci_slot_of_parse(slot); 2590eff8f2f5SLars-Peter Clausen 25913cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 25923cf890fcSDoug Anderson if (ret) 25933cf890fcSDoug Anderson goto err_host_allocated; 2594f95f3850SWill Newton 2595f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 25963fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2597a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2598a39e5746SJaehoon Chung mmc->max_blk_size = 65536; 2599575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 26001a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 26011a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 26023fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 26033fc7eaefSShawn Lin mmc->max_segs = 64; 26043fc7eaefSShawn Lin mmc->max_blk_size = 65536; 26053fc7eaefSShawn Lin mmc->max_blk_count = 65535; 26063fc7eaefSShawn Lin mmc->max_req_size = 26073fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 26083fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2609575c319dSHeiko Stuebner } else { 26103fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2611f95f3850SWill Newton mmc->max_segs = 64; 2612f95f3850SWill Newton mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2613f95f3850SWill Newton mmc->max_blk_count = 512; 2614575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2615575c319dSHeiko Stuebner mmc->max_blk_count; 2616f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2617575c319dSHeiko Stuebner } 2618f95f3850SWill Newton 2619ae0eb348SJaehoon Chung if (dw_mci_get_cd(mmc)) 2620ae0eb348SJaehoon Chung set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2621ae0eb348SJaehoon Chung else 2622ae0eb348SJaehoon Chung clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2623ae0eb348SJaehoon Chung 26240cea529dSJaehoon Chung ret = mmc_add_host(mmc); 26250cea529dSJaehoon Chung if (ret) 26263cf890fcSDoug Anderson goto err_host_allocated; 2627f95f3850SWill Newton 2628f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2629f95f3850SWill Newton dw_mci_init_debugfs(slot); 2630f95f3850SWill Newton #endif 2631f95f3850SWill Newton 2632f95f3850SWill Newton return 0; 2633800d78bfSThomas Abraham 26343cf890fcSDoug Anderson err_host_allocated: 2635800d78bfSThomas Abraham mmc_free_host(mmc); 263651da2240SYuvaraj CD return ret; 2637f95f3850SWill Newton } 2638f95f3850SWill Newton 2639f95f3850SWill Newton static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2640f95f3850SWill Newton { 2641f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2642f95f3850SWill Newton mmc_remove_host(slot->mmc); 2643f95f3850SWill Newton slot->host->slot[id] = NULL; 2644f95f3850SWill Newton mmc_free_host(slot->mmc); 2645f95f3850SWill Newton } 2646f95f3850SWill Newton 2647f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2648f95f3850SWill Newton { 264969d99fdcSPrabu Thangamuthu int addr_config; 26503fc7eaefSShawn Lin struct device *dev = host->dev; 26513fc7eaefSShawn Lin struct device_node *np = dev->of_node; 26523fc7eaefSShawn Lin 26533fc7eaefSShawn Lin /* 26543fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 26553fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 26563fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 26573fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 26583fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 26593fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 26603fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 26613fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 26623fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 26633fc7eaefSShawn Lin */ 26643fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 26653fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 26663fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 26673fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 26683fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 26693fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 26703fc7eaefSShawn Lin } else { 26713fc7eaefSShawn Lin goto no_dma; 26723fc7eaefSShawn Lin } 26733fc7eaefSShawn Lin 26743fc7eaefSShawn Lin /* Determine which DMA interface to use */ 26753fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 26763fc7eaefSShawn Lin /* 26773fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 26783fc7eaefSShawn Lin * IDMAC address bus width 26793fc7eaefSShawn Lin */ 268070692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 268169d99fdcSPrabu Thangamuthu 268269d99fdcSPrabu Thangamuthu if (addr_config == 1) { 268369d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 268469d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 26853fc7eaefSShawn Lin dev_info(host->dev, 26863fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 268769d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 26883fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 26893fc7eaefSShawn Lin DMA_BIT_MASK(64)); 269069d99fdcSPrabu Thangamuthu } else { 269169d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 269269d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 26933fc7eaefSShawn Lin dev_info(host->dev, 26943fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 269569d99fdcSPrabu Thangamuthu } 269669d99fdcSPrabu Thangamuthu 2697f95f3850SWill Newton /* Alloc memory for sg translation */ 2698780f22afSSeungwon Jeon host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2699f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2700f95f3850SWill Newton if (!host->sg_cpu) { 27013fc7eaefSShawn Lin dev_err(host->dev, 27023fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2703f95f3850SWill Newton __func__); 2704f95f3850SWill Newton goto no_dma; 2705f95f3850SWill Newton } 2706f95f3850SWill Newton 2707f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 270800956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 27093fc7eaefSShawn Lin } else { 27103fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 27113fc7eaefSShawn Lin if ((of_property_count_strings(np, "dma-names") < 0) || 27123fc7eaefSShawn Lin (!of_find_property(np, "dmas", NULL))) { 2713f95f3850SWill Newton goto no_dma; 27143fc7eaefSShawn Lin } 27153fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 27163fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 27173fc7eaefSShawn Lin } 2718f95f3850SWill Newton 2719e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2720e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2721f95f3850SWill Newton if (host->dma_ops->init(host)) { 27220e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 27230e3a22c0SShawn Lin __func__); 2724f95f3850SWill Newton goto no_dma; 2725f95f3850SWill Newton } 2726f95f3850SWill Newton } else { 27274a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2728f95f3850SWill Newton goto no_dma; 2729f95f3850SWill Newton } 2730f95f3850SWill Newton 2731f95f3850SWill Newton return; 2732f95f3850SWill Newton 2733f95f3850SWill Newton no_dma: 27344a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 27353fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2736f95f3850SWill Newton } 2737f95f3850SWill Newton 273831bff450SSeungwon Jeon static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2739f95f3850SWill Newton { 2740f95f3850SWill Newton unsigned long timeout = jiffies + msecs_to_jiffies(500); 274131bff450SSeungwon Jeon u32 ctrl; 2742f95f3850SWill Newton 274331bff450SSeungwon Jeon ctrl = mci_readl(host, CTRL); 274431bff450SSeungwon Jeon ctrl |= reset; 274531bff450SSeungwon Jeon mci_writel(host, CTRL, ctrl); 2746f95f3850SWill Newton 2747f95f3850SWill Newton /* wait till resets clear */ 2748f95f3850SWill Newton do { 2749f95f3850SWill Newton ctrl = mci_readl(host, CTRL); 275031bff450SSeungwon Jeon if (!(ctrl & reset)) 2751f95f3850SWill Newton return true; 2752f95f3850SWill Newton } while (time_before(jiffies, timeout)); 2753f95f3850SWill Newton 275431bff450SSeungwon Jeon dev_err(host->dev, 275531bff450SSeungwon Jeon "Timeout resetting block (ctrl reset %#x)\n", 275631bff450SSeungwon Jeon ctrl & reset); 2757f95f3850SWill Newton 2758f95f3850SWill Newton return false; 2759f95f3850SWill Newton } 2760f95f3850SWill Newton 27613a33a94cSSonny Rao static bool dw_mci_reset(struct dw_mci *host) 276231bff450SSeungwon Jeon { 27633a33a94cSSonny Rao u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 27643a33a94cSSonny Rao bool ret = false; 27653a33a94cSSonny Rao 276631bff450SSeungwon Jeon /* 276731bff450SSeungwon Jeon * Reseting generates a block interrupt, hence setting 276831bff450SSeungwon Jeon * the scatter-gather pointer to NULL. 276931bff450SSeungwon Jeon */ 277031bff450SSeungwon Jeon if (host->sg) { 277131bff450SSeungwon Jeon sg_miter_stop(&host->sg_miter); 277231bff450SSeungwon Jeon host->sg = NULL; 277331bff450SSeungwon Jeon } 277431bff450SSeungwon Jeon 27753a33a94cSSonny Rao if (host->use_dma) 27763a33a94cSSonny Rao flags |= SDMMC_CTRL_DMA_RESET; 27773a33a94cSSonny Rao 27783a33a94cSSonny Rao if (dw_mci_ctrl_reset(host, flags)) { 27793a33a94cSSonny Rao /* 27803a33a94cSSonny Rao * In all cases we clear the RAWINTS register to clear any 27813a33a94cSSonny Rao * interrupts. 27823a33a94cSSonny Rao */ 27833a33a94cSSonny Rao mci_writel(host, RINTSTS, 0xFFFFFFFF); 27843a33a94cSSonny Rao 27853a33a94cSSonny Rao /* if using dma we wait for dma_req to clear */ 27863a33a94cSSonny Rao if (host->use_dma) { 27873a33a94cSSonny Rao unsigned long timeout = jiffies + msecs_to_jiffies(500); 27883a33a94cSSonny Rao u32 status; 27890e3a22c0SShawn Lin 27903a33a94cSSonny Rao do { 27913a33a94cSSonny Rao status = mci_readl(host, STATUS); 27923a33a94cSSonny Rao if (!(status & SDMMC_STATUS_DMA_REQ)) 27933a33a94cSSonny Rao break; 27943a33a94cSSonny Rao cpu_relax(); 27953a33a94cSSonny Rao } while (time_before(jiffies, timeout)); 27963a33a94cSSonny Rao 27973a33a94cSSonny Rao if (status & SDMMC_STATUS_DMA_REQ) { 27983a33a94cSSonny Rao dev_err(host->dev, 27990e3a22c0SShawn Lin "%s: Timeout waiting for dma_req to clear during reset\n", 28000e3a22c0SShawn Lin __func__); 28013a33a94cSSonny Rao goto ciu_out; 280231bff450SSeungwon Jeon } 280331bff450SSeungwon Jeon 28043a33a94cSSonny Rao /* when using DMA next we reset the fifo again */ 28053a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 28063a33a94cSSonny Rao goto ciu_out; 28073a33a94cSSonny Rao } 28083a33a94cSSonny Rao } else { 28093a33a94cSSonny Rao /* if the controller reset bit did clear, then set clock regs */ 28103a33a94cSSonny Rao if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 28110e3a22c0SShawn Lin dev_err(host->dev, 28120e3a22c0SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 28133a33a94cSSonny Rao __func__); 28143a33a94cSSonny Rao goto ciu_out; 28153a33a94cSSonny Rao } 28163a33a94cSSonny Rao } 28173a33a94cSSonny Rao 28183fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 28193a33a94cSSonny Rao /* It is also recommended that we reset and reprogram idmac */ 28203a33a94cSSonny Rao dw_mci_idmac_reset(host); 28213a33a94cSSonny Rao 28223a33a94cSSonny Rao ret = true; 28233a33a94cSSonny Rao 28243a33a94cSSonny Rao ciu_out: 28253a33a94cSSonny Rao /* After a CTRL reset we need to have CIU set clock registers */ 28263a33a94cSSonny Rao mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 28273a33a94cSSonny Rao 28283a33a94cSSonny Rao return ret; 282931bff450SSeungwon Jeon } 283031bff450SSeungwon Jeon 28315c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 28325c935165SDoug Anderson { 28335c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 28345c935165SDoug Anderson 2835fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 2836fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2837fd674198SDoug Anderson return; 2838fd674198SDoug Anderson } 28395c935165SDoug Anderson 28405c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 28415c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 28425c935165SDoug Anderson tasklet_schedule(&host->tasklet); 28435c935165SDoug Anderson } 28445c935165SDoug Anderson 284557e10486SAddy Ke static void dw_mci_dto_timer(unsigned long arg) 284657e10486SAddy Ke { 284757e10486SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 284857e10486SAddy Ke 284957e10486SAddy Ke switch (host->state) { 285057e10486SAddy Ke case STATE_SENDING_DATA: 285157e10486SAddy Ke case STATE_DATA_BUSY: 285257e10486SAddy Ke /* 285357e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 285457e10486SAddy Ke * we should notify the driver to terminate current transfer 285557e10486SAddy Ke * and report a data timeout to the core. 285657e10486SAddy Ke */ 285757e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 285857e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 285957e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 286057e10486SAddy Ke tasklet_schedule(&host->tasklet); 286157e10486SAddy Ke break; 286257e10486SAddy Ke default: 286357e10486SAddy Ke break; 286457e10486SAddy Ke } 286557e10486SAddy Ke } 286657e10486SAddy Ke 2867c91eab4bSThomas Abraham #ifdef CONFIG_OF 2868c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2869c91eab4bSThomas Abraham { 2870c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2871c91eab4bSThomas Abraham struct device *dev = host->dev; 2872c91eab4bSThomas Abraham struct device_node *np = dev->of_node; 2873e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2874e8cc37b8SShawn Lin int ret; 28753c6d89eaSDoug Anderson u32 clock_frequency; 2876c91eab4bSThomas Abraham 2877c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2878bf3707eaSBeomho Seo if (!pdata) 2879c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2880c91eab4bSThomas Abraham 2881c91eab4bSThomas Abraham /* find out number of slots supported */ 2882c91eab4bSThomas Abraham if (of_property_read_u32(dev->of_node, "num-slots", 2883c91eab4bSThomas Abraham &pdata->num_slots)) { 28840e3a22c0SShawn Lin dev_info(dev, 28850e3a22c0SShawn Lin "num-slots property not found, assuming 1 slot is available\n"); 2886c91eab4bSThomas Abraham pdata->num_slots = 1; 2887c91eab4bSThomas Abraham } 2888c91eab4bSThomas Abraham 2889c91eab4bSThomas Abraham if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 28900e3a22c0SShawn Lin dev_info(dev, 28910e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 2892c91eab4bSThomas Abraham 2893c91eab4bSThomas Abraham of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2894c91eab4bSThomas Abraham 28953c6d89eaSDoug Anderson if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 28963c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 28973c6d89eaSDoug Anderson 2898cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 2899cb27a843SJames Hogan ret = drv_data->parse_dt(host); 2900800d78bfSThomas Abraham if (ret) 2901800d78bfSThomas Abraham return ERR_PTR(ret); 2902800d78bfSThomas Abraham } 2903800d78bfSThomas Abraham 290440a7a463SJaehoon Chung if (of_find_property(np, "supports-highspeed", NULL)) { 290540a7a463SJaehoon Chung dev_info(dev, "supports-highspeed property is deprecated.\n"); 290610b49841SSeungwon Jeon pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 290740a7a463SJaehoon Chung } 290810b49841SSeungwon Jeon 2909c91eab4bSThomas Abraham return pdata; 2910c91eab4bSThomas Abraham } 2911c91eab4bSThomas Abraham 2912c91eab4bSThomas Abraham #else /* CONFIG_OF */ 2913c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2914c91eab4bSThomas Abraham { 2915c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 2916c91eab4bSThomas Abraham } 2917c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 2918c91eab4bSThomas Abraham 2919fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 2920fa0c3283SDoug Anderson { 2921fa0c3283SDoug Anderson unsigned long irqflags; 2922fa0c3283SDoug Anderson u32 temp; 2923fa0c3283SDoug Anderson int i; 2924e8cc37b8SShawn Lin struct dw_mci_slot *slot; 2925fa0c3283SDoug Anderson 2926e8cc37b8SShawn Lin /* 2927e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 2928e8cc37b8SShawn Lin * as well as broken card detection is found. 2929e8cc37b8SShawn Lin */ 2930fa0c3283SDoug Anderson for (i = 0; i < host->num_slots; i++) { 2931e8cc37b8SShawn Lin slot = host->slot[i]; 2932e8cc37b8SShawn Lin if (slot->mmc->caps & MMC_CAP_NEEDS_POLL) 2933e8cc37b8SShawn Lin return; 2934fa0c3283SDoug Anderson 2935fa0c3283SDoug Anderson if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) 2936fa0c3283SDoug Anderson break; 2937fa0c3283SDoug Anderson } 2938fa0c3283SDoug Anderson if (i == host->num_slots) 2939fa0c3283SDoug Anderson return; 2940fa0c3283SDoug Anderson 2941fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 2942fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 2943fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 2944fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 2945fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 2946fa0c3283SDoug Anderson } 2947fa0c3283SDoug Anderson 294862ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 2949f95f3850SWill Newton { 2950e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 295162ca8034SShashidhar Hiremath int width, i, ret = 0; 2952f95f3850SWill Newton u32 fifo_size; 29531c2215b7SThomas Abraham int init_slots = 0; 2954f95f3850SWill Newton 2955c91eab4bSThomas Abraham if (!host->pdata) { 2956c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 2957c91eab4bSThomas Abraham if (IS_ERR(host->pdata)) { 2958c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 2959c91eab4bSThomas Abraham return -EINVAL; 2960c91eab4bSThomas Abraham } 2961f95f3850SWill Newton } 2962f95f3850SWill Newton 29639e747b7eSJaehoon Chung if (host->pdata->num_slots < 1) { 29644a90920cSThomas Abraham dev_err(host->dev, 2965907abd51SJaehoon Chung "Platform data must supply num_slots.\n"); 296662ca8034SShashidhar Hiremath return -ENODEV; 2967f95f3850SWill Newton } 2968f95f3850SWill Newton 2969780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 2970f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 2971f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 2972f90a0612SThomas Abraham } else { 2973f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 2974f90a0612SThomas Abraham if (ret) { 2975f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 2976f90a0612SThomas Abraham return ret; 2977f90a0612SThomas Abraham } 2978f95f3850SWill Newton } 2979f95f3850SWill Newton 2980780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2981f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 2982f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 29833c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 2984f90a0612SThomas Abraham } else { 2985f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 2986f90a0612SThomas Abraham if (ret) { 2987f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 2988f90a0612SThomas Abraham goto err_clk_biu; 2989f90a0612SThomas Abraham } 2990f90a0612SThomas Abraham 29913c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 29923c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 29933c6d89eaSDoug Anderson if (ret) 29943c6d89eaSDoug Anderson dev_warn(host->dev, 2995612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 29963c6d89eaSDoug Anderson host->pdata->bus_hz); 29973c6d89eaSDoug Anderson } 2998f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 29993c6d89eaSDoug Anderson } 3000f90a0612SThomas Abraham 3001612de4c1SJaehoon Chung if (!host->bus_hz) { 3002612de4c1SJaehoon Chung dev_err(host->dev, 3003612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3004612de4c1SJaehoon Chung ret = -ENODEV; 3005612de4c1SJaehoon Chung goto err_clk_ciu; 3006612de4c1SJaehoon Chung } 3007612de4c1SJaehoon Chung 3008002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3009002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3010002f0d5cSYuvaraj Kumar C D if (ret) { 3011002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3012002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3013002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3014002f0d5cSYuvaraj Kumar C D } 3015002f0d5cSYuvaraj Kumar C D } 3016002f0d5cSYuvaraj Kumar C D 3017cb27a843SJames Hogan if (drv_data && drv_data->setup_clock) { 3018cb27a843SJames Hogan ret = drv_data->setup_clock(host); 3019800d78bfSThomas Abraham if (ret) { 3020800d78bfSThomas Abraham dev_err(host->dev, 3021800d78bfSThomas Abraham "implementation specific clock setup failed\n"); 3022800d78bfSThomas Abraham goto err_clk_ciu; 3023800d78bfSThomas Abraham } 3024800d78bfSThomas Abraham } 3025800d78bfSThomas Abraham 30265c935165SDoug Anderson setup_timer(&host->cmd11_timer, 30275c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 30285c935165SDoug Anderson 302962ca8034SShashidhar Hiremath host->quirks = host->pdata->quirks; 3030f95f3850SWill Newton 303157e10486SAddy Ke if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO) 303257e10486SAddy Ke setup_timer(&host->dto_timer, 303357e10486SAddy Ke dw_mci_dto_timer, (unsigned long)host); 303457e10486SAddy Ke 3035f95f3850SWill Newton spin_lock_init(&host->lock); 3036f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3037f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3038f95f3850SWill Newton 3039f95f3850SWill Newton /* 3040f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3041f95f3850SWill Newton * the correct values. 3042f95f3850SWill Newton */ 304370692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3044f95f3850SWill Newton if (!i) { 3045f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3046f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3047f95f3850SWill Newton width = 16; 3048f95f3850SWill Newton host->data_shift = 1; 3049f95f3850SWill Newton } else if (i == 2) { 3050f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3051f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3052f95f3850SWill Newton width = 64; 3053f95f3850SWill Newton host->data_shift = 3; 3054f95f3850SWill Newton } else { 3055f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3056f95f3850SWill Newton WARN((i != 1), 3057f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3058f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3059f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3060f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3061f95f3850SWill Newton width = 32; 3062f95f3850SWill Newton host->data_shift = 2; 3063f95f3850SWill Newton } 3064f95f3850SWill Newton 3065f95f3850SWill Newton /* Reset all blocks */ 3066*3744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3067*3744415cSShawn Lin ret = -ENODEV; 3068*3744415cSShawn Lin goto err_clk_ciu; 3069*3744415cSShawn Lin } 3070141a712aSSeungwon Jeon 3071141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3072141a712aSSeungwon Jeon dw_mci_init_dma(host); 3073f95f3850SWill Newton 3074f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3075f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3076f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3077f95f3850SWill Newton 3078f95f3850SWill Newton /* Put in max timeout */ 3079f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3080f95f3850SWill Newton 3081f95f3850SWill Newton /* 3082f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3083f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3084f95f3850SWill Newton */ 3085b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3086b86d8253SJames Hogan /* 3087b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3088b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3089b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3090b86d8253SJames Hogan * should put it in the platform data. 3091b86d8253SJames Hogan */ 3092f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 30938234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3094b86d8253SJames Hogan } else { 3095b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3096b86d8253SJames Hogan } 3097b86d8253SJames Hogan host->fifo_depth = fifo_size; 309852426899SSeungwon Jeon host->fifoth_val = 309952426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3100e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3101f95f3850SWill Newton 3102f95f3850SWill Newton /* disable clock to CIU */ 3103f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3104f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3105f95f3850SWill Newton 310663008768SJames Hogan /* 310763008768SJames Hogan * In 2.40a spec, Data offset is changed. 310863008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 310963008768SJames Hogan */ 311063008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 311163008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 311263008768SJames Hogan 311363008768SJames Hogan if (host->verid < DW_MMC_240A) 311476184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 311563008768SJames Hogan else 311676184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 311763008768SJames Hogan 3118f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3119780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3120780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3121f95f3850SWill Newton if (ret) 31226130e7a9SDoug Anderson goto err_dmaunmap; 3123f95f3850SWill Newton 3124f95f3850SWill Newton if (host->pdata->num_slots) 3125f95f3850SWill Newton host->num_slots = host->pdata->num_slots; 3126f95f3850SWill Newton else 312770692752SShawn Lin host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON)); 3128f95f3850SWill Newton 31292da1d7f2SYuvaraj CD /* 3130fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 31312da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 31322da1d7f2SYuvaraj CD */ 31332da1d7f2SYuvaraj CD mci_writel(host, RINTSTS, 0xFFFFFFFF); 31342da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 31352da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3136fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 31370e3a22c0SShawn Lin /* Enable mci interrupt */ 31380e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 31392da1d7f2SYuvaraj CD 31400e3a22c0SShawn Lin dev_info(host->dev, 31410e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 31422da1d7f2SYuvaraj CD host->irq, width, fifo_size); 31432da1d7f2SYuvaraj CD 3144f95f3850SWill Newton /* We need at least one slot to succeed */ 3145f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3146f95f3850SWill Newton ret = dw_mci_init_slot(host, i); 31471c2215b7SThomas Abraham if (ret) 31481c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 31491c2215b7SThomas Abraham else 31501c2215b7SThomas Abraham init_slots++; 3151f95f3850SWill Newton } 31521c2215b7SThomas Abraham 31531c2215b7SThomas Abraham if (init_slots) { 31541c2215b7SThomas Abraham dev_info(host->dev, "%d slots initialized\n", init_slots); 31551c2215b7SThomas Abraham } else { 31560e3a22c0SShawn Lin dev_dbg(host->dev, 31570e3a22c0SShawn Lin "attempted to initialize %d slots, but failed on all\n", 31580e3a22c0SShawn Lin host->num_slots); 31596130e7a9SDoug Anderson goto err_dmaunmap; 3160f95f3850SWill Newton } 3161f95f3850SWill Newton 3162b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3163b793f658SDoug Anderson dw_mci_enable_cd(host); 3164b793f658SDoug Anderson 3165f95f3850SWill Newton return 0; 3166f95f3850SWill Newton 3167f95f3850SWill Newton err_dmaunmap: 3168f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3169f95f3850SWill Newton host->dma_ops->exit(host); 3170f90a0612SThomas Abraham 3171f90a0612SThomas Abraham err_clk_ciu: 3172780f22afSSeungwon Jeon if (!IS_ERR(host->ciu_clk)) 3173f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3174780f22afSSeungwon Jeon 3175f90a0612SThomas Abraham err_clk_biu: 3176780f22afSSeungwon Jeon if (!IS_ERR(host->biu_clk)) 3177f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3178780f22afSSeungwon Jeon 3179f95f3850SWill Newton return ret; 3180f95f3850SWill Newton } 318162ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3182f95f3850SWill Newton 318362ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3184f95f3850SWill Newton { 3185f95f3850SWill Newton int i; 3186f95f3850SWill Newton 3187f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 31884a90920cSThomas Abraham dev_dbg(host->dev, "remove slot %d\n", i); 3189f95f3850SWill Newton if (host->slot[i]) 3190f95f3850SWill Newton dw_mci_cleanup_slot(host->slot[i], i); 3191f95f3850SWill Newton } 3192f95f3850SWill Newton 3193048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3194048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3195048fd7e6SPrabu Thangamuthu 3196f95f3850SWill Newton /* disable clock to CIU */ 3197f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3198f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3199f95f3850SWill Newton 3200f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3201f95f3850SWill Newton host->dma_ops->exit(host); 3202f95f3850SWill Newton 3203f90a0612SThomas Abraham if (!IS_ERR(host->ciu_clk)) 3204f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3205780f22afSSeungwon Jeon 3206f90a0612SThomas Abraham if (!IS_ERR(host->biu_clk)) 3207f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3208f95f3850SWill Newton } 320962ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 321062ca8034SShashidhar Hiremath 321162ca8034SShashidhar Hiremath 3212f95f3850SWill Newton 32136fe8890dSJaehoon Chung #ifdef CONFIG_PM_SLEEP 3214f95f3850SWill Newton /* 3215f95f3850SWill Newton * TODO: we should probably disable the clock to the card in the suspend path. 3216f95f3850SWill Newton */ 321762ca8034SShashidhar Hiremath int dw_mci_suspend(struct dw_mci *host) 3218f95f3850SWill Newton { 32193fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 32203fc7eaefSShawn Lin host->dma_ops->exit(host); 32213fc7eaefSShawn Lin 3222f95f3850SWill Newton return 0; 3223f95f3850SWill Newton } 322462ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_suspend); 3225f95f3850SWill Newton 322662ca8034SShashidhar Hiremath int dw_mci_resume(struct dw_mci *host) 3227f95f3850SWill Newton { 3228f95f3850SWill Newton int i, ret; 3229f95f3850SWill Newton 32303a33a94cSSonny Rao if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3231e61cf118SJaehoon Chung ret = -ENODEV; 3232e61cf118SJaehoon Chung return ret; 3233e61cf118SJaehoon Chung } 3234e61cf118SJaehoon Chung 32353bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3236141a712aSSeungwon Jeon host->dma_ops->init(host); 3237141a712aSSeungwon Jeon 323852426899SSeungwon Jeon /* 323952426899SSeungwon Jeon * Restore the initial value at FIFOTH register 324052426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 324152426899SSeungwon Jeon */ 3242e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 324352426899SSeungwon Jeon host->prev_blksz = 0; 3244e61cf118SJaehoon Chung 32452eb2944fSDoug Anderson /* Put in max timeout */ 32462eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 32472eb2944fSDoug Anderson 3248e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3249e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3250e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3251fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3252e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3253e61cf118SJaehoon Chung 3254f95f3850SWill Newton for (i = 0; i < host->num_slots; i++) { 3255f95f3850SWill Newton struct dw_mci_slot *slot = host->slot[i]; 32560e3a22c0SShawn Lin 3257f95f3850SWill Newton if (!slot) 3258f95f3850SWill Newton continue; 3259ab269128SAbhilash Kesavan if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 3260ab269128SAbhilash Kesavan dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3261ab269128SAbhilash Kesavan dw_mci_setup_bus(slot, true); 3262ab269128SAbhilash Kesavan } 3263f95f3850SWill Newton } 3264fa0c3283SDoug Anderson 3265fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3266fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3267fa0c3283SDoug Anderson 3268f95f3850SWill Newton return 0; 3269f95f3850SWill Newton } 327062ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_resume); 32716fe8890dSJaehoon Chung #endif /* CONFIG_PM_SLEEP */ 32726fe8890dSJaehoon Chung 3273f95f3850SWill Newton static int __init dw_mci_init(void) 3274f95f3850SWill Newton { 32758e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 327662ca8034SShashidhar Hiremath return 0; 3277f95f3850SWill Newton } 3278f95f3850SWill Newton 3279f95f3850SWill Newton static void __exit dw_mci_exit(void) 3280f95f3850SWill Newton { 3281f95f3850SWill Newton } 3282f95f3850SWill Newton 3283f95f3850SWill Newton module_init(dw_mci_init); 3284f95f3850SWill Newton module_exit(dw_mci_exit); 3285f95f3850SWill Newton 3286f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3287f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3288f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3289f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3290