1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #include <linux/blkdev.h> 15f95f3850SWill Newton #include <linux/clk.h> 16f95f3850SWill Newton #include <linux/debugfs.h> 17f95f3850SWill Newton #include <linux/device.h> 18f95f3850SWill Newton #include <linux/dma-mapping.h> 19f95f3850SWill Newton #include <linux/err.h> 20f95f3850SWill Newton #include <linux/init.h> 21f95f3850SWill Newton #include <linux/interrupt.h> 22b6d2d81cSShawn Lin #include <linux/iopoll.h> 23f95f3850SWill Newton #include <linux/ioport.h> 24f95f3850SWill Newton #include <linux/module.h> 25f95f3850SWill Newton #include <linux/platform_device.h> 26a6db2c86SDouglas Anderson #include <linux/pm_runtime.h> 27f95f3850SWill Newton #include <linux/seq_file.h> 28f95f3850SWill Newton #include <linux/slab.h> 29f95f3850SWill Newton #include <linux/stat.h> 30f95f3850SWill Newton #include <linux/delay.h> 31f95f3850SWill Newton #include <linux/irq.h> 32b24c8b26SDoug Anderson #include <linux/mmc/card.h> 33f95f3850SWill Newton #include <linux/mmc/host.h> 34f95f3850SWill Newton #include <linux/mmc/mmc.h> 3501730558SDoug Anderson #include <linux/mmc/sd.h> 3690c2143aSSeungwon Jeon #include <linux/mmc/sdio.h> 37f95f3850SWill Newton #include <linux/bitops.h> 38c07946a3SJaehoon Chung #include <linux/regulator/consumer.h> 39c91eab4bSThomas Abraham #include <linux/of.h> 4055a6ceb2SDoug Anderson #include <linux/of_gpio.h> 41bf626e55SZhangfei Gao #include <linux/mmc/slot-gpio.h> 42f95f3850SWill Newton 43f95f3850SWill Newton #include "dw_mmc.h" 44f95f3850SWill Newton 45f95f3850SWill Newton /* Common flag combinations */ 463f7eec62SJaehoon Chung #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47f95f3850SWill Newton SDMMC_INT_HTO | SDMMC_INT_SBE | \ 487a3c5677SDoug Anderson SDMMC_INT_EBE | SDMMC_INT_HLE) 49f95f3850SWill Newton #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 507a3c5677SDoug Anderson SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51f95f3850SWill Newton #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 527a3c5677SDoug Anderson DW_MCI_CMD_ERROR_FLAGS) 53f95f3850SWill Newton #define DW_MCI_SEND_STATUS 1 54f95f3850SWill Newton #define DW_MCI_RECV_STATUS 2 55f95f3850SWill Newton #define DW_MCI_DMA_THRESHOLD 16 56f95f3850SWill Newton 571f44a2a5SSeungwon Jeon #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 5872e83577SJaehoon Chung #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 591f44a2a5SSeungwon Jeon 60fc79a4d6SJoonyoung Shim #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63fc79a4d6SJoonyoung Shim SDMMC_IDMAC_INT_TI) 64fc79a4d6SJoonyoung Shim 65cc190d4cSShawn Lin #define DESC_RING_BUF_SZ PAGE_SIZE 66cc190d4cSShawn Lin 6769d99fdcSPrabu Thangamuthu struct idmac_desc_64addr { 6869d99fdcSPrabu Thangamuthu u32 des0; /* Control Descriptor */ 69b6d2d81cSShawn Lin #define IDMAC_OWN_CLR64(x) \ 70b6d2d81cSShawn Lin !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 7169d99fdcSPrabu Thangamuthu 7269d99fdcSPrabu Thangamuthu u32 des1; /* Reserved */ 7369d99fdcSPrabu Thangamuthu 7469d99fdcSPrabu Thangamuthu u32 des2; /*Buffer sizes */ 7569d99fdcSPrabu Thangamuthu #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 766687c42fSBen Dooks ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 776687c42fSBen Dooks ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 7869d99fdcSPrabu Thangamuthu 7969d99fdcSPrabu Thangamuthu u32 des3; /* Reserved */ 8069d99fdcSPrabu Thangamuthu 8169d99fdcSPrabu Thangamuthu u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 8269d99fdcSPrabu Thangamuthu u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 8369d99fdcSPrabu Thangamuthu 8469d99fdcSPrabu Thangamuthu u32 des6; /* Lower 32-bits of Next Descriptor Address */ 8569d99fdcSPrabu Thangamuthu u32 des7; /* Upper 32-bits of Next Descriptor Address */ 8669d99fdcSPrabu Thangamuthu }; 8769d99fdcSPrabu Thangamuthu 88f95f3850SWill Newton struct idmac_desc { 896687c42fSBen Dooks __le32 des0; /* Control Descriptor */ 90f95f3850SWill Newton #define IDMAC_DES0_DIC BIT(1) 91f95f3850SWill Newton #define IDMAC_DES0_LD BIT(2) 92f95f3850SWill Newton #define IDMAC_DES0_FD BIT(3) 93f95f3850SWill Newton #define IDMAC_DES0_CH BIT(4) 94f95f3850SWill Newton #define IDMAC_DES0_ER BIT(5) 95f95f3850SWill Newton #define IDMAC_DES0_CES BIT(30) 96f95f3850SWill Newton #define IDMAC_DES0_OWN BIT(31) 97f95f3850SWill Newton 986687c42fSBen Dooks __le32 des1; /* Buffer sizes */ 99f95f3850SWill Newton #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100e5306c3aSBen Dooks ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101f95f3850SWill Newton 1026687c42fSBen Dooks __le32 des2; /* buffer 1 physical address */ 103f95f3850SWill Newton 1046687c42fSBen Dooks __le32 des3; /* buffer 2 physical address */ 105f95f3850SWill Newton }; 1065959b32eSAlexey Brodkin 1075959b32eSAlexey Brodkin /* Each descriptor can transfer up to 4KB of data in chained mode */ 1085959b32eSAlexey Brodkin #define DW_MCI_DESC_DATA_LENGTH 0x1000 109f95f3850SWill Newton 110f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 111f95f3850SWill Newton static int dw_mci_req_show(struct seq_file *s, void *v) 112f95f3850SWill Newton { 113f95f3850SWill Newton struct dw_mci_slot *slot = s->private; 114f95f3850SWill Newton struct mmc_request *mrq; 115f95f3850SWill Newton struct mmc_command *cmd; 116f95f3850SWill Newton struct mmc_command *stop; 117f95f3850SWill Newton struct mmc_data *data; 118f95f3850SWill Newton 119f95f3850SWill Newton /* Make sure we get a consistent snapshot */ 120f95f3850SWill Newton spin_lock_bh(&slot->host->lock); 121f95f3850SWill Newton mrq = slot->mrq; 122f95f3850SWill Newton 123f95f3850SWill Newton if (mrq) { 124f95f3850SWill Newton cmd = mrq->cmd; 125f95f3850SWill Newton data = mrq->data; 126f95f3850SWill Newton stop = mrq->stop; 127f95f3850SWill Newton 128f95f3850SWill Newton if (cmd) 129f95f3850SWill Newton seq_printf(s, 130f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131f95f3850SWill Newton cmd->opcode, cmd->arg, cmd->flags, 132f95f3850SWill Newton cmd->resp[0], cmd->resp[1], cmd->resp[2], 133f95f3850SWill Newton cmd->resp[2], cmd->error); 134f95f3850SWill Newton if (data) 135f95f3850SWill Newton seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136f95f3850SWill Newton data->bytes_xfered, data->blocks, 137f95f3850SWill Newton data->blksz, data->flags, data->error); 138f95f3850SWill Newton if (stop) 139f95f3850SWill Newton seq_printf(s, 140f95f3850SWill Newton "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141f95f3850SWill Newton stop->opcode, stop->arg, stop->flags, 142f95f3850SWill Newton stop->resp[0], stop->resp[1], stop->resp[2], 143f95f3850SWill Newton stop->resp[2], stop->error); 144f95f3850SWill Newton } 145f95f3850SWill Newton 146f95f3850SWill Newton spin_unlock_bh(&slot->host->lock); 147f95f3850SWill Newton 148f95f3850SWill Newton return 0; 149f95f3850SWill Newton } 150f95f3850SWill Newton 151f95f3850SWill Newton static int dw_mci_req_open(struct inode *inode, struct file *file) 152f95f3850SWill Newton { 153f95f3850SWill Newton return single_open(file, dw_mci_req_show, inode->i_private); 154f95f3850SWill Newton } 155f95f3850SWill Newton 156f95f3850SWill Newton static const struct file_operations dw_mci_req_fops = { 157f95f3850SWill Newton .owner = THIS_MODULE, 158f95f3850SWill Newton .open = dw_mci_req_open, 159f95f3850SWill Newton .read = seq_read, 160f95f3850SWill Newton .llseek = seq_lseek, 161f95f3850SWill Newton .release = single_release, 162f95f3850SWill Newton }; 163f95f3850SWill Newton 164f95f3850SWill Newton static int dw_mci_regs_show(struct seq_file *s, void *v) 165f95f3850SWill Newton { 16621657ebdSJaehoon Chung struct dw_mci *host = s->private; 16721657ebdSJaehoon Chung 16821657ebdSJaehoon Chung seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 16921657ebdSJaehoon Chung seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 17021657ebdSJaehoon Chung seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 17121657ebdSJaehoon Chung seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 17221657ebdSJaehoon Chung seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 17321657ebdSJaehoon Chung seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 174f95f3850SWill Newton 175f95f3850SWill Newton return 0; 176f95f3850SWill Newton } 177f95f3850SWill Newton 178f95f3850SWill Newton static int dw_mci_regs_open(struct inode *inode, struct file *file) 179f95f3850SWill Newton { 180f95f3850SWill Newton return single_open(file, dw_mci_regs_show, inode->i_private); 181f95f3850SWill Newton } 182f95f3850SWill Newton 183f95f3850SWill Newton static const struct file_operations dw_mci_regs_fops = { 184f95f3850SWill Newton .owner = THIS_MODULE, 185f95f3850SWill Newton .open = dw_mci_regs_open, 186f95f3850SWill Newton .read = seq_read, 187f95f3850SWill Newton .llseek = seq_lseek, 188f95f3850SWill Newton .release = single_release, 189f95f3850SWill Newton }; 190f95f3850SWill Newton 191f95f3850SWill Newton static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 192f95f3850SWill Newton { 193f95f3850SWill Newton struct mmc_host *mmc = slot->mmc; 194f95f3850SWill Newton struct dw_mci *host = slot->host; 195f95f3850SWill Newton struct dentry *root; 196f95f3850SWill Newton struct dentry *node; 197f95f3850SWill Newton 198f95f3850SWill Newton root = mmc->debugfs_root; 199f95f3850SWill Newton if (!root) 200f95f3850SWill Newton return; 201f95f3850SWill Newton 202f95f3850SWill Newton node = debugfs_create_file("regs", S_IRUSR, root, host, 203f95f3850SWill Newton &dw_mci_regs_fops); 204f95f3850SWill Newton if (!node) 205f95f3850SWill Newton goto err; 206f95f3850SWill Newton 207f95f3850SWill Newton node = debugfs_create_file("req", S_IRUSR, root, slot, 208f95f3850SWill Newton &dw_mci_req_fops); 209f95f3850SWill Newton if (!node) 210f95f3850SWill Newton goto err; 211f95f3850SWill Newton 212f95f3850SWill Newton node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 213f95f3850SWill Newton if (!node) 214f95f3850SWill Newton goto err; 215f95f3850SWill Newton 216f95f3850SWill Newton node = debugfs_create_x32("pending_events", S_IRUSR, root, 217f95f3850SWill Newton (u32 *)&host->pending_events); 218f95f3850SWill Newton if (!node) 219f95f3850SWill Newton goto err; 220f95f3850SWill Newton 221f95f3850SWill Newton node = debugfs_create_x32("completed_events", S_IRUSR, root, 222f95f3850SWill Newton (u32 *)&host->completed_events); 223f95f3850SWill Newton if (!node) 224f95f3850SWill Newton goto err; 225f95f3850SWill Newton 226f95f3850SWill Newton return; 227f95f3850SWill Newton 228f95f3850SWill Newton err: 229f95f3850SWill Newton dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 230f95f3850SWill Newton } 231f95f3850SWill Newton #endif /* defined(CONFIG_DEBUG_FS) */ 232f95f3850SWill Newton 2338e6db1f6SShawn Lin static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2348e6db1f6SShawn Lin { 2358e6db1f6SShawn Lin u32 ctrl; 2368e6db1f6SShawn Lin 2378e6db1f6SShawn Lin ctrl = mci_readl(host, CTRL); 2388e6db1f6SShawn Lin ctrl |= reset; 2398e6db1f6SShawn Lin mci_writel(host, CTRL, ctrl); 2408e6db1f6SShawn Lin 2418e6db1f6SShawn Lin /* wait till resets clear */ 2428e6db1f6SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 2438e6db1f6SShawn Lin !(ctrl & reset), 2448e6db1f6SShawn Lin 1, 500 * USEC_PER_MSEC)) { 2458e6db1f6SShawn Lin dev_err(host->dev, 2468e6db1f6SShawn Lin "Timeout resetting block (ctrl reset %#x)\n", 2478e6db1f6SShawn Lin ctrl & reset); 2488e6db1f6SShawn Lin return false; 2498e6db1f6SShawn Lin } 2508e6db1f6SShawn Lin 2518e6db1f6SShawn Lin return true; 2528e6db1f6SShawn Lin } 25301730558SDoug Anderson 2544dba18deSShawn Lin static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 2554dba18deSShawn Lin { 2564dba18deSShawn Lin u32 status; 2574dba18deSShawn Lin 2584dba18deSShawn Lin /* 2594dba18deSShawn Lin * Databook says that before issuing a new data transfer command 2604dba18deSShawn Lin * we need to check to see if the card is busy. Data transfer commands 2614dba18deSShawn Lin * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 2624dba18deSShawn Lin * 2634dba18deSShawn Lin * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 2644dba18deSShawn Lin * expected. 2654dba18deSShawn Lin */ 2664dba18deSShawn Lin if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 2674dba18deSShawn Lin !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 2684dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 2694dba18deSShawn Lin status, 2704dba18deSShawn Lin !(status & SDMMC_STATUS_BUSY), 2714dba18deSShawn Lin 10, 500 * USEC_PER_MSEC)) 2724dba18deSShawn Lin dev_err(host->dev, "Busy; trying anyway\n"); 2734dba18deSShawn Lin } 2744dba18deSShawn Lin } 2754dba18deSShawn Lin 2764dba18deSShawn Lin static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 2774dba18deSShawn Lin { 2784dba18deSShawn Lin struct dw_mci *host = slot->host; 2794dba18deSShawn Lin unsigned int cmd_status = 0; 2804dba18deSShawn Lin 2814dba18deSShawn Lin mci_writel(host, CMDARG, arg); 2824dba18deSShawn Lin wmb(); /* drain writebuffer */ 2834dba18deSShawn Lin dw_mci_wait_while_busy(host, cmd); 2844dba18deSShawn Lin mci_writel(host, CMD, SDMMC_CMD_START | cmd); 2854dba18deSShawn Lin 2864dba18deSShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 2874dba18deSShawn Lin !(cmd_status & SDMMC_CMD_START), 2884dba18deSShawn Lin 1, 500 * USEC_PER_MSEC)) 2894dba18deSShawn Lin dev_err(&slot->mmc->class_dev, 2904dba18deSShawn Lin "Timeout sending command (cmd %#x arg %#x status %#x)\n", 2914dba18deSShawn Lin cmd, arg, cmd_status); 2924dba18deSShawn Lin } 2934dba18deSShawn Lin 294f95f3850SWill Newton static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 295f95f3850SWill Newton { 296800d78bfSThomas Abraham struct dw_mci_slot *slot = mmc_priv(mmc); 29701730558SDoug Anderson struct dw_mci *host = slot->host; 298f95f3850SWill Newton u32 cmdr; 299f95f3850SWill Newton 3000e3a22c0SShawn Lin cmd->error = -EINPROGRESS; 301f95f3850SWill Newton cmdr = cmd->opcode; 302f95f3850SWill Newton 30390c2143aSSeungwon Jeon if (cmd->opcode == MMC_STOP_TRANSMISSION || 30490c2143aSSeungwon Jeon cmd->opcode == MMC_GO_IDLE_STATE || 30590c2143aSSeungwon Jeon cmd->opcode == MMC_GO_INACTIVE_STATE || 30690c2143aSSeungwon Jeon (cmd->opcode == SD_IO_RW_DIRECT && 30790c2143aSSeungwon Jeon ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 308f95f3850SWill Newton cmdr |= SDMMC_CMD_STOP; 3094a1b27adSJaehoon Chung else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 310f95f3850SWill Newton cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 311f95f3850SWill Newton 31201730558SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 31301730558SDoug Anderson u32 clk_en_a; 31401730558SDoug Anderson 31501730558SDoug Anderson /* Special bit makes CMD11 not die */ 31601730558SDoug Anderson cmdr |= SDMMC_CMD_VOLT_SWITCH; 31701730558SDoug Anderson 31801730558SDoug Anderson /* Change state to continue to handle CMD11 weirdness */ 31901730558SDoug Anderson WARN_ON(slot->host->state != STATE_SENDING_CMD); 32001730558SDoug Anderson slot->host->state = STATE_SENDING_CMD11; 32101730558SDoug Anderson 32201730558SDoug Anderson /* 32301730558SDoug Anderson * We need to disable low power mode (automatic clock stop) 32401730558SDoug Anderson * while doing voltage switch so we don't confuse the card, 32501730558SDoug Anderson * since stopping the clock is a specific part of the UHS 32601730558SDoug Anderson * voltage change dance. 32701730558SDoug Anderson * 32801730558SDoug Anderson * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 32901730558SDoug Anderson * unconditionally turned back on in dw_mci_setup_bus() if it's 33001730558SDoug Anderson * ever called with a non-zero clock. That shouldn't happen 33101730558SDoug Anderson * until the voltage change is all done. 33201730558SDoug Anderson */ 33301730558SDoug Anderson clk_en_a = mci_readl(host, CLKENA); 33401730558SDoug Anderson clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 33501730558SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 33601730558SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 33701730558SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 33801730558SDoug Anderson } 33901730558SDoug Anderson 340f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 341f95f3850SWill Newton /* We expect a response, so set this bit */ 342f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_EXP; 343f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) 344f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_LONG; 345f95f3850SWill Newton } 346f95f3850SWill Newton 347f95f3850SWill Newton if (cmd->flags & MMC_RSP_CRC) 348f95f3850SWill Newton cmdr |= SDMMC_CMD_RESP_CRC; 349f95f3850SWill Newton 3500349c085SJaehoon Chung if (cmd->data) { 351f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_EXP; 3520349c085SJaehoon Chung if (cmd->data->flags & MMC_DATA_WRITE) 353f95f3850SWill Newton cmdr |= SDMMC_CMD_DAT_WR; 354f95f3850SWill Newton } 355f95f3850SWill Newton 356aaaaeb7aSJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 357aaaaeb7aSJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 358800d78bfSThomas Abraham 359f95f3850SWill Newton return cmdr; 360f95f3850SWill Newton } 361f95f3850SWill Newton 36290c2143aSSeungwon Jeon static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 36390c2143aSSeungwon Jeon { 36490c2143aSSeungwon Jeon struct mmc_command *stop; 36590c2143aSSeungwon Jeon u32 cmdr; 36690c2143aSSeungwon Jeon 36790c2143aSSeungwon Jeon if (!cmd->data) 36890c2143aSSeungwon Jeon return 0; 36990c2143aSSeungwon Jeon 37090c2143aSSeungwon Jeon stop = &host->stop_abort; 37190c2143aSSeungwon Jeon cmdr = cmd->opcode; 37290c2143aSSeungwon Jeon memset(stop, 0, sizeof(struct mmc_command)); 37390c2143aSSeungwon Jeon 37490c2143aSSeungwon Jeon if (cmdr == MMC_READ_SINGLE_BLOCK || 37590c2143aSSeungwon Jeon cmdr == MMC_READ_MULTIPLE_BLOCK || 37690c2143aSSeungwon Jeon cmdr == MMC_WRITE_BLOCK || 3776c2c6506SUlf Hansson cmdr == MMC_WRITE_MULTIPLE_BLOCK || 3786c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK || 3796c2c6506SUlf Hansson cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 38090c2143aSSeungwon Jeon stop->opcode = MMC_STOP_TRANSMISSION; 38190c2143aSSeungwon Jeon stop->arg = 0; 38290c2143aSSeungwon Jeon stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 38390c2143aSSeungwon Jeon } else if (cmdr == SD_IO_RW_EXTENDED) { 38490c2143aSSeungwon Jeon stop->opcode = SD_IO_RW_DIRECT; 38590c2143aSSeungwon Jeon stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 38690c2143aSSeungwon Jeon ((cmd->arg >> 28) & 0x7); 38790c2143aSSeungwon Jeon stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 38890c2143aSSeungwon Jeon } else { 38990c2143aSSeungwon Jeon return 0; 39090c2143aSSeungwon Jeon } 39190c2143aSSeungwon Jeon 39290c2143aSSeungwon Jeon cmdr = stop->opcode | SDMMC_CMD_STOP | 39390c2143aSSeungwon Jeon SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 39490c2143aSSeungwon Jeon 39542f989c0SJaehoon Chung if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 3968c005b40SJaehoon Chung cmdr |= SDMMC_CMD_USE_HOLD_REG; 3978c005b40SJaehoon Chung 39890c2143aSSeungwon Jeon return cmdr; 39990c2143aSSeungwon Jeon } 40090c2143aSSeungwon Jeon 401*03de1921SAddy Ke static inline void dw_mci_set_cto(struct dw_mci *host) 402*03de1921SAddy Ke { 403*03de1921SAddy Ke unsigned int cto_clks; 404*03de1921SAddy Ke unsigned int cto_ms; 405*03de1921SAddy Ke 406*03de1921SAddy Ke cto_clks = mci_readl(host, TMOUT) & 0xff; 407*03de1921SAddy Ke cto_ms = DIV_ROUND_UP(cto_clks, host->bus_hz / 1000); 408*03de1921SAddy Ke 409*03de1921SAddy Ke /* add a bit spare time */ 410*03de1921SAddy Ke cto_ms += 10; 411*03de1921SAddy Ke 412*03de1921SAddy Ke mod_timer(&host->cto_timer, 413*03de1921SAddy Ke jiffies + msecs_to_jiffies(cto_ms) + 1); 414*03de1921SAddy Ke } 415*03de1921SAddy Ke 416f95f3850SWill Newton static void dw_mci_start_command(struct dw_mci *host, 417f95f3850SWill Newton struct mmc_command *cmd, u32 cmd_flags) 418f95f3850SWill Newton { 419f95f3850SWill Newton host->cmd = cmd; 4204a90920cSThomas Abraham dev_vdbg(host->dev, 421f95f3850SWill Newton "start command: ARGR=0x%08x CMDR=0x%08x\n", 422f95f3850SWill Newton cmd->arg, cmd_flags); 423f95f3850SWill Newton 424f95f3850SWill Newton mci_writel(host, CMDARG, cmd->arg); 4250e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 4260bdbd0e8SDoug Anderson dw_mci_wait_while_busy(host, cmd_flags); 427f95f3850SWill Newton 428*03de1921SAddy Ke /* response expected command only */ 429*03de1921SAddy Ke if (cmd_flags & SDMMC_CMD_RESP_EXP) 430*03de1921SAddy Ke dw_mci_set_cto(host); 431*03de1921SAddy Ke 432f95f3850SWill Newton mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 433f95f3850SWill Newton } 434f95f3850SWill Newton 43590c2143aSSeungwon Jeon static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 436f95f3850SWill Newton { 437e13c3c08SJaehoon Chung struct mmc_command *stop = &host->stop_abort; 4380e3a22c0SShawn Lin 43990c2143aSSeungwon Jeon dw_mci_start_command(host, stop, host->stop_cmdr); 440f95f3850SWill Newton } 441f95f3850SWill Newton 442f95f3850SWill Newton /* DMA interface functions */ 443f95f3850SWill Newton static void dw_mci_stop_dma(struct dw_mci *host) 444f95f3850SWill Newton { 44503e8cb53SJames Hogan if (host->using_dma) { 446f95f3850SWill Newton host->dma_ops->stop(host); 447f95f3850SWill Newton host->dma_ops->cleanup(host); 448aa50f259SSeungwon Jeon } 449aa50f259SSeungwon Jeon 450f95f3850SWill Newton /* Data transfer was stopped by the interrupt handler */ 451f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 452f95f3850SWill Newton } 453f95f3850SWill Newton 454f95f3850SWill Newton static void dw_mci_dma_cleanup(struct dw_mci *host) 455f95f3850SWill Newton { 456f95f3850SWill Newton struct mmc_data *data = host->data; 457f95f3850SWill Newton 458a4cc7eb4SJaehoon Chung if (data && data->host_cookie == COOKIE_MAPPED) { 4594a90920cSThomas Abraham dma_unmap_sg(host->dev, 4609aa51408SSeungwon Jeon data->sg, 4619aa51408SSeungwon Jeon data->sg_len, 462feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 463a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 464a4cc7eb4SJaehoon Chung } 465f95f3850SWill Newton } 466f95f3850SWill Newton 4675ce9d961SSeungwon Jeon static void dw_mci_idmac_reset(struct dw_mci *host) 4685ce9d961SSeungwon Jeon { 4695ce9d961SSeungwon Jeon u32 bmod = mci_readl(host, BMOD); 4705ce9d961SSeungwon Jeon /* Software reset of DMA */ 4715ce9d961SSeungwon Jeon bmod |= SDMMC_IDMAC_SWRESET; 4725ce9d961SSeungwon Jeon mci_writel(host, BMOD, bmod); 4735ce9d961SSeungwon Jeon } 4745ce9d961SSeungwon Jeon 475f95f3850SWill Newton static void dw_mci_idmac_stop_dma(struct dw_mci *host) 476f95f3850SWill Newton { 477f95f3850SWill Newton u32 temp; 478f95f3850SWill Newton 479f95f3850SWill Newton /* Disable and reset the IDMAC interface */ 480f95f3850SWill Newton temp = mci_readl(host, CTRL); 481f95f3850SWill Newton temp &= ~SDMMC_CTRL_USE_IDMAC; 482f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_RESET; 483f95f3850SWill Newton mci_writel(host, CTRL, temp); 484f95f3850SWill Newton 485f95f3850SWill Newton /* Stop the IDMAC running */ 486f95f3850SWill Newton temp = mci_readl(host, BMOD); 487a5289a43SJaehoon Chung temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 4885ce9d961SSeungwon Jeon temp |= SDMMC_IDMAC_SWRESET; 489f95f3850SWill Newton mci_writel(host, BMOD, temp); 490f95f3850SWill Newton } 491f95f3850SWill Newton 4923fc7eaefSShawn Lin static void dw_mci_dmac_complete_dma(void *arg) 493f95f3850SWill Newton { 4943fc7eaefSShawn Lin struct dw_mci *host = arg; 495f95f3850SWill Newton struct mmc_data *data = host->data; 496f95f3850SWill Newton 4974a90920cSThomas Abraham dev_vdbg(host->dev, "DMA complete\n"); 498f95f3850SWill Newton 4993fc7eaefSShawn Lin if ((host->use_dma == TRANS_MODE_EDMAC) && 5003fc7eaefSShawn Lin data && (data->flags & MMC_DATA_READ)) 5013fc7eaefSShawn Lin /* Invalidate cache after read */ 50242f989c0SJaehoon Chung dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 5033fc7eaefSShawn Lin data->sg, 5043fc7eaefSShawn Lin data->sg_len, 5053fc7eaefSShawn Lin DMA_FROM_DEVICE); 5063fc7eaefSShawn Lin 507f95f3850SWill Newton host->dma_ops->cleanup(host); 508f95f3850SWill Newton 509f95f3850SWill Newton /* 510f95f3850SWill Newton * If the card was removed, data will be NULL. No point in trying to 511f95f3850SWill Newton * send the stop command or waiting for NBUSY in this case. 512f95f3850SWill Newton */ 513f95f3850SWill Newton if (data) { 514f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 515f95f3850SWill Newton tasklet_schedule(&host->tasklet); 516f95f3850SWill Newton } 517f95f3850SWill Newton } 518f95f3850SWill Newton 519f95f3850SWill Newton static int dw_mci_idmac_init(struct dw_mci *host) 520f95f3850SWill Newton { 521897b69e7SSeungwon Jeon int i; 522f95f3850SWill Newton 52369d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 52469d99fdcSPrabu Thangamuthu struct idmac_desc_64addr *p; 52569d99fdcSPrabu Thangamuthu /* Number of descriptors in the ring buffer */ 526cc190d4cSShawn Lin host->ring_size = 527cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 52869d99fdcSPrabu Thangamuthu 52969d99fdcSPrabu Thangamuthu /* Forward link the descriptor list */ 53069d99fdcSPrabu Thangamuthu for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 53169d99fdcSPrabu Thangamuthu i++, p++) { 53269d99fdcSPrabu Thangamuthu p->des6 = (host->sg_dma + 53369d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 53469d99fdcSPrabu Thangamuthu (i + 1))) & 0xffffffff; 53569d99fdcSPrabu Thangamuthu 53669d99fdcSPrabu Thangamuthu p->des7 = (u64)(host->sg_dma + 53769d99fdcSPrabu Thangamuthu (sizeof(struct idmac_desc_64addr) * 53869d99fdcSPrabu Thangamuthu (i + 1))) >> 32; 53969d99fdcSPrabu Thangamuthu /* Initialize reserved and buffer size fields to "0" */ 54069d99fdcSPrabu Thangamuthu p->des1 = 0; 54169d99fdcSPrabu Thangamuthu p->des2 = 0; 54269d99fdcSPrabu Thangamuthu p->des3 = 0; 54369d99fdcSPrabu Thangamuthu } 54469d99fdcSPrabu Thangamuthu 54569d99fdcSPrabu Thangamuthu /* Set the last descriptor as the end-of-ring descriptor */ 54669d99fdcSPrabu Thangamuthu p->des6 = host->sg_dma & 0xffffffff; 54769d99fdcSPrabu Thangamuthu p->des7 = (u64)host->sg_dma >> 32; 54869d99fdcSPrabu Thangamuthu p->des0 = IDMAC_DES0_ER; 54969d99fdcSPrabu Thangamuthu 55069d99fdcSPrabu Thangamuthu } else { 55169d99fdcSPrabu Thangamuthu struct idmac_desc *p; 552f95f3850SWill Newton /* Number of descriptors in the ring buffer */ 553cc190d4cSShawn Lin host->ring_size = 554cc190d4cSShawn Lin DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 555f95f3850SWill Newton 556f95f3850SWill Newton /* Forward link the descriptor list */ 5570e3a22c0SShawn Lin for (i = 0, p = host->sg_cpu; 5580e3a22c0SShawn Lin i < host->ring_size - 1; 5590e3a22c0SShawn Lin i++, p++) { 5606687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma + 5616687c42fSBen Dooks (sizeof(struct idmac_desc) * (i + 1))); 5624b244724SZhangfei Gao p->des1 = 0; 5634b244724SZhangfei Gao } 564f95f3850SWill Newton 565f95f3850SWill Newton /* Set the last descriptor as the end-of-ring descriptor */ 5666687c42fSBen Dooks p->des3 = cpu_to_le32(host->sg_dma); 5676687c42fSBen Dooks p->des0 = cpu_to_le32(IDMAC_DES0_ER); 56869d99fdcSPrabu Thangamuthu } 569f95f3850SWill Newton 5705ce9d961SSeungwon Jeon dw_mci_idmac_reset(host); 571141a712aSSeungwon Jeon 57269d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 57369d99fdcSPrabu Thangamuthu /* Mask out interrupts - get Tx & Rx complete only */ 57469d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, IDMAC_INT_CLR); 57569d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 57669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 57769d99fdcSPrabu Thangamuthu 57869d99fdcSPrabu Thangamuthu /* Set the descriptor base address */ 57969d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 58069d99fdcSPrabu Thangamuthu mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 58169d99fdcSPrabu Thangamuthu 58269d99fdcSPrabu Thangamuthu } else { 583f95f3850SWill Newton /* Mask out interrupts - get Tx & Rx complete only */ 584fc79a4d6SJoonyoung Shim mci_writel(host, IDSTS, IDMAC_INT_CLR); 58569d99fdcSPrabu Thangamuthu mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 58669d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 587f95f3850SWill Newton 588f95f3850SWill Newton /* Set the descriptor base address */ 589f95f3850SWill Newton mci_writel(host, DBADDR, host->sg_dma); 59069d99fdcSPrabu Thangamuthu } 59169d99fdcSPrabu Thangamuthu 592f95f3850SWill Newton return 0; 593f95f3850SWill Newton } 594f95f3850SWill Newton 5953b2a067bSShawn Lin static inline int dw_mci_prepare_desc64(struct dw_mci *host, 5963b2a067bSShawn Lin struct mmc_data *data, 5973b2a067bSShawn Lin unsigned int sg_len) 5983b2a067bSShawn Lin { 5993b2a067bSShawn Lin unsigned int desc_len; 6003b2a067bSShawn Lin struct idmac_desc_64addr *desc_first, *desc_last, *desc; 601b6d2d81cSShawn Lin u32 val; 6023b2a067bSShawn Lin int i; 6033b2a067bSShawn Lin 6043b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6053b2a067bSShawn Lin 6063b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6073b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6083b2a067bSShawn Lin 6093b2a067bSShawn Lin u64 mem_addr = sg_dma_address(&data->sg[i]); 6103b2a067bSShawn Lin 6113b2a067bSShawn Lin for ( ; length ; desc++) { 6123b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6133b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6143b2a067bSShawn Lin 6153b2a067bSShawn Lin length -= desc_len; 6163b2a067bSShawn Lin 6173b2a067bSShawn Lin /* 6183b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6193b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6203b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6213b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6223b2a067bSShawn Lin */ 623b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 624b6d2d81cSShawn Lin !(val & IDMAC_DES0_OWN), 625b6d2d81cSShawn Lin 10, 100 * USEC_PER_MSEC)) 6263b2a067bSShawn Lin goto err_own_bit; 6273b2a067bSShawn Lin 6283b2a067bSShawn Lin /* 6293b2a067bSShawn Lin * Set the OWN bit and disable interrupts 6303b2a067bSShawn Lin * for this descriptor 6313b2a067bSShawn Lin */ 6323b2a067bSShawn Lin desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 6333b2a067bSShawn Lin IDMAC_DES0_CH; 6343b2a067bSShawn Lin 6353b2a067bSShawn Lin /* Buffer length */ 6363b2a067bSShawn Lin IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 6373b2a067bSShawn Lin 6383b2a067bSShawn Lin /* Physical address to DMA to/from */ 6393b2a067bSShawn Lin desc->des4 = mem_addr & 0xffffffff; 6403b2a067bSShawn Lin desc->des5 = mem_addr >> 32; 6413b2a067bSShawn Lin 6423b2a067bSShawn Lin /* Update physical address for the next desc */ 6433b2a067bSShawn Lin mem_addr += desc_len; 6443b2a067bSShawn Lin 6453b2a067bSShawn Lin /* Save pointer to the last descriptor */ 6463b2a067bSShawn Lin desc_last = desc; 6473b2a067bSShawn Lin } 6483b2a067bSShawn Lin } 6493b2a067bSShawn Lin 6503b2a067bSShawn Lin /* Set first descriptor */ 6513b2a067bSShawn Lin desc_first->des0 |= IDMAC_DES0_FD; 6523b2a067bSShawn Lin 6533b2a067bSShawn Lin /* Set last descriptor */ 6543b2a067bSShawn Lin desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 6553b2a067bSShawn Lin desc_last->des0 |= IDMAC_DES0_LD; 6563b2a067bSShawn Lin 6573b2a067bSShawn Lin return 0; 6583b2a067bSShawn Lin err_own_bit: 6593b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 66026be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 661cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 6623b2a067bSShawn Lin dw_mci_idmac_init(host); 6633b2a067bSShawn Lin return -EINVAL; 6643b2a067bSShawn Lin } 6653b2a067bSShawn Lin 6663b2a067bSShawn Lin 6673b2a067bSShawn Lin static inline int dw_mci_prepare_desc32(struct dw_mci *host, 6683b2a067bSShawn Lin struct mmc_data *data, 6693b2a067bSShawn Lin unsigned int sg_len) 6703b2a067bSShawn Lin { 6713b2a067bSShawn Lin unsigned int desc_len; 6723b2a067bSShawn Lin struct idmac_desc *desc_first, *desc_last, *desc; 673b6d2d81cSShawn Lin u32 val; 6743b2a067bSShawn Lin int i; 6753b2a067bSShawn Lin 6763b2a067bSShawn Lin desc_first = desc_last = desc = host->sg_cpu; 6773b2a067bSShawn Lin 6783b2a067bSShawn Lin for (i = 0; i < sg_len; i++) { 6793b2a067bSShawn Lin unsigned int length = sg_dma_len(&data->sg[i]); 6803b2a067bSShawn Lin 6813b2a067bSShawn Lin u32 mem_addr = sg_dma_address(&data->sg[i]); 6823b2a067bSShawn Lin 6833b2a067bSShawn Lin for ( ; length ; desc++) { 6843b2a067bSShawn Lin desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 6853b2a067bSShawn Lin length : DW_MCI_DESC_DATA_LENGTH; 6863b2a067bSShawn Lin 6873b2a067bSShawn Lin length -= desc_len; 6883b2a067bSShawn Lin 6893b2a067bSShawn Lin /* 6903b2a067bSShawn Lin * Wait for the former clear OWN bit operation 6913b2a067bSShawn Lin * of IDMAC to make sure that this descriptor 6923b2a067bSShawn Lin * isn't still owned by IDMAC as IDMAC's write 6933b2a067bSShawn Lin * ops and CPU's read ops are asynchronous. 6943b2a067bSShawn Lin */ 695b6d2d81cSShawn Lin if (readl_poll_timeout_atomic(&desc->des0, val, 696b6d2d81cSShawn Lin IDMAC_OWN_CLR64(val), 697b6d2d81cSShawn Lin 10, 698b6d2d81cSShawn Lin 100 * USEC_PER_MSEC)) 6993b2a067bSShawn Lin goto err_own_bit; 7003b2a067bSShawn Lin 7013b2a067bSShawn Lin /* 7023b2a067bSShawn Lin * Set the OWN bit and disable interrupts 7033b2a067bSShawn Lin * for this descriptor 7043b2a067bSShawn Lin */ 7053b2a067bSShawn Lin desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 7063b2a067bSShawn Lin IDMAC_DES0_DIC | 7073b2a067bSShawn Lin IDMAC_DES0_CH); 7083b2a067bSShawn Lin 7093b2a067bSShawn Lin /* Buffer length */ 7103b2a067bSShawn Lin IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 7113b2a067bSShawn Lin 7123b2a067bSShawn Lin /* Physical address to DMA to/from */ 7133b2a067bSShawn Lin desc->des2 = cpu_to_le32(mem_addr); 7143b2a067bSShawn Lin 7153b2a067bSShawn Lin /* Update physical address for the next desc */ 7163b2a067bSShawn Lin mem_addr += desc_len; 7173b2a067bSShawn Lin 7183b2a067bSShawn Lin /* Save pointer to the last descriptor */ 7193b2a067bSShawn Lin desc_last = desc; 7203b2a067bSShawn Lin } 7213b2a067bSShawn Lin } 7223b2a067bSShawn Lin 7233b2a067bSShawn Lin /* Set first descriptor */ 7243b2a067bSShawn Lin desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 7253b2a067bSShawn Lin 7263b2a067bSShawn Lin /* Set last descriptor */ 7273b2a067bSShawn Lin desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 7283b2a067bSShawn Lin IDMAC_DES0_DIC)); 7293b2a067bSShawn Lin desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 7303b2a067bSShawn Lin 7313b2a067bSShawn Lin return 0; 7323b2a067bSShawn Lin err_own_bit: 7333b2a067bSShawn Lin /* restore the descriptor chain as it's polluted */ 73426be9d70SColin Ian King dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 735cc190d4cSShawn Lin memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 7363b2a067bSShawn Lin dw_mci_idmac_init(host); 7373b2a067bSShawn Lin return -EINVAL; 7383b2a067bSShawn Lin } 7393b2a067bSShawn Lin 7403b2a067bSShawn Lin static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 7413b2a067bSShawn Lin { 7423b2a067bSShawn Lin u32 temp; 7433b2a067bSShawn Lin int ret; 7443b2a067bSShawn Lin 7453b2a067bSShawn Lin if (host->dma_64bit_address == 1) 7463b2a067bSShawn Lin ret = dw_mci_prepare_desc64(host, host->data, sg_len); 7473b2a067bSShawn Lin else 7483b2a067bSShawn Lin ret = dw_mci_prepare_desc32(host, host->data, sg_len); 7493b2a067bSShawn Lin 7503b2a067bSShawn Lin if (ret) 7513b2a067bSShawn Lin goto out; 7523b2a067bSShawn Lin 7533b2a067bSShawn Lin /* drain writebuffer */ 7543b2a067bSShawn Lin wmb(); 7553b2a067bSShawn Lin 7563b2a067bSShawn Lin /* Make sure to reset DMA in case we did PIO before this */ 7573b2a067bSShawn Lin dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 7583b2a067bSShawn Lin dw_mci_idmac_reset(host); 7593b2a067bSShawn Lin 7603b2a067bSShawn Lin /* Select IDMAC interface */ 7613b2a067bSShawn Lin temp = mci_readl(host, CTRL); 7623b2a067bSShawn Lin temp |= SDMMC_CTRL_USE_IDMAC; 7633b2a067bSShawn Lin mci_writel(host, CTRL, temp); 7643b2a067bSShawn Lin 7653b2a067bSShawn Lin /* drain writebuffer */ 7663b2a067bSShawn Lin wmb(); 7673b2a067bSShawn Lin 7683b2a067bSShawn Lin /* Enable the IDMAC */ 7693b2a067bSShawn Lin temp = mci_readl(host, BMOD); 7703b2a067bSShawn Lin temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 7713b2a067bSShawn Lin mci_writel(host, BMOD, temp); 7723b2a067bSShawn Lin 7733b2a067bSShawn Lin /* Start it running */ 7743b2a067bSShawn Lin mci_writel(host, PLDMND, 1); 7753b2a067bSShawn Lin 7763b2a067bSShawn Lin out: 7773b2a067bSShawn Lin return ret; 7783b2a067bSShawn Lin } 7793b2a067bSShawn Lin 7808e2b36eaSArnd Bergmann static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 781885c3e80SSeungwon Jeon .init = dw_mci_idmac_init, 782885c3e80SSeungwon Jeon .start = dw_mci_idmac_start_dma, 783885c3e80SSeungwon Jeon .stop = dw_mci_idmac_stop_dma, 7843fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 785885c3e80SSeungwon Jeon .cleanup = dw_mci_dma_cleanup, 786885c3e80SSeungwon Jeon }; 7873fc7eaefSShawn Lin 7883fc7eaefSShawn Lin static void dw_mci_edmac_stop_dma(struct dw_mci *host) 7893fc7eaefSShawn Lin { 790ab925a31SShawn Lin dmaengine_terminate_async(host->dms->ch); 7913fc7eaefSShawn Lin } 7923fc7eaefSShawn Lin 7933fc7eaefSShawn Lin static int dw_mci_edmac_start_dma(struct dw_mci *host, 7943fc7eaefSShawn Lin unsigned int sg_len) 7953fc7eaefSShawn Lin { 7963fc7eaefSShawn Lin struct dma_slave_config cfg; 7973fc7eaefSShawn Lin struct dma_async_tx_descriptor *desc = NULL; 7983fc7eaefSShawn Lin struct scatterlist *sgl = host->data->sg; 7993fc7eaefSShawn Lin const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 8003fc7eaefSShawn Lin u32 sg_elems = host->data->sg_len; 8013fc7eaefSShawn Lin u32 fifoth_val; 8023fc7eaefSShawn Lin u32 fifo_offset = host->fifo_reg - host->regs; 8033fc7eaefSShawn Lin int ret = 0; 8043fc7eaefSShawn Lin 8053fc7eaefSShawn Lin /* Set external dma config: burst size, burst width */ 806260b3164SArnd Bergmann cfg.dst_addr = host->phy_regs + fifo_offset; 8073fc7eaefSShawn Lin cfg.src_addr = cfg.dst_addr; 8083fc7eaefSShawn Lin cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 8093fc7eaefSShawn Lin cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 8103fc7eaefSShawn Lin 8113fc7eaefSShawn Lin /* Match burst msize with external dma config */ 8123fc7eaefSShawn Lin fifoth_val = mci_readl(host, FIFOTH); 8133fc7eaefSShawn Lin cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 8143fc7eaefSShawn Lin cfg.src_maxburst = cfg.dst_maxburst; 8153fc7eaefSShawn Lin 8163fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 8173fc7eaefSShawn Lin cfg.direction = DMA_MEM_TO_DEV; 8183fc7eaefSShawn Lin else 8193fc7eaefSShawn Lin cfg.direction = DMA_DEV_TO_MEM; 8203fc7eaefSShawn Lin 8213fc7eaefSShawn Lin ret = dmaengine_slave_config(host->dms->ch, &cfg); 8223fc7eaefSShawn Lin if (ret) { 8233fc7eaefSShawn Lin dev_err(host->dev, "Failed to config edmac.\n"); 8243fc7eaefSShawn Lin return -EBUSY; 8253fc7eaefSShawn Lin } 8263fc7eaefSShawn Lin 8273fc7eaefSShawn Lin desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 8283fc7eaefSShawn Lin sg_len, cfg.direction, 8293fc7eaefSShawn Lin DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 8303fc7eaefSShawn Lin if (!desc) { 8313fc7eaefSShawn Lin dev_err(host->dev, "Can't prepare slave sg.\n"); 8323fc7eaefSShawn Lin return -EBUSY; 8333fc7eaefSShawn Lin } 8343fc7eaefSShawn Lin 8353fc7eaefSShawn Lin /* Set dw_mci_dmac_complete_dma as callback */ 8363fc7eaefSShawn Lin desc->callback = dw_mci_dmac_complete_dma; 8373fc7eaefSShawn Lin desc->callback_param = (void *)host; 8383fc7eaefSShawn Lin dmaengine_submit(desc); 8393fc7eaefSShawn Lin 8403fc7eaefSShawn Lin /* Flush cache before write */ 8413fc7eaefSShawn Lin if (host->data->flags & MMC_DATA_WRITE) 84242f989c0SJaehoon Chung dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 8433fc7eaefSShawn Lin sg_elems, DMA_TO_DEVICE); 8443fc7eaefSShawn Lin 8453fc7eaefSShawn Lin dma_async_issue_pending(host->dms->ch); 8463fc7eaefSShawn Lin 8473fc7eaefSShawn Lin return 0; 8483fc7eaefSShawn Lin } 8493fc7eaefSShawn Lin 8503fc7eaefSShawn Lin static int dw_mci_edmac_init(struct dw_mci *host) 8513fc7eaefSShawn Lin { 8523fc7eaefSShawn Lin /* Request external dma channel */ 8533fc7eaefSShawn Lin host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 8543fc7eaefSShawn Lin if (!host->dms) 8553fc7eaefSShawn Lin return -ENOMEM; 8563fc7eaefSShawn Lin 8573fc7eaefSShawn Lin host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 8583fc7eaefSShawn Lin if (!host->dms->ch) { 8594539d36eSDan Carpenter dev_err(host->dev, "Failed to get external DMA channel.\n"); 8603fc7eaefSShawn Lin kfree(host->dms); 8613fc7eaefSShawn Lin host->dms = NULL; 8623fc7eaefSShawn Lin return -ENXIO; 8633fc7eaefSShawn Lin } 8643fc7eaefSShawn Lin 8653fc7eaefSShawn Lin return 0; 8663fc7eaefSShawn Lin } 8673fc7eaefSShawn Lin 8683fc7eaefSShawn Lin static void dw_mci_edmac_exit(struct dw_mci *host) 8693fc7eaefSShawn Lin { 8703fc7eaefSShawn Lin if (host->dms) { 8713fc7eaefSShawn Lin if (host->dms->ch) { 8723fc7eaefSShawn Lin dma_release_channel(host->dms->ch); 8733fc7eaefSShawn Lin host->dms->ch = NULL; 8743fc7eaefSShawn Lin } 8753fc7eaefSShawn Lin kfree(host->dms); 8763fc7eaefSShawn Lin host->dms = NULL; 8773fc7eaefSShawn Lin } 8783fc7eaefSShawn Lin } 8793fc7eaefSShawn Lin 8803fc7eaefSShawn Lin static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 8813fc7eaefSShawn Lin .init = dw_mci_edmac_init, 8823fc7eaefSShawn Lin .exit = dw_mci_edmac_exit, 8833fc7eaefSShawn Lin .start = dw_mci_edmac_start_dma, 8843fc7eaefSShawn Lin .stop = dw_mci_edmac_stop_dma, 8853fc7eaefSShawn Lin .complete = dw_mci_dmac_complete_dma, 8863fc7eaefSShawn Lin .cleanup = dw_mci_dma_cleanup, 8873fc7eaefSShawn Lin }; 888885c3e80SSeungwon Jeon 8899aa51408SSeungwon Jeon static int dw_mci_pre_dma_transfer(struct dw_mci *host, 8909aa51408SSeungwon Jeon struct mmc_data *data, 891a4cc7eb4SJaehoon Chung int cookie) 892f95f3850SWill Newton { 893f95f3850SWill Newton struct scatterlist *sg; 8949aa51408SSeungwon Jeon unsigned int i, sg_len; 895f95f3850SWill Newton 896a4cc7eb4SJaehoon Chung if (data->host_cookie == COOKIE_PRE_MAPPED) 897a4cc7eb4SJaehoon Chung return data->sg_len; 898f95f3850SWill Newton 899f95f3850SWill Newton /* 900f95f3850SWill Newton * We don't do DMA on "complex" transfers, i.e. with 901f95f3850SWill Newton * non-word-aligned buffers or lengths. Also, we don't bother 902f95f3850SWill Newton * with all the DMA setup overhead for short transfers. 903f95f3850SWill Newton */ 904f95f3850SWill Newton if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 905f95f3850SWill Newton return -EINVAL; 9069aa51408SSeungwon Jeon 907f95f3850SWill Newton if (data->blksz & 3) 908f95f3850SWill Newton return -EINVAL; 909f95f3850SWill Newton 910f95f3850SWill Newton for_each_sg(data->sg, sg, data->sg_len, i) { 911f95f3850SWill Newton if (sg->offset & 3 || sg->length & 3) 912f95f3850SWill Newton return -EINVAL; 913f95f3850SWill Newton } 914f95f3850SWill Newton 9154a90920cSThomas Abraham sg_len = dma_map_sg(host->dev, 9169aa51408SSeungwon Jeon data->sg, 9179aa51408SSeungwon Jeon data->sg_len, 918feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 9199aa51408SSeungwon Jeon if (sg_len == 0) 9209aa51408SSeungwon Jeon return -EINVAL; 9219aa51408SSeungwon Jeon 922a4cc7eb4SJaehoon Chung data->host_cookie = cookie; 9239aa51408SSeungwon Jeon 9249aa51408SSeungwon Jeon return sg_len; 9259aa51408SSeungwon Jeon } 9269aa51408SSeungwon Jeon 9279aa51408SSeungwon Jeon static void dw_mci_pre_req(struct mmc_host *mmc, 928d3c6aac3SLinus Walleij struct mmc_request *mrq) 9299aa51408SSeungwon Jeon { 9309aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9319aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9329aa51408SSeungwon Jeon 9339aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9349aa51408SSeungwon Jeon return; 9359aa51408SSeungwon Jeon 936a4cc7eb4SJaehoon Chung /* This data might be unmapped at this time */ 937a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9389aa51408SSeungwon Jeon 939a4cc7eb4SJaehoon Chung if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 940a4cc7eb4SJaehoon Chung COOKIE_PRE_MAPPED) < 0) 941a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9429aa51408SSeungwon Jeon } 9439aa51408SSeungwon Jeon 9449aa51408SSeungwon Jeon static void dw_mci_post_req(struct mmc_host *mmc, 9459aa51408SSeungwon Jeon struct mmc_request *mrq, 9469aa51408SSeungwon Jeon int err) 9479aa51408SSeungwon Jeon { 9489aa51408SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 9499aa51408SSeungwon Jeon struct mmc_data *data = mrq->data; 9509aa51408SSeungwon Jeon 9519aa51408SSeungwon Jeon if (!slot->host->use_dma || !data) 9529aa51408SSeungwon Jeon return; 9539aa51408SSeungwon Jeon 954a4cc7eb4SJaehoon Chung if (data->host_cookie != COOKIE_UNMAPPED) 9554a90920cSThomas Abraham dma_unmap_sg(slot->host->dev, 9569aa51408SSeungwon Jeon data->sg, 9579aa51408SSeungwon Jeon data->sg_len, 958feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 959a4cc7eb4SJaehoon Chung data->host_cookie = COOKIE_UNMAPPED; 9609aa51408SSeungwon Jeon } 9619aa51408SSeungwon Jeon 962671fa142SShawn Lin static int dw_mci_get_cd(struct mmc_host *mmc) 963671fa142SShawn Lin { 964671fa142SShawn Lin int present; 965671fa142SShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 966671fa142SShawn Lin struct dw_mci *host = slot->host; 967671fa142SShawn Lin int gpio_cd = mmc_gpio_get_cd(mmc); 968671fa142SShawn Lin 969671fa142SShawn Lin /* Use platform get_cd function, else try onboard card detect */ 970671fa142SShawn Lin if (((mmc->caps & MMC_CAP_NEEDS_POLL) 971671fa142SShawn Lin || !mmc_card_is_removable(mmc))) { 972671fa142SShawn Lin present = 1; 973671fa142SShawn Lin 974671fa142SShawn Lin if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 975671fa142SShawn Lin if (mmc->caps & MMC_CAP_NEEDS_POLL) { 976671fa142SShawn Lin dev_info(&mmc->class_dev, 977671fa142SShawn Lin "card is polling.\n"); 978671fa142SShawn Lin } else { 979671fa142SShawn Lin dev_info(&mmc->class_dev, 980671fa142SShawn Lin "card is non-removable.\n"); 981671fa142SShawn Lin } 982671fa142SShawn Lin set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 983671fa142SShawn Lin } 984671fa142SShawn Lin 985671fa142SShawn Lin return present; 986671fa142SShawn Lin } else if (gpio_cd >= 0) 987671fa142SShawn Lin present = gpio_cd; 988671fa142SShawn Lin else 989671fa142SShawn Lin present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 990671fa142SShawn Lin == 0 ? 1 : 0; 991671fa142SShawn Lin 992671fa142SShawn Lin spin_lock_bh(&host->lock); 993671fa142SShawn Lin if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 994671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is present\n"); 995671fa142SShawn Lin else if (!present && 996671fa142SShawn Lin !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 997671fa142SShawn Lin dev_dbg(&mmc->class_dev, "card is not present\n"); 998671fa142SShawn Lin spin_unlock_bh(&host->lock); 999671fa142SShawn Lin 1000671fa142SShawn Lin return present; 1001671fa142SShawn Lin } 1002671fa142SShawn Lin 100352426899SSeungwon Jeon static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 100452426899SSeungwon Jeon { 100552426899SSeungwon Jeon unsigned int blksz = data->blksz; 100652426899SSeungwon Jeon const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 100752426899SSeungwon Jeon u32 fifo_width = 1 << host->data_shift; 100852426899SSeungwon Jeon u32 blksz_depth = blksz / fifo_width, fifoth_val; 100952426899SSeungwon Jeon u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 10100e3a22c0SShawn Lin int idx = ARRAY_SIZE(mszs) - 1; 101152426899SSeungwon Jeon 10123fc7eaefSShawn Lin /* pio should ship this scenario */ 10133fc7eaefSShawn Lin if (!host->use_dma) 10143fc7eaefSShawn Lin return; 10153fc7eaefSShawn Lin 101652426899SSeungwon Jeon tx_wmark = (host->fifo_depth) / 2; 101752426899SSeungwon Jeon tx_wmark_invers = host->fifo_depth - tx_wmark; 101852426899SSeungwon Jeon 101952426899SSeungwon Jeon /* 102052426899SSeungwon Jeon * MSIZE is '1', 102152426899SSeungwon Jeon * if blksz is not a multiple of the FIFO width 102252426899SSeungwon Jeon */ 102320753569SShawn Lin if (blksz % fifo_width) 102452426899SSeungwon Jeon goto done; 102552426899SSeungwon Jeon 102652426899SSeungwon Jeon do { 102752426899SSeungwon Jeon if (!((blksz_depth % mszs[idx]) || 102852426899SSeungwon Jeon (tx_wmark_invers % mszs[idx]))) { 102952426899SSeungwon Jeon msize = idx; 103052426899SSeungwon Jeon rx_wmark = mszs[idx] - 1; 103152426899SSeungwon Jeon break; 103252426899SSeungwon Jeon } 103352426899SSeungwon Jeon } while (--idx > 0); 103452426899SSeungwon Jeon /* 103552426899SSeungwon Jeon * If idx is '0', it won't be tried 103652426899SSeungwon Jeon * Thus, initial values are uesed 103752426899SSeungwon Jeon */ 103852426899SSeungwon Jeon done: 103952426899SSeungwon Jeon fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 104052426899SSeungwon Jeon mci_writel(host, FIFOTH, fifoth_val); 104152426899SSeungwon Jeon } 104252426899SSeungwon Jeon 10437e4bf1bcSJaehoon Chung static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1044f1d2736cSSeungwon Jeon { 1045f1d2736cSSeungwon Jeon unsigned int blksz = data->blksz; 1046f1d2736cSSeungwon Jeon u32 blksz_depth, fifo_depth; 1047f1d2736cSSeungwon Jeon u16 thld_size; 10487e4bf1bcSJaehoon Chung u8 enable; 1049f1d2736cSSeungwon Jeon 105066dfd101SJames Hogan /* 105166dfd101SJames Hogan * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 105266dfd101SJames Hogan * in the FIFO region, so we really shouldn't access it). 105366dfd101SJames Hogan */ 10547e4bf1bcSJaehoon Chung if (host->verid < DW_MMC_240A || 10557e4bf1bcSJaehoon Chung (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 105666dfd101SJames Hogan return; 105766dfd101SJames Hogan 10587e4bf1bcSJaehoon Chung /* 10597e4bf1bcSJaehoon Chung * Card write Threshold is introduced since 2.80a 10607e4bf1bcSJaehoon Chung * It's used when HS400 mode is enabled. 10617e4bf1bcSJaehoon Chung */ 10627e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE && 10637e4bf1bcSJaehoon Chung !(host->timing != MMC_TIMING_MMC_HS400)) 10647e4bf1bcSJaehoon Chung return; 10657e4bf1bcSJaehoon Chung 10667e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_WRITE) 10677e4bf1bcSJaehoon Chung enable = SDMMC_CARD_WR_THR_EN; 10687e4bf1bcSJaehoon Chung else 10697e4bf1bcSJaehoon Chung enable = SDMMC_CARD_RD_THR_EN; 10707e4bf1bcSJaehoon Chung 1071f1d2736cSSeungwon Jeon if (host->timing != MMC_TIMING_MMC_HS200 && 1072f1d2736cSSeungwon Jeon host->timing != MMC_TIMING_UHS_SDR104) 1073f1d2736cSSeungwon Jeon goto disable; 1074f1d2736cSSeungwon Jeon 1075f1d2736cSSeungwon Jeon blksz_depth = blksz / (1 << host->data_shift); 1076f1d2736cSSeungwon Jeon fifo_depth = host->fifo_depth; 1077f1d2736cSSeungwon Jeon 1078f1d2736cSSeungwon Jeon if (blksz_depth > fifo_depth) 1079f1d2736cSSeungwon Jeon goto disable; 1080f1d2736cSSeungwon Jeon 1081f1d2736cSSeungwon Jeon /* 1082f1d2736cSSeungwon Jeon * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1083f1d2736cSSeungwon Jeon * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1084f1d2736cSSeungwon Jeon * Currently just choose blksz. 1085f1d2736cSSeungwon Jeon */ 1086f1d2736cSSeungwon Jeon thld_size = blksz; 10877e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1088f1d2736cSSeungwon Jeon return; 1089f1d2736cSSeungwon Jeon 1090f1d2736cSSeungwon Jeon disable: 10917e4bf1bcSJaehoon Chung mci_writel(host, CDTHRCTL, 0); 1092f1d2736cSSeungwon Jeon } 1093f1d2736cSSeungwon Jeon 10949aa51408SSeungwon Jeon static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 10959aa51408SSeungwon Jeon { 1096f8c58c11SDoug Anderson unsigned long irqflags; 10979aa51408SSeungwon Jeon int sg_len; 10989aa51408SSeungwon Jeon u32 temp; 10999aa51408SSeungwon Jeon 11009aa51408SSeungwon Jeon host->using_dma = 0; 11019aa51408SSeungwon Jeon 11029aa51408SSeungwon Jeon /* If we don't have a channel, we can't do DMA */ 11039aa51408SSeungwon Jeon if (!host->use_dma) 11049aa51408SSeungwon Jeon return -ENODEV; 11059aa51408SSeungwon Jeon 1106a4cc7eb4SJaehoon Chung sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1107a99aa9b9SSeungwon Jeon if (sg_len < 0) { 1108a99aa9b9SSeungwon Jeon host->dma_ops->stop(host); 11099aa51408SSeungwon Jeon return sg_len; 1110a99aa9b9SSeungwon Jeon } 11119aa51408SSeungwon Jeon 111203e8cb53SJames Hogan host->using_dma = 1; 111303e8cb53SJames Hogan 11143fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 11154a90920cSThomas Abraham dev_vdbg(host->dev, 1116f95f3850SWill Newton "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 11173fc7eaefSShawn Lin (unsigned long)host->sg_cpu, 11183fc7eaefSShawn Lin (unsigned long)host->sg_dma, 1119f95f3850SWill Newton sg_len); 1120f95f3850SWill Newton 112152426899SSeungwon Jeon /* 112252426899SSeungwon Jeon * Decide the MSIZE and RX/TX Watermark. 112352426899SSeungwon Jeon * If current block size is same with previous size, 112452426899SSeungwon Jeon * no need to update fifoth. 112552426899SSeungwon Jeon */ 112652426899SSeungwon Jeon if (host->prev_blksz != data->blksz) 112752426899SSeungwon Jeon dw_mci_adjust_fifoth(host, data); 112852426899SSeungwon Jeon 1129f95f3850SWill Newton /* Enable the DMA interface */ 1130f95f3850SWill Newton temp = mci_readl(host, CTRL); 1131f95f3850SWill Newton temp |= SDMMC_CTRL_DMA_ENABLE; 1132f95f3850SWill Newton mci_writel(host, CTRL, temp); 1133f95f3850SWill Newton 1134f95f3850SWill Newton /* Disable RX/TX IRQs, let DMA handle it */ 1135f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1136f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1137f95f3850SWill Newton temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1138f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1139f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1140f95f3850SWill Newton 11413fc7eaefSShawn Lin if (host->dma_ops->start(host, sg_len)) { 1142647f80a1SJaehoon Chung host->dma_ops->stop(host); 1143d12d0cb1SShawn Lin /* We can't do DMA, try PIO for this one */ 1144d12d0cb1SShawn Lin dev_dbg(host->dev, 1145d12d0cb1SShawn Lin "%s: fall back to PIO mode for current transfer\n", 1146d12d0cb1SShawn Lin __func__); 11473fc7eaefSShawn Lin return -ENODEV; 11483fc7eaefSShawn Lin } 1149f95f3850SWill Newton 1150f95f3850SWill Newton return 0; 1151f95f3850SWill Newton } 1152f95f3850SWill Newton 1153f95f3850SWill Newton static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1154f95f3850SWill Newton { 1155f8c58c11SDoug Anderson unsigned long irqflags; 11560e3a22c0SShawn Lin int flags = SG_MITER_ATOMIC; 1157f95f3850SWill Newton u32 temp; 1158f95f3850SWill Newton 1159f95f3850SWill Newton data->error = -EINPROGRESS; 1160f95f3850SWill Newton 1161f95f3850SWill Newton WARN_ON(host->data); 1162f95f3850SWill Newton host->sg = NULL; 1163f95f3850SWill Newton host->data = data; 1164f95f3850SWill Newton 11657e4bf1bcSJaehoon Chung if (data->flags & MMC_DATA_READ) 116655c5efbcSJames Hogan host->dir_status = DW_MCI_RECV_STATUS; 11677e4bf1bcSJaehoon Chung else 116855c5efbcSJames Hogan host->dir_status = DW_MCI_SEND_STATUS; 11697e4bf1bcSJaehoon Chung 11707e4bf1bcSJaehoon Chung dw_mci_ctrl_thld(host, data); 117155c5efbcSJames Hogan 1172f95f3850SWill Newton if (dw_mci_submit_data_dma(host, data)) { 1173f9c2a0dcSSeungwon Jeon if (host->data->flags & MMC_DATA_READ) 1174f9c2a0dcSSeungwon Jeon flags |= SG_MITER_TO_SG; 1175f9c2a0dcSSeungwon Jeon else 1176f9c2a0dcSSeungwon Jeon flags |= SG_MITER_FROM_SG; 1177f9c2a0dcSSeungwon Jeon 1178f9c2a0dcSSeungwon Jeon sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1179f95f3850SWill Newton host->sg = data->sg; 118034b664a2SJames Hogan host->part_buf_start = 0; 118134b664a2SJames Hogan host->part_buf_count = 0; 1182f95f3850SWill Newton 1183b40af3aaSJames Hogan mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1184f8c58c11SDoug Anderson 1185f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1186f95f3850SWill Newton temp = mci_readl(host, INTMASK); 1187f95f3850SWill Newton temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1188f95f3850SWill Newton mci_writel(host, INTMASK, temp); 1189f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 1190f95f3850SWill Newton 1191f95f3850SWill Newton temp = mci_readl(host, CTRL); 1192f95f3850SWill Newton temp &= ~SDMMC_CTRL_DMA_ENABLE; 1193f95f3850SWill Newton mci_writel(host, CTRL, temp); 119452426899SSeungwon Jeon 119552426899SSeungwon Jeon /* 1196d6fced83SJun Nie * Use the initial fifoth_val for PIO mode. If wm_algined 1197d6fced83SJun Nie * is set, we set watermark same as data size. 119852426899SSeungwon Jeon * If next issued data may be transfered by DMA mode, 119952426899SSeungwon Jeon * prev_blksz should be invalidated. 120052426899SSeungwon Jeon */ 1201d6fced83SJun Nie if (host->wm_aligned) 1202d6fced83SJun Nie dw_mci_adjust_fifoth(host, data); 1203d6fced83SJun Nie else 120452426899SSeungwon Jeon mci_writel(host, FIFOTH, host->fifoth_val); 120552426899SSeungwon Jeon host->prev_blksz = 0; 120652426899SSeungwon Jeon } else { 120752426899SSeungwon Jeon /* 120852426899SSeungwon Jeon * Keep the current block size. 120952426899SSeungwon Jeon * It will be used to decide whether to update 121052426899SSeungwon Jeon * fifoth register next time. 121152426899SSeungwon Jeon */ 121252426899SSeungwon Jeon host->prev_blksz = data->blksz; 1213f95f3850SWill Newton } 1214f95f3850SWill Newton } 1215f95f3850SWill Newton 1216ab269128SAbhilash Kesavan static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1217f95f3850SWill Newton { 1218f95f3850SWill Newton struct dw_mci *host = slot->host; 1219fdf492a1SDoug Anderson unsigned int clock = slot->clock; 1220f95f3850SWill Newton u32 div; 12219623b5b9SDoug Anderson u32 clk_en_a; 122201730558SDoug Anderson u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 122301730558SDoug Anderson 122401730558SDoug Anderson /* We must continue to set bit 28 in CMD until the change is complete */ 122501730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) 122601730558SDoug Anderson sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1227f95f3850SWill Newton 1228fdf492a1SDoug Anderson if (!clock) { 1229fdf492a1SDoug Anderson mci_writel(host, CLKENA, 0); 123001730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1231fdf492a1SDoug Anderson } else if (clock != host->current_speed || force_clkinit) { 1232fdf492a1SDoug Anderson div = host->bus_hz / clock; 1233fdf492a1SDoug Anderson if (host->bus_hz % clock && host->bus_hz > clock) 1234f95f3850SWill Newton /* 1235f95f3850SWill Newton * move the + 1 after the divide to prevent 1236f95f3850SWill Newton * over-clocking the card. 1237f95f3850SWill Newton */ 1238e419990bSSeungwon Jeon div += 1; 1239e419990bSSeungwon Jeon 1240fdf492a1SDoug Anderson div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1241f95f3850SWill Newton 1242e6cd7a8eSJaehoon Chung if ((clock != slot->__clk_old && 1243e6cd7a8eSJaehoon Chung !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1244e6cd7a8eSJaehoon Chung force_clkinit) { 1245ce69e2feSShawn Lin /* Silent the verbose log if calling from PM context */ 1246ce69e2feSShawn Lin if (!force_clkinit) 1247f95f3850SWill Newton dev_info(&slot->mmc->class_dev, 1248fdf492a1SDoug Anderson "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1249fdf492a1SDoug Anderson slot->id, host->bus_hz, clock, 1250fdf492a1SDoug Anderson div ? ((host->bus_hz / div) >> 1) : 1251fdf492a1SDoug Anderson host->bus_hz, div); 1252f95f3850SWill Newton 1253e6cd7a8eSJaehoon Chung /* 1254e6cd7a8eSJaehoon Chung * If card is polling, display the message only 1255e6cd7a8eSJaehoon Chung * one time at boot time. 1256e6cd7a8eSJaehoon Chung */ 1257e6cd7a8eSJaehoon Chung if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1258e6cd7a8eSJaehoon Chung slot->mmc->f_min == clock) 1259e6cd7a8eSJaehoon Chung set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1260e6cd7a8eSJaehoon Chung } 1261e6cd7a8eSJaehoon Chung 1262f95f3850SWill Newton /* disable clock */ 1263f95f3850SWill Newton mci_writel(host, CLKENA, 0); 1264f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 1265f95f3850SWill Newton 1266f95f3850SWill Newton /* inform CIU */ 126701730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1268f95f3850SWill Newton 1269f95f3850SWill Newton /* set clock to desired speed */ 1270f95f3850SWill Newton mci_writel(host, CLKDIV, div); 1271f95f3850SWill Newton 1272f95f3850SWill Newton /* inform CIU */ 127301730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1274f95f3850SWill Newton 12759623b5b9SDoug Anderson /* enable clock; only low power if no SDIO */ 12769623b5b9SDoug Anderson clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1277b24c8b26SDoug Anderson if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 12789623b5b9SDoug Anderson clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 12799623b5b9SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 1280f95f3850SWill Newton 1281f95f3850SWill Newton /* inform CIU */ 128201730558SDoug Anderson mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1283005d675aSJaehoon Chung 1284005d675aSJaehoon Chung /* keep the last clock value that was requested from core */ 1285005d675aSJaehoon Chung slot->__clk_old = clock; 1286f95f3850SWill Newton } 1287f95f3850SWill Newton 1288fdf492a1SDoug Anderson host->current_speed = clock; 1289fdf492a1SDoug Anderson 1290f95f3850SWill Newton /* Set the current slot bus width */ 12911d56c453SSeungwon Jeon mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1292f95f3850SWill Newton } 1293f95f3850SWill Newton 1294053b3ce6SSeungwon Jeon static void __dw_mci_start_request(struct dw_mci *host, 1295053b3ce6SSeungwon Jeon struct dw_mci_slot *slot, 1296053b3ce6SSeungwon Jeon struct mmc_command *cmd) 1297f95f3850SWill Newton { 1298f95f3850SWill Newton struct mmc_request *mrq; 1299f95f3850SWill Newton struct mmc_data *data; 1300f95f3850SWill Newton u32 cmdflags; 1301f95f3850SWill Newton 1302f95f3850SWill Newton mrq = slot->mrq; 1303f95f3850SWill Newton 1304f95f3850SWill Newton host->mrq = mrq; 1305f95f3850SWill Newton 1306f95f3850SWill Newton host->pending_events = 0; 1307f95f3850SWill Newton host->completed_events = 0; 1308e352c813SSeungwon Jeon host->cmd_status = 0; 1309f95f3850SWill Newton host->data_status = 0; 1310e352c813SSeungwon Jeon host->dir_status = 0; 1311f95f3850SWill Newton 1312053b3ce6SSeungwon Jeon data = cmd->data; 1313f95f3850SWill Newton if (data) { 1314f16afa88SJaehoon Chung mci_writel(host, TMOUT, 0xFFFFFFFF); 1315f95f3850SWill Newton mci_writel(host, BYTCNT, data->blksz*data->blocks); 1316f95f3850SWill Newton mci_writel(host, BLKSIZ, data->blksz); 1317f95f3850SWill Newton } 1318f95f3850SWill Newton 1319f95f3850SWill Newton cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1320f95f3850SWill Newton 1321f95f3850SWill Newton /* this is the first command, send the initialization clock */ 1322f95f3850SWill Newton if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1323f95f3850SWill Newton cmdflags |= SDMMC_CMD_INIT; 1324f95f3850SWill Newton 1325f95f3850SWill Newton if (data) { 1326f95f3850SWill Newton dw_mci_submit_data(host, data); 13270e3a22c0SShawn Lin wmb(); /* drain writebuffer */ 1328f95f3850SWill Newton } 1329f95f3850SWill Newton 1330f95f3850SWill Newton dw_mci_start_command(host, cmd, cmdflags); 1331f95f3850SWill Newton 13325c935165SDoug Anderson if (cmd->opcode == SD_SWITCH_VOLTAGE) { 133349ba0302SDoug Anderson unsigned long irqflags; 133449ba0302SDoug Anderson 13355c935165SDoug Anderson /* 13368886a6fdSDoug Anderson * Databook says to fail after 2ms w/ no response, but evidence 13378886a6fdSDoug Anderson * shows that sometimes the cmd11 interrupt takes over 130ms. 13388886a6fdSDoug Anderson * We'll set to 500ms, plus an extra jiffy just in case jiffies 13398886a6fdSDoug Anderson * is just about to roll over. 134049ba0302SDoug Anderson * 134149ba0302SDoug Anderson * We do this whole thing under spinlock and only if the 134249ba0302SDoug Anderson * command hasn't already completed (indicating the the irq 134349ba0302SDoug Anderson * already ran so we don't want the timeout). 13445c935165SDoug Anderson */ 134549ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 134649ba0302SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 13475c935165SDoug Anderson mod_timer(&host->cmd11_timer, 13488886a6fdSDoug Anderson jiffies + msecs_to_jiffies(500) + 1); 134949ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 13505c935165SDoug Anderson } 13515c935165SDoug Anderson 135290c2143aSSeungwon Jeon host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1353f95f3850SWill Newton } 1354f95f3850SWill Newton 1355053b3ce6SSeungwon Jeon static void dw_mci_start_request(struct dw_mci *host, 1356053b3ce6SSeungwon Jeon struct dw_mci_slot *slot) 1357053b3ce6SSeungwon Jeon { 1358053b3ce6SSeungwon Jeon struct mmc_request *mrq = slot->mrq; 1359053b3ce6SSeungwon Jeon struct mmc_command *cmd; 1360053b3ce6SSeungwon Jeon 1361053b3ce6SSeungwon Jeon cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1362053b3ce6SSeungwon Jeon __dw_mci_start_request(host, slot, cmd); 1363053b3ce6SSeungwon Jeon } 1364053b3ce6SSeungwon Jeon 13657456caaeSJames Hogan /* must be called with host->lock held */ 1366f95f3850SWill Newton static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1367f95f3850SWill Newton struct mmc_request *mrq) 1368f95f3850SWill Newton { 1369f95f3850SWill Newton dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1370f95f3850SWill Newton host->state); 1371f95f3850SWill Newton 1372f95f3850SWill Newton slot->mrq = mrq; 1373f95f3850SWill Newton 137401730558SDoug Anderson if (host->state == STATE_WAITING_CMD11_DONE) { 137501730558SDoug Anderson dev_warn(&slot->mmc->class_dev, 137601730558SDoug Anderson "Voltage change didn't complete\n"); 137701730558SDoug Anderson /* 137801730558SDoug Anderson * this case isn't expected to happen, so we can 137901730558SDoug Anderson * either crash here or just try to continue on 138001730558SDoug Anderson * in the closest possible state 138101730558SDoug Anderson */ 138201730558SDoug Anderson host->state = STATE_IDLE; 138301730558SDoug Anderson } 138401730558SDoug Anderson 1385f95f3850SWill Newton if (host->state == STATE_IDLE) { 1386f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1387f95f3850SWill Newton dw_mci_start_request(host, slot); 1388f95f3850SWill Newton } else { 1389f95f3850SWill Newton list_add_tail(&slot->queue_node, &host->queue); 1390f95f3850SWill Newton } 1391f95f3850SWill Newton } 1392f95f3850SWill Newton 1393f95f3850SWill Newton static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1394f95f3850SWill Newton { 1395f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1396f95f3850SWill Newton struct dw_mci *host = slot->host; 1397f95f3850SWill Newton 1398f95f3850SWill Newton WARN_ON(slot->mrq); 1399f95f3850SWill Newton 14007456caaeSJames Hogan /* 14017456caaeSJames Hogan * The check for card presence and queueing of the request must be 14027456caaeSJames Hogan * atomic, otherwise the card could be removed in between and the 14037456caaeSJames Hogan * request wouldn't fail until another card was inserted. 14047456caaeSJames Hogan */ 14057456caaeSJames Hogan 140656f6911cSShawn Lin if (!dw_mci_get_cd(mmc)) { 1407f95f3850SWill Newton mrq->cmd->error = -ENOMEDIUM; 1408f95f3850SWill Newton mmc_request_done(mmc, mrq); 1409f95f3850SWill Newton return; 1410f95f3850SWill Newton } 1411f95f3850SWill Newton 141256f6911cSShawn Lin spin_lock_bh(&host->lock); 141356f6911cSShawn Lin 1414f95f3850SWill Newton dw_mci_queue_request(host, slot, mrq); 14157456caaeSJames Hogan 14167456caaeSJames Hogan spin_unlock_bh(&host->lock); 1417f95f3850SWill Newton } 1418f95f3850SWill Newton 1419f95f3850SWill Newton static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1420f95f3850SWill Newton { 1421f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 1422e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 142341babf75SJaehoon Chung u32 regs; 142451da2240SYuvaraj CD int ret; 1425f95f3850SWill Newton 1426f95f3850SWill Newton switch (ios->bus_width) { 1427f95f3850SWill Newton case MMC_BUS_WIDTH_4: 1428f95f3850SWill Newton slot->ctype = SDMMC_CTYPE_4BIT; 1429f95f3850SWill Newton break; 1430c9b2a06fSJaehoon Chung case MMC_BUS_WIDTH_8: 1431c9b2a06fSJaehoon Chung slot->ctype = SDMMC_CTYPE_8BIT; 1432c9b2a06fSJaehoon Chung break; 1433b2f7cb45SJaehoon Chung default: 1434b2f7cb45SJaehoon Chung /* set default 1 bit mode */ 1435b2f7cb45SJaehoon Chung slot->ctype = SDMMC_CTYPE_1BIT; 1436f95f3850SWill Newton } 1437f95f3850SWill Newton 143841babf75SJaehoon Chung regs = mci_readl(slot->host, UHS_REG); 14393f514291SSeungwon Jeon 14403f514291SSeungwon Jeon /* DDR mode set */ 144180113132SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52 || 14427cc8d580SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 144380113132SSeungwon Jeon ios->timing == MMC_TIMING_MMC_HS400) 1444c69042a5SHyeonsu Kim regs |= ((0x1 << slot->id) << 16); 14453f514291SSeungwon Jeon else 1446c69042a5SHyeonsu Kim regs &= ~((0x1 << slot->id) << 16); 14473f514291SSeungwon Jeon 144841babf75SJaehoon Chung mci_writel(slot->host, UHS_REG, regs); 1449f1d2736cSSeungwon Jeon slot->host->timing = ios->timing; 145041babf75SJaehoon Chung 1451f95f3850SWill Newton /* 1452f95f3850SWill Newton * Use mirror of ios->clock to prevent race with mmc 1453f95f3850SWill Newton * core ios update when finding the minimum. 1454f95f3850SWill Newton */ 1455f95f3850SWill Newton slot->clock = ios->clock; 1456f95f3850SWill Newton 1457cb27a843SJames Hogan if (drv_data && drv_data->set_ios) 1458cb27a843SJames Hogan drv_data->set_ios(slot->host, ios); 1459800d78bfSThomas Abraham 1460f95f3850SWill Newton switch (ios->power_mode) { 1461f95f3850SWill Newton case MMC_POWER_UP: 146251da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) { 146351da2240SYuvaraj CD ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 146451da2240SYuvaraj CD ios->vdd); 146551da2240SYuvaraj CD if (ret) { 146651da2240SYuvaraj CD dev_err(slot->host->dev, 146751da2240SYuvaraj CD "failed to enable vmmc regulator\n"); 146851da2240SYuvaraj CD /*return, if failed turn on vmmc*/ 146951da2240SYuvaraj CD return; 147051da2240SYuvaraj CD } 147151da2240SYuvaraj CD } 147229d0d161SDoug Anderson set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 147329d0d161SDoug Anderson regs = mci_readl(slot->host, PWREN); 147429d0d161SDoug Anderson regs |= (1 << slot->id); 147529d0d161SDoug Anderson mci_writel(slot->host, PWREN, regs); 147629d0d161SDoug Anderson break; 147729d0d161SDoug Anderson case MMC_POWER_ON: 1478d1f1dd86SDoug Anderson if (!slot->host->vqmmc_enabled) { 1479d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 148051da2240SYuvaraj CD ret = regulator_enable(mmc->supply.vqmmc); 148151da2240SYuvaraj CD if (ret < 0) 148251da2240SYuvaraj CD dev_err(slot->host->dev, 1483d1f1dd86SDoug Anderson "failed to enable vqmmc\n"); 148451da2240SYuvaraj CD else 148551da2240SYuvaraj CD slot->host->vqmmc_enabled = true; 1486d1f1dd86SDoug Anderson 1487d1f1dd86SDoug Anderson } else { 1488d1f1dd86SDoug Anderson /* Keep track so we don't reset again */ 1489d1f1dd86SDoug Anderson slot->host->vqmmc_enabled = true; 1490d1f1dd86SDoug Anderson } 1491d1f1dd86SDoug Anderson 1492d1f1dd86SDoug Anderson /* Reset our state machine after powering on */ 1493d1f1dd86SDoug Anderson dw_mci_ctrl_reset(slot->host, 1494d1f1dd86SDoug Anderson SDMMC_CTRL_ALL_RESET_FLAGS); 149551da2240SYuvaraj CD } 1496655babbdSDoug Anderson 1497655babbdSDoug Anderson /* Adjust clock / bus width after power is up */ 1498655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1499655babbdSDoug Anderson 1500e6f34e2fSJames Hogan break; 1501e6f34e2fSJames Hogan case MMC_POWER_OFF: 1502655babbdSDoug Anderson /* Turn clock off before power goes down */ 1503655babbdSDoug Anderson dw_mci_setup_bus(slot, false); 1504655babbdSDoug Anderson 150551da2240SYuvaraj CD if (!IS_ERR(mmc->supply.vmmc)) 150651da2240SYuvaraj CD mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 150751da2240SYuvaraj CD 1508d1f1dd86SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 150951da2240SYuvaraj CD regulator_disable(mmc->supply.vqmmc); 151051da2240SYuvaraj CD slot->host->vqmmc_enabled = false; 151151da2240SYuvaraj CD 15124366dcc5SJaehoon Chung regs = mci_readl(slot->host, PWREN); 15134366dcc5SJaehoon Chung regs &= ~(1 << slot->id); 15144366dcc5SJaehoon Chung mci_writel(slot->host, PWREN, regs); 1515f95f3850SWill Newton break; 1516f95f3850SWill Newton default: 1517f95f3850SWill Newton break; 1518f95f3850SWill Newton } 1519655babbdSDoug Anderson 1520655babbdSDoug Anderson if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1521655babbdSDoug Anderson slot->host->state = STATE_IDLE; 1522f95f3850SWill Newton } 1523f95f3850SWill Newton 152401730558SDoug Anderson static int dw_mci_card_busy(struct mmc_host *mmc) 152501730558SDoug Anderson { 152601730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 152701730558SDoug Anderson u32 status; 152801730558SDoug Anderson 152901730558SDoug Anderson /* 153001730558SDoug Anderson * Check the busy bit which is low when DAT[3:0] 153101730558SDoug Anderson * (the data lines) are 0000 153201730558SDoug Anderson */ 153301730558SDoug Anderson status = mci_readl(slot->host, STATUS); 153401730558SDoug Anderson 153501730558SDoug Anderson return !!(status & SDMMC_STATUS_BUSY); 153601730558SDoug Anderson } 153701730558SDoug Anderson 153801730558SDoug Anderson static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 153901730558SDoug Anderson { 154001730558SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 154101730558SDoug Anderson struct dw_mci *host = slot->host; 15428f7849c4SZhangfei Gao const struct dw_mci_drv_data *drv_data = host->drv_data; 154301730558SDoug Anderson u32 uhs; 154401730558SDoug Anderson u32 v18 = SDMMC_UHS_18V << slot->id; 154501730558SDoug Anderson int ret; 154601730558SDoug Anderson 15478f7849c4SZhangfei Gao if (drv_data && drv_data->switch_voltage) 15488f7849c4SZhangfei Gao return drv_data->switch_voltage(mmc, ios); 15498f7849c4SZhangfei Gao 155001730558SDoug Anderson /* 155101730558SDoug Anderson * Program the voltage. Note that some instances of dw_mmc may use 155201730558SDoug Anderson * the UHS_REG for this. For other instances (like exynos) the UHS_REG 155301730558SDoug Anderson * does no harm but you need to set the regulator directly. Try both. 155401730558SDoug Anderson */ 155501730558SDoug Anderson uhs = mci_readl(host, UHS_REG); 1556e0848f5dSDouglas Anderson if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 155701730558SDoug Anderson uhs &= ~v18; 1558e0848f5dSDouglas Anderson else 155901730558SDoug Anderson uhs |= v18; 1560e0848f5dSDouglas Anderson 156101730558SDoug Anderson if (!IS_ERR(mmc->supply.vqmmc)) { 1562e0848f5dSDouglas Anderson ret = mmc_regulator_set_vqmmc(mmc, ios); 156301730558SDoug Anderson 156401730558SDoug Anderson if (ret) { 1565b19caf37SDoug Anderson dev_dbg(&mmc->class_dev, 1566e0848f5dSDouglas Anderson "Regulator set error %d - %s V\n", 1567e0848f5dSDouglas Anderson ret, uhs & v18 ? "1.8" : "3.3"); 156801730558SDoug Anderson return ret; 156901730558SDoug Anderson } 157001730558SDoug Anderson } 157101730558SDoug Anderson mci_writel(host, UHS_REG, uhs); 157201730558SDoug Anderson 157301730558SDoug Anderson return 0; 157401730558SDoug Anderson } 157501730558SDoug Anderson 1576f95f3850SWill Newton static int dw_mci_get_ro(struct mmc_host *mmc) 1577f95f3850SWill Newton { 1578f95f3850SWill Newton int read_only; 1579f95f3850SWill Newton struct dw_mci_slot *slot = mmc_priv(mmc); 15809795a846SJaehoon Chung int gpio_ro = mmc_gpio_get_ro(mmc); 1581f95f3850SWill Newton 1582f95f3850SWill Newton /* Use platform get_ro function, else try on board write protect */ 1583287980e4SArnd Bergmann if (gpio_ro >= 0) 15849795a846SJaehoon Chung read_only = gpio_ro; 1585f95f3850SWill Newton else 1586f95f3850SWill Newton read_only = 1587f95f3850SWill Newton mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1588f95f3850SWill Newton 1589f95f3850SWill Newton dev_dbg(&mmc->class_dev, "card is %s\n", 1590f95f3850SWill Newton read_only ? "read-only" : "read-write"); 1591f95f3850SWill Newton 1592f95f3850SWill Newton return read_only; 1593f95f3850SWill Newton } 1594f95f3850SWill Newton 1595935a665eSShawn Lin static void dw_mci_hw_reset(struct mmc_host *mmc) 1596935a665eSShawn Lin { 1597935a665eSShawn Lin struct dw_mci_slot *slot = mmc_priv(mmc); 1598935a665eSShawn Lin struct dw_mci *host = slot->host; 1599935a665eSShawn Lin int reset; 1600935a665eSShawn Lin 1601935a665eSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 1602935a665eSShawn Lin dw_mci_idmac_reset(host); 1603935a665eSShawn Lin 1604935a665eSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1605935a665eSShawn Lin SDMMC_CTRL_FIFO_RESET)) 1606935a665eSShawn Lin return; 1607935a665eSShawn Lin 1608935a665eSShawn Lin /* 1609935a665eSShawn Lin * According to eMMC spec, card reset procedure: 1610935a665eSShawn Lin * tRstW >= 1us: RST_n pulse width 1611935a665eSShawn Lin * tRSCA >= 200us: RST_n to Command time 1612935a665eSShawn Lin * tRSTH >= 1us: RST_n high period 1613935a665eSShawn Lin */ 1614935a665eSShawn Lin reset = mci_readl(host, RST_N); 1615935a665eSShawn Lin reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1616935a665eSShawn Lin mci_writel(host, RST_N, reset); 1617935a665eSShawn Lin usleep_range(1, 2); 1618935a665eSShawn Lin reset |= SDMMC_RST_HWACTIVE << slot->id; 1619935a665eSShawn Lin mci_writel(host, RST_N, reset); 1620935a665eSShawn Lin usleep_range(200, 300); 1621935a665eSShawn Lin } 1622935a665eSShawn Lin 1623b24c8b26SDoug Anderson static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1624b24c8b26SDoug Anderson { 1625b24c8b26SDoug Anderson struct dw_mci_slot *slot = mmc_priv(mmc); 1626b24c8b26SDoug Anderson struct dw_mci *host = slot->host; 1627b24c8b26SDoug Anderson 16289623b5b9SDoug Anderson /* 16299623b5b9SDoug Anderson * Low power mode will stop the card clock when idle. According to the 16309623b5b9SDoug Anderson * description of the CLKENA register we should disable low power mode 16319623b5b9SDoug Anderson * for SDIO cards if we need SDIO interrupts to work. 16329623b5b9SDoug Anderson */ 1633b24c8b26SDoug Anderson if (mmc->caps & MMC_CAP_SDIO_IRQ) { 16349623b5b9SDoug Anderson const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1635b24c8b26SDoug Anderson u32 clk_en_a_old; 1636b24c8b26SDoug Anderson u32 clk_en_a; 16379623b5b9SDoug Anderson 1638b24c8b26SDoug Anderson clk_en_a_old = mci_readl(host, CLKENA); 16399623b5b9SDoug Anderson 1640b24c8b26SDoug Anderson if (card->type == MMC_TYPE_SDIO || 1641b24c8b26SDoug Anderson card->type == MMC_TYPE_SD_COMBO) { 1642b24c8b26SDoug Anderson set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1643b24c8b26SDoug Anderson clk_en_a = clk_en_a_old & ~clken_low_pwr; 1644b24c8b26SDoug Anderson } else { 1645b24c8b26SDoug Anderson clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1646b24c8b26SDoug Anderson clk_en_a = clk_en_a_old | clken_low_pwr; 1647b24c8b26SDoug Anderson } 1648b24c8b26SDoug Anderson 1649b24c8b26SDoug Anderson if (clk_en_a != clk_en_a_old) { 1650b24c8b26SDoug Anderson mci_writel(host, CLKENA, clk_en_a); 16519623b5b9SDoug Anderson mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 16529623b5b9SDoug Anderson SDMMC_CMD_PRV_DAT_WAIT, 0); 16539623b5b9SDoug Anderson } 16549623b5b9SDoug Anderson } 1655b24c8b26SDoug Anderson } 16569623b5b9SDoug Anderson 165732dba737SUlf Hansson static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 16581a5c8e1fSShashidhar Hiremath { 16591a5c8e1fSShashidhar Hiremath struct dw_mci *host = slot->host; 1660f8c58c11SDoug Anderson unsigned long irqflags; 16611a5c8e1fSShashidhar Hiremath u32 int_mask; 16621a5c8e1fSShashidhar Hiremath 1663f8c58c11SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 1664f8c58c11SDoug Anderson 16651a5c8e1fSShashidhar Hiremath /* Enable/disable Slot Specific SDIO interrupt */ 16661a5c8e1fSShashidhar Hiremath int_mask = mci_readl(host, INTMASK); 1667b24c8b26SDoug Anderson if (enb) 1668b24c8b26SDoug Anderson int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1669b24c8b26SDoug Anderson else 1670b24c8b26SDoug Anderson int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1671b24c8b26SDoug Anderson mci_writel(host, INTMASK, int_mask); 1672f8c58c11SDoug Anderson 1673f8c58c11SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 16741a5c8e1fSShashidhar Hiremath } 16751a5c8e1fSShashidhar Hiremath 167632dba737SUlf Hansson static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 167732dba737SUlf Hansson { 167832dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 1679ca8971caSUlf Hansson struct dw_mci *host = slot->host; 168032dba737SUlf Hansson 168132dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, enb); 1682ca8971caSUlf Hansson 1683ca8971caSUlf Hansson /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1684ca8971caSUlf Hansson if (enb) 1685ca8971caSUlf Hansson pm_runtime_get_noresume(host->dev); 1686ca8971caSUlf Hansson else 1687ca8971caSUlf Hansson pm_runtime_put_noidle(host->dev); 168832dba737SUlf Hansson } 168932dba737SUlf Hansson 169032dba737SUlf Hansson static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 169132dba737SUlf Hansson { 169232dba737SUlf Hansson struct dw_mci_slot *slot = mmc_priv(mmc); 169332dba737SUlf Hansson 169432dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 1); 169532dba737SUlf Hansson } 169632dba737SUlf Hansson 16970976f16dSSeungwon Jeon static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 16980976f16dSSeungwon Jeon { 16990976f16dSSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 17000976f16dSSeungwon Jeon struct dw_mci *host = slot->host; 17010976f16dSSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 17020e3a22c0SShawn Lin int err = -EINVAL; 17030976f16dSSeungwon Jeon 17040976f16dSSeungwon Jeon if (drv_data && drv_data->execute_tuning) 17059979dbe5SChaotian Jing err = drv_data->execute_tuning(slot, opcode); 17060976f16dSSeungwon Jeon return err; 17070976f16dSSeungwon Jeon } 17080976f16dSSeungwon Jeon 17090e3a22c0SShawn Lin static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 17100e3a22c0SShawn Lin struct mmc_ios *ios) 171180113132SSeungwon Jeon { 171280113132SSeungwon Jeon struct dw_mci_slot *slot = mmc_priv(mmc); 171380113132SSeungwon Jeon struct dw_mci *host = slot->host; 171480113132SSeungwon Jeon const struct dw_mci_drv_data *drv_data = host->drv_data; 171580113132SSeungwon Jeon 171680113132SSeungwon Jeon if (drv_data && drv_data->prepare_hs400_tuning) 171780113132SSeungwon Jeon return drv_data->prepare_hs400_tuning(host, ios); 171880113132SSeungwon Jeon 171980113132SSeungwon Jeon return 0; 172080113132SSeungwon Jeon } 172180113132SSeungwon Jeon 17224e7392b2SShawn Lin static bool dw_mci_reset(struct dw_mci *host) 17234e7392b2SShawn Lin { 17244e7392b2SShawn Lin u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 17254e7392b2SShawn Lin bool ret = false; 1726bc2dcc1aSShawn Lin u32 status = 0; 17274e7392b2SShawn Lin 17284e7392b2SShawn Lin /* 17294e7392b2SShawn Lin * Resetting generates a block interrupt, hence setting 17304e7392b2SShawn Lin * the scatter-gather pointer to NULL. 17314e7392b2SShawn Lin */ 17324e7392b2SShawn Lin if (host->sg) { 17334e7392b2SShawn Lin sg_miter_stop(&host->sg_miter); 17344e7392b2SShawn Lin host->sg = NULL; 17354e7392b2SShawn Lin } 17364e7392b2SShawn Lin 17374e7392b2SShawn Lin if (host->use_dma) 17384e7392b2SShawn Lin flags |= SDMMC_CTRL_DMA_RESET; 17394e7392b2SShawn Lin 17404e7392b2SShawn Lin if (dw_mci_ctrl_reset(host, flags)) { 17414e7392b2SShawn Lin /* 1742bc2dcc1aSShawn Lin * In all cases we clear the RAWINTS 1743bc2dcc1aSShawn Lin * register to clear any interrupts. 17444e7392b2SShawn Lin */ 17454e7392b2SShawn Lin mci_writel(host, RINTSTS, 0xFFFFFFFF); 17464e7392b2SShawn Lin 1747bc2dcc1aSShawn Lin if (!host->use_dma) { 1748bc2dcc1aSShawn Lin ret = true; 1749bc2dcc1aSShawn Lin goto ciu_out; 1750bc2dcc1aSShawn Lin } 17514e7392b2SShawn Lin 1752bc2dcc1aSShawn Lin /* Wait for dma_req to be cleared */ 17534e7392b2SShawn Lin if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 17544e7392b2SShawn Lin status, 17554e7392b2SShawn Lin !(status & SDMMC_STATUS_DMA_REQ), 17564e7392b2SShawn Lin 1, 500 * USEC_PER_MSEC)) { 17574e7392b2SShawn Lin dev_err(host->dev, 1758bc2dcc1aSShawn Lin "%s: Timeout waiting for dma_req to be cleared\n", 17594e7392b2SShawn Lin __func__); 17604e7392b2SShawn Lin goto ciu_out; 17614e7392b2SShawn Lin } 17624e7392b2SShawn Lin 17634e7392b2SShawn Lin /* when using DMA next we reset the fifo again */ 17644e7392b2SShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 17654e7392b2SShawn Lin goto ciu_out; 17664e7392b2SShawn Lin } else { 17674e7392b2SShawn Lin /* if the controller reset bit did clear, then set clock regs */ 17684e7392b2SShawn Lin if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 17694e7392b2SShawn Lin dev_err(host->dev, 17704e7392b2SShawn Lin "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 17714e7392b2SShawn Lin __func__); 17724e7392b2SShawn Lin goto ciu_out; 17734e7392b2SShawn Lin } 17744e7392b2SShawn Lin } 17754e7392b2SShawn Lin 17764e7392b2SShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) 17774e7392b2SShawn Lin /* It is also recommended that we reset and reprogram idmac */ 17784e7392b2SShawn Lin dw_mci_idmac_reset(host); 17794e7392b2SShawn Lin 17804e7392b2SShawn Lin ret = true; 17814e7392b2SShawn Lin 17824e7392b2SShawn Lin ciu_out: 17834e7392b2SShawn Lin /* After a CTRL reset we need to have CIU set clock registers */ 178442f989c0SJaehoon Chung mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 17854e7392b2SShawn Lin 17864e7392b2SShawn Lin return ret; 17874e7392b2SShawn Lin } 17884e7392b2SShawn Lin 1789f95f3850SWill Newton static const struct mmc_host_ops dw_mci_ops = { 1790f95f3850SWill Newton .request = dw_mci_request, 17919aa51408SSeungwon Jeon .pre_req = dw_mci_pre_req, 17929aa51408SSeungwon Jeon .post_req = dw_mci_post_req, 1793f95f3850SWill Newton .set_ios = dw_mci_set_ios, 1794f95f3850SWill Newton .get_ro = dw_mci_get_ro, 1795f95f3850SWill Newton .get_cd = dw_mci_get_cd, 1796935a665eSShawn Lin .hw_reset = dw_mci_hw_reset, 17971a5c8e1fSShashidhar Hiremath .enable_sdio_irq = dw_mci_enable_sdio_irq, 179832dba737SUlf Hansson .ack_sdio_irq = dw_mci_ack_sdio_irq, 17990976f16dSSeungwon Jeon .execute_tuning = dw_mci_execute_tuning, 180001730558SDoug Anderson .card_busy = dw_mci_card_busy, 180101730558SDoug Anderson .start_signal_voltage_switch = dw_mci_switch_voltage, 1802b24c8b26SDoug Anderson .init_card = dw_mci_init_card, 180380113132SSeungwon Jeon .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1804f95f3850SWill Newton }; 1805f95f3850SWill Newton 1806f95f3850SWill Newton static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1807f95f3850SWill Newton __releases(&host->lock) 1808f95f3850SWill Newton __acquires(&host->lock) 1809f95f3850SWill Newton { 1810f95f3850SWill Newton struct dw_mci_slot *slot; 181142f989c0SJaehoon Chung struct mmc_host *prev_mmc = host->slot->mmc; 1812f95f3850SWill Newton 1813f95f3850SWill Newton WARN_ON(host->cmd || host->data); 1814f95f3850SWill Newton 181542f989c0SJaehoon Chung host->slot->mrq = NULL; 1816f95f3850SWill Newton host->mrq = NULL; 1817f95f3850SWill Newton if (!list_empty(&host->queue)) { 1818f95f3850SWill Newton slot = list_entry(host->queue.next, 1819f95f3850SWill Newton struct dw_mci_slot, queue_node); 1820f95f3850SWill Newton list_del(&slot->queue_node); 18214a90920cSThomas Abraham dev_vdbg(host->dev, "list not empty: %s is next\n", 1822f95f3850SWill Newton mmc_hostname(slot->mmc)); 1823f95f3850SWill Newton host->state = STATE_SENDING_CMD; 1824f95f3850SWill Newton dw_mci_start_request(host, slot); 1825f95f3850SWill Newton } else { 18264a90920cSThomas Abraham dev_vdbg(host->dev, "list empty\n"); 182701730558SDoug Anderson 182801730558SDoug Anderson if (host->state == STATE_SENDING_CMD11) 182901730558SDoug Anderson host->state = STATE_WAITING_CMD11_DONE; 183001730558SDoug Anderson else 1831f95f3850SWill Newton host->state = STATE_IDLE; 1832f95f3850SWill Newton } 1833f95f3850SWill Newton 1834f95f3850SWill Newton spin_unlock(&host->lock); 1835f95f3850SWill Newton mmc_request_done(prev_mmc, mrq); 1836f95f3850SWill Newton spin_lock(&host->lock); 1837f95f3850SWill Newton } 1838f95f3850SWill Newton 1839e352c813SSeungwon Jeon static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1840f95f3850SWill Newton { 1841f95f3850SWill Newton u32 status = host->cmd_status; 1842f95f3850SWill Newton 1843f95f3850SWill Newton host->cmd_status = 0; 1844f95f3850SWill Newton 1845f95f3850SWill Newton /* Read the response from the card (up to 16 bytes) */ 1846f95f3850SWill Newton if (cmd->flags & MMC_RSP_PRESENT) { 1847f95f3850SWill Newton if (cmd->flags & MMC_RSP_136) { 1848f95f3850SWill Newton cmd->resp[3] = mci_readl(host, RESP0); 1849f95f3850SWill Newton cmd->resp[2] = mci_readl(host, RESP1); 1850f95f3850SWill Newton cmd->resp[1] = mci_readl(host, RESP2); 1851f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP3); 1852f95f3850SWill Newton } else { 1853f95f3850SWill Newton cmd->resp[0] = mci_readl(host, RESP0); 1854f95f3850SWill Newton cmd->resp[1] = 0; 1855f95f3850SWill Newton cmd->resp[2] = 0; 1856f95f3850SWill Newton cmd->resp[3] = 0; 1857f95f3850SWill Newton } 1858f95f3850SWill Newton } 1859f95f3850SWill Newton 1860f95f3850SWill Newton if (status & SDMMC_INT_RTO) 1861f95f3850SWill Newton cmd->error = -ETIMEDOUT; 1862f95f3850SWill Newton else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1863f95f3850SWill Newton cmd->error = -EILSEQ; 1864f95f3850SWill Newton else if (status & SDMMC_INT_RESP_ERR) 1865f95f3850SWill Newton cmd->error = -EIO; 1866f95f3850SWill Newton else 1867f95f3850SWill Newton cmd->error = 0; 1868f95f3850SWill Newton 1869e352c813SSeungwon Jeon return cmd->error; 1870e352c813SSeungwon Jeon } 1871e352c813SSeungwon Jeon 1872e352c813SSeungwon Jeon static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1873e352c813SSeungwon Jeon { 187431bff450SSeungwon Jeon u32 status = host->data_status; 1875e352c813SSeungwon Jeon 1876e352c813SSeungwon Jeon if (status & DW_MCI_DATA_ERROR_FLAGS) { 1877e352c813SSeungwon Jeon if (status & SDMMC_INT_DRTO) { 1878e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1879e352c813SSeungwon Jeon } else if (status & SDMMC_INT_DCRC) { 1880e352c813SSeungwon Jeon data->error = -EILSEQ; 1881e352c813SSeungwon Jeon } else if (status & SDMMC_INT_EBE) { 1882e352c813SSeungwon Jeon if (host->dir_status == 1883e352c813SSeungwon Jeon DW_MCI_SEND_STATUS) { 1884e352c813SSeungwon Jeon /* 1885e352c813SSeungwon Jeon * No data CRC status was returned. 1886e352c813SSeungwon Jeon * The number of bytes transferred 1887e352c813SSeungwon Jeon * will be exaggerated in PIO mode. 1888e352c813SSeungwon Jeon */ 1889e352c813SSeungwon Jeon data->bytes_xfered = 0; 1890e352c813SSeungwon Jeon data->error = -ETIMEDOUT; 1891e352c813SSeungwon Jeon } else if (host->dir_status == 1892e352c813SSeungwon Jeon DW_MCI_RECV_STATUS) { 1893e7a1dec1SShawn Lin data->error = -EILSEQ; 1894e352c813SSeungwon Jeon } 1895e352c813SSeungwon Jeon } else { 1896e352c813SSeungwon Jeon /* SDMMC_INT_SBE is included */ 1897e7a1dec1SShawn Lin data->error = -EILSEQ; 1898e352c813SSeungwon Jeon } 1899e352c813SSeungwon Jeon 1900e6cc0123SDoug Anderson dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1901e352c813SSeungwon Jeon 1902e352c813SSeungwon Jeon /* 1903e352c813SSeungwon Jeon * After an error, there may be data lingering 190431bff450SSeungwon Jeon * in the FIFO 1905e352c813SSeungwon Jeon */ 19063a33a94cSSonny Rao dw_mci_reset(host); 1907e352c813SSeungwon Jeon } else { 1908e352c813SSeungwon Jeon data->bytes_xfered = data->blocks * data->blksz; 1909e352c813SSeungwon Jeon data->error = 0; 1910e352c813SSeungwon Jeon } 1911e352c813SSeungwon Jeon 1912e352c813SSeungwon Jeon return data->error; 1913f95f3850SWill Newton } 1914f95f3850SWill Newton 191557e10486SAddy Ke static void dw_mci_set_drto(struct dw_mci *host) 191657e10486SAddy Ke { 191757e10486SAddy Ke unsigned int drto_clks; 191857e10486SAddy Ke unsigned int drto_ms; 191957e10486SAddy Ke 192057e10486SAddy Ke drto_clks = mci_readl(host, TMOUT) >> 8; 192157e10486SAddy Ke drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 192257e10486SAddy Ke 192357e10486SAddy Ke /* add a bit spare time */ 192457e10486SAddy Ke drto_ms += 10; 192557e10486SAddy Ke 192657e10486SAddy Ke mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 192757e10486SAddy Ke } 192857e10486SAddy Ke 1929f95f3850SWill Newton static void dw_mci_tasklet_func(unsigned long priv) 1930f95f3850SWill Newton { 1931f95f3850SWill Newton struct dw_mci *host = (struct dw_mci *)priv; 1932f95f3850SWill Newton struct mmc_data *data; 1933f95f3850SWill Newton struct mmc_command *cmd; 1934e352c813SSeungwon Jeon struct mmc_request *mrq; 1935f95f3850SWill Newton enum dw_mci_state state; 1936f95f3850SWill Newton enum dw_mci_state prev_state; 1937e352c813SSeungwon Jeon unsigned int err; 1938f95f3850SWill Newton 1939f95f3850SWill Newton spin_lock(&host->lock); 1940f95f3850SWill Newton 1941f95f3850SWill Newton state = host->state; 1942f95f3850SWill Newton data = host->data; 1943e352c813SSeungwon Jeon mrq = host->mrq; 1944f95f3850SWill Newton 1945f95f3850SWill Newton do { 1946f95f3850SWill Newton prev_state = state; 1947f95f3850SWill Newton 1948f95f3850SWill Newton switch (state) { 1949f95f3850SWill Newton case STATE_IDLE: 195001730558SDoug Anderson case STATE_WAITING_CMD11_DONE: 1951f95f3850SWill Newton break; 1952f95f3850SWill Newton 195301730558SDoug Anderson case STATE_SENDING_CMD11: 1954f95f3850SWill Newton case STATE_SENDING_CMD: 1955f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1956f95f3850SWill Newton &host->pending_events)) 1957f95f3850SWill Newton break; 1958f95f3850SWill Newton 1959f95f3850SWill Newton cmd = host->cmd; 1960f95f3850SWill Newton host->cmd = NULL; 1961f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1962e352c813SSeungwon Jeon err = dw_mci_command_complete(host, cmd); 1963e352c813SSeungwon Jeon if (cmd == mrq->sbc && !err) { 1964053b3ce6SSeungwon Jeon prev_state = state = STATE_SENDING_CMD; 196542f989c0SJaehoon Chung __dw_mci_start_request(host, host->slot, 1966e352c813SSeungwon Jeon mrq->cmd); 1967053b3ce6SSeungwon Jeon goto unlock; 1968053b3ce6SSeungwon Jeon } 1969053b3ce6SSeungwon Jeon 1970e352c813SSeungwon Jeon if (cmd->data && err) { 197146d17952SDoug Anderson /* 197246d17952SDoug Anderson * During UHS tuning sequence, sending the stop 197346d17952SDoug Anderson * command after the response CRC error would 197446d17952SDoug Anderson * throw the system into a confused state 197546d17952SDoug Anderson * causing all future tuning phases to report 197646d17952SDoug Anderson * failure. 197746d17952SDoug Anderson * 197846d17952SDoug Anderson * In such case controller will move into a data 197946d17952SDoug Anderson * transfer state after a response error or 198046d17952SDoug Anderson * response CRC error. Let's let that finish 198146d17952SDoug Anderson * before trying to send a stop, so we'll go to 198246d17952SDoug Anderson * STATE_SENDING_DATA. 198346d17952SDoug Anderson * 198446d17952SDoug Anderson * Although letting the data transfer take place 198546d17952SDoug Anderson * will waste a bit of time (we already know 198646d17952SDoug Anderson * the command was bad), it can't cause any 198746d17952SDoug Anderson * errors since it's possible it would have 198846d17952SDoug Anderson * taken place anyway if this tasklet got 198946d17952SDoug Anderson * delayed. Allowing the transfer to take place 199046d17952SDoug Anderson * avoids races and keeps things simple. 199146d17952SDoug Anderson */ 199246d17952SDoug Anderson if ((err != -ETIMEDOUT) && 199346d17952SDoug Anderson (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 199446d17952SDoug Anderson state = STATE_SENDING_DATA; 199546d17952SDoug Anderson continue; 199646d17952SDoug Anderson } 199746d17952SDoug Anderson 199871abb133SSeungwon Jeon dw_mci_stop_dma(host); 199990c2143aSSeungwon Jeon send_stop_abort(host, data); 200071abb133SSeungwon Jeon state = STATE_SENDING_STOP; 200171abb133SSeungwon Jeon break; 200271abb133SSeungwon Jeon } 200371abb133SSeungwon Jeon 2004e352c813SSeungwon Jeon if (!cmd->data || err) { 2005e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2006f95f3850SWill Newton goto unlock; 2007f95f3850SWill Newton } 2008f95f3850SWill Newton 2009f95f3850SWill Newton prev_state = state = STATE_SENDING_DATA; 2010f95f3850SWill Newton /* fall through */ 2011f95f3850SWill Newton 2012f95f3850SWill Newton case STATE_SENDING_DATA: 20132aa35465SDoug Anderson /* 20142aa35465SDoug Anderson * We could get a data error and never a transfer 20152aa35465SDoug Anderson * complete so we'd better check for it here. 20162aa35465SDoug Anderson * 20172aa35465SDoug Anderson * Note that we don't really care if we also got a 20182aa35465SDoug Anderson * transfer complete; stopping the DMA and sending an 20192aa35465SDoug Anderson * abort won't hurt. 20202aa35465SDoug Anderson */ 2021f95f3850SWill Newton if (test_and_clear_bit(EVENT_DATA_ERROR, 2022f95f3850SWill Newton &host->pending_events)) { 2023f95f3850SWill Newton dw_mci_stop_dma(host); 2024e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2025bdb9a90bSaddy ke SDMMC_INT_EBE))) 202690c2143aSSeungwon Jeon send_stop_abort(host, data); 2027f95f3850SWill Newton state = STATE_DATA_ERROR; 2028f95f3850SWill Newton break; 2029f95f3850SWill Newton } 2030f95f3850SWill Newton 2031f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 203257e10486SAddy Ke &host->pending_events)) { 203357e10486SAddy Ke /* 203457e10486SAddy Ke * If all data-related interrupts don't come 203557e10486SAddy Ke * within the given time in reading data state. 203657e10486SAddy Ke */ 203716a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 203857e10486SAddy Ke dw_mci_set_drto(host); 2039f95f3850SWill Newton break; 204057e10486SAddy Ke } 2041f95f3850SWill Newton 2042f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 20432aa35465SDoug Anderson 20442aa35465SDoug Anderson /* 20452aa35465SDoug Anderson * Handle an EVENT_DATA_ERROR that might have shown up 20462aa35465SDoug Anderson * before the transfer completed. This might not have 20472aa35465SDoug Anderson * been caught by the check above because the interrupt 20482aa35465SDoug Anderson * could have gone off between the previous check and 20492aa35465SDoug Anderson * the check for transfer complete. 20502aa35465SDoug Anderson * 20512aa35465SDoug Anderson * Technically this ought not be needed assuming we 20522aa35465SDoug Anderson * get a DATA_COMPLETE eventually (we'll notice the 20532aa35465SDoug Anderson * error and end the request), but it shouldn't hurt. 20542aa35465SDoug Anderson * 20552aa35465SDoug Anderson * This has the advantage of sending the stop command. 20562aa35465SDoug Anderson */ 20572aa35465SDoug Anderson if (test_and_clear_bit(EVENT_DATA_ERROR, 20582aa35465SDoug Anderson &host->pending_events)) { 20592aa35465SDoug Anderson dw_mci_stop_dma(host); 2060e13c3c08SJaehoon Chung if (!(host->data_status & (SDMMC_INT_DRTO | 2061bdb9a90bSaddy ke SDMMC_INT_EBE))) 20622aa35465SDoug Anderson send_stop_abort(host, data); 20632aa35465SDoug Anderson state = STATE_DATA_ERROR; 20642aa35465SDoug Anderson break; 20652aa35465SDoug Anderson } 2066f95f3850SWill Newton prev_state = state = STATE_DATA_BUSY; 20672aa35465SDoug Anderson 2068f95f3850SWill Newton /* fall through */ 2069f95f3850SWill Newton 2070f95f3850SWill Newton case STATE_DATA_BUSY: 2071f95f3850SWill Newton if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 207257e10486SAddy Ke &host->pending_events)) { 207357e10486SAddy Ke /* 207457e10486SAddy Ke * If data error interrupt comes but data over 207557e10486SAddy Ke * interrupt doesn't come within the given time. 207657e10486SAddy Ke * in reading data state. 207757e10486SAddy Ke */ 207816a34574SJaehoon Chung if (host->dir_status == DW_MCI_RECV_STATUS) 207957e10486SAddy Ke dw_mci_set_drto(host); 2080f95f3850SWill Newton break; 208157e10486SAddy Ke } 2082f95f3850SWill Newton 2083f95f3850SWill Newton host->data = NULL; 2084f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2085e352c813SSeungwon Jeon err = dw_mci_data_complete(host, data); 2086f95f3850SWill Newton 2087e352c813SSeungwon Jeon if (!err) { 2088e352c813SSeungwon Jeon if (!data->stop || mrq->sbc) { 208917c8bc85SSachin Kamat if (mrq->sbc && data->stop) 2090053b3ce6SSeungwon Jeon data->stop->error = 0; 2091e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2092053b3ce6SSeungwon Jeon goto unlock; 2093053b3ce6SSeungwon Jeon } 2094053b3ce6SSeungwon Jeon 209590c2143aSSeungwon Jeon /* stop command for open-ended transfer*/ 2096e352c813SSeungwon Jeon if (data->stop) 209790c2143aSSeungwon Jeon send_stop_abort(host, data); 20982aa35465SDoug Anderson } else { 20992aa35465SDoug Anderson /* 21002aa35465SDoug Anderson * If we don't have a command complete now we'll 21012aa35465SDoug Anderson * never get one since we just reset everything; 21022aa35465SDoug Anderson * better end the request. 21032aa35465SDoug Anderson * 21042aa35465SDoug Anderson * If we do have a command complete we'll fall 21052aa35465SDoug Anderson * through to the SENDING_STOP command and 21062aa35465SDoug Anderson * everything will be peachy keen. 21072aa35465SDoug Anderson */ 21082aa35465SDoug Anderson if (!test_bit(EVENT_CMD_COMPLETE, 21092aa35465SDoug Anderson &host->pending_events)) { 21102aa35465SDoug Anderson host->cmd = NULL; 21112aa35465SDoug Anderson dw_mci_request_end(host, mrq); 21122aa35465SDoug Anderson goto unlock; 21132aa35465SDoug Anderson } 211490c2143aSSeungwon Jeon } 2115e352c813SSeungwon Jeon 2116e352c813SSeungwon Jeon /* 2117e352c813SSeungwon Jeon * If err has non-zero, 2118e352c813SSeungwon Jeon * stop-abort command has been already issued. 2119e352c813SSeungwon Jeon */ 2120e352c813SSeungwon Jeon prev_state = state = STATE_SENDING_STOP; 2121e352c813SSeungwon Jeon 2122f95f3850SWill Newton /* fall through */ 2123f95f3850SWill Newton 2124f95f3850SWill Newton case STATE_SENDING_STOP: 2125f95f3850SWill Newton if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 2126f95f3850SWill Newton &host->pending_events)) 2127f95f3850SWill Newton break; 2128f95f3850SWill Newton 212971abb133SSeungwon Jeon /* CMD error in data command */ 213031bff450SSeungwon Jeon if (mrq->cmd->error && mrq->data) 21313a33a94cSSonny Rao dw_mci_reset(host); 213271abb133SSeungwon Jeon 2133f95f3850SWill Newton host->cmd = NULL; 213471abb133SSeungwon Jeon host->data = NULL; 213590c2143aSSeungwon Jeon 2136e13c3c08SJaehoon Chung if (!mrq->sbc && mrq->stop) 2137e352c813SSeungwon Jeon dw_mci_command_complete(host, mrq->stop); 213890c2143aSSeungwon Jeon else 213990c2143aSSeungwon Jeon host->cmd_status = 0; 214090c2143aSSeungwon Jeon 2141e352c813SSeungwon Jeon dw_mci_request_end(host, mrq); 2142f95f3850SWill Newton goto unlock; 2143f95f3850SWill Newton 2144f95f3850SWill Newton case STATE_DATA_ERROR: 2145f95f3850SWill Newton if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2146f95f3850SWill Newton &host->pending_events)) 2147f95f3850SWill Newton break; 2148f95f3850SWill Newton 2149f95f3850SWill Newton state = STATE_DATA_BUSY; 2150f95f3850SWill Newton break; 2151f95f3850SWill Newton } 2152f95f3850SWill Newton } while (state != prev_state); 2153f95f3850SWill Newton 2154f95f3850SWill Newton host->state = state; 2155f95f3850SWill Newton unlock: 2156f95f3850SWill Newton spin_unlock(&host->lock); 2157f95f3850SWill Newton 2158f95f3850SWill Newton } 2159f95f3850SWill Newton 216034b664a2SJames Hogan /* push final bytes to part_buf, only use during push */ 216134b664a2SJames Hogan static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 216234b664a2SJames Hogan { 216334b664a2SJames Hogan memcpy((void *)&host->part_buf, buf, cnt); 216434b664a2SJames Hogan host->part_buf_count = cnt; 216534b664a2SJames Hogan } 216634b664a2SJames Hogan 216734b664a2SJames Hogan /* append bytes to part_buf, only use during push */ 216834b664a2SJames Hogan static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 216934b664a2SJames Hogan { 217034b664a2SJames Hogan cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 217134b664a2SJames Hogan memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 217234b664a2SJames Hogan host->part_buf_count += cnt; 217334b664a2SJames Hogan return cnt; 217434b664a2SJames Hogan } 217534b664a2SJames Hogan 217634b664a2SJames Hogan /* pull first bytes from part_buf, only use during pull */ 217734b664a2SJames Hogan static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 217834b664a2SJames Hogan { 21790e3a22c0SShawn Lin cnt = min_t(int, cnt, host->part_buf_count); 218034b664a2SJames Hogan if (cnt) { 218134b664a2SJames Hogan memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 218234b664a2SJames Hogan cnt); 218334b664a2SJames Hogan host->part_buf_count -= cnt; 218434b664a2SJames Hogan host->part_buf_start += cnt; 218534b664a2SJames Hogan } 218634b664a2SJames Hogan return cnt; 218734b664a2SJames Hogan } 218834b664a2SJames Hogan 218934b664a2SJames Hogan /* pull final bytes from the part_buf, assuming it's just been filled */ 219034b664a2SJames Hogan static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 219134b664a2SJames Hogan { 219234b664a2SJames Hogan memcpy(buf, &host->part_buf, cnt); 219334b664a2SJames Hogan host->part_buf_start = cnt; 219434b664a2SJames Hogan host->part_buf_count = (1 << host->data_shift) - cnt; 219534b664a2SJames Hogan } 219634b664a2SJames Hogan 2197f95f3850SWill Newton static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2198f95f3850SWill Newton { 2199cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2200cfbeb59cSMarkos Chandras int init_cnt = cnt; 2201cfbeb59cSMarkos Chandras 220234b664a2SJames Hogan /* try and push anything in the part_buf */ 220334b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 220434b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 22050e3a22c0SShawn Lin 220634b664a2SJames Hogan buf += len; 220734b664a2SJames Hogan cnt -= len; 2208cfbeb59cSMarkos Chandras if (host->part_buf_count == 2) { 220976184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 221034b664a2SJames Hogan host->part_buf_count = 0; 221134b664a2SJames Hogan } 221234b664a2SJames Hogan } 221334b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 221434b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 221534b664a2SJames Hogan while (cnt >= 2) { 221634b664a2SJames Hogan u16 aligned_buf[64]; 221734b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 221834b664a2SJames Hogan int items = len >> 1; 221934b664a2SJames Hogan int i; 222034b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 222134b664a2SJames Hogan memcpy(aligned_buf, buf, len); 222234b664a2SJames Hogan buf += len; 222334b664a2SJames Hogan cnt -= len; 222434b664a2SJames Hogan /* push data from aligned buffer into fifo */ 222534b664a2SJames Hogan for (i = 0; i < items; ++i) 222676184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 222734b664a2SJames Hogan } 222834b664a2SJames Hogan } else 222934b664a2SJames Hogan #endif 223034b664a2SJames Hogan { 223134b664a2SJames Hogan u16 *pdata = buf; 22320e3a22c0SShawn Lin 223334b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 223476184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, *pdata++); 223534b664a2SJames Hogan buf = pdata; 223634b664a2SJames Hogan } 223734b664a2SJames Hogan /* put anything remaining in the part_buf */ 223834b664a2SJames Hogan if (cnt) { 223934b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2240cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2241cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2242cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 224376184ac1SBen Dooks mci_fifo_writew(host->fifo_reg, host->part_buf16); 2244f95f3850SWill Newton } 2245f95f3850SWill Newton } 2246f95f3850SWill Newton 2247f95f3850SWill Newton static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2248f95f3850SWill Newton { 224934b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 225034b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x1)) { 225134b664a2SJames Hogan while (cnt >= 2) { 225234b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 225334b664a2SJames Hogan u16 aligned_buf[64]; 225434b664a2SJames Hogan int len = min(cnt & -2, (int)sizeof(aligned_buf)); 225534b664a2SJames Hogan int items = len >> 1; 225634b664a2SJames Hogan int i; 22570e3a22c0SShawn Lin 225834b664a2SJames Hogan for (i = 0; i < items; ++i) 225976184ac1SBen Dooks aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 226034b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 226134b664a2SJames Hogan memcpy(buf, aligned_buf, len); 226234b664a2SJames Hogan buf += len; 226334b664a2SJames Hogan cnt -= len; 226434b664a2SJames Hogan } 226534b664a2SJames Hogan } else 226634b664a2SJames Hogan #endif 226734b664a2SJames Hogan { 226834b664a2SJames Hogan u16 *pdata = buf; 22690e3a22c0SShawn Lin 227034b664a2SJames Hogan for (; cnt >= 2; cnt -= 2) 227176184ac1SBen Dooks *pdata++ = mci_fifo_readw(host->fifo_reg); 227234b664a2SJames Hogan buf = pdata; 227334b664a2SJames Hogan } 227434b664a2SJames Hogan if (cnt) { 227576184ac1SBen Dooks host->part_buf16 = mci_fifo_readw(host->fifo_reg); 227634b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2277f95f3850SWill Newton } 2278f95f3850SWill Newton } 2279f95f3850SWill Newton 2280f95f3850SWill Newton static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2281f95f3850SWill Newton { 2282cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2283cfbeb59cSMarkos Chandras int init_cnt = cnt; 2284cfbeb59cSMarkos Chandras 228534b664a2SJames Hogan /* try and push anything in the part_buf */ 228634b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 228734b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 22880e3a22c0SShawn Lin 228934b664a2SJames Hogan buf += len; 229034b664a2SJames Hogan cnt -= len; 2291cfbeb59cSMarkos Chandras if (host->part_buf_count == 4) { 229276184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 229334b664a2SJames Hogan host->part_buf_count = 0; 229434b664a2SJames Hogan } 229534b664a2SJames Hogan } 229634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 229734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 229834b664a2SJames Hogan while (cnt >= 4) { 229934b664a2SJames Hogan u32 aligned_buf[32]; 230034b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 230134b664a2SJames Hogan int items = len >> 2; 230234b664a2SJames Hogan int i; 230334b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 230434b664a2SJames Hogan memcpy(aligned_buf, buf, len); 230534b664a2SJames Hogan buf += len; 230634b664a2SJames Hogan cnt -= len; 230734b664a2SJames Hogan /* push data from aligned buffer into fifo */ 230834b664a2SJames Hogan for (i = 0; i < items; ++i) 230976184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 231034b664a2SJames Hogan } 231134b664a2SJames Hogan } else 231234b664a2SJames Hogan #endif 231334b664a2SJames Hogan { 231434b664a2SJames Hogan u32 *pdata = buf; 23150e3a22c0SShawn Lin 231634b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 231776184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, *pdata++); 231834b664a2SJames Hogan buf = pdata; 231934b664a2SJames Hogan } 232034b664a2SJames Hogan /* put anything remaining in the part_buf */ 232134b664a2SJames Hogan if (cnt) { 232234b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2323cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2324cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2325cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 232676184ac1SBen Dooks mci_fifo_writel(host->fifo_reg, host->part_buf32); 2327f95f3850SWill Newton } 2328f95f3850SWill Newton } 2329f95f3850SWill Newton 2330f95f3850SWill Newton static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2331f95f3850SWill Newton { 233234b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 233334b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x3)) { 233434b664a2SJames Hogan while (cnt >= 4) { 233534b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 233634b664a2SJames Hogan u32 aligned_buf[32]; 233734b664a2SJames Hogan int len = min(cnt & -4, (int)sizeof(aligned_buf)); 233834b664a2SJames Hogan int items = len >> 2; 233934b664a2SJames Hogan int i; 23400e3a22c0SShawn Lin 234134b664a2SJames Hogan for (i = 0; i < items; ++i) 234276184ac1SBen Dooks aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 234334b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 234434b664a2SJames Hogan memcpy(buf, aligned_buf, len); 234534b664a2SJames Hogan buf += len; 234634b664a2SJames Hogan cnt -= len; 234734b664a2SJames Hogan } 234834b664a2SJames Hogan } else 234934b664a2SJames Hogan #endif 235034b664a2SJames Hogan { 235134b664a2SJames Hogan u32 *pdata = buf; 23520e3a22c0SShawn Lin 235334b664a2SJames Hogan for (; cnt >= 4; cnt -= 4) 235476184ac1SBen Dooks *pdata++ = mci_fifo_readl(host->fifo_reg); 235534b664a2SJames Hogan buf = pdata; 235634b664a2SJames Hogan } 235734b664a2SJames Hogan if (cnt) { 235876184ac1SBen Dooks host->part_buf32 = mci_fifo_readl(host->fifo_reg); 235934b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 2360f95f3850SWill Newton } 2361f95f3850SWill Newton } 2362f95f3850SWill Newton 2363f95f3850SWill Newton static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2364f95f3850SWill Newton { 2365cfbeb59cSMarkos Chandras struct mmc_data *data = host->data; 2366cfbeb59cSMarkos Chandras int init_cnt = cnt; 2367cfbeb59cSMarkos Chandras 236834b664a2SJames Hogan /* try and push anything in the part_buf */ 236934b664a2SJames Hogan if (unlikely(host->part_buf_count)) { 237034b664a2SJames Hogan int len = dw_mci_push_part_bytes(host, buf, cnt); 23710e3a22c0SShawn Lin 237234b664a2SJames Hogan buf += len; 237334b664a2SJames Hogan cnt -= len; 2374c09fbd74SSeungwon Jeon 2375cfbeb59cSMarkos Chandras if (host->part_buf_count == 8) { 237676184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 237734b664a2SJames Hogan host->part_buf_count = 0; 237834b664a2SJames Hogan } 237934b664a2SJames Hogan } 238034b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 238134b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 238234b664a2SJames Hogan while (cnt >= 8) { 238334b664a2SJames Hogan u64 aligned_buf[16]; 238434b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 238534b664a2SJames Hogan int items = len >> 3; 238634b664a2SJames Hogan int i; 238734b664a2SJames Hogan /* memcpy from input buffer into aligned buffer */ 238834b664a2SJames Hogan memcpy(aligned_buf, buf, len); 238934b664a2SJames Hogan buf += len; 239034b664a2SJames Hogan cnt -= len; 239134b664a2SJames Hogan /* push data from aligned buffer into fifo */ 239234b664a2SJames Hogan for (i = 0; i < items; ++i) 239376184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 239434b664a2SJames Hogan } 239534b664a2SJames Hogan } else 239634b664a2SJames Hogan #endif 239734b664a2SJames Hogan { 239834b664a2SJames Hogan u64 *pdata = buf; 23990e3a22c0SShawn Lin 240034b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 240176184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, *pdata++); 240234b664a2SJames Hogan buf = pdata; 240334b664a2SJames Hogan } 240434b664a2SJames Hogan /* put anything remaining in the part_buf */ 240534b664a2SJames Hogan if (cnt) { 240634b664a2SJames Hogan dw_mci_set_part_bytes(host, buf, cnt); 2407cfbeb59cSMarkos Chandras /* Push data if we have reached the expected data length */ 2408cfbeb59cSMarkos Chandras if ((data->bytes_xfered + init_cnt) == 2409cfbeb59cSMarkos Chandras (data->blksz * data->blocks)) 241076184ac1SBen Dooks mci_fifo_writeq(host->fifo_reg, host->part_buf); 2411f95f3850SWill Newton } 2412f95f3850SWill Newton } 2413f95f3850SWill Newton 2414f95f3850SWill Newton static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2415f95f3850SWill Newton { 241634b664a2SJames Hogan #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 241734b664a2SJames Hogan if (unlikely((unsigned long)buf & 0x7)) { 241834b664a2SJames Hogan while (cnt >= 8) { 241934b664a2SJames Hogan /* pull data from fifo into aligned buffer */ 242034b664a2SJames Hogan u64 aligned_buf[16]; 242134b664a2SJames Hogan int len = min(cnt & -8, (int)sizeof(aligned_buf)); 242234b664a2SJames Hogan int items = len >> 3; 242334b664a2SJames Hogan int i; 24240e3a22c0SShawn Lin 242534b664a2SJames Hogan for (i = 0; i < items; ++i) 242676184ac1SBen Dooks aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 242776184ac1SBen Dooks 242834b664a2SJames Hogan /* memcpy from aligned buffer into output buffer */ 242934b664a2SJames Hogan memcpy(buf, aligned_buf, len); 243034b664a2SJames Hogan buf += len; 243134b664a2SJames Hogan cnt -= len; 2432f95f3850SWill Newton } 243334b664a2SJames Hogan } else 243434b664a2SJames Hogan #endif 243534b664a2SJames Hogan { 243634b664a2SJames Hogan u64 *pdata = buf; 24370e3a22c0SShawn Lin 243834b664a2SJames Hogan for (; cnt >= 8; cnt -= 8) 243976184ac1SBen Dooks *pdata++ = mci_fifo_readq(host->fifo_reg); 244034b664a2SJames Hogan buf = pdata; 244134b664a2SJames Hogan } 244234b664a2SJames Hogan if (cnt) { 244376184ac1SBen Dooks host->part_buf = mci_fifo_readq(host->fifo_reg); 244434b664a2SJames Hogan dw_mci_pull_final_bytes(host, buf, cnt); 244534b664a2SJames Hogan } 244634b664a2SJames Hogan } 244734b664a2SJames Hogan 244834b664a2SJames Hogan static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 244934b664a2SJames Hogan { 245034b664a2SJames Hogan int len; 245134b664a2SJames Hogan 245234b664a2SJames Hogan /* get remaining partial bytes */ 245334b664a2SJames Hogan len = dw_mci_pull_part_bytes(host, buf, cnt); 245434b664a2SJames Hogan if (unlikely(len == cnt)) 245534b664a2SJames Hogan return; 245634b664a2SJames Hogan buf += len; 245734b664a2SJames Hogan cnt -= len; 245834b664a2SJames Hogan 245934b664a2SJames Hogan /* get the rest of the data */ 246034b664a2SJames Hogan host->pull_data(host, buf, cnt); 2461f95f3850SWill Newton } 2462f95f3850SWill Newton 246387a74d39SKyoungil Kim static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2464f95f3850SWill Newton { 2465f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2466f9c2a0dcSSeungwon Jeon void *buf; 2467f9c2a0dcSSeungwon Jeon unsigned int offset; 2468f95f3850SWill Newton struct mmc_data *data = host->data; 2469f95f3850SWill Newton int shift = host->data_shift; 2470f95f3850SWill Newton u32 status; 24713e4b0d8bSMarkos Chandras unsigned int len; 2472f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2473f95f3850SWill Newton 2474f95f3850SWill Newton do { 2475f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2476f9c2a0dcSSeungwon Jeon goto done; 2477f95f3850SWill Newton 24784225fc85SImre Deak host->sg = sg_miter->piter.sg; 2479f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2480f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2481f9c2a0dcSSeungwon Jeon offset = 0; 2482f9c2a0dcSSeungwon Jeon 2483f9c2a0dcSSeungwon Jeon do { 2484f9c2a0dcSSeungwon Jeon fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2485f9c2a0dcSSeungwon Jeon << shift) + host->part_buf_count; 2486f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2487f9c2a0dcSSeungwon Jeon if (!len) 2488f9c2a0dcSSeungwon Jeon break; 2489f9c2a0dcSSeungwon Jeon dw_mci_pull_data(host, (void *)(buf + offset), len); 24903e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2491f95f3850SWill Newton offset += len; 2492f9c2a0dcSSeungwon Jeon remain -= len; 2493f9c2a0dcSSeungwon Jeon } while (remain); 2494f95f3850SWill Newton 2495e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2496f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2497f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 249887a74d39SKyoungil Kim /* if the RXDR is ready read again */ 249987a74d39SKyoungil Kim } while ((status & SDMMC_INT_RXDR) || 250087a74d39SKyoungil Kim (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2501f9c2a0dcSSeungwon Jeon 2502f9c2a0dcSSeungwon Jeon if (!remain) { 2503f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2504f9c2a0dcSSeungwon Jeon goto done; 2505f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2506f9c2a0dcSSeungwon Jeon } 2507f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2508f95f3850SWill Newton return; 2509f95f3850SWill Newton 2510f95f3850SWill Newton done: 2511f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2512f9c2a0dcSSeungwon Jeon host->sg = NULL; 25130e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2514f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2515f95f3850SWill Newton } 2516f95f3850SWill Newton 2517f95f3850SWill Newton static void dw_mci_write_data_pio(struct dw_mci *host) 2518f95f3850SWill Newton { 2519f9c2a0dcSSeungwon Jeon struct sg_mapping_iter *sg_miter = &host->sg_miter; 2520f9c2a0dcSSeungwon Jeon void *buf; 2521f9c2a0dcSSeungwon Jeon unsigned int offset; 2522f95f3850SWill Newton struct mmc_data *data = host->data; 2523f95f3850SWill Newton int shift = host->data_shift; 2524f95f3850SWill Newton u32 status; 25253e4b0d8bSMarkos Chandras unsigned int len; 2526f9c2a0dcSSeungwon Jeon unsigned int fifo_depth = host->fifo_depth; 2527f9c2a0dcSSeungwon Jeon unsigned int remain, fcnt; 2528f95f3850SWill Newton 2529f95f3850SWill Newton do { 2530f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2531f9c2a0dcSSeungwon Jeon goto done; 2532f95f3850SWill Newton 25334225fc85SImre Deak host->sg = sg_miter->piter.sg; 2534f9c2a0dcSSeungwon Jeon buf = sg_miter->addr; 2535f9c2a0dcSSeungwon Jeon remain = sg_miter->length; 2536f9c2a0dcSSeungwon Jeon offset = 0; 2537f9c2a0dcSSeungwon Jeon 2538f9c2a0dcSSeungwon Jeon do { 2539f9c2a0dcSSeungwon Jeon fcnt = ((fifo_depth - 2540f9c2a0dcSSeungwon Jeon SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2541f9c2a0dcSSeungwon Jeon << shift) - host->part_buf_count; 2542f9c2a0dcSSeungwon Jeon len = min(remain, fcnt); 2543f9c2a0dcSSeungwon Jeon if (!len) 2544f9c2a0dcSSeungwon Jeon break; 2545f9c2a0dcSSeungwon Jeon host->push_data(host, (void *)(buf + offset), len); 25463e4b0d8bSMarkos Chandras data->bytes_xfered += len; 2547f95f3850SWill Newton offset += len; 2548f9c2a0dcSSeungwon Jeon remain -= len; 2549f9c2a0dcSSeungwon Jeon } while (remain); 2550f95f3850SWill Newton 2551e74f3a9cSSeungwon Jeon sg_miter->consumed = offset; 2552f95f3850SWill Newton status = mci_readl(host, MINTSTS); 2553f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2554f95f3850SWill Newton } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2555f9c2a0dcSSeungwon Jeon 2556f9c2a0dcSSeungwon Jeon if (!remain) { 2557f9c2a0dcSSeungwon Jeon if (!sg_miter_next(sg_miter)) 2558f9c2a0dcSSeungwon Jeon goto done; 2559f9c2a0dcSSeungwon Jeon sg_miter->consumed = 0; 2560f9c2a0dcSSeungwon Jeon } 2561f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2562f95f3850SWill Newton return; 2563f95f3850SWill Newton 2564f95f3850SWill Newton done: 2565f9c2a0dcSSeungwon Jeon sg_miter_stop(sg_miter); 2566f9c2a0dcSSeungwon Jeon host->sg = NULL; 25670e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2568f95f3850SWill Newton set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2569f95f3850SWill Newton } 2570f95f3850SWill Newton 2571f95f3850SWill Newton static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2572f95f3850SWill Newton { 2573f95f3850SWill Newton if (!host->cmd_status) 2574f95f3850SWill Newton host->cmd_status = status; 2575f95f3850SWill Newton 25760e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2577f95f3850SWill Newton 2578f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2579f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2580f95f3850SWill Newton } 2581f95f3850SWill Newton 25826130e7a9SDoug Anderson static void dw_mci_handle_cd(struct dw_mci *host) 25836130e7a9SDoug Anderson { 2584b23475faSJaehoon Chung struct dw_mci_slot *slot = host->slot; 25856130e7a9SDoug Anderson 25866130e7a9SDoug Anderson if (slot->mmc->ops->card_event) 25876130e7a9SDoug Anderson slot->mmc->ops->card_event(slot->mmc); 25886130e7a9SDoug Anderson mmc_detect_change(slot->mmc, 25896130e7a9SDoug Anderson msecs_to_jiffies(host->pdata->detect_delay_ms)); 25906130e7a9SDoug Anderson } 25916130e7a9SDoug Anderson 2592f95f3850SWill Newton static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2593f95f3850SWill Newton { 2594f95f3850SWill Newton struct dw_mci *host = dev_id; 2595182c9081SSeungwon Jeon u32 pending; 2596b23475faSJaehoon Chung struct dw_mci_slot *slot = host->slot; 2597f95f3850SWill Newton 2598f95f3850SWill Newton pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2599f95f3850SWill Newton 2600476d79f1SDoug Anderson if (pending) { 260101730558SDoug Anderson /* Check volt switch first, since it can look like an error */ 260201730558SDoug Anderson if ((host->state == STATE_SENDING_CMD11) && 260301730558SDoug Anderson (pending & SDMMC_INT_VOLT_SWITCH)) { 260449ba0302SDoug Anderson unsigned long irqflags; 26055c935165SDoug Anderson 260601730558SDoug Anderson mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 260701730558SDoug Anderson pending &= ~SDMMC_INT_VOLT_SWITCH; 260849ba0302SDoug Anderson 260949ba0302SDoug Anderson /* 261049ba0302SDoug Anderson * Hold the lock; we know cmd11_timer can't be kicked 261149ba0302SDoug Anderson * off after the lock is released, so safe to delete. 261249ba0302SDoug Anderson */ 261349ba0302SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 261401730558SDoug Anderson dw_mci_cmd_interrupt(host, pending); 261549ba0302SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 261649ba0302SDoug Anderson 261749ba0302SDoug Anderson del_timer(&host->cmd11_timer); 261801730558SDoug Anderson } 261901730558SDoug Anderson 2620f95f3850SWill Newton if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2621*03de1921SAddy Ke del_timer(&host->cto_timer); 2622f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2623182c9081SSeungwon Jeon host->cmd_status = pending; 26240e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2625f95f3850SWill Newton set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2626f95f3850SWill Newton } 2627f95f3850SWill Newton 2628f95f3850SWill Newton if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2629f95f3850SWill Newton /* if there is an error report DATA_ERROR */ 2630f95f3850SWill Newton mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2631182c9081SSeungwon Jeon host->data_status = pending; 26320e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2633f95f3850SWill Newton set_bit(EVENT_DATA_ERROR, &host->pending_events); 2634f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2635f95f3850SWill Newton } 2636f95f3850SWill Newton 2637f95f3850SWill Newton if (pending & SDMMC_INT_DATA_OVER) { 263857e10486SAddy Ke del_timer(&host->dto_timer); 263957e10486SAddy Ke 2640f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2641f95f3850SWill Newton if (!host->data_status) 2642182c9081SSeungwon Jeon host->data_status = pending; 26430e3a22c0SShawn Lin smp_wmb(); /* drain writebuffer */ 2644f95f3850SWill Newton if (host->dir_status == DW_MCI_RECV_STATUS) { 2645f95f3850SWill Newton if (host->sg != NULL) 264687a74d39SKyoungil Kim dw_mci_read_data_pio(host, true); 2647f95f3850SWill Newton } 2648f95f3850SWill Newton set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2649f95f3850SWill Newton tasklet_schedule(&host->tasklet); 2650f95f3850SWill Newton } 2651f95f3850SWill Newton 2652f95f3850SWill Newton if (pending & SDMMC_INT_RXDR) { 2653f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2654b40af3aaSJames Hogan if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 265587a74d39SKyoungil Kim dw_mci_read_data_pio(host, false); 2656f95f3850SWill Newton } 2657f95f3850SWill Newton 2658f95f3850SWill Newton if (pending & SDMMC_INT_TXDR) { 2659f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2660b40af3aaSJames Hogan if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2661f95f3850SWill Newton dw_mci_write_data_pio(host); 2662f95f3850SWill Newton } 2663f95f3850SWill Newton 2664f95f3850SWill Newton if (pending & SDMMC_INT_CMD_DONE) { 2665*03de1921SAddy Ke del_timer(&host->cto_timer); 2666f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2667182c9081SSeungwon Jeon dw_mci_cmd_interrupt(host, pending); 2668f95f3850SWill Newton } 2669f95f3850SWill Newton 2670f95f3850SWill Newton if (pending & SDMMC_INT_CD) { 2671f95f3850SWill Newton mci_writel(host, RINTSTS, SDMMC_INT_CD); 26726130e7a9SDoug Anderson dw_mci_handle_cd(host); 2673f95f3850SWill Newton } 2674f95f3850SWill Newton 267576756234SAddy Ke if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 267676756234SAddy Ke mci_writel(host, RINTSTS, 267776756234SAddy Ke SDMMC_INT_SDIO(slot->sdio_id)); 267832dba737SUlf Hansson __dw_mci_enable_sdio_irq(slot, 0); 267932dba737SUlf Hansson sdio_signal_irq(slot->mmc); 26801a5c8e1fSShashidhar Hiremath } 26811a5c8e1fSShashidhar Hiremath 26821fb5f68aSMarkos Chandras } 2683f95f3850SWill Newton 26843fc7eaefSShawn Lin if (host->use_dma != TRANS_MODE_IDMAC) 26853fc7eaefSShawn Lin return IRQ_HANDLED; 26863fc7eaefSShawn Lin 26873fc7eaefSShawn Lin /* Handle IDMA interrupts */ 268869d99fdcSPrabu Thangamuthu if (host->dma_64bit_address == 1) { 268969d99fdcSPrabu Thangamuthu pending = mci_readl(host, IDSTS64); 269069d99fdcSPrabu Thangamuthu if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 269169d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 269269d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 269369d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2694faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 26953fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 269669d99fdcSPrabu Thangamuthu } 269769d99fdcSPrabu Thangamuthu } else { 2698f95f3850SWill Newton pending = mci_readl(host, IDSTS); 2699f95f3850SWill Newton if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 270069d99fdcSPrabu Thangamuthu mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 270169d99fdcSPrabu Thangamuthu SDMMC_IDMAC_INT_RI); 2702f95f3850SWill Newton mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2703faecf411SShawn Lin if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 27043fc7eaefSShawn Lin host->dma_ops->complete((void *)host); 2705f95f3850SWill Newton } 270669d99fdcSPrabu Thangamuthu } 2707f95f3850SWill Newton 2708f95f3850SWill Newton return IRQ_HANDLED; 2709f95f3850SWill Newton } 2710f95f3850SWill Newton 2711e4a65ef7SJaehoon Chung static int dw_mci_init_slot(struct dw_mci *host) 2712f95f3850SWill Newton { 2713f95f3850SWill Newton struct mmc_host *mmc; 2714f95f3850SWill Newton struct dw_mci_slot *slot; 2715e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2716800d78bfSThomas Abraham int ctrl_id, ret; 27171f44a2a5SSeungwon Jeon u32 freq[2]; 2718f95f3850SWill Newton 27194a90920cSThomas Abraham mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2720f95f3850SWill Newton if (!mmc) 2721f95f3850SWill Newton return -ENOMEM; 2722f95f3850SWill Newton 2723f95f3850SWill Newton slot = mmc_priv(mmc); 2724e4a65ef7SJaehoon Chung slot->id = 0; 2725e4a65ef7SJaehoon Chung slot->sdio_id = host->sdio_id0 + slot->id; 2726f95f3850SWill Newton slot->mmc = mmc; 2727f95f3850SWill Newton slot->host = host; 2728b23475faSJaehoon Chung host->slot = slot; 2729f95f3850SWill Newton 2730f95f3850SWill Newton mmc->ops = &dw_mci_ops; 2731852ff5feSDavid Woods if (device_property_read_u32_array(host->dev, "clock-freq-min-max", 2732852ff5feSDavid Woods freq, 2)) { 27331f44a2a5SSeungwon Jeon mmc->f_min = DW_MCI_FREQ_MIN; 27341f44a2a5SSeungwon Jeon mmc->f_max = DW_MCI_FREQ_MAX; 27351f44a2a5SSeungwon Jeon } else { 2736b023030fSJaehoon Chung dev_info(host->dev, 2737b023030fSJaehoon Chung "'clock-freq-min-max' property was deprecated.\n"); 27381f44a2a5SSeungwon Jeon mmc->f_min = freq[0]; 27391f44a2a5SSeungwon Jeon mmc->f_max = freq[1]; 27401f44a2a5SSeungwon Jeon } 2741f95f3850SWill Newton 274251da2240SYuvaraj CD /*if there are external regulators, get them*/ 274351da2240SYuvaraj CD ret = mmc_regulator_get_supply(mmc); 274451da2240SYuvaraj CD if (ret == -EPROBE_DEFER) 27453cf890fcSDoug Anderson goto err_host_allocated; 274651da2240SYuvaraj CD 274751da2240SYuvaraj CD if (!mmc->ocr_avail) 2748f95f3850SWill Newton mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2749f95f3850SWill Newton 2750fc3d7720SJaehoon Chung if (host->pdata->caps) 2751fc3d7720SJaehoon Chung mmc->caps = host->pdata->caps; 2752fc3d7720SJaehoon Chung 27536024e166SJaehoon Chung /* 27546024e166SJaehoon Chung * Support MMC_CAP_ERASE by default. 27556024e166SJaehoon Chung * It needs to use trim/discard/erase commands. 27566024e166SJaehoon Chung */ 27576024e166SJaehoon Chung mmc->caps |= MMC_CAP_ERASE; 27586024e166SJaehoon Chung 2759ab269128SAbhilash Kesavan if (host->pdata->pm_caps) 2760ab269128SAbhilash Kesavan mmc->pm_caps = host->pdata->pm_caps; 2761ab269128SAbhilash Kesavan 2762800d78bfSThomas Abraham if (host->dev->of_node) { 2763800d78bfSThomas Abraham ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2764800d78bfSThomas Abraham if (ctrl_id < 0) 2765800d78bfSThomas Abraham ctrl_id = 0; 2766800d78bfSThomas Abraham } else { 2767800d78bfSThomas Abraham ctrl_id = to_platform_device(host->dev)->id; 2768800d78bfSThomas Abraham } 2769cb27a843SJames Hogan if (drv_data && drv_data->caps) 2770cb27a843SJames Hogan mmc->caps |= drv_data->caps[ctrl_id]; 2771800d78bfSThomas Abraham 27724f408cc6SSeungwon Jeon if (host->pdata->caps2) 27734f408cc6SSeungwon Jeon mmc->caps2 = host->pdata->caps2; 27744f408cc6SSeungwon Jeon 27753cf890fcSDoug Anderson ret = mmc_of_parse(mmc); 27763cf890fcSDoug Anderson if (ret) 27773cf890fcSDoug Anderson goto err_host_allocated; 2778f95f3850SWill Newton 277932dba737SUlf Hansson /* Process SDIO IRQs through the sdio_irq_work. */ 278032dba737SUlf Hansson if (mmc->caps & MMC_CAP_SDIO_IRQ) 278132dba737SUlf Hansson mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 278232dba737SUlf Hansson 2783f95f3850SWill Newton /* Useful defaults if platform data is unset. */ 27843fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 2785a39e5746SJaehoon Chung mmc->max_segs = host->ring_size; 2786225faf87SJaehoon Chung mmc->max_blk_size = 65535; 2787575c319dSHeiko Stuebner mmc->max_seg_size = 0x1000; 27881a25b1b4SSeungwon Jeon mmc->max_req_size = mmc->max_seg_size * host->ring_size; 27891a25b1b4SSeungwon Jeon mmc->max_blk_count = mmc->max_req_size / 512; 27903fc7eaefSShawn Lin } else if (host->use_dma == TRANS_MODE_EDMAC) { 27913fc7eaefSShawn Lin mmc->max_segs = 64; 2792225faf87SJaehoon Chung mmc->max_blk_size = 65535; 27933fc7eaefSShawn Lin mmc->max_blk_count = 65535; 27943fc7eaefSShawn Lin mmc->max_req_size = 27953fc7eaefSShawn Lin mmc->max_blk_size * mmc->max_blk_count; 27963fc7eaefSShawn Lin mmc->max_seg_size = mmc->max_req_size; 2797575c319dSHeiko Stuebner } else { 27983fc7eaefSShawn Lin /* TRANS_MODE_PIO */ 2799f95f3850SWill Newton mmc->max_segs = 64; 2800225faf87SJaehoon Chung mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2801f95f3850SWill Newton mmc->max_blk_count = 512; 2802575c319dSHeiko Stuebner mmc->max_req_size = mmc->max_blk_size * 2803575c319dSHeiko Stuebner mmc->max_blk_count; 2804f95f3850SWill Newton mmc->max_seg_size = mmc->max_req_size; 2805575c319dSHeiko Stuebner } 2806f95f3850SWill Newton 2807c0834a58SShawn Lin dw_mci_get_cd(mmc); 2808ae0eb348SJaehoon Chung 28090cea529dSJaehoon Chung ret = mmc_add_host(mmc); 28100cea529dSJaehoon Chung if (ret) 28113cf890fcSDoug Anderson goto err_host_allocated; 2812f95f3850SWill Newton 2813f95f3850SWill Newton #if defined(CONFIG_DEBUG_FS) 2814f95f3850SWill Newton dw_mci_init_debugfs(slot); 2815f95f3850SWill Newton #endif 2816f95f3850SWill Newton 2817f95f3850SWill Newton return 0; 2818800d78bfSThomas Abraham 28193cf890fcSDoug Anderson err_host_allocated: 2820800d78bfSThomas Abraham mmc_free_host(mmc); 282151da2240SYuvaraj CD return ret; 2822f95f3850SWill Newton } 2823f95f3850SWill Newton 2824e4a65ef7SJaehoon Chung static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2825f95f3850SWill Newton { 2826f95f3850SWill Newton /* Debugfs stuff is cleaned up by mmc core */ 2827f95f3850SWill Newton mmc_remove_host(slot->mmc); 2828b23475faSJaehoon Chung slot->host->slot = NULL; 2829f95f3850SWill Newton mmc_free_host(slot->mmc); 2830f95f3850SWill Newton } 2831f95f3850SWill Newton 2832f95f3850SWill Newton static void dw_mci_init_dma(struct dw_mci *host) 2833f95f3850SWill Newton { 283469d99fdcSPrabu Thangamuthu int addr_config; 28353fc7eaefSShawn Lin struct device *dev = host->dev; 28363fc7eaefSShawn Lin 28373fc7eaefSShawn Lin /* 28383fc7eaefSShawn Lin * Check tansfer mode from HCON[17:16] 28393fc7eaefSShawn Lin * Clear the ambiguous description of dw_mmc databook: 28403fc7eaefSShawn Lin * 2b'00: No DMA Interface -> Actually means using Internal DMA block 28413fc7eaefSShawn Lin * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 28423fc7eaefSShawn Lin * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 28433fc7eaefSShawn Lin * 2b'11: Non DW DMA Interface -> pio only 28443fc7eaefSShawn Lin * Compared to DesignWare DMA Interface, Generic DMA Interface has a 28453fc7eaefSShawn Lin * simpler request/acknowledge handshake mechanism and both of them 28463fc7eaefSShawn Lin * are regarded as external dma master for dw_mmc. 28473fc7eaefSShawn Lin */ 28483fc7eaefSShawn Lin host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 28493fc7eaefSShawn Lin if (host->use_dma == DMA_INTERFACE_IDMA) { 28503fc7eaefSShawn Lin host->use_dma = TRANS_MODE_IDMAC; 28513fc7eaefSShawn Lin } else if (host->use_dma == DMA_INTERFACE_DWDMA || 28523fc7eaefSShawn Lin host->use_dma == DMA_INTERFACE_GDMA) { 28533fc7eaefSShawn Lin host->use_dma = TRANS_MODE_EDMAC; 28543fc7eaefSShawn Lin } else { 28553fc7eaefSShawn Lin goto no_dma; 28563fc7eaefSShawn Lin } 28573fc7eaefSShawn Lin 28583fc7eaefSShawn Lin /* Determine which DMA interface to use */ 28593fc7eaefSShawn Lin if (host->use_dma == TRANS_MODE_IDMAC) { 28603fc7eaefSShawn Lin /* 28613fc7eaefSShawn Lin * Check ADDR_CONFIG bit in HCON to find 28623fc7eaefSShawn Lin * IDMAC address bus width 28633fc7eaefSShawn Lin */ 286470692752SShawn Lin addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 286569d99fdcSPrabu Thangamuthu 286669d99fdcSPrabu Thangamuthu if (addr_config == 1) { 286769d99fdcSPrabu Thangamuthu /* host supports IDMAC in 64-bit address mode */ 286869d99fdcSPrabu Thangamuthu host->dma_64bit_address = 1; 28693fc7eaefSShawn Lin dev_info(host->dev, 28703fc7eaefSShawn Lin "IDMAC supports 64-bit address mode.\n"); 287169d99fdcSPrabu Thangamuthu if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 28723fc7eaefSShawn Lin dma_set_coherent_mask(host->dev, 28733fc7eaefSShawn Lin DMA_BIT_MASK(64)); 287469d99fdcSPrabu Thangamuthu } else { 287569d99fdcSPrabu Thangamuthu /* host supports IDMAC in 32-bit address mode */ 287669d99fdcSPrabu Thangamuthu host->dma_64bit_address = 0; 28773fc7eaefSShawn Lin dev_info(host->dev, 28783fc7eaefSShawn Lin "IDMAC supports 32-bit address mode.\n"); 287969d99fdcSPrabu Thangamuthu } 288069d99fdcSPrabu Thangamuthu 2881f95f3850SWill Newton /* Alloc memory for sg translation */ 2882cc190d4cSShawn Lin host->sg_cpu = dmam_alloc_coherent(host->dev, 2883cc190d4cSShawn Lin DESC_RING_BUF_SZ, 2884f95f3850SWill Newton &host->sg_dma, GFP_KERNEL); 2885f95f3850SWill Newton if (!host->sg_cpu) { 28863fc7eaefSShawn Lin dev_err(host->dev, 28873fc7eaefSShawn Lin "%s: could not alloc DMA memory\n", 2888f95f3850SWill Newton __func__); 2889f95f3850SWill Newton goto no_dma; 2890f95f3850SWill Newton } 2891f95f3850SWill Newton 2892f95f3850SWill Newton host->dma_ops = &dw_mci_idmac_ops; 289300956ea3SSeungwon Jeon dev_info(host->dev, "Using internal DMA controller.\n"); 28943fc7eaefSShawn Lin } else { 28953fc7eaefSShawn Lin /* TRANS_MODE_EDMAC: check dma bindings again */ 2896852ff5feSDavid Woods if ((device_property_read_string_array(dev, "dma-names", 2897852ff5feSDavid Woods NULL, 0) < 0) || 2898852ff5feSDavid Woods !device_property_present(dev, "dmas")) { 2899f95f3850SWill Newton goto no_dma; 29003fc7eaefSShawn Lin } 29013fc7eaefSShawn Lin host->dma_ops = &dw_mci_edmac_ops; 29023fc7eaefSShawn Lin dev_info(host->dev, "Using external DMA controller.\n"); 29033fc7eaefSShawn Lin } 2904f95f3850SWill Newton 2905e1631f98SJaehoon Chung if (host->dma_ops->init && host->dma_ops->start && 2906e1631f98SJaehoon Chung host->dma_ops->stop && host->dma_ops->cleanup) { 2907f95f3850SWill Newton if (host->dma_ops->init(host)) { 29080e3a22c0SShawn Lin dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 29090e3a22c0SShawn Lin __func__); 2910f95f3850SWill Newton goto no_dma; 2911f95f3850SWill Newton } 2912f95f3850SWill Newton } else { 29134a90920cSThomas Abraham dev_err(host->dev, "DMA initialization not found.\n"); 2914f95f3850SWill Newton goto no_dma; 2915f95f3850SWill Newton } 2916f95f3850SWill Newton 2917f95f3850SWill Newton return; 2918f95f3850SWill Newton 2919f95f3850SWill Newton no_dma: 29204a90920cSThomas Abraham dev_info(host->dev, "Using PIO mode.\n"); 29213fc7eaefSShawn Lin host->use_dma = TRANS_MODE_PIO; 2922f95f3850SWill Newton } 2923f95f3850SWill Newton 29245c935165SDoug Anderson static void dw_mci_cmd11_timer(unsigned long arg) 29255c935165SDoug Anderson { 29265c935165SDoug Anderson struct dw_mci *host = (struct dw_mci *)arg; 29275c935165SDoug Anderson 2928fd674198SDoug Anderson if (host->state != STATE_SENDING_CMD11) { 2929fd674198SDoug Anderson dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2930fd674198SDoug Anderson return; 2931fd674198SDoug Anderson } 29325c935165SDoug Anderson 29335c935165SDoug Anderson host->cmd_status = SDMMC_INT_RTO; 29345c935165SDoug Anderson set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 29355c935165SDoug Anderson tasklet_schedule(&host->tasklet); 29365c935165SDoug Anderson } 29375c935165SDoug Anderson 2938*03de1921SAddy Ke static void dw_mci_cto_timer(unsigned long arg) 2939*03de1921SAddy Ke { 2940*03de1921SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 2941*03de1921SAddy Ke 2942*03de1921SAddy Ke switch (host->state) { 2943*03de1921SAddy Ke case STATE_SENDING_CMD11: 2944*03de1921SAddy Ke case STATE_SENDING_CMD: 2945*03de1921SAddy Ke case STATE_SENDING_STOP: 2946*03de1921SAddy Ke /* 2947*03de1921SAddy Ke * If CMD_DONE interrupt does NOT come in sending command 2948*03de1921SAddy Ke * state, we should notify the driver to terminate current 2949*03de1921SAddy Ke * transfer and report a command timeout to the core. 2950*03de1921SAddy Ke */ 2951*03de1921SAddy Ke host->cmd_status = SDMMC_INT_RTO; 2952*03de1921SAddy Ke set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2953*03de1921SAddy Ke tasklet_schedule(&host->tasklet); 2954*03de1921SAddy Ke break; 2955*03de1921SAddy Ke default: 2956*03de1921SAddy Ke dev_warn(host->dev, "Unexpected command timeout, state %d\n", 2957*03de1921SAddy Ke host->state); 2958*03de1921SAddy Ke break; 2959*03de1921SAddy Ke } 2960*03de1921SAddy Ke } 2961*03de1921SAddy Ke 296257e10486SAddy Ke static void dw_mci_dto_timer(unsigned long arg) 296357e10486SAddy Ke { 296457e10486SAddy Ke struct dw_mci *host = (struct dw_mci *)arg; 296557e10486SAddy Ke 296657e10486SAddy Ke switch (host->state) { 296757e10486SAddy Ke case STATE_SENDING_DATA: 296857e10486SAddy Ke case STATE_DATA_BUSY: 296957e10486SAddy Ke /* 297057e10486SAddy Ke * If DTO interrupt does NOT come in sending data state, 297157e10486SAddy Ke * we should notify the driver to terminate current transfer 297257e10486SAddy Ke * and report a data timeout to the core. 297357e10486SAddy Ke */ 297457e10486SAddy Ke host->data_status = SDMMC_INT_DRTO; 297557e10486SAddy Ke set_bit(EVENT_DATA_ERROR, &host->pending_events); 297657e10486SAddy Ke set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 297757e10486SAddy Ke tasklet_schedule(&host->tasklet); 297857e10486SAddy Ke break; 297957e10486SAddy Ke default: 298057e10486SAddy Ke break; 298157e10486SAddy Ke } 298257e10486SAddy Ke } 298357e10486SAddy Ke 2984c91eab4bSThomas Abraham #ifdef CONFIG_OF 2985c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2986c91eab4bSThomas Abraham { 2987c91eab4bSThomas Abraham struct dw_mci_board *pdata; 2988c91eab4bSThomas Abraham struct device *dev = host->dev; 2989e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 2990e8cc37b8SShawn Lin int ret; 29913c6d89eaSDoug Anderson u32 clock_frequency; 2992c91eab4bSThomas Abraham 2993c91eab4bSThomas Abraham pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2994bf3707eaSBeomho Seo if (!pdata) 2995c91eab4bSThomas Abraham return ERR_PTR(-ENOMEM); 2996c91eab4bSThomas Abraham 2997d6786fefSGuodong Xu /* find reset controller when exist */ 2998a93d6f31SPhilipp Zabel pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 2999d6786fefSGuodong Xu if (IS_ERR(pdata->rstc)) { 3000d6786fefSGuodong Xu if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3001d6786fefSGuodong Xu return ERR_PTR(-EPROBE_DEFER); 3002d6786fefSGuodong Xu } 3003d6786fefSGuodong Xu 3004c91eab4bSThomas Abraham /* find out number of slots supported */ 300516f5df8bSShawn Lin if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots)) 3006d30a8f7bSJaehoon Chung dev_info(dev, "'num-slots' was deprecated.\n"); 3007c91eab4bSThomas Abraham 3008852ff5feSDavid Woods if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 30090e3a22c0SShawn Lin dev_info(dev, 30100e3a22c0SShawn Lin "fifo-depth property not found, using value of FIFOTH register as default\n"); 3011c91eab4bSThomas Abraham 3012852ff5feSDavid Woods device_property_read_u32(dev, "card-detect-delay", 3013852ff5feSDavid Woods &pdata->detect_delay_ms); 3014c91eab4bSThomas Abraham 3015852ff5feSDavid Woods device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3016a0361c1aSJun Nie 3017852ff5feSDavid Woods if (device_property_present(dev, "fifo-watermark-aligned")) 3018d6fced83SJun Nie host->wm_aligned = true; 3019d6fced83SJun Nie 3020852ff5feSDavid Woods if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 30213c6d89eaSDoug Anderson pdata->bus_hz = clock_frequency; 30223c6d89eaSDoug Anderson 3023cb27a843SJames Hogan if (drv_data && drv_data->parse_dt) { 3024cb27a843SJames Hogan ret = drv_data->parse_dt(host); 3025800d78bfSThomas Abraham if (ret) 3026800d78bfSThomas Abraham return ERR_PTR(ret); 3027800d78bfSThomas Abraham } 3028800d78bfSThomas Abraham 3029c91eab4bSThomas Abraham return pdata; 3030c91eab4bSThomas Abraham } 3031c91eab4bSThomas Abraham 3032c91eab4bSThomas Abraham #else /* CONFIG_OF */ 3033c91eab4bSThomas Abraham static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3034c91eab4bSThomas Abraham { 3035c91eab4bSThomas Abraham return ERR_PTR(-EINVAL); 3036c91eab4bSThomas Abraham } 3037c91eab4bSThomas Abraham #endif /* CONFIG_OF */ 3038c91eab4bSThomas Abraham 3039fa0c3283SDoug Anderson static void dw_mci_enable_cd(struct dw_mci *host) 3040fa0c3283SDoug Anderson { 3041fa0c3283SDoug Anderson unsigned long irqflags; 3042fa0c3283SDoug Anderson u32 temp; 3043fa0c3283SDoug Anderson 3044e8cc37b8SShawn Lin /* 3045e8cc37b8SShawn Lin * No need for CD if all slots have a non-error GPIO 3046e8cc37b8SShawn Lin * as well as broken card detection is found. 3047e8cc37b8SShawn Lin */ 3048e47c0b96SJaehoon Chung if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3049e8cc37b8SShawn Lin return; 3050fa0c3283SDoug Anderson 3051e47c0b96SJaehoon Chung if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3052fa0c3283SDoug Anderson spin_lock_irqsave(&host->irq_lock, irqflags); 3053fa0c3283SDoug Anderson temp = mci_readl(host, INTMASK); 3054fa0c3283SDoug Anderson temp |= SDMMC_INT_CD; 3055fa0c3283SDoug Anderson mci_writel(host, INTMASK, temp); 3056fa0c3283SDoug Anderson spin_unlock_irqrestore(&host->irq_lock, irqflags); 3057fa0c3283SDoug Anderson } 305858870241SJaehoon Chung } 3059fa0c3283SDoug Anderson 306062ca8034SShashidhar Hiremath int dw_mci_probe(struct dw_mci *host) 3061f95f3850SWill Newton { 3062e95baf13SArnd Bergmann const struct dw_mci_drv_data *drv_data = host->drv_data; 306362ca8034SShashidhar Hiremath int width, i, ret = 0; 3064f95f3850SWill Newton u32 fifo_size; 3065f95f3850SWill Newton 3066c91eab4bSThomas Abraham if (!host->pdata) { 3067c91eab4bSThomas Abraham host->pdata = dw_mci_parse_dt(host); 3068d6786fefSGuodong Xu if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3069d6786fefSGuodong Xu return -EPROBE_DEFER; 3070d6786fefSGuodong Xu } else if (IS_ERR(host->pdata)) { 3071c91eab4bSThomas Abraham dev_err(host->dev, "platform data not available\n"); 3072c91eab4bSThomas Abraham return -EINVAL; 3073c91eab4bSThomas Abraham } 3074f95f3850SWill Newton } 3075f95f3850SWill Newton 3076780f22afSSeungwon Jeon host->biu_clk = devm_clk_get(host->dev, "biu"); 3077f90a0612SThomas Abraham if (IS_ERR(host->biu_clk)) { 3078f90a0612SThomas Abraham dev_dbg(host->dev, "biu clock not available\n"); 3079f90a0612SThomas Abraham } else { 3080f90a0612SThomas Abraham ret = clk_prepare_enable(host->biu_clk); 3081f90a0612SThomas Abraham if (ret) { 3082f90a0612SThomas Abraham dev_err(host->dev, "failed to enable biu clock\n"); 3083f90a0612SThomas Abraham return ret; 3084f90a0612SThomas Abraham } 3085f95f3850SWill Newton } 3086f95f3850SWill Newton 3087780f22afSSeungwon Jeon host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3088f90a0612SThomas Abraham if (IS_ERR(host->ciu_clk)) { 3089f90a0612SThomas Abraham dev_dbg(host->dev, "ciu clock not available\n"); 30903c6d89eaSDoug Anderson host->bus_hz = host->pdata->bus_hz; 3091f90a0612SThomas Abraham } else { 3092f90a0612SThomas Abraham ret = clk_prepare_enable(host->ciu_clk); 3093f90a0612SThomas Abraham if (ret) { 3094f90a0612SThomas Abraham dev_err(host->dev, "failed to enable ciu clock\n"); 3095f90a0612SThomas Abraham goto err_clk_biu; 3096f90a0612SThomas Abraham } 3097f90a0612SThomas Abraham 30983c6d89eaSDoug Anderson if (host->pdata->bus_hz) { 30993c6d89eaSDoug Anderson ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 31003c6d89eaSDoug Anderson if (ret) 31013c6d89eaSDoug Anderson dev_warn(host->dev, 3102612de4c1SJaehoon Chung "Unable to set bus rate to %uHz\n", 31033c6d89eaSDoug Anderson host->pdata->bus_hz); 31043c6d89eaSDoug Anderson } 3105f90a0612SThomas Abraham host->bus_hz = clk_get_rate(host->ciu_clk); 31063c6d89eaSDoug Anderson } 3107f90a0612SThomas Abraham 3108612de4c1SJaehoon Chung if (!host->bus_hz) { 3109612de4c1SJaehoon Chung dev_err(host->dev, 3110612de4c1SJaehoon Chung "Platform data must supply bus speed\n"); 3111612de4c1SJaehoon Chung ret = -ENODEV; 3112612de4c1SJaehoon Chung goto err_clk_ciu; 3113612de4c1SJaehoon Chung } 3114612de4c1SJaehoon Chung 3115941e372dSliwei if (!IS_ERR(host->pdata->rstc)) { 3116941e372dSliwei reset_control_assert(host->pdata->rstc); 3117941e372dSliwei usleep_range(10, 50); 3118941e372dSliwei reset_control_deassert(host->pdata->rstc); 3119941e372dSliwei } 3120941e372dSliwei 3121002f0d5cSYuvaraj Kumar C D if (drv_data && drv_data->init) { 3122002f0d5cSYuvaraj Kumar C D ret = drv_data->init(host); 3123002f0d5cSYuvaraj Kumar C D if (ret) { 3124002f0d5cSYuvaraj Kumar C D dev_err(host->dev, 3125002f0d5cSYuvaraj Kumar C D "implementation specific init failed\n"); 3126002f0d5cSYuvaraj Kumar C D goto err_clk_ciu; 3127002f0d5cSYuvaraj Kumar C D } 3128002f0d5cSYuvaraj Kumar C D } 3129002f0d5cSYuvaraj Kumar C D 31305c935165SDoug Anderson setup_timer(&host->cmd11_timer, 31315c935165SDoug Anderson dw_mci_cmd11_timer, (unsigned long)host); 31325c935165SDoug Anderson 3133*03de1921SAddy Ke setup_timer(&host->cto_timer, 3134*03de1921SAddy Ke dw_mci_cto_timer, (unsigned long)host); 3135*03de1921SAddy Ke 313657e10486SAddy Ke setup_timer(&host->dto_timer, 313757e10486SAddy Ke dw_mci_dto_timer, (unsigned long)host); 313857e10486SAddy Ke 3139f95f3850SWill Newton spin_lock_init(&host->lock); 3140f8c58c11SDoug Anderson spin_lock_init(&host->irq_lock); 3141f95f3850SWill Newton INIT_LIST_HEAD(&host->queue); 3142f95f3850SWill Newton 3143f95f3850SWill Newton /* 3144f95f3850SWill Newton * Get the host data width - this assumes that HCON has been set with 3145f95f3850SWill Newton * the correct values. 3146f95f3850SWill Newton */ 314770692752SShawn Lin i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3148f95f3850SWill Newton if (!i) { 3149f95f3850SWill Newton host->push_data = dw_mci_push_data16; 3150f95f3850SWill Newton host->pull_data = dw_mci_pull_data16; 3151f95f3850SWill Newton width = 16; 3152f95f3850SWill Newton host->data_shift = 1; 3153f95f3850SWill Newton } else if (i == 2) { 3154f95f3850SWill Newton host->push_data = dw_mci_push_data64; 3155f95f3850SWill Newton host->pull_data = dw_mci_pull_data64; 3156f95f3850SWill Newton width = 64; 3157f95f3850SWill Newton host->data_shift = 3; 3158f95f3850SWill Newton } else { 3159f95f3850SWill Newton /* Check for a reserved value, and warn if it is */ 3160f95f3850SWill Newton WARN((i != 1), 3161f95f3850SWill Newton "HCON reports a reserved host data width!\n" 3162f95f3850SWill Newton "Defaulting to 32-bit access.\n"); 3163f95f3850SWill Newton host->push_data = dw_mci_push_data32; 3164f95f3850SWill Newton host->pull_data = dw_mci_pull_data32; 3165f95f3850SWill Newton width = 32; 3166f95f3850SWill Newton host->data_shift = 2; 3167f95f3850SWill Newton } 3168f95f3850SWill Newton 3169f95f3850SWill Newton /* Reset all blocks */ 31703744415cSShawn Lin if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 31713744415cSShawn Lin ret = -ENODEV; 31723744415cSShawn Lin goto err_clk_ciu; 31733744415cSShawn Lin } 3174141a712aSSeungwon Jeon 3175141a712aSSeungwon Jeon host->dma_ops = host->pdata->dma_ops; 3176141a712aSSeungwon Jeon dw_mci_init_dma(host); 3177f95f3850SWill Newton 3178f95f3850SWill Newton /* Clear the interrupts for the host controller */ 3179f95f3850SWill Newton mci_writel(host, RINTSTS, 0xFFFFFFFF); 3180f95f3850SWill Newton mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3181f95f3850SWill Newton 3182f95f3850SWill Newton /* Put in max timeout */ 3183f95f3850SWill Newton mci_writel(host, TMOUT, 0xFFFFFFFF); 3184f95f3850SWill Newton 3185f95f3850SWill Newton /* 3186f95f3850SWill Newton * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3187f95f3850SWill Newton * Tx Mark = fifo_size / 2 DMA Size = 8 3188f95f3850SWill Newton */ 3189b86d8253SJames Hogan if (!host->pdata->fifo_depth) { 3190b86d8253SJames Hogan /* 3191b86d8253SJames Hogan * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3192b86d8253SJames Hogan * have been overwritten by the bootloader, just like we're 3193b86d8253SJames Hogan * about to do, so if you know the value for your hardware, you 3194b86d8253SJames Hogan * should put it in the platform data. 3195b86d8253SJames Hogan */ 3196f95f3850SWill Newton fifo_size = mci_readl(host, FIFOTH); 31978234e869SJaehoon Chung fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3198b86d8253SJames Hogan } else { 3199b86d8253SJames Hogan fifo_size = host->pdata->fifo_depth; 3200b86d8253SJames Hogan } 3201b86d8253SJames Hogan host->fifo_depth = fifo_size; 320252426899SSeungwon Jeon host->fifoth_val = 320352426899SSeungwon Jeon SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3204e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 3205f95f3850SWill Newton 3206f95f3850SWill Newton /* disable clock to CIU */ 3207f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3208f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3209f95f3850SWill Newton 321063008768SJames Hogan /* 321163008768SJames Hogan * In 2.40a spec, Data offset is changed. 321263008768SJames Hogan * Need to check the version-id and set data-offset for DATA register. 321363008768SJames Hogan */ 321463008768SJames Hogan host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 321563008768SJames Hogan dev_info(host->dev, "Version ID is %04x\n", host->verid); 321663008768SJames Hogan 3217a0361c1aSJun Nie if (host->data_addr_override) 3218a0361c1aSJun Nie host->fifo_reg = host->regs + host->data_addr_override; 3219a0361c1aSJun Nie else if (host->verid < DW_MMC_240A) 322076184ac1SBen Dooks host->fifo_reg = host->regs + DATA_OFFSET; 322163008768SJames Hogan else 322276184ac1SBen Dooks host->fifo_reg = host->regs + DATA_240A_OFFSET; 322363008768SJames Hogan 3224f95f3850SWill Newton tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3225780f22afSSeungwon Jeon ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3226780f22afSSeungwon Jeon host->irq_flags, "dw-mci", host); 3227f95f3850SWill Newton if (ret) 32286130e7a9SDoug Anderson goto err_dmaunmap; 3229f95f3850SWill Newton 3230d30a8f7bSJaehoon Chung /* 3231fa0c3283SDoug Anderson * Enable interrupts for command done, data over, data empty, 32322da1d7f2SYuvaraj CD * receive ready and error such as transmit, receive timeout, crc error 32332da1d7f2SYuvaraj CD */ 32342da1d7f2SYuvaraj CD mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 32352da1d7f2SYuvaraj CD SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3236fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 32370e3a22c0SShawn Lin /* Enable mci interrupt */ 32380e3a22c0SShawn Lin mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 32392da1d7f2SYuvaraj CD 32400e3a22c0SShawn Lin dev_info(host->dev, 32410e3a22c0SShawn Lin "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 32422da1d7f2SYuvaraj CD host->irq, width, fifo_size); 32432da1d7f2SYuvaraj CD 3244f95f3850SWill Newton /* We need at least one slot to succeed */ 3245e4a65ef7SJaehoon Chung ret = dw_mci_init_slot(host); 324658870241SJaehoon Chung if (ret) { 32471c2215b7SThomas Abraham dev_dbg(host->dev, "slot %d init failed\n", i); 32486130e7a9SDoug Anderson goto err_dmaunmap; 3249f95f3850SWill Newton } 3250f95f3850SWill Newton 3251b793f658SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3252b793f658SDoug Anderson dw_mci_enable_cd(host); 3253b793f658SDoug Anderson 3254f95f3850SWill Newton return 0; 3255f95f3850SWill Newton 3256f95f3850SWill Newton err_dmaunmap: 3257f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3258f95f3850SWill Newton host->dma_ops->exit(host); 3259f90a0612SThomas Abraham 3260d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3261d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3262d6786fefSGuodong Xu 3263f90a0612SThomas Abraham err_clk_ciu: 3264f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3265780f22afSSeungwon Jeon 3266f90a0612SThomas Abraham err_clk_biu: 3267f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3268780f22afSSeungwon Jeon 3269f95f3850SWill Newton return ret; 3270f95f3850SWill Newton } 327162ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_probe); 3272f95f3850SWill Newton 327362ca8034SShashidhar Hiremath void dw_mci_remove(struct dw_mci *host) 3274f95f3850SWill Newton { 3275e4a65ef7SJaehoon Chung dev_dbg(host->dev, "remove slot\n"); 3276b23475faSJaehoon Chung if (host->slot) 3277e4a65ef7SJaehoon Chung dw_mci_cleanup_slot(host->slot); 3278f95f3850SWill Newton 3279048fd7e6SPrabu Thangamuthu mci_writel(host, RINTSTS, 0xFFFFFFFF); 3280048fd7e6SPrabu Thangamuthu mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3281048fd7e6SPrabu Thangamuthu 3282f95f3850SWill Newton /* disable clock to CIU */ 3283f95f3850SWill Newton mci_writel(host, CLKENA, 0); 3284f95f3850SWill Newton mci_writel(host, CLKSRC, 0); 3285f95f3850SWill Newton 3286f95f3850SWill Newton if (host->use_dma && host->dma_ops->exit) 3287f95f3850SWill Newton host->dma_ops->exit(host); 3288f95f3850SWill Newton 3289d6786fefSGuodong Xu if (!IS_ERR(host->pdata->rstc)) 3290d6786fefSGuodong Xu reset_control_assert(host->pdata->rstc); 3291d6786fefSGuodong Xu 3292f90a0612SThomas Abraham clk_disable_unprepare(host->ciu_clk); 3293f90a0612SThomas Abraham clk_disable_unprepare(host->biu_clk); 3294f95f3850SWill Newton } 329562ca8034SShashidhar Hiremath EXPORT_SYMBOL(dw_mci_remove); 329662ca8034SShashidhar Hiremath 329762ca8034SShashidhar Hiremath 3298f95f3850SWill Newton 3299e9ed8835SShawn Lin #ifdef CONFIG_PM 3300ed24e1ffSShawn Lin int dw_mci_runtime_suspend(struct device *dev) 3301f95f3850SWill Newton { 3302ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3303ed24e1ffSShawn Lin 33043fc7eaefSShawn Lin if (host->use_dma && host->dma_ops->exit) 33053fc7eaefSShawn Lin host->dma_ops->exit(host); 33063fc7eaefSShawn Lin 3307ed24e1ffSShawn Lin clk_disable_unprepare(host->ciu_clk); 3308ed24e1ffSShawn Lin 330942f989c0SJaehoon Chung if (host->slot && 331042f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 331142f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) 3312ed24e1ffSShawn Lin clk_disable_unprepare(host->biu_clk); 3313ed24e1ffSShawn Lin 3314f95f3850SWill Newton return 0; 3315f95f3850SWill Newton } 3316ed24e1ffSShawn Lin EXPORT_SYMBOL(dw_mci_runtime_suspend); 3317f95f3850SWill Newton 3318ed24e1ffSShawn Lin int dw_mci_runtime_resume(struct device *dev) 3319f95f3850SWill Newton { 3320b23475faSJaehoon Chung int ret = 0; 3321ed24e1ffSShawn Lin struct dw_mci *host = dev_get_drvdata(dev); 3322f95f3850SWill Newton 332342f989c0SJaehoon Chung if (host->slot && 332442f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 332542f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) { 3326ed24e1ffSShawn Lin ret = clk_prepare_enable(host->biu_clk); 3327ed24e1ffSShawn Lin if (ret) 3328e61cf118SJaehoon Chung return ret; 3329e61cf118SJaehoon Chung } 3330e61cf118SJaehoon Chung 3331ed24e1ffSShawn Lin ret = clk_prepare_enable(host->ciu_clk); 3332ed24e1ffSShawn Lin if (ret) 3333df9bcc2bSJoonyoung Shim goto err; 3334df9bcc2bSJoonyoung Shim 3335df9bcc2bSJoonyoung Shim if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3336df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->ciu_clk); 3337df9bcc2bSJoonyoung Shim ret = -ENODEV; 3338df9bcc2bSJoonyoung Shim goto err; 3339df9bcc2bSJoonyoung Shim } 3340ed24e1ffSShawn Lin 33413bfe619dSJonathan Kliegman if (host->use_dma && host->dma_ops->init) 3342141a712aSSeungwon Jeon host->dma_ops->init(host); 3343141a712aSSeungwon Jeon 334452426899SSeungwon Jeon /* 334552426899SSeungwon Jeon * Restore the initial value at FIFOTH register 334652426899SSeungwon Jeon * And Invalidate the prev_blksz with zero 334752426899SSeungwon Jeon */ 3348e61cf118SJaehoon Chung mci_writel(host, FIFOTH, host->fifoth_val); 334952426899SSeungwon Jeon host->prev_blksz = 0; 3350e61cf118SJaehoon Chung 33512eb2944fSDoug Anderson /* Put in max timeout */ 33522eb2944fSDoug Anderson mci_writel(host, TMOUT, 0xFFFFFFFF); 33532eb2944fSDoug Anderson 3354e61cf118SJaehoon Chung mci_writel(host, RINTSTS, 0xFFFFFFFF); 3355e61cf118SJaehoon Chung mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3356e61cf118SJaehoon Chung SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3357fa0c3283SDoug Anderson DW_MCI_ERROR_FLAGS); 3358e61cf118SJaehoon Chung mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3359e61cf118SJaehoon Chung 33600e3a22c0SShawn Lin 3361e47c0b96SJaehoon Chung if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3362e47c0b96SJaehoon Chung dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3363e9748e03SZiyuan Xu 3364e9748e03SZiyuan Xu /* Force setup bus to guarantee available clock output */ 3365e47c0b96SJaehoon Chung dw_mci_setup_bus(host->slot, true); 3366fa0c3283SDoug Anderson 3367fa0c3283SDoug Anderson /* Now that slots are all setup, we can enable card detect */ 3368fa0c3283SDoug Anderson dw_mci_enable_cd(host); 3369fa0c3283SDoug Anderson 3370df9bcc2bSJoonyoung Shim return 0; 3371df9bcc2bSJoonyoung Shim 3372df9bcc2bSJoonyoung Shim err: 337342f989c0SJaehoon Chung if (host->slot && 337442f989c0SJaehoon Chung (mmc_can_gpio_cd(host->slot->mmc) || 337542f989c0SJaehoon Chung !mmc_card_is_removable(host->slot->mmc))) 3376df9bcc2bSJoonyoung Shim clk_disable_unprepare(host->biu_clk); 3377df9bcc2bSJoonyoung Shim 33781f5c51d7SShawn Lin return ret; 33791f5c51d7SShawn Lin } 3380e9ed8835SShawn Lin EXPORT_SYMBOL(dw_mci_runtime_resume); 3381e9ed8835SShawn Lin #endif /* CONFIG_PM */ 33826fe8890dSJaehoon Chung 3383f95f3850SWill Newton static int __init dw_mci_init(void) 3384f95f3850SWill Newton { 33858e1c4e4dSSachin Kamat pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 338662ca8034SShashidhar Hiremath return 0; 3387f95f3850SWill Newton } 3388f95f3850SWill Newton 3389f95f3850SWill Newton static void __exit dw_mci_exit(void) 3390f95f3850SWill Newton { 3391f95f3850SWill Newton } 3392f95f3850SWill Newton 3393f95f3850SWill Newton module_init(dw_mci_init); 3394f95f3850SWill Newton module_exit(dw_mci_exit); 3395f95f3850SWill Newton 3396f95f3850SWill Newton MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3397f95f3850SWill Newton MODULE_AUTHOR("NXP Semiconductor VietNam"); 3398f95f3850SWill Newton MODULE_AUTHOR("Imagination Technologies Ltd"); 3399f95f3850SWill Newton MODULE_LICENSE("GPL v2"); 3400