1 /* 2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/clk.h> 13 #include <linux/mmc/host.h> 14 #include <linux/of_address.h> 15 #include <linux/mmc/slot-gpio.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/slab.h> 18 19 #include "dw_mmc.h" 20 #include "dw_mmc-pltfm.h" 21 22 #define RK3288_CLKGEN_DIV 2 23 24 struct dw_mci_rockchip_priv_data { 25 struct clk *drv_clk; 26 struct clk *sample_clk; 27 int default_sample_phase; 28 int num_phases; 29 }; 30 31 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) 32 { 33 struct dw_mci_rockchip_priv_data *priv = host->priv; 34 int ret; 35 unsigned int cclkin; 36 u32 bus_hz; 37 38 if (ios->clock == 0) 39 return; 40 41 /* 42 * cclkin: source clock of mmc controller 43 * bus_hz: card interface clock generated by CLKGEN 44 * bus_hz = cclkin / RK3288_CLKGEN_DIV 45 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) 46 * 47 * Note: div can only be 0 or 1, but div must be set to 1 for eMMC 48 * DDR52 8-bit mode. 49 */ 50 if (ios->bus_width == MMC_BUS_WIDTH_8 && 51 ios->timing == MMC_TIMING_MMC_DDR52) 52 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; 53 else 54 cclkin = ios->clock * RK3288_CLKGEN_DIV; 55 56 ret = clk_set_rate(host->ciu_clk, cclkin); 57 if (ret) 58 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); 59 60 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; 61 if (bus_hz != host->bus_hz) { 62 host->bus_hz = bus_hz; 63 /* force dw_mci_setup_bus() */ 64 host->current_speed = 0; 65 } 66 67 /* Make sure we use phases which we can enumerate with */ 68 if (!IS_ERR(priv->sample_clk)) 69 clk_set_phase(priv->sample_clk, priv->default_sample_phase); 70 71 /* 72 * Set the drive phase offset based on speed mode to achieve hold times. 73 * 74 * NOTE: this is _not_ a value that is dynamically tuned and is also 75 * _not_ a value that will vary from board to board. It is a value 76 * that could vary between different SoC models if they had massively 77 * different output clock delays inside their dw_mmc IP block (delay_o), 78 * but since it's OK to overshoot a little we don't need to do complex 79 * calculations and can pick values that will just work for everyone. 80 * 81 * When picking values we'll stick with picking 0/90/180/270 since 82 * those can be made very accurately on all known Rockchip SoCs. 83 * 84 * Note that these values match values from the DesignWare Databook 85 * tables for the most part except for SDR12 and "ID mode". For those 86 * two modes the databook calculations assume a clock in of 50MHz. As 87 * seen above, we always use a clock in rate that is exactly the 88 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided 89 * back out before the controller sees it). 90 * 91 * From measurement of a single device, it appears that delay_o is 92 * about .5 ns. Since we try to leave a bit of margin, it's expected 93 * that numbers here will be fine even with much larger delay_o 94 * (the 1.4 ns assumed by the DesignWare Databook would result in the 95 * same results, for instance). 96 */ 97 if (!IS_ERR(priv->drv_clk)) { 98 int phase; 99 100 /* 101 * In almost all cases a 90 degree phase offset will provide 102 * sufficient hold times across all valid input clock rates 103 * assuming delay_o is not absurd for a given SoC. We'll use 104 * that as a default. 105 */ 106 phase = 90; 107 108 switch (ios->timing) { 109 case MMC_TIMING_MMC_DDR52: 110 /* 111 * Since clock in rate with MMC_DDR52 is doubled when 112 * bus width is 8 we need to double the phase offset 113 * to get the same timings. 114 */ 115 if (ios->bus_width == MMC_BUS_WIDTH_8) 116 phase = 180; 117 break; 118 case MMC_TIMING_UHS_SDR104: 119 case MMC_TIMING_MMC_HS200: 120 /* 121 * In the case of 150 MHz clock (typical max for 122 * Rockchip SoCs), 90 degree offset will add a delay 123 * of 1.67 ns. That will meet min hold time of .8 ns 124 * as long as clock output delay is < .87 ns. On 125 * SoCs measured this seems to be OK, but it doesn't 126 * hurt to give margin here, so we use 180. 127 */ 128 phase = 180; 129 break; 130 } 131 132 clk_set_phase(priv->drv_clk, phase); 133 } 134 } 135 136 #define TUNING_ITERATION_TO_PHASE(i, num_phases) \ 137 (DIV_ROUND_UP((i) * 360, num_phases)) 138 139 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) 140 { 141 struct dw_mci *host = slot->host; 142 struct dw_mci_rockchip_priv_data *priv = host->priv; 143 struct mmc_host *mmc = slot->mmc; 144 int ret = 0; 145 int i; 146 bool v, prev_v = 0, first_v; 147 struct range_t { 148 int start; 149 int end; /* inclusive */ 150 }; 151 struct range_t *ranges; 152 unsigned int range_count = 0; 153 int longest_range_len = -1; 154 int longest_range = -1; 155 int middle_phase; 156 157 if (IS_ERR(priv->sample_clk)) { 158 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); 159 return -EIO; 160 } 161 162 ranges = kmalloc_array(priv->num_phases / 2 + 1, 163 sizeof(*ranges), GFP_KERNEL); 164 if (!ranges) 165 return -ENOMEM; 166 167 /* Try each phase and extract good ranges */ 168 for (i = 0; i < priv->num_phases; ) { 169 clk_set_phase(priv->sample_clk, 170 TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); 171 172 v = !mmc_send_tuning(mmc, opcode, NULL); 173 174 if (i == 0) 175 first_v = v; 176 177 if ((!prev_v) && v) { 178 range_count++; 179 ranges[range_count-1].start = i; 180 } 181 if (v) { 182 ranges[range_count-1].end = i; 183 i++; 184 } else if (i == priv->num_phases - 1) { 185 /* No extra skipping rules if we're at the end */ 186 i++; 187 } else { 188 /* 189 * No need to check too close to an invalid 190 * one since testing bad phases is slow. Skip 191 * 20 degrees. 192 */ 193 i += DIV_ROUND_UP(20 * priv->num_phases, 360); 194 195 /* Always test the last one */ 196 if (i >= priv->num_phases) 197 i = priv->num_phases - 1; 198 } 199 200 prev_v = v; 201 } 202 203 if (range_count == 0) { 204 dev_warn(host->dev, "All phases bad!"); 205 ret = -EIO; 206 goto free; 207 } 208 209 /* wrap around case, merge the end points */ 210 if ((range_count > 1) && first_v && v) { 211 ranges[0].start = ranges[range_count-1].start; 212 range_count--; 213 } 214 215 if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { 216 clk_set_phase(priv->sample_clk, priv->default_sample_phase); 217 dev_info(host->dev, "All phases work, using default phase %d.", 218 priv->default_sample_phase); 219 goto free; 220 } 221 222 /* Find the longest range */ 223 for (i = 0; i < range_count; i++) { 224 int len = (ranges[i].end - ranges[i].start + 1); 225 226 if (len < 0) 227 len += priv->num_phases; 228 229 if (longest_range_len < len) { 230 longest_range_len = len; 231 longest_range = i; 232 } 233 234 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n", 235 TUNING_ITERATION_TO_PHASE(ranges[i].start, 236 priv->num_phases), 237 TUNING_ITERATION_TO_PHASE(ranges[i].end, 238 priv->num_phases), 239 len 240 ); 241 } 242 243 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n", 244 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start, 245 priv->num_phases), 246 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end, 247 priv->num_phases), 248 longest_range_len 249 ); 250 251 middle_phase = ranges[longest_range].start + longest_range_len / 2; 252 middle_phase %= priv->num_phases; 253 dev_info(host->dev, "Successfully tuned phase to %d\n", 254 TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases)); 255 256 clk_set_phase(priv->sample_clk, 257 TUNING_ITERATION_TO_PHASE(middle_phase, 258 priv->num_phases)); 259 260 free: 261 kfree(ranges); 262 return ret; 263 } 264 265 static int dw_mci_rk3288_parse_dt(struct dw_mci *host) 266 { 267 struct device_node *np = host->dev->of_node; 268 struct dw_mci_rockchip_priv_data *priv; 269 270 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 271 if (!priv) 272 return -ENOMEM; 273 274 if (of_property_read_u32(np, "rockchip,desired-num-phases", 275 &priv->num_phases)) 276 priv->num_phases = 360; 277 278 if (of_property_read_u32(np, "rockchip,default-sample-phase", 279 &priv->default_sample_phase)) 280 priv->default_sample_phase = 0; 281 282 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); 283 if (IS_ERR(priv->drv_clk)) 284 dev_dbg(host->dev, "ciu-drive not available\n"); 285 286 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); 287 if (IS_ERR(priv->sample_clk)) 288 dev_dbg(host->dev, "ciu-sample not available\n"); 289 290 host->priv = priv; 291 292 return 0; 293 } 294 295 static int dw_mci_rockchip_init(struct dw_mci *host) 296 { 297 /* It is slot 8 on Rockchip SoCs */ 298 host->sdio_id0 = 8; 299 300 if (of_device_is_compatible(host->dev->of_node, 301 "rockchip,rk3288-dw-mshc")) 302 host->bus_hz /= RK3288_CLKGEN_DIV; 303 304 return 0; 305 } 306 307 /* Common capabilities of RK3288 SoC */ 308 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = { 309 MMC_CAP_CMD23, 310 MMC_CAP_CMD23, 311 MMC_CAP_CMD23, 312 MMC_CAP_CMD23, 313 }; 314 315 static const struct dw_mci_drv_data rk2928_drv_data = { 316 .init = dw_mci_rockchip_init, 317 }; 318 319 static const struct dw_mci_drv_data rk3288_drv_data = { 320 .caps = dw_mci_rk3288_dwmmc_caps, 321 .num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps), 322 .set_ios = dw_mci_rk3288_set_ios, 323 .execute_tuning = dw_mci_rk3288_execute_tuning, 324 .parse_dt = dw_mci_rk3288_parse_dt, 325 .init = dw_mci_rockchip_init, 326 }; 327 328 static const struct of_device_id dw_mci_rockchip_match[] = { 329 { .compatible = "rockchip,rk2928-dw-mshc", 330 .data = &rk2928_drv_data }, 331 { .compatible = "rockchip,rk3288-dw-mshc", 332 .data = &rk3288_drv_data }, 333 {}, 334 }; 335 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); 336 337 static int dw_mci_rockchip_probe(struct platform_device *pdev) 338 { 339 const struct dw_mci_drv_data *drv_data; 340 const struct of_device_id *match; 341 int ret; 342 343 if (!pdev->dev.of_node) 344 return -ENODEV; 345 346 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); 347 drv_data = match->data; 348 349 pm_runtime_get_noresume(&pdev->dev); 350 pm_runtime_set_active(&pdev->dev); 351 pm_runtime_enable(&pdev->dev); 352 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 353 pm_runtime_use_autosuspend(&pdev->dev); 354 355 ret = dw_mci_pltfm_register(pdev, drv_data); 356 if (ret) { 357 pm_runtime_disable(&pdev->dev); 358 pm_runtime_set_suspended(&pdev->dev); 359 pm_runtime_put_noidle(&pdev->dev); 360 return ret; 361 } 362 363 pm_runtime_put_autosuspend(&pdev->dev); 364 365 return 0; 366 } 367 368 static int dw_mci_rockchip_remove(struct platform_device *pdev) 369 { 370 pm_runtime_get_sync(&pdev->dev); 371 pm_runtime_disable(&pdev->dev); 372 pm_runtime_put_noidle(&pdev->dev); 373 374 return dw_mci_pltfm_remove(pdev); 375 } 376 377 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = { 378 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 379 pm_runtime_force_resume) 380 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend, 381 dw_mci_runtime_resume, 382 NULL) 383 }; 384 385 static struct platform_driver dw_mci_rockchip_pltfm_driver = { 386 .probe = dw_mci_rockchip_probe, 387 .remove = dw_mci_rockchip_remove, 388 .driver = { 389 .name = "dwmmc_rockchip", 390 .of_match_table = dw_mci_rockchip_match, 391 .pm = &dw_mci_rockchip_dev_pm_ops, 392 }, 393 }; 394 395 module_platform_driver(dw_mci_rockchip_pltfm_driver); 396 397 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 398 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension"); 399 MODULE_ALIAS("platform:dwmmc_rockchip"); 400 MODULE_LICENSE("GPL v2"); 401