1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2013 Linaro Ltd. 4 * Copyright (c) 2013 HiSilicon Limited. 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/mmc/host.h> 12 #include <linux/module.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 19 #include "dw_mmc.h" 20 #include "dw_mmc-pltfm.h" 21 22 /* 23 * hi6220 sd only support io voltage 1.8v and 3v 24 * Also need config AO_SCTRL_SEL18 accordingly 25 */ 26 #define AO_SCTRL_SEL18 BIT(10) 27 #define AO_SCTRL_CTRL3 0x40C 28 29 #define DWMMC_SDIO_ID 2 30 31 #define SOC_SCTRL_SCPERCTRL5 (0x314) 32 #define SDCARD_IO_SEL18 BIT(2) 33 34 #define SDCARD_RD_THRESHOLD (512) 35 36 #define GENCLK_DIV (7) 37 38 #define GPIO_CLK_ENABLE BIT(16) 39 #define GPIO_CLK_DIV_MASK GENMASK(11, 8) 40 #define GPIO_USE_SAMPLE_DLY_MASK GENMASK(13, 13) 41 #define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16) 42 #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK GENMASK(25, 21) 43 #define UHS_REG_EXT_SAMPLE_DLY_MASK GENMASK(30, 26) 44 45 #define TIMING_MODE 3 46 #define TIMING_CFG_NUM 10 47 48 #define NUM_PHASES (40) 49 50 #define ENABLE_SHIFT_MIN_SMPL (4) 51 #define ENABLE_SHIFT_MAX_SMPL (12) 52 #define USE_DLY_MIN_SMPL (11) 53 #define USE_DLY_MAX_SMPL (14) 54 55 struct k3_priv { 56 u32 cur_speed; 57 struct regmap *reg; 58 }; 59 60 static unsigned long dw_mci_hi6220_caps[] = { 61 MMC_CAP_CMD23, 62 MMC_CAP_CMD23, 63 0 64 }; 65 66 struct hs_timing { 67 u32 drv_phase; 68 u32 smpl_dly; 69 u32 smpl_phase_max; 70 u32 smpl_phase_min; 71 }; 72 73 static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = { 74 { /* reserved */ }, 75 { /* SD */ 76 {7, 0, 15, 15,}, /* 0: LEGACY 400k */ 77 {6, 0, 4, 4,}, /* 1: MMC_HS */ 78 {6, 0, 3, 3,}, /* 2: SD_HS */ 79 {6, 0, 15, 15,}, /* 3: SDR12 */ 80 {6, 0, 2, 2,}, /* 4: SDR25 */ 81 {4, 0, 11, 0,}, /* 5: SDR50 */ 82 {6, 4, 15, 0,}, /* 6: SDR104 */ 83 {0}, /* 7: DDR50 */ 84 {0}, /* 8: DDR52 */ 85 {0}, /* 9: HS200 */ 86 }, 87 { /* SDIO */ 88 {7, 0, 15, 15,}, /* 0: LEGACY 400k */ 89 {0}, /* 1: MMC_HS */ 90 {6, 0, 15, 15,}, /* 2: SD_HS */ 91 {6, 0, 15, 15,}, /* 3: SDR12 */ 92 {6, 0, 0, 0,}, /* 4: SDR25 */ 93 {4, 0, 12, 0,}, /* 5: SDR50 */ 94 {5, 4, 15, 0,}, /* 6: SDR104 */ 95 {0}, /* 7: DDR50 */ 96 {0}, /* 8: DDR52 */ 97 {0}, /* 9: HS200 */ 98 } 99 }; 100 101 static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios) 102 { 103 int ret; 104 105 ret = clk_set_rate(host->ciu_clk, ios->clock); 106 if (ret) 107 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); 108 109 host->bus_hz = clk_get_rate(host->ciu_clk); 110 } 111 112 static const struct dw_mci_drv_data k3_drv_data = { 113 .set_ios = dw_mci_k3_set_ios, 114 }; 115 116 static int dw_mci_hi6220_parse_dt(struct dw_mci *host) 117 { 118 struct k3_priv *priv; 119 120 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 121 if (!priv) 122 return -ENOMEM; 123 124 priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node, 125 "hisilicon,peripheral-syscon"); 126 if (IS_ERR(priv->reg)) 127 priv->reg = NULL; 128 129 host->priv = priv; 130 return 0; 131 } 132 133 static int dw_mci_hi6220_switch_voltage(struct dw_mci *host, struct mmc_ios *ios) 134 { 135 struct k3_priv *priv; 136 struct mmc_host *mmc = host->mmc; 137 int min_uv, max_uv; 138 int ret; 139 140 priv = host->priv; 141 142 if (!priv || !priv->reg) 143 return 0; 144 145 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 146 ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, 147 AO_SCTRL_SEL18, 0); 148 min_uv = 3000000; 149 max_uv = 3000000; 150 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 151 ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, 152 AO_SCTRL_SEL18, AO_SCTRL_SEL18); 153 min_uv = 1800000; 154 max_uv = 1800000; 155 } else { 156 dev_dbg(host->dev, "voltage not supported\n"); 157 return -EINVAL; 158 } 159 160 if (ret) { 161 dev_dbg(host->dev, "switch voltage failed\n"); 162 return ret; 163 } 164 165 if (IS_ERR_OR_NULL(mmc->supply.vqmmc)) 166 return 0; 167 168 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 169 if (ret) { 170 dev_dbg(host->dev, "Regulator set error %d: %d - %d\n", 171 ret, min_uv, max_uv); 172 return ret; 173 } 174 175 return 0; 176 } 177 178 static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios) 179 { 180 int ret; 181 unsigned int clock; 182 183 clock = (ios->clock <= 25000000) ? 25000000 : ios->clock; 184 185 ret = clk_set_rate(host->biu_clk, clock); 186 if (ret) 187 dev_warn(host->dev, "failed to set rate %uHz\n", clock); 188 189 host->bus_hz = clk_get_rate(host->biu_clk); 190 } 191 192 static int dw_mci_hi6220_execute_tuning(struct dw_mci *host, u32 opcode) 193 { 194 return 0; 195 } 196 197 static const struct dw_mci_drv_data hi6220_data = { 198 .caps = dw_mci_hi6220_caps, 199 .num_caps = ARRAY_SIZE(dw_mci_hi6220_caps), 200 .switch_voltage = dw_mci_hi6220_switch_voltage, 201 .set_ios = dw_mci_hi6220_set_ios, 202 .parse_dt = dw_mci_hi6220_parse_dt, 203 .execute_tuning = dw_mci_hi6220_execute_tuning, 204 }; 205 206 static int dw_mci_hs_set_timing(struct dw_mci *host, int timing, 207 int smpl_phase) 208 { 209 u32 drv_phase; 210 u32 smpl_dly; 211 u32 use_smpl_dly = 0; 212 u32 enable_shift = 0; 213 u32 reg_value; 214 int ctrl_id; 215 216 ctrl_id = host->mmc->index; 217 if (ctrl_id >= TIMING_MODE) 218 return -EINVAL; 219 220 drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase; 221 smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly; 222 if (smpl_phase == -1) 223 smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max + 224 hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2; 225 226 switch (timing) { 227 case MMC_TIMING_UHS_SDR104: 228 if (smpl_phase >= USE_DLY_MIN_SMPL && 229 smpl_phase <= USE_DLY_MAX_SMPL) 230 use_smpl_dly = 1; 231 fallthrough; 232 case MMC_TIMING_UHS_SDR50: 233 if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL && 234 smpl_phase <= ENABLE_SHIFT_MAX_SMPL) 235 enable_shift = 1; 236 break; 237 } 238 239 mci_writel(host, GPIO, 0x0); 240 usleep_range(5, 10); 241 242 reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) | 243 FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) | 244 FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase); 245 mci_writel(host, UHS_REG_EXT, reg_value); 246 247 mci_writel(host, ENABLE_SHIFT, enable_shift); 248 249 reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) | 250 FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly); 251 mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE); 252 253 /* We should delay 1ms wait for timing setting finished. */ 254 usleep_range(1000, 2000); 255 256 return 0; 257 } 258 259 static int dw_mci_hi3660_init(struct dw_mci *host) 260 { 261 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD, 262 SDMMC_CARD_RD_THR_EN)); 263 264 host->bus_hz /= (GENCLK_DIV + 1); 265 266 return dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1); 267 } 268 269 static int dw_mci_set_sel18(struct dw_mci *host, bool set) 270 { 271 int ret; 272 unsigned int val; 273 struct k3_priv *priv; 274 275 priv = host->priv; 276 277 val = set ? SDCARD_IO_SEL18 : 0; 278 ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5, 279 SDCARD_IO_SEL18, val); 280 if (ret) { 281 dev_err(host->dev, "sel18 %u error\n", val); 282 return ret; 283 } 284 285 return 0; 286 } 287 288 static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios) 289 { 290 int ret; 291 unsigned long wanted; 292 unsigned long actual; 293 struct k3_priv *priv = host->priv; 294 295 if (!ios->clock || ios->clock == priv->cur_speed) 296 return; 297 298 wanted = ios->clock * (GENCLK_DIV + 1); 299 ret = clk_set_rate(host->ciu_clk, wanted); 300 if (ret) { 301 dev_err(host->dev, "failed to set rate %luHz\n", wanted); 302 return; 303 } 304 actual = clk_get_rate(host->ciu_clk); 305 306 dw_mci_hs_set_timing(host, ios->timing, -1); 307 host->bus_hz = actual / (GENCLK_DIV + 1); 308 host->current_speed = 0; 309 priv->cur_speed = host->bus_hz; 310 } 311 312 static int dw_mci_get_best_clksmpl(unsigned int sample_flag) 313 { 314 int i; 315 int interval; 316 unsigned int v; 317 unsigned int len; 318 unsigned int range_start = 0; 319 unsigned int range_length = 0; 320 unsigned int middle_range = 0; 321 322 if (!sample_flag) 323 return -EIO; 324 325 if (~sample_flag == 0) 326 return 0; 327 328 i = ffs(sample_flag) - 1; 329 330 /* 331 * A clock cycle is divided into 32 phases, 332 * each of which is represented by a bit, 333 * finding the optimal phase. 334 */ 335 while (i < 32) { 336 v = ror32(sample_flag, i); 337 len = ffs(~v) - 1; 338 339 if (len > range_length) { 340 range_length = len; 341 range_start = i; 342 } 343 344 interval = ffs(v >> len) - 1; 345 if (interval < 0) 346 break; 347 348 i += len + interval; 349 } 350 351 middle_range = range_start + range_length / 2; 352 if (middle_range >= 32) 353 middle_range %= 32; 354 355 return middle_range; 356 } 357 358 static int dw_mci_hi3660_execute_tuning(struct dw_mci *host, u32 opcode) 359 { 360 int i = 0; 361 struct mmc_host *mmc = host->mmc; 362 int smpl_phase = 0; 363 u32 tuning_sample_flag = 0; 364 int best_clksmpl = 0; 365 366 for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) { 367 smpl_phase %= 32; 368 369 mci_writel(host, TMOUT, ~0); 370 dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase); 371 372 if (!mmc_send_tuning(mmc, opcode, NULL)) 373 tuning_sample_flag |= (1 << smpl_phase); 374 else 375 tuning_sample_flag &= ~(1 << smpl_phase); 376 } 377 378 best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag); 379 if (best_clksmpl < 0) { 380 dev_err(host->dev, "All phases bad!\n"); 381 return -EIO; 382 } 383 384 dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl); 385 386 dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n", 387 best_clksmpl, tuning_sample_flag); 388 return 0; 389 } 390 391 static int dw_mci_hi3660_switch_voltage(struct dw_mci *host, 392 struct mmc_ios *ios) 393 { 394 struct k3_priv *priv; 395 struct mmc_host *mmc = host->mmc; 396 int ret = 0; 397 398 priv = host->priv; 399 400 if (!priv || !priv->reg) 401 return 0; 402 403 if (mmc->index == DWMMC_SDIO_ID) 404 return 0; 405 406 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 407 ret = dw_mci_set_sel18(host, 0); 408 else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 409 ret = dw_mci_set_sel18(host, 1); 410 if (ret) 411 return ret; 412 413 if (!IS_ERR(mmc->supply.vqmmc)) { 414 ret = mmc_regulator_set_vqmmc(mmc, ios); 415 if (ret < 0) { 416 dev_err(host->dev, "Regulator set error %d\n", ret); 417 return ret; 418 } 419 } 420 421 return 0; 422 } 423 424 static const struct dw_mci_drv_data hi3660_data = { 425 .init = dw_mci_hi3660_init, 426 .set_ios = dw_mci_hi3660_set_ios, 427 .parse_dt = dw_mci_hi6220_parse_dt, 428 .execute_tuning = dw_mci_hi3660_execute_tuning, 429 .switch_voltage = dw_mci_hi3660_switch_voltage, 430 }; 431 432 static const struct of_device_id dw_mci_k3_match[] = { 433 { .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, }, 434 { .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, }, 435 { .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, }, 436 {}, 437 }; 438 MODULE_DEVICE_TABLE(of, dw_mci_k3_match); 439 440 static int dw_mci_k3_probe(struct platform_device *pdev) 441 { 442 const struct dw_mci_drv_data *drv_data; 443 const struct of_device_id *match; 444 445 match = of_match_node(dw_mci_k3_match, pdev->dev.of_node); 446 drv_data = match->data; 447 448 return dw_mci_pltfm_register(pdev, drv_data); 449 } 450 451 static struct platform_driver dw_mci_k3_pltfm_driver = { 452 .probe = dw_mci_k3_probe, 453 .remove = dw_mci_pltfm_remove, 454 .driver = { 455 .name = "dwmmc_k3", 456 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 457 .of_match_table = dw_mci_k3_match, 458 .pm = pm_ptr(&dw_mci_pmops), 459 }, 460 }; 461 462 module_platform_driver(dw_mci_k3_pltfm_driver); 463 464 MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension"); 465 MODULE_LICENSE("GPL v2"); 466 MODULE_ALIAS("platform:dwmmc_k3"); 467