10b5fce48SSeungwon Jeon /* 20b5fce48SSeungwon Jeon * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 30b5fce48SSeungwon Jeon * 40b5fce48SSeungwon Jeon * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd. 50b5fce48SSeungwon Jeon * 60b5fce48SSeungwon Jeon * This program is free software; you can redistribute it and/or modify 70b5fce48SSeungwon Jeon * it under the terms of the GNU General Public License as published by 80b5fce48SSeungwon Jeon * the Free Software Foundation; either version 2 of the License, or 90b5fce48SSeungwon Jeon * (at your option) any later version. 100b5fce48SSeungwon Jeon */ 110b5fce48SSeungwon Jeon 120b5fce48SSeungwon Jeon #ifndef _DW_MMC_EXYNOS_H_ 130b5fce48SSeungwon Jeon #define _DW_MMC_EXYNOS_H_ 140b5fce48SSeungwon Jeon 150b5fce48SSeungwon Jeon #define SDMMC_CLKSEL 0x09C 160b5fce48SSeungwon Jeon #define SDMMC_CLKSEL64 0x0A8 170b5fce48SSeungwon Jeon 18*80113132SSeungwon Jeon /* Extended Register's Offset */ 19*80113132SSeungwon Jeon #define SDMMC_HS400_DQS_EN 0x180 20*80113132SSeungwon Jeon #define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184 21*80113132SSeungwon Jeon #define SDMMC_HS400_DLINE_CTRL 0x188 22*80113132SSeungwon Jeon 230b5fce48SSeungwon Jeon /* CLKSEL register defines */ 240b5fce48SSeungwon Jeon #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) 250b5fce48SSeungwon Jeon #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) 260b5fce48SSeungwon Jeon #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) 270b5fce48SSeungwon Jeon #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) 28*80113132SSeungwon Jeon #define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7) 29*80113132SSeungwon Jeon #define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\ 30*80113132SSeungwon Jeon SDMMC_CLKSEL_CCLK_SAMPLE(y)) 310b5fce48SSeungwon Jeon #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ 320b5fce48SSeungwon Jeon SDMMC_CLKSEL_CCLK_DRIVE(y) | \ 330b5fce48SSeungwon Jeon SDMMC_CLKSEL_CCLK_DIVIDER(z)) 34*80113132SSeungwon Jeon #define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7) 350b5fce48SSeungwon Jeon #define SDMMC_CLKSEL_WAKEUP_INT BIT(11) 360b5fce48SSeungwon Jeon 37*80113132SSeungwon Jeon /* RCLK_EN register defines */ 38*80113132SSeungwon Jeon #define DATA_STROBE_EN BIT(0) 39*80113132SSeungwon Jeon #define AXI_NON_BLOCKING_WR BIT(7) 40*80113132SSeungwon Jeon 41*80113132SSeungwon Jeon /* DLINE_CTRL register defines */ 42*80113132SSeungwon Jeon #define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF)) 43*80113132SSeungwon Jeon #define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF) 44*80113132SSeungwon Jeon 450b5fce48SSeungwon Jeon /* Protector Register */ 460b5fce48SSeungwon Jeon #define SDMMC_EMMCP_BASE 0x1000 470b5fce48SSeungwon Jeon #define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) 480b5fce48SSeungwon Jeon #define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) 490b5fce48SSeungwon Jeon #define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) 500b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) 510b5fce48SSeungwon Jeon 520b5fce48SSeungwon Jeon /* SMU control defines */ 530b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7) 540b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6) 550b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5) 560b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) 570b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3) 580b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_ECB_MODE BIT(2) 590b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_ENCRYPTION BIT(1) 600b5fce48SSeungwon Jeon #define SDMMC_MPSCTRL_VALID BIT(0) 610b5fce48SSeungwon Jeon 620b5fce48SSeungwon Jeon /* Maximum number of Ending sector */ 630b5fce48SSeungwon Jeon #define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF 640b5fce48SSeungwon Jeon 650b5fce48SSeungwon Jeon /* Fixed clock divider */ 660b5fce48SSeungwon Jeon #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 670b5fce48SSeungwon Jeon #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 68*80113132SSeungwon Jeon #define HS400_FIXED_CIU_CLK_DIV 1 690b5fce48SSeungwon Jeon 700b5fce48SSeungwon Jeon /* Minimal required clock frequency for cclkin, unit: HZ */ 710b5fce48SSeungwon Jeon #define EXYNOS_CCLKIN_MIN 50000000 720b5fce48SSeungwon Jeon 730b5fce48SSeungwon Jeon #endif /* _DW_MMC_EXYNOS_H_ */ 74