1 /* 2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Original author: Purushotam Kumar 6 * Copyright (C) 2009 David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/ioport.h> 25 #include <linux/platform_device.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/cpufreq.h> 29 #include <linux/mmc/host.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/delay.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/mmc/mmc.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/mmc/slot-gpio.h> 39 #include <linux/interrupt.h> 40 41 #include <linux/platform_data/mmc-davinci.h> 42 43 /* 44 * Register Definitions 45 */ 46 #define DAVINCI_MMCCTL 0x00 /* Control Register */ 47 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 48 #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 49 #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 50 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 51 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 52 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 53 #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 54 #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 55 #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 56 #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 57 #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 58 #define DAVINCI_MMCCMD 0x30 /* Command Register */ 59 #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 60 #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 61 #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 62 #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 63 #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 64 #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 65 #define DAVINCI_MMCETOK 0x4C 66 #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 67 #define DAVINCI_MMCCKC 0x54 68 #define DAVINCI_MMCTORC 0x58 69 #define DAVINCI_MMCTODC 0x5C 70 #define DAVINCI_MMCBLNC 0x60 71 #define DAVINCI_SDIOCTL 0x64 72 #define DAVINCI_SDIOST0 0x68 73 #define DAVINCI_SDIOIEN 0x6C 74 #define DAVINCI_SDIOIST 0x70 75 #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 76 77 /* DAVINCI_MMCCTL definitions */ 78 #define MMCCTL_DATRST (1 << 0) 79 #define MMCCTL_CMDRST (1 << 1) 80 #define MMCCTL_WIDTH_8_BIT (1 << 8) 81 #define MMCCTL_WIDTH_4_BIT (1 << 2) 82 #define MMCCTL_DATEG_DISABLED (0 << 6) 83 #define MMCCTL_DATEG_RISING (1 << 6) 84 #define MMCCTL_DATEG_FALLING (2 << 6) 85 #define MMCCTL_DATEG_BOTH (3 << 6) 86 #define MMCCTL_PERMDR_LE (0 << 9) 87 #define MMCCTL_PERMDR_BE (1 << 9) 88 #define MMCCTL_PERMDX_LE (0 << 10) 89 #define MMCCTL_PERMDX_BE (1 << 10) 90 91 /* DAVINCI_MMCCLK definitions */ 92 #define MMCCLK_CLKEN (1 << 8) 93 #define MMCCLK_CLKRT_MASK (0xFF << 0) 94 95 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 96 #define MMCST0_DATDNE BIT(0) /* data done */ 97 #define MMCST0_BSYDNE BIT(1) /* busy done */ 98 #define MMCST0_RSPDNE BIT(2) /* command done */ 99 #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 100 #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 101 #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 102 #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 103 #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 104 #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 105 #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 106 #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 107 #define MMCST0_TRNDNE BIT(12) /* transfer done */ 108 109 /* DAVINCI_MMCST1 definitions */ 110 #define MMCST1_BUSY (1 << 0) 111 112 /* DAVINCI_MMCCMD definitions */ 113 #define MMCCMD_CMD_MASK (0x3F << 0) 114 #define MMCCMD_PPLEN (1 << 7) 115 #define MMCCMD_BSYEXP (1 << 8) 116 #define MMCCMD_RSPFMT_MASK (3 << 9) 117 #define MMCCMD_RSPFMT_NONE (0 << 9) 118 #define MMCCMD_RSPFMT_R1456 (1 << 9) 119 #define MMCCMD_RSPFMT_R2 (2 << 9) 120 #define MMCCMD_RSPFMT_R3 (3 << 9) 121 #define MMCCMD_DTRW (1 << 11) 122 #define MMCCMD_STRMTP (1 << 12) 123 #define MMCCMD_WDATX (1 << 13) 124 #define MMCCMD_INITCK (1 << 14) 125 #define MMCCMD_DCLR (1 << 15) 126 #define MMCCMD_DMATRIG (1 << 16) 127 128 /* DAVINCI_MMCFIFOCTL definitions */ 129 #define MMCFIFOCTL_FIFORST (1 << 0) 130 #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 131 #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 132 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 133 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 134 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 135 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 136 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 137 138 /* DAVINCI_SDIOST0 definitions */ 139 #define SDIOST0_DAT1_HI BIT(0) 140 141 /* DAVINCI_SDIOIEN definitions */ 142 #define SDIOIEN_IOINTEN BIT(0) 143 144 /* DAVINCI_SDIOIST definitions */ 145 #define SDIOIST_IOINT BIT(0) 146 147 /* MMCSD Init clock in Hz in opendrain mode */ 148 #define MMCSD_INIT_CLOCK 200000 149 150 /* 151 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 152 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 153 * for drivers with max_segs == 1, making the segments bigger (64KB) 154 * than the page or two that's otherwise typical. nr_sg (passed from 155 * platform data) == 16 gives at least the same throughput boost, using 156 * EDMA transfer linkage instead of spending CPU time copying pages. 157 */ 158 #define MAX_CCNT ((1 << 16) - 1) 159 160 #define MAX_NR_SG 16 161 162 static unsigned rw_threshold = 32; 163 module_param(rw_threshold, uint, S_IRUGO); 164 MODULE_PARM_DESC(rw_threshold, 165 "Read/Write threshold. Default = 32"); 166 167 static unsigned poll_threshold = 128; 168 module_param(poll_threshold, uint, S_IRUGO); 169 MODULE_PARM_DESC(poll_threshold, 170 "Polling transaction size threshold. Default = 128"); 171 172 static unsigned poll_loopcount = 32; 173 module_param(poll_loopcount, uint, S_IRUGO); 174 MODULE_PARM_DESC(poll_loopcount, 175 "Maximum polling loop count. Default = 32"); 176 177 static unsigned use_dma = 1; 178 module_param(use_dma, uint, 0); 179 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 180 181 struct mmc_davinci_host { 182 struct mmc_command *cmd; 183 struct mmc_data *data; 184 struct mmc_host *mmc; 185 struct clk *clk; 186 unsigned int mmc_input_clk; 187 void __iomem *base; 188 struct resource *mem_res; 189 int mmc_irq, sdio_irq; 190 unsigned char bus_mode; 191 192 #define DAVINCI_MMC_DATADIR_NONE 0 193 #define DAVINCI_MMC_DATADIR_READ 1 194 #define DAVINCI_MMC_DATADIR_WRITE 2 195 unsigned char data_dir; 196 197 /* buffer is used during PIO of one scatterlist segment, and 198 * is updated along with buffer_bytes_left. bytes_left applies 199 * to all N blocks of the PIO transfer. 200 */ 201 u8 *buffer; 202 u32 buffer_bytes_left; 203 u32 bytes_left; 204 205 struct dma_chan *dma_tx; 206 struct dma_chan *dma_rx; 207 bool use_dma; 208 bool do_dma; 209 bool sdio_int; 210 bool active_request; 211 212 /* For PIO we walk scatterlists one segment at a time. */ 213 unsigned int sg_len; 214 struct scatterlist *sg; 215 216 /* Version of the MMC/SD controller */ 217 u8 version; 218 /* for ns in one cycle calculation */ 219 unsigned ns_in_one_cycle; 220 /* Number of sg segments */ 221 u8 nr_sg; 222 #ifdef CONFIG_CPU_FREQ 223 struct notifier_block freq_transition; 224 #endif 225 }; 226 227 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); 228 229 /* PIO only */ 230 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 231 { 232 host->buffer_bytes_left = sg_dma_len(host->sg); 233 host->buffer = sg_virt(host->sg); 234 if (host->buffer_bytes_left > host->bytes_left) 235 host->buffer_bytes_left = host->bytes_left; 236 } 237 238 static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 239 unsigned int n) 240 { 241 u8 *p; 242 unsigned int i; 243 244 if (host->buffer_bytes_left == 0) { 245 host->sg = sg_next(host->data->sg); 246 mmc_davinci_sg_to_buf(host); 247 } 248 249 p = host->buffer; 250 if (n > host->buffer_bytes_left) 251 n = host->buffer_bytes_left; 252 host->buffer_bytes_left -= n; 253 host->bytes_left -= n; 254 255 /* NOTE: we never transfer more than rw_threshold bytes 256 * to/from the fifo here; there's no I/O overlap. 257 * This also assumes that access width( i.e. ACCWD) is 4 bytes 258 */ 259 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 260 for (i = 0; i < (n >> 2); i++) { 261 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 262 p = p + 4; 263 } 264 if (n & 3) { 265 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 266 p = p + (n & 3); 267 } 268 } else { 269 for (i = 0; i < (n >> 2); i++) { 270 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 271 p = p + 4; 272 } 273 if (n & 3) { 274 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 275 p = p + (n & 3); 276 } 277 } 278 host->buffer = p; 279 } 280 281 static void mmc_davinci_start_command(struct mmc_davinci_host *host, 282 struct mmc_command *cmd) 283 { 284 u32 cmd_reg = 0; 285 u32 im_val; 286 287 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 288 cmd->opcode, cmd->arg, 289 ({ char *s; 290 switch (mmc_resp_type(cmd)) { 291 case MMC_RSP_R1: 292 s = ", R1/R5/R6/R7 response"; 293 break; 294 case MMC_RSP_R1B: 295 s = ", R1b response"; 296 break; 297 case MMC_RSP_R2: 298 s = ", R2 response"; 299 break; 300 case MMC_RSP_R3: 301 s = ", R3/R4 response"; 302 break; 303 default: 304 s = ", (R? response)"; 305 break; 306 }; s; })); 307 host->cmd = cmd; 308 309 switch (mmc_resp_type(cmd)) { 310 case MMC_RSP_R1B: 311 /* There's some spec confusion about when R1B is 312 * allowed, but if the card doesn't issue a BUSY 313 * then it's harmless for us to allow it. 314 */ 315 cmd_reg |= MMCCMD_BSYEXP; 316 /* FALLTHROUGH */ 317 case MMC_RSP_R1: /* 48 bits, CRC */ 318 cmd_reg |= MMCCMD_RSPFMT_R1456; 319 break; 320 case MMC_RSP_R2: /* 136 bits, CRC */ 321 cmd_reg |= MMCCMD_RSPFMT_R2; 322 break; 323 case MMC_RSP_R3: /* 48 bits, no CRC */ 324 cmd_reg |= MMCCMD_RSPFMT_R3; 325 break; 326 default: 327 cmd_reg |= MMCCMD_RSPFMT_NONE; 328 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 329 mmc_resp_type(cmd)); 330 break; 331 } 332 333 /* Set command index */ 334 cmd_reg |= cmd->opcode; 335 336 /* Enable EDMA transfer triggers */ 337 if (host->do_dma) 338 cmd_reg |= MMCCMD_DMATRIG; 339 340 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 341 host->data_dir == DAVINCI_MMC_DATADIR_READ) 342 cmd_reg |= MMCCMD_DMATRIG; 343 344 /* Setting whether command involves data transfer or not */ 345 if (cmd->data) 346 cmd_reg |= MMCCMD_WDATX; 347 348 /* Setting whether data read or write */ 349 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 350 cmd_reg |= MMCCMD_DTRW; 351 352 if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 353 cmd_reg |= MMCCMD_PPLEN; 354 355 /* set Command timeout */ 356 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 357 358 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 359 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 360 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 361 im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 362 363 if (!host->do_dma) 364 im_val |= MMCST0_DXRDY; 365 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 366 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 367 368 if (!host->do_dma) 369 im_val |= MMCST0_DRRDY; 370 } 371 372 /* 373 * Before non-DMA WRITE commands the controller needs priming: 374 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 375 */ 376 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 377 davinci_fifo_data_trans(host, rw_threshold); 378 379 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 380 writel(cmd_reg, host->base + DAVINCI_MMCCMD); 381 382 host->active_request = true; 383 384 if (!host->do_dma && host->bytes_left <= poll_threshold) { 385 u32 count = poll_loopcount; 386 387 while (host->active_request && count--) { 388 mmc_davinci_irq(0, host); 389 cpu_relax(); 390 } 391 } 392 393 if (host->active_request) 394 writel(im_val, host->base + DAVINCI_MMCIM); 395 } 396 397 /*----------------------------------------------------------------------*/ 398 399 /* DMA infrastructure */ 400 401 static void davinci_abort_dma(struct mmc_davinci_host *host) 402 { 403 struct dma_chan *sync_dev; 404 405 if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 406 sync_dev = host->dma_rx; 407 else 408 sync_dev = host->dma_tx; 409 410 dmaengine_terminate_all(sync_dev); 411 } 412 413 static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 414 struct mmc_data *data) 415 { 416 struct dma_chan *chan; 417 struct dma_async_tx_descriptor *desc; 418 int ret = 0; 419 420 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 421 struct dma_slave_config dma_tx_conf = { 422 .direction = DMA_MEM_TO_DEV, 423 .dst_addr = host->mem_res->start + DAVINCI_MMCDXR, 424 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 425 .dst_maxburst = 426 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 427 }; 428 chan = host->dma_tx; 429 dmaengine_slave_config(host->dma_tx, &dma_tx_conf); 430 431 desc = dmaengine_prep_slave_sg(host->dma_tx, 432 data->sg, 433 host->sg_len, 434 DMA_MEM_TO_DEV, 435 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 436 if (!desc) { 437 dev_dbg(mmc_dev(host->mmc), 438 "failed to allocate DMA TX descriptor"); 439 ret = -1; 440 goto out; 441 } 442 } else { 443 struct dma_slave_config dma_rx_conf = { 444 .direction = DMA_DEV_TO_MEM, 445 .src_addr = host->mem_res->start + DAVINCI_MMCDRR, 446 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 447 .src_maxburst = 448 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, 449 }; 450 chan = host->dma_rx; 451 dmaengine_slave_config(host->dma_rx, &dma_rx_conf); 452 453 desc = dmaengine_prep_slave_sg(host->dma_rx, 454 data->sg, 455 host->sg_len, 456 DMA_DEV_TO_MEM, 457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 458 if (!desc) { 459 dev_dbg(mmc_dev(host->mmc), 460 "failed to allocate DMA RX descriptor"); 461 ret = -1; 462 goto out; 463 } 464 } 465 466 dmaengine_submit(desc); 467 dma_async_issue_pending(chan); 468 469 out: 470 return ret; 471 } 472 473 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 474 struct mmc_data *data) 475 { 476 int i; 477 int mask = rw_threshold - 1; 478 int ret = 0; 479 480 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 481 mmc_get_dma_dir(data)); 482 483 /* no individual DMA segment should need a partial FIFO */ 484 for (i = 0; i < host->sg_len; i++) { 485 if (sg_dma_len(data->sg + i) & mask) { 486 dma_unmap_sg(mmc_dev(host->mmc), 487 data->sg, data->sg_len, 488 mmc_get_dma_dir(data)); 489 return -1; 490 } 491 } 492 493 host->do_dma = 1; 494 ret = mmc_davinci_send_dma_request(host, data); 495 496 return ret; 497 } 498 499 static void davinci_release_dma_channels(struct mmc_davinci_host *host) 500 { 501 if (!host->use_dma) 502 return; 503 504 dma_release_channel(host->dma_tx); 505 dma_release_channel(host->dma_rx); 506 } 507 508 static int davinci_acquire_dma_channels(struct mmc_davinci_host *host) 509 { 510 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); 511 if (IS_ERR(host->dma_tx)) { 512 dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); 513 return PTR_ERR(host->dma_tx); 514 } 515 516 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); 517 if (IS_ERR(host->dma_rx)) { 518 dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); 519 dma_release_channel(host->dma_tx); 520 return PTR_ERR(host->dma_rx); 521 } 522 523 return 0; 524 } 525 526 /*----------------------------------------------------------------------*/ 527 528 static void 529 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 530 { 531 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 532 int timeout; 533 struct mmc_data *data = req->data; 534 535 if (host->version == MMC_CTLR_VERSION_2) 536 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 537 538 host->data = data; 539 if (data == NULL) { 540 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 541 writel(0, host->base + DAVINCI_MMCBLEN); 542 writel(0, host->base + DAVINCI_MMCNBLK); 543 return; 544 } 545 546 dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n", 547 (data->flags & MMC_DATA_WRITE) ? "write" : "read", 548 data->blocks, data->blksz); 549 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 550 data->timeout_clks, data->timeout_ns); 551 timeout = data->timeout_clks + 552 (data->timeout_ns / host->ns_in_one_cycle); 553 if (timeout > 0xffff) 554 timeout = 0xffff; 555 556 writel(timeout, host->base + DAVINCI_MMCTOD); 557 writel(data->blocks, host->base + DAVINCI_MMCNBLK); 558 writel(data->blksz, host->base + DAVINCI_MMCBLEN); 559 560 /* Configure the FIFO */ 561 if (data->flags & MMC_DATA_WRITE) { 562 host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 563 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 564 host->base + DAVINCI_MMCFIFOCTL); 565 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 566 host->base + DAVINCI_MMCFIFOCTL); 567 } else { 568 host->data_dir = DAVINCI_MMC_DATADIR_READ; 569 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 570 host->base + DAVINCI_MMCFIFOCTL); 571 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 572 host->base + DAVINCI_MMCFIFOCTL); 573 } 574 575 host->buffer = NULL; 576 host->bytes_left = data->blocks * data->blksz; 577 578 /* For now we try to use DMA whenever we won't need partial FIFO 579 * reads or writes, either for the whole transfer (as tested here) 580 * or for any individual scatterlist segment (tested when we call 581 * start_dma_transfer). 582 * 583 * While we *could* change that, unusual block sizes are rarely 584 * used. The occasional fallback to PIO should't hurt. 585 */ 586 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 587 && mmc_davinci_start_dma_transfer(host, data) == 0) { 588 /* zero this to ensure we take no PIO paths */ 589 host->bytes_left = 0; 590 } else { 591 /* Revert to CPU Copy */ 592 host->sg_len = data->sg_len; 593 host->sg = host->data->sg; 594 mmc_davinci_sg_to_buf(host); 595 } 596 } 597 598 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 599 { 600 struct mmc_davinci_host *host = mmc_priv(mmc); 601 unsigned long timeout = jiffies + msecs_to_jiffies(900); 602 u32 mmcst1 = 0; 603 604 /* Card may still be sending BUSY after a previous operation, 605 * typically some kind of write. If so, we can't proceed yet. 606 */ 607 while (time_before(jiffies, timeout)) { 608 mmcst1 = readl(host->base + DAVINCI_MMCST1); 609 if (!(mmcst1 & MMCST1_BUSY)) 610 break; 611 cpu_relax(); 612 } 613 if (mmcst1 & MMCST1_BUSY) { 614 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 615 req->cmd->error = -ETIMEDOUT; 616 mmc_request_done(mmc, req); 617 return; 618 } 619 620 host->do_dma = 0; 621 mmc_davinci_prepare_data(host, req); 622 mmc_davinci_start_command(host, req->cmd); 623 } 624 625 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 626 unsigned int mmc_req_freq) 627 { 628 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 629 630 mmc_pclk = host->mmc_input_clk; 631 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 632 mmc_push_pull_divisor = ((unsigned int)mmc_pclk 633 / (2 * mmc_req_freq)) - 1; 634 else 635 mmc_push_pull_divisor = 0; 636 637 mmc_freq = (unsigned int)mmc_pclk 638 / (2 * (mmc_push_pull_divisor + 1)); 639 640 if (mmc_freq > mmc_req_freq) 641 mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 642 /* Convert ns to clock cycles */ 643 if (mmc_req_freq <= 400000) 644 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 645 / (2 * (mmc_push_pull_divisor + 1)))/1000)); 646 else 647 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 648 / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 649 650 return mmc_push_pull_divisor; 651 } 652 653 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 654 { 655 unsigned int open_drain_freq = 0, mmc_pclk = 0; 656 unsigned int mmc_push_pull_freq = 0; 657 struct mmc_davinci_host *host = mmc_priv(mmc); 658 659 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 660 u32 temp; 661 662 /* Ignoring the init clock value passed for fixing the inter 663 * operability with different cards. 664 */ 665 open_drain_freq = ((unsigned int)mmc_pclk 666 / (2 * MMCSD_INIT_CLOCK)) - 1; 667 668 if (open_drain_freq > 0xFF) 669 open_drain_freq = 0xFF; 670 671 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 672 temp |= open_drain_freq; 673 writel(temp, host->base + DAVINCI_MMCCLK); 674 675 /* Convert ns to clock cycles */ 676 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 677 } else { 678 u32 temp; 679 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 680 681 if (mmc_push_pull_freq > 0xFF) 682 mmc_push_pull_freq = 0xFF; 683 684 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 685 writel(temp, host->base + DAVINCI_MMCCLK); 686 687 udelay(10); 688 689 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 690 temp |= mmc_push_pull_freq; 691 writel(temp, host->base + DAVINCI_MMCCLK); 692 693 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 694 695 udelay(10); 696 } 697 } 698 699 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 700 { 701 struct mmc_davinci_host *host = mmc_priv(mmc); 702 struct platform_device *pdev = to_platform_device(mmc->parent); 703 struct davinci_mmc_config *config = pdev->dev.platform_data; 704 705 dev_dbg(mmc_dev(host->mmc), 706 "clock %dHz busmode %d powermode %d Vdd %04x\n", 707 ios->clock, ios->bus_mode, ios->power_mode, 708 ios->vdd); 709 710 switch (ios->power_mode) { 711 case MMC_POWER_OFF: 712 if (config && config->set_power) 713 config->set_power(pdev->id, false); 714 break; 715 case MMC_POWER_UP: 716 if (config && config->set_power) 717 config->set_power(pdev->id, true); 718 break; 719 } 720 721 switch (ios->bus_width) { 722 case MMC_BUS_WIDTH_8: 723 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 724 writel((readl(host->base + DAVINCI_MMCCTL) & 725 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 726 host->base + DAVINCI_MMCCTL); 727 break; 728 case MMC_BUS_WIDTH_4: 729 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 730 if (host->version == MMC_CTLR_VERSION_2) 731 writel((readl(host->base + DAVINCI_MMCCTL) & 732 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 733 host->base + DAVINCI_MMCCTL); 734 else 735 writel(readl(host->base + DAVINCI_MMCCTL) | 736 MMCCTL_WIDTH_4_BIT, 737 host->base + DAVINCI_MMCCTL); 738 break; 739 case MMC_BUS_WIDTH_1: 740 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 741 if (host->version == MMC_CTLR_VERSION_2) 742 writel(readl(host->base + DAVINCI_MMCCTL) & 743 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 744 host->base + DAVINCI_MMCCTL); 745 else 746 writel(readl(host->base + DAVINCI_MMCCTL) & 747 ~MMCCTL_WIDTH_4_BIT, 748 host->base + DAVINCI_MMCCTL); 749 break; 750 } 751 752 calculate_clk_divider(mmc, ios); 753 754 host->bus_mode = ios->bus_mode; 755 if (ios->power_mode == MMC_POWER_UP) { 756 unsigned long timeout = jiffies + msecs_to_jiffies(50); 757 bool lose = true; 758 759 /* Send clock cycles, poll completion */ 760 writel(0, host->base + DAVINCI_MMCARGHL); 761 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 762 while (time_before(jiffies, timeout)) { 763 u32 tmp = readl(host->base + DAVINCI_MMCST0); 764 765 if (tmp & MMCST0_RSPDNE) { 766 lose = false; 767 break; 768 } 769 cpu_relax(); 770 } 771 if (lose) 772 dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 773 } 774 775 /* FIXME on power OFF, reset things ... */ 776 } 777 778 static void 779 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 780 { 781 host->data = NULL; 782 783 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 784 /* 785 * SDIO Interrupt Detection work-around as suggested by 786 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 787 * 2.1.6): Signal SDIO interrupt only if it is enabled by core 788 */ 789 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 790 SDIOST0_DAT1_HI)) { 791 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 792 mmc_signal_sdio_irq(host->mmc); 793 } 794 } 795 796 if (host->do_dma) { 797 davinci_abort_dma(host); 798 799 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 800 mmc_get_dma_dir(data)); 801 host->do_dma = false; 802 } 803 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 804 805 if (!data->stop || (host->cmd && host->cmd->error)) { 806 mmc_request_done(host->mmc, data->mrq); 807 writel(0, host->base + DAVINCI_MMCIM); 808 host->active_request = false; 809 } else 810 mmc_davinci_start_command(host, data->stop); 811 } 812 813 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 814 struct mmc_command *cmd) 815 { 816 host->cmd = NULL; 817 818 if (cmd->flags & MMC_RSP_PRESENT) { 819 if (cmd->flags & MMC_RSP_136) { 820 /* response type 2 */ 821 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 822 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 823 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 824 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 825 } else { 826 /* response types 1, 1b, 3, 4, 5, 6 */ 827 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 828 } 829 } 830 831 if (host->data == NULL || cmd->error) { 832 if (cmd->error == -ETIMEDOUT) 833 cmd->mrq->cmd->retries = 0; 834 mmc_request_done(host->mmc, cmd->mrq); 835 writel(0, host->base + DAVINCI_MMCIM); 836 host->active_request = false; 837 } 838 } 839 840 static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 841 int val) 842 { 843 u32 temp; 844 845 temp = readl(host->base + DAVINCI_MMCCTL); 846 if (val) /* reset */ 847 temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 848 else /* enable */ 849 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 850 851 writel(temp, host->base + DAVINCI_MMCCTL); 852 udelay(10); 853 } 854 855 static void 856 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 857 { 858 mmc_davinci_reset_ctrl(host, 1); 859 mmc_davinci_reset_ctrl(host, 0); 860 } 861 862 static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 863 { 864 struct mmc_davinci_host *host = dev_id; 865 unsigned int status; 866 867 status = readl(host->base + DAVINCI_SDIOIST); 868 if (status & SDIOIST_IOINT) { 869 dev_dbg(mmc_dev(host->mmc), 870 "SDIO interrupt status %x\n", status); 871 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 872 mmc_signal_sdio_irq(host->mmc); 873 } 874 return IRQ_HANDLED; 875 } 876 877 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 878 { 879 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 880 unsigned int status, qstatus; 881 int end_command = 0; 882 int end_transfer = 0; 883 struct mmc_data *data = host->data; 884 885 if (host->cmd == NULL && host->data == NULL) { 886 status = readl(host->base + DAVINCI_MMCST0); 887 dev_dbg(mmc_dev(host->mmc), 888 "Spurious interrupt 0x%04x\n", status); 889 /* Disable the interrupt from mmcsd */ 890 writel(0, host->base + DAVINCI_MMCIM); 891 return IRQ_NONE; 892 } 893 894 status = readl(host->base + DAVINCI_MMCST0); 895 qstatus = status; 896 897 /* handle FIFO first when using PIO for data. 898 * bytes_left will decrease to zero as I/O progress and status will 899 * read zero over iteration because this controller status 900 * register(MMCST0) reports any status only once and it is cleared 901 * by read. So, it is not unbouned loop even in the case of 902 * non-dma. 903 */ 904 if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 905 unsigned long im_val; 906 907 /* 908 * If interrupts fire during the following loop, they will be 909 * handled by the handler, but the PIC will still buffer these. 910 * As a result, the handler will be called again to serve these 911 * needlessly. In order to avoid these spurious interrupts, 912 * keep interrupts masked during the loop. 913 */ 914 im_val = readl(host->base + DAVINCI_MMCIM); 915 writel(0, host->base + DAVINCI_MMCIM); 916 917 do { 918 davinci_fifo_data_trans(host, rw_threshold); 919 status = readl(host->base + DAVINCI_MMCST0); 920 qstatus |= status; 921 } while (host->bytes_left && 922 (status & (MMCST0_DXRDY | MMCST0_DRRDY))); 923 924 /* 925 * If an interrupt is pending, it is assumed it will fire when 926 * it is unmasked. This assumption is also taken when the MMCIM 927 * is first set. Otherwise, writing to MMCIM after reading the 928 * status is race-prone. 929 */ 930 writel(im_val, host->base + DAVINCI_MMCIM); 931 } 932 933 if (qstatus & MMCST0_DATDNE) { 934 /* All blocks sent/received, and CRC checks passed */ 935 if (data != NULL) { 936 if ((host->do_dma == 0) && (host->bytes_left > 0)) { 937 /* if datasize < rw_threshold 938 * no RX ints are generated 939 */ 940 davinci_fifo_data_trans(host, host->bytes_left); 941 } 942 end_transfer = 1; 943 data->bytes_xfered = data->blocks * data->blksz; 944 } else { 945 dev_err(mmc_dev(host->mmc), 946 "DATDNE with no host->data\n"); 947 } 948 } 949 950 if (qstatus & MMCST0_TOUTRD) { 951 /* Read data timeout */ 952 data->error = -ETIMEDOUT; 953 end_transfer = 1; 954 955 dev_dbg(mmc_dev(host->mmc), 956 "read data timeout, status %x\n", 957 qstatus); 958 959 davinci_abort_data(host, data); 960 } 961 962 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 963 /* Data CRC error */ 964 data->error = -EILSEQ; 965 end_transfer = 1; 966 967 /* NOTE: this controller uses CRCWR to report both CRC 968 * errors and timeouts (on writes). MMCDRSP values are 969 * only weakly documented, but 0x9f was clearly a timeout 970 * case and the two three-bit patterns in various SD specs 971 * (101, 010) aren't part of it ... 972 */ 973 if (qstatus & MMCST0_CRCWR) { 974 u32 temp = readb(host->base + DAVINCI_MMCDRSP); 975 976 if (temp == 0x9f) 977 data->error = -ETIMEDOUT; 978 } 979 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 980 (qstatus & MMCST0_CRCWR) ? "write" : "read", 981 (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 982 983 davinci_abort_data(host, data); 984 } 985 986 if (qstatus & MMCST0_TOUTRS) { 987 /* Command timeout */ 988 if (host->cmd) { 989 dev_dbg(mmc_dev(host->mmc), 990 "CMD%d timeout, status %x\n", 991 host->cmd->opcode, qstatus); 992 host->cmd->error = -ETIMEDOUT; 993 if (data) { 994 end_transfer = 1; 995 davinci_abort_data(host, data); 996 } else 997 end_command = 1; 998 } 999 } 1000 1001 if (qstatus & MMCST0_CRCRS) { 1002 /* Command CRC error */ 1003 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1004 if (host->cmd) { 1005 host->cmd->error = -EILSEQ; 1006 end_command = 1; 1007 } 1008 } 1009 1010 if (qstatus & MMCST0_RSPDNE) { 1011 /* End of command phase */ 1012 end_command = (int) host->cmd; 1013 } 1014 1015 if (end_command) 1016 mmc_davinci_cmd_done(host, host->cmd); 1017 if (end_transfer) 1018 mmc_davinci_xfer_done(host, data); 1019 return IRQ_HANDLED; 1020 } 1021 1022 static int mmc_davinci_get_cd(struct mmc_host *mmc) 1023 { 1024 struct platform_device *pdev = to_platform_device(mmc->parent); 1025 struct davinci_mmc_config *config = pdev->dev.platform_data; 1026 1027 if (config && config->get_cd) 1028 return config->get_cd(pdev->id); 1029 1030 return mmc_gpio_get_cd(mmc); 1031 } 1032 1033 static int mmc_davinci_get_ro(struct mmc_host *mmc) 1034 { 1035 struct platform_device *pdev = to_platform_device(mmc->parent); 1036 struct davinci_mmc_config *config = pdev->dev.platform_data; 1037 1038 if (config && config->get_ro) 1039 return config->get_ro(pdev->id); 1040 1041 return mmc_gpio_get_ro(mmc); 1042 } 1043 1044 static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1045 { 1046 struct mmc_davinci_host *host = mmc_priv(mmc); 1047 1048 if (enable) { 1049 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1050 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1051 mmc_signal_sdio_irq(host->mmc); 1052 } else { 1053 host->sdio_int = true; 1054 writel(readl(host->base + DAVINCI_SDIOIEN) | 1055 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1056 } 1057 } else { 1058 host->sdio_int = false; 1059 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1060 host->base + DAVINCI_SDIOIEN); 1061 } 1062 } 1063 1064 static const struct mmc_host_ops mmc_davinci_ops = { 1065 .request = mmc_davinci_request, 1066 .set_ios = mmc_davinci_set_ios, 1067 .get_cd = mmc_davinci_get_cd, 1068 .get_ro = mmc_davinci_get_ro, 1069 .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1070 }; 1071 1072 /*----------------------------------------------------------------------*/ 1073 1074 #ifdef CONFIG_CPU_FREQ 1075 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 1076 unsigned long val, void *data) 1077 { 1078 struct mmc_davinci_host *host; 1079 unsigned int mmc_pclk; 1080 struct mmc_host *mmc; 1081 unsigned long flags; 1082 1083 host = container_of(nb, struct mmc_davinci_host, freq_transition); 1084 mmc = host->mmc; 1085 mmc_pclk = clk_get_rate(host->clk); 1086 1087 if (val == CPUFREQ_POSTCHANGE) { 1088 spin_lock_irqsave(&mmc->lock, flags); 1089 host->mmc_input_clk = mmc_pclk; 1090 calculate_clk_divider(mmc, &mmc->ios); 1091 spin_unlock_irqrestore(&mmc->lock, flags); 1092 } 1093 1094 return 0; 1095 } 1096 1097 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1098 { 1099 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 1100 1101 return cpufreq_register_notifier(&host->freq_transition, 1102 CPUFREQ_TRANSITION_NOTIFIER); 1103 } 1104 1105 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1106 { 1107 cpufreq_unregister_notifier(&host->freq_transition, 1108 CPUFREQ_TRANSITION_NOTIFIER); 1109 } 1110 #else 1111 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1112 { 1113 return 0; 1114 } 1115 1116 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1117 { 1118 } 1119 #endif 1120 static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1121 { 1122 1123 mmc_davinci_reset_ctrl(host, 1); 1124 1125 writel(0, host->base + DAVINCI_MMCCLK); 1126 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1127 1128 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1129 writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1130 1131 mmc_davinci_reset_ctrl(host, 0); 1132 } 1133 1134 static const struct platform_device_id davinci_mmc_devtype[] = { 1135 { 1136 .name = "dm6441-mmc", 1137 .driver_data = MMC_CTLR_VERSION_1, 1138 }, { 1139 .name = "da830-mmc", 1140 .driver_data = MMC_CTLR_VERSION_2, 1141 }, 1142 {}, 1143 }; 1144 MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype); 1145 1146 static const struct of_device_id davinci_mmc_dt_ids[] = { 1147 { 1148 .compatible = "ti,dm6441-mmc", 1149 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1], 1150 }, 1151 { 1152 .compatible = "ti,da830-mmc", 1153 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2], 1154 }, 1155 {}, 1156 }; 1157 MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids); 1158 1159 static int mmc_davinci_parse_pdata(struct mmc_host *mmc) 1160 { 1161 struct platform_device *pdev = to_platform_device(mmc->parent); 1162 struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1163 struct mmc_davinci_host *host; 1164 int ret; 1165 1166 if (!pdata) 1167 return -EINVAL; 1168 1169 host = mmc_priv(mmc); 1170 if (!host) 1171 return -EINVAL; 1172 1173 if (pdata && pdata->nr_sg) 1174 host->nr_sg = pdata->nr_sg - 1; 1175 1176 if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1177 mmc->caps |= MMC_CAP_4_BIT_DATA; 1178 1179 if (pdata && (pdata->wires == 8)) 1180 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1181 1182 mmc->f_min = 312500; 1183 mmc->f_max = 25000000; 1184 if (pdata && pdata->max_freq) 1185 mmc->f_max = pdata->max_freq; 1186 if (pdata && pdata->caps) 1187 mmc->caps |= pdata->caps; 1188 1189 /* Register a cd gpio, if there is not one, enable polling */ 1190 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1191 if (ret == -EPROBE_DEFER) 1192 return ret; 1193 else if (ret) 1194 mmc->caps |= MMC_CAP_NEEDS_POLL; 1195 1196 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1197 if (ret == -EPROBE_DEFER) 1198 return ret; 1199 1200 return 0; 1201 } 1202 1203 static int davinci_mmcsd_probe(struct platform_device *pdev) 1204 { 1205 const struct of_device_id *match; 1206 struct mmc_davinci_host *host = NULL; 1207 struct mmc_host *mmc = NULL; 1208 struct resource *r, *mem = NULL; 1209 int ret, irq; 1210 size_t mem_size; 1211 const struct platform_device_id *id_entry; 1212 1213 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1214 if (!r) 1215 return -ENODEV; 1216 irq = platform_get_irq(pdev, 0); 1217 if (irq < 0) 1218 return irq; 1219 1220 mem_size = resource_size(r); 1221 mem = devm_request_mem_region(&pdev->dev, r->start, mem_size, 1222 pdev->name); 1223 if (!mem) 1224 return -EBUSY; 1225 1226 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1227 if (!mmc) 1228 return -ENOMEM; 1229 1230 host = mmc_priv(mmc); 1231 host->mmc = mmc; /* Important */ 1232 1233 host->mem_res = mem; 1234 host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); 1235 if (!host->base) { 1236 ret = -ENOMEM; 1237 goto ioremap_fail; 1238 } 1239 1240 host->clk = devm_clk_get(&pdev->dev, NULL); 1241 if (IS_ERR(host->clk)) { 1242 ret = PTR_ERR(host->clk); 1243 goto clk_get_fail; 1244 } 1245 ret = clk_prepare_enable(host->clk); 1246 if (ret) 1247 goto clk_prepare_enable_fail; 1248 1249 host->mmc_input_clk = clk_get_rate(host->clk); 1250 1251 match = of_match_device(davinci_mmc_dt_ids, &pdev->dev); 1252 if (match) { 1253 pdev->id_entry = match->data; 1254 ret = mmc_of_parse(mmc); 1255 if (ret) { 1256 if (ret != -EPROBE_DEFER) 1257 dev_err(&pdev->dev, 1258 "could not parse of data: %d\n", ret); 1259 goto parse_fail; 1260 } 1261 } else { 1262 ret = mmc_davinci_parse_pdata(mmc); 1263 if (ret) { 1264 dev_err(&pdev->dev, 1265 "could not parse platform data: %d\n", ret); 1266 goto parse_fail; 1267 } } 1268 1269 if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1270 host->nr_sg = MAX_NR_SG; 1271 1272 init_mmcsd_host(host); 1273 1274 host->use_dma = use_dma; 1275 host->mmc_irq = irq; 1276 host->sdio_irq = platform_get_irq(pdev, 1); 1277 1278 if (host->use_dma) { 1279 ret = davinci_acquire_dma_channels(host); 1280 if (ret == -EPROBE_DEFER) 1281 goto dma_probe_defer; 1282 else if (ret) 1283 host->use_dma = 0; 1284 } 1285 1286 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1287 1288 id_entry = platform_get_device_id(pdev); 1289 if (id_entry) 1290 host->version = id_entry->driver_data; 1291 1292 mmc->ops = &mmc_davinci_ops; 1293 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1294 1295 /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1296 * Each hw_seg uses one EDMA parameter RAM slot, always one 1297 * channel and then usually some linked slots. 1298 */ 1299 mmc->max_segs = MAX_NR_SG; 1300 1301 /* EDMA limit per hw segment (one or two MBytes) */ 1302 mmc->max_seg_size = MAX_CCNT * rw_threshold; 1303 1304 /* MMC/SD controller limits for multiblock requests */ 1305 mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1306 mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1307 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1308 1309 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1310 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1311 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1312 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1313 1314 platform_set_drvdata(pdev, host); 1315 1316 ret = mmc_davinci_cpufreq_register(host); 1317 if (ret) { 1318 dev_err(&pdev->dev, "failed to register cpufreq\n"); 1319 goto cpu_freq_fail; 1320 } 1321 1322 ret = mmc_add_host(mmc); 1323 if (ret < 0) 1324 goto mmc_add_host_fail; 1325 1326 ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0, 1327 mmc_hostname(mmc), host); 1328 if (ret) 1329 goto request_irq_fail; 1330 1331 if (host->sdio_irq >= 0) { 1332 ret = devm_request_irq(&pdev->dev, host->sdio_irq, 1333 mmc_davinci_sdio_irq, 0, 1334 mmc_hostname(mmc), host); 1335 if (!ret) 1336 mmc->caps |= MMC_CAP_SDIO_IRQ; 1337 } 1338 1339 rename_region(mem, mmc_hostname(mmc)); 1340 1341 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1342 host->use_dma ? "DMA" : "PIO", 1343 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1344 1345 return 0; 1346 1347 request_irq_fail: 1348 mmc_remove_host(mmc); 1349 mmc_add_host_fail: 1350 mmc_davinci_cpufreq_deregister(host); 1351 cpu_freq_fail: 1352 davinci_release_dma_channels(host); 1353 parse_fail: 1354 dma_probe_defer: 1355 clk_disable_unprepare(host->clk); 1356 clk_prepare_enable_fail: 1357 clk_get_fail: 1358 ioremap_fail: 1359 mmc_free_host(mmc); 1360 1361 return ret; 1362 } 1363 1364 static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1365 { 1366 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1367 1368 mmc_remove_host(host->mmc); 1369 mmc_davinci_cpufreq_deregister(host); 1370 davinci_release_dma_channels(host); 1371 clk_disable_unprepare(host->clk); 1372 mmc_free_host(host->mmc); 1373 1374 return 0; 1375 } 1376 1377 #ifdef CONFIG_PM 1378 static int davinci_mmcsd_suspend(struct device *dev) 1379 { 1380 struct mmc_davinci_host *host = dev_get_drvdata(dev); 1381 1382 writel(0, host->base + DAVINCI_MMCIM); 1383 mmc_davinci_reset_ctrl(host, 1); 1384 clk_disable(host->clk); 1385 1386 return 0; 1387 } 1388 1389 static int davinci_mmcsd_resume(struct device *dev) 1390 { 1391 struct mmc_davinci_host *host = dev_get_drvdata(dev); 1392 1393 clk_enable(host->clk); 1394 mmc_davinci_reset_ctrl(host, 0); 1395 1396 return 0; 1397 } 1398 1399 static const struct dev_pm_ops davinci_mmcsd_pm = { 1400 .suspend = davinci_mmcsd_suspend, 1401 .resume = davinci_mmcsd_resume, 1402 }; 1403 1404 #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1405 #else 1406 #define davinci_mmcsd_pm_ops NULL 1407 #endif 1408 1409 static struct platform_driver davinci_mmcsd_driver = { 1410 .driver = { 1411 .name = "davinci_mmc", 1412 .pm = davinci_mmcsd_pm_ops, 1413 .of_match_table = davinci_mmc_dt_ids, 1414 }, 1415 .probe = davinci_mmcsd_probe, 1416 .remove = __exit_p(davinci_mmcsd_remove), 1417 .id_table = davinci_mmc_devtype, 1418 }; 1419 1420 module_platform_driver(davinci_mmcsd_driver); 1421 1422 MODULE_AUTHOR("Texas Instruments India"); 1423 MODULE_LICENSE("GPL"); 1424 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 1425 MODULE_ALIAS("platform:davinci_mmc"); 1426 1427