1 /* 2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Original author: Purushotam Kumar 6 * Copyright (C) 2009 David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/ioport.h> 25 #include <linux/platform_device.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/cpufreq.h> 29 #include <linux/mmc/host.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/delay.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/mmc/mmc.h> 35 36 #include <mach/mmc.h> 37 #include <mach/edma.h> 38 39 /* 40 * Register Definitions 41 */ 42 #define DAVINCI_MMCCTL 0x00 /* Control Register */ 43 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 44 #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 45 #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 46 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 47 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 48 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 49 #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 50 #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 51 #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 52 #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 53 #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 54 #define DAVINCI_MMCCMD 0x30 /* Command Register */ 55 #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 56 #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 57 #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 58 #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 59 #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 60 #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 61 #define DAVINCI_MMCETOK 0x4C 62 #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 63 #define DAVINCI_MMCCKC 0x54 64 #define DAVINCI_MMCTORC 0x58 65 #define DAVINCI_MMCTODC 0x5C 66 #define DAVINCI_MMCBLNC 0x60 67 #define DAVINCI_SDIOCTL 0x64 68 #define DAVINCI_SDIOST0 0x68 69 #define DAVINCI_SDIOIEN 0x6C 70 #define DAVINCI_SDIOIST 0x70 71 #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 72 73 /* DAVINCI_MMCCTL definitions */ 74 #define MMCCTL_DATRST (1 << 0) 75 #define MMCCTL_CMDRST (1 << 1) 76 #define MMCCTL_WIDTH_8_BIT (1 << 8) 77 #define MMCCTL_WIDTH_4_BIT (1 << 2) 78 #define MMCCTL_DATEG_DISABLED (0 << 6) 79 #define MMCCTL_DATEG_RISING (1 << 6) 80 #define MMCCTL_DATEG_FALLING (2 << 6) 81 #define MMCCTL_DATEG_BOTH (3 << 6) 82 #define MMCCTL_PERMDR_LE (0 << 9) 83 #define MMCCTL_PERMDR_BE (1 << 9) 84 #define MMCCTL_PERMDX_LE (0 << 10) 85 #define MMCCTL_PERMDX_BE (1 << 10) 86 87 /* DAVINCI_MMCCLK definitions */ 88 #define MMCCLK_CLKEN (1 << 8) 89 #define MMCCLK_CLKRT_MASK (0xFF << 0) 90 91 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 92 #define MMCST0_DATDNE BIT(0) /* data done */ 93 #define MMCST0_BSYDNE BIT(1) /* busy done */ 94 #define MMCST0_RSPDNE BIT(2) /* command done */ 95 #define MMCST0_TOUTRD BIT(3) /* data read timeout */ 96 #define MMCST0_TOUTRS BIT(4) /* command response timeout */ 97 #define MMCST0_CRCWR BIT(5) /* data write CRC error */ 98 #define MMCST0_CRCRD BIT(6) /* data read CRC error */ 99 #define MMCST0_CRCRS BIT(7) /* command response CRC error */ 100 #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 101 #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 102 #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 103 #define MMCST0_TRNDNE BIT(12) /* transfer done */ 104 105 /* DAVINCI_MMCST1 definitions */ 106 #define MMCST1_BUSY (1 << 0) 107 108 /* DAVINCI_MMCCMD definitions */ 109 #define MMCCMD_CMD_MASK (0x3F << 0) 110 #define MMCCMD_PPLEN (1 << 7) 111 #define MMCCMD_BSYEXP (1 << 8) 112 #define MMCCMD_RSPFMT_MASK (3 << 9) 113 #define MMCCMD_RSPFMT_NONE (0 << 9) 114 #define MMCCMD_RSPFMT_R1456 (1 << 9) 115 #define MMCCMD_RSPFMT_R2 (2 << 9) 116 #define MMCCMD_RSPFMT_R3 (3 << 9) 117 #define MMCCMD_DTRW (1 << 11) 118 #define MMCCMD_STRMTP (1 << 12) 119 #define MMCCMD_WDATX (1 << 13) 120 #define MMCCMD_INITCK (1 << 14) 121 #define MMCCMD_DCLR (1 << 15) 122 #define MMCCMD_DMATRIG (1 << 16) 123 124 /* DAVINCI_MMCFIFOCTL definitions */ 125 #define MMCFIFOCTL_FIFORST (1 << 0) 126 #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 127 #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 128 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 129 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 130 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 131 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 132 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 133 134 /* DAVINCI_SDIOST0 definitions */ 135 #define SDIOST0_DAT1_HI BIT(0) 136 137 /* DAVINCI_SDIOIEN definitions */ 138 #define SDIOIEN_IOINTEN BIT(0) 139 140 /* DAVINCI_SDIOIST definitions */ 141 #define SDIOIST_IOINT BIT(0) 142 143 /* MMCSD Init clock in Hz in opendrain mode */ 144 #define MMCSD_INIT_CLOCK 200000 145 146 /* 147 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 148 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 149 * for drivers with max_segs == 1, making the segments bigger (64KB) 150 * than the page or two that's otherwise typical. nr_sg (passed from 151 * platform data) == 16 gives at least the same throughput boost, using 152 * EDMA transfer linkage instead of spending CPU time copying pages. 153 */ 154 #define MAX_CCNT ((1 << 16) - 1) 155 156 #define MAX_NR_SG 16 157 158 static unsigned rw_threshold = 32; 159 module_param(rw_threshold, uint, S_IRUGO); 160 MODULE_PARM_DESC(rw_threshold, 161 "Read/Write threshold. Default = 32"); 162 163 static unsigned __initdata use_dma = 1; 164 module_param(use_dma, uint, 0); 165 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 166 167 struct mmc_davinci_host { 168 struct mmc_command *cmd; 169 struct mmc_data *data; 170 struct mmc_host *mmc; 171 struct clk *clk; 172 unsigned int mmc_input_clk; 173 void __iomem *base; 174 struct resource *mem_res; 175 int mmc_irq, sdio_irq; 176 unsigned char bus_mode; 177 178 #define DAVINCI_MMC_DATADIR_NONE 0 179 #define DAVINCI_MMC_DATADIR_READ 1 180 #define DAVINCI_MMC_DATADIR_WRITE 2 181 unsigned char data_dir; 182 unsigned char suspended; 183 184 /* buffer is used during PIO of one scatterlist segment, and 185 * is updated along with buffer_bytes_left. bytes_left applies 186 * to all N blocks of the PIO transfer. 187 */ 188 u8 *buffer; 189 u32 buffer_bytes_left; 190 u32 bytes_left; 191 192 u32 rxdma, txdma; 193 bool use_dma; 194 bool do_dma; 195 bool sdio_int; 196 197 /* Scatterlist DMA uses one or more parameter RAM entries: 198 * the main one (associated with rxdma or txdma) plus zero or 199 * more links. The entries for a given transfer differ only 200 * by memory buffer (address, length) and link field. 201 */ 202 struct edmacc_param tx_template; 203 struct edmacc_param rx_template; 204 unsigned n_link; 205 u32 links[MAX_NR_SG - 1]; 206 207 /* For PIO we walk scatterlists one segment at a time. */ 208 unsigned int sg_len; 209 struct scatterlist *sg; 210 211 /* Version of the MMC/SD controller */ 212 u8 version; 213 /* for ns in one cycle calculation */ 214 unsigned ns_in_one_cycle; 215 /* Number of sg segments */ 216 u8 nr_sg; 217 #ifdef CONFIG_CPU_FREQ 218 struct notifier_block freq_transition; 219 #endif 220 }; 221 222 223 /* PIO only */ 224 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 225 { 226 host->buffer_bytes_left = sg_dma_len(host->sg); 227 host->buffer = sg_virt(host->sg); 228 if (host->buffer_bytes_left > host->bytes_left) 229 host->buffer_bytes_left = host->bytes_left; 230 } 231 232 static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 233 unsigned int n) 234 { 235 u8 *p; 236 unsigned int i; 237 238 if (host->buffer_bytes_left == 0) { 239 host->sg = sg_next(host->data->sg); 240 mmc_davinci_sg_to_buf(host); 241 } 242 243 p = host->buffer; 244 if (n > host->buffer_bytes_left) 245 n = host->buffer_bytes_left; 246 host->buffer_bytes_left -= n; 247 host->bytes_left -= n; 248 249 /* NOTE: we never transfer more than rw_threshold bytes 250 * to/from the fifo here; there's no I/O overlap. 251 * This also assumes that access width( i.e. ACCWD) is 4 bytes 252 */ 253 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 254 for (i = 0; i < (n >> 2); i++) { 255 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 256 p = p + 4; 257 } 258 if (n & 3) { 259 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 260 p = p + (n & 3); 261 } 262 } else { 263 for (i = 0; i < (n >> 2); i++) { 264 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 265 p = p + 4; 266 } 267 if (n & 3) { 268 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 269 p = p + (n & 3); 270 } 271 } 272 host->buffer = p; 273 } 274 275 static void mmc_davinci_start_command(struct mmc_davinci_host *host, 276 struct mmc_command *cmd) 277 { 278 u32 cmd_reg = 0; 279 u32 im_val; 280 281 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 282 cmd->opcode, cmd->arg, 283 ({ char *s; 284 switch (mmc_resp_type(cmd)) { 285 case MMC_RSP_R1: 286 s = ", R1/R5/R6/R7 response"; 287 break; 288 case MMC_RSP_R1B: 289 s = ", R1b response"; 290 break; 291 case MMC_RSP_R2: 292 s = ", R2 response"; 293 break; 294 case MMC_RSP_R3: 295 s = ", R3/R4 response"; 296 break; 297 default: 298 s = ", (R? response)"; 299 break; 300 }; s; })); 301 host->cmd = cmd; 302 303 switch (mmc_resp_type(cmd)) { 304 case MMC_RSP_R1B: 305 /* There's some spec confusion about when R1B is 306 * allowed, but if the card doesn't issue a BUSY 307 * then it's harmless for us to allow it. 308 */ 309 cmd_reg |= MMCCMD_BSYEXP; 310 /* FALLTHROUGH */ 311 case MMC_RSP_R1: /* 48 bits, CRC */ 312 cmd_reg |= MMCCMD_RSPFMT_R1456; 313 break; 314 case MMC_RSP_R2: /* 136 bits, CRC */ 315 cmd_reg |= MMCCMD_RSPFMT_R2; 316 break; 317 case MMC_RSP_R3: /* 48 bits, no CRC */ 318 cmd_reg |= MMCCMD_RSPFMT_R3; 319 break; 320 default: 321 cmd_reg |= MMCCMD_RSPFMT_NONE; 322 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 323 mmc_resp_type(cmd)); 324 break; 325 } 326 327 /* Set command index */ 328 cmd_reg |= cmd->opcode; 329 330 /* Enable EDMA transfer triggers */ 331 if (host->do_dma) 332 cmd_reg |= MMCCMD_DMATRIG; 333 334 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 335 host->data_dir == DAVINCI_MMC_DATADIR_READ) 336 cmd_reg |= MMCCMD_DMATRIG; 337 338 /* Setting whether command involves data transfer or not */ 339 if (cmd->data) 340 cmd_reg |= MMCCMD_WDATX; 341 342 /* Setting whether stream or block transfer */ 343 if (cmd->flags & MMC_DATA_STREAM) 344 cmd_reg |= MMCCMD_STRMTP; 345 346 /* Setting whether data read or write */ 347 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 348 cmd_reg |= MMCCMD_DTRW; 349 350 if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 351 cmd_reg |= MMCCMD_PPLEN; 352 353 /* set Command timeout */ 354 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 355 356 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 357 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 358 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 359 im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 360 361 if (!host->do_dma) 362 im_val |= MMCST0_DXRDY; 363 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 364 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 365 366 if (!host->do_dma) 367 im_val |= MMCST0_DRRDY; 368 } 369 370 /* 371 * Before non-DMA WRITE commands the controller needs priming: 372 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 373 */ 374 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 375 davinci_fifo_data_trans(host, rw_threshold); 376 377 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 378 writel(cmd_reg, host->base + DAVINCI_MMCCMD); 379 writel(im_val, host->base + DAVINCI_MMCIM); 380 } 381 382 /*----------------------------------------------------------------------*/ 383 384 /* DMA infrastructure */ 385 386 static void davinci_abort_dma(struct mmc_davinci_host *host) 387 { 388 int sync_dev; 389 390 if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 391 sync_dev = host->rxdma; 392 else 393 sync_dev = host->txdma; 394 395 edma_stop(sync_dev); 396 edma_clean_channel(sync_dev); 397 } 398 399 static void 400 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data); 401 402 static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data) 403 { 404 if (DMA_COMPLETE != ch_status) { 405 struct mmc_davinci_host *host = data; 406 407 /* Currently means: DMA Event Missed, or "null" transfer 408 * request was seen. In the future, TC errors (like bad 409 * addresses) might be presented too. 410 */ 411 dev_warn(mmc_dev(host->mmc), "DMA %s error\n", 412 (host->data->flags & MMC_DATA_WRITE) 413 ? "write" : "read"); 414 host->data->error = -EIO; 415 mmc_davinci_xfer_done(host, host->data); 416 } 417 } 418 419 /* Set up tx or rx template, to be modified and updated later */ 420 static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host, 421 bool tx, struct edmacc_param *template) 422 { 423 unsigned sync_dev; 424 const u16 acnt = 4; 425 const u16 bcnt = rw_threshold >> 2; 426 const u16 ccnt = 0; 427 u32 src_port = 0; 428 u32 dst_port = 0; 429 s16 src_bidx, dst_bidx; 430 s16 src_cidx, dst_cidx; 431 432 /* 433 * A-B Sync transfer: each DMA request is for one "frame" of 434 * rw_threshold bytes, broken into "acnt"-size chunks repeated 435 * "bcnt" times. Each segment needs "ccnt" such frames; since 436 * we tell the block layer our mmc->max_seg_size limit, we can 437 * trust (later) that it's within bounds. 438 * 439 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and 440 * EDMA will optimize memory operations to use larger bursts. 441 */ 442 if (tx) { 443 sync_dev = host->txdma; 444 445 /* src_prt, ccnt, and link to be set up later */ 446 src_bidx = acnt; 447 src_cidx = acnt * bcnt; 448 449 dst_port = host->mem_res->start + DAVINCI_MMCDXR; 450 dst_bidx = 0; 451 dst_cidx = 0; 452 } else { 453 sync_dev = host->rxdma; 454 455 src_port = host->mem_res->start + DAVINCI_MMCDRR; 456 src_bidx = 0; 457 src_cidx = 0; 458 459 /* dst_prt, ccnt, and link to be set up later */ 460 dst_bidx = acnt; 461 dst_cidx = acnt * bcnt; 462 } 463 464 /* 465 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses 466 * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT 467 * parameter is ignored. 468 */ 469 edma_set_src(sync_dev, src_port, INCR, W8BIT); 470 edma_set_dest(sync_dev, dst_port, INCR, W8BIT); 471 472 edma_set_src_index(sync_dev, src_bidx, src_cidx); 473 edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); 474 475 edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); 476 477 edma_read_slot(sync_dev, template); 478 479 /* don't bother with irqs or chaining */ 480 template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; 481 } 482 483 static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 484 struct mmc_data *data) 485 { 486 struct edmacc_param *template; 487 int channel, slot; 488 unsigned link; 489 struct scatterlist *sg; 490 unsigned sg_len; 491 unsigned bytes_left = host->bytes_left; 492 const unsigned shift = ffs(rw_threshold) - 1; 493 494 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 495 template = &host->tx_template; 496 channel = host->txdma; 497 } else { 498 template = &host->rx_template; 499 channel = host->rxdma; 500 } 501 502 /* We know sg_len and ccnt will never be out of range because 503 * we told the mmc layer which in turn tells the block layer 504 * to ensure that it only hands us one scatterlist segment 505 * per EDMA PARAM entry. Update the PARAM 506 * entries needed for each segment of this scatterlist. 507 */ 508 for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len; 509 sg_len-- != 0 && bytes_left; 510 sg = sg_next(sg), slot = host->links[link++]) { 511 u32 buf = sg_dma_address(sg); 512 unsigned count = sg_dma_len(sg); 513 514 template->link_bcntrld = sg_len 515 ? (EDMA_CHAN_SLOT(host->links[link]) << 5) 516 : 0xffff; 517 518 if (count > bytes_left) 519 count = bytes_left; 520 bytes_left -= count; 521 522 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 523 template->src = buf; 524 else 525 template->dst = buf; 526 template->ccnt = count >> shift; 527 528 edma_write_slot(slot, template); 529 } 530 531 if (host->version == MMC_CTLR_VERSION_2) 532 edma_clear_event(channel); 533 534 edma_start(channel); 535 } 536 537 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 538 struct mmc_data *data) 539 { 540 int i; 541 int mask = rw_threshold - 1; 542 543 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 544 ((data->flags & MMC_DATA_WRITE) 545 ? DMA_TO_DEVICE 546 : DMA_FROM_DEVICE)); 547 548 /* no individual DMA segment should need a partial FIFO */ 549 for (i = 0; i < host->sg_len; i++) { 550 if (sg_dma_len(data->sg + i) & mask) { 551 dma_unmap_sg(mmc_dev(host->mmc), 552 data->sg, data->sg_len, 553 (data->flags & MMC_DATA_WRITE) 554 ? DMA_TO_DEVICE 555 : DMA_FROM_DEVICE); 556 return -1; 557 } 558 } 559 560 host->do_dma = 1; 561 mmc_davinci_send_dma_request(host, data); 562 563 return 0; 564 } 565 566 static void __init_or_module 567 davinci_release_dma_channels(struct mmc_davinci_host *host) 568 { 569 unsigned i; 570 571 if (!host->use_dma) 572 return; 573 574 for (i = 0; i < host->n_link; i++) 575 edma_free_slot(host->links[i]); 576 577 edma_free_channel(host->txdma); 578 edma_free_channel(host->rxdma); 579 } 580 581 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 582 { 583 u32 link_size; 584 int r, i; 585 586 /* Acquire master DMA write channel */ 587 r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, 588 EVENTQ_DEFAULT); 589 if (r < 0) { 590 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 591 "tx", r); 592 return r; 593 } 594 mmc_davinci_dma_setup(host, true, &host->tx_template); 595 596 /* Acquire master DMA read channel */ 597 r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, 598 EVENTQ_DEFAULT); 599 if (r < 0) { 600 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 601 "rx", r); 602 goto free_master_write; 603 } 604 mmc_davinci_dma_setup(host, false, &host->rx_template); 605 606 /* Allocate parameter RAM slots, which will later be bound to a 607 * channel as needed to handle a scatterlist. 608 */ 609 link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); 610 for (i = 0; i < link_size; i++) { 611 r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); 612 if (r < 0) { 613 dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n", 614 r); 615 break; 616 } 617 host->links[i] = r; 618 } 619 host->n_link = i; 620 621 return 0; 622 623 free_master_write: 624 edma_free_channel(host->txdma); 625 626 return r; 627 } 628 629 /*----------------------------------------------------------------------*/ 630 631 static void 632 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 633 { 634 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 635 int timeout; 636 struct mmc_data *data = req->data; 637 638 if (host->version == MMC_CTLR_VERSION_2) 639 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 640 641 host->data = data; 642 if (data == NULL) { 643 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 644 writel(0, host->base + DAVINCI_MMCBLEN); 645 writel(0, host->base + DAVINCI_MMCNBLK); 646 return; 647 } 648 649 dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", 650 (data->flags & MMC_DATA_STREAM) ? "stream" : "block", 651 (data->flags & MMC_DATA_WRITE) ? "write" : "read", 652 data->blocks, data->blksz); 653 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 654 data->timeout_clks, data->timeout_ns); 655 timeout = data->timeout_clks + 656 (data->timeout_ns / host->ns_in_one_cycle); 657 if (timeout > 0xffff) 658 timeout = 0xffff; 659 660 writel(timeout, host->base + DAVINCI_MMCTOD); 661 writel(data->blocks, host->base + DAVINCI_MMCNBLK); 662 writel(data->blksz, host->base + DAVINCI_MMCBLEN); 663 664 /* Configure the FIFO */ 665 switch (data->flags & MMC_DATA_WRITE) { 666 case MMC_DATA_WRITE: 667 host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 668 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 669 host->base + DAVINCI_MMCFIFOCTL); 670 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 671 host->base + DAVINCI_MMCFIFOCTL); 672 break; 673 674 default: 675 host->data_dir = DAVINCI_MMC_DATADIR_READ; 676 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 677 host->base + DAVINCI_MMCFIFOCTL); 678 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 679 host->base + DAVINCI_MMCFIFOCTL); 680 break; 681 } 682 683 host->buffer = NULL; 684 host->bytes_left = data->blocks * data->blksz; 685 686 /* For now we try to use DMA whenever we won't need partial FIFO 687 * reads or writes, either for the whole transfer (as tested here) 688 * or for any individual scatterlist segment (tested when we call 689 * start_dma_transfer). 690 * 691 * While we *could* change that, unusual block sizes are rarely 692 * used. The occasional fallback to PIO should't hurt. 693 */ 694 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 695 && mmc_davinci_start_dma_transfer(host, data) == 0) { 696 /* zero this to ensure we take no PIO paths */ 697 host->bytes_left = 0; 698 } else { 699 /* Revert to CPU Copy */ 700 host->sg_len = data->sg_len; 701 host->sg = host->data->sg; 702 mmc_davinci_sg_to_buf(host); 703 } 704 } 705 706 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 707 { 708 struct mmc_davinci_host *host = mmc_priv(mmc); 709 unsigned long timeout = jiffies + msecs_to_jiffies(900); 710 u32 mmcst1 = 0; 711 712 /* Card may still be sending BUSY after a previous operation, 713 * typically some kind of write. If so, we can't proceed yet. 714 */ 715 while (time_before(jiffies, timeout)) { 716 mmcst1 = readl(host->base + DAVINCI_MMCST1); 717 if (!(mmcst1 & MMCST1_BUSY)) 718 break; 719 cpu_relax(); 720 } 721 if (mmcst1 & MMCST1_BUSY) { 722 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 723 req->cmd->error = -ETIMEDOUT; 724 mmc_request_done(mmc, req); 725 return; 726 } 727 728 host->do_dma = 0; 729 mmc_davinci_prepare_data(host, req); 730 mmc_davinci_start_command(host, req->cmd); 731 } 732 733 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 734 unsigned int mmc_req_freq) 735 { 736 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 737 738 mmc_pclk = host->mmc_input_clk; 739 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 740 mmc_push_pull_divisor = ((unsigned int)mmc_pclk 741 / (2 * mmc_req_freq)) - 1; 742 else 743 mmc_push_pull_divisor = 0; 744 745 mmc_freq = (unsigned int)mmc_pclk 746 / (2 * (mmc_push_pull_divisor + 1)); 747 748 if (mmc_freq > mmc_req_freq) 749 mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 750 /* Convert ns to clock cycles */ 751 if (mmc_req_freq <= 400000) 752 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 753 / (2 * (mmc_push_pull_divisor + 1)))/1000)); 754 else 755 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 756 / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 757 758 return mmc_push_pull_divisor; 759 } 760 761 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 762 { 763 unsigned int open_drain_freq = 0, mmc_pclk = 0; 764 unsigned int mmc_push_pull_freq = 0; 765 struct mmc_davinci_host *host = mmc_priv(mmc); 766 767 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 768 u32 temp; 769 770 /* Ignoring the init clock value passed for fixing the inter 771 * operability with different cards. 772 */ 773 open_drain_freq = ((unsigned int)mmc_pclk 774 / (2 * MMCSD_INIT_CLOCK)) - 1; 775 776 if (open_drain_freq > 0xFF) 777 open_drain_freq = 0xFF; 778 779 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 780 temp |= open_drain_freq; 781 writel(temp, host->base + DAVINCI_MMCCLK); 782 783 /* Convert ns to clock cycles */ 784 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 785 } else { 786 u32 temp; 787 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 788 789 if (mmc_push_pull_freq > 0xFF) 790 mmc_push_pull_freq = 0xFF; 791 792 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 793 writel(temp, host->base + DAVINCI_MMCCLK); 794 795 udelay(10); 796 797 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 798 temp |= mmc_push_pull_freq; 799 writel(temp, host->base + DAVINCI_MMCCLK); 800 801 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 802 803 udelay(10); 804 } 805 } 806 807 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 808 { 809 struct mmc_davinci_host *host = mmc_priv(mmc); 810 struct platform_device *pdev = to_platform_device(mmc->parent); 811 struct davinci_mmc_config *config = pdev->dev.platform_data; 812 813 dev_dbg(mmc_dev(host->mmc), 814 "clock %dHz busmode %d powermode %d Vdd %04x\n", 815 ios->clock, ios->bus_mode, ios->power_mode, 816 ios->vdd); 817 818 switch (ios->power_mode) { 819 case MMC_POWER_OFF: 820 if (config && config->set_power) 821 config->set_power(pdev->id, false); 822 break; 823 case MMC_POWER_UP: 824 if (config && config->set_power) 825 config->set_power(pdev->id, true); 826 break; 827 } 828 829 switch (ios->bus_width) { 830 case MMC_BUS_WIDTH_8: 831 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 832 writel((readl(host->base + DAVINCI_MMCCTL) & 833 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 834 host->base + DAVINCI_MMCCTL); 835 break; 836 case MMC_BUS_WIDTH_4: 837 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 838 if (host->version == MMC_CTLR_VERSION_2) 839 writel((readl(host->base + DAVINCI_MMCCTL) & 840 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 841 host->base + DAVINCI_MMCCTL); 842 else 843 writel(readl(host->base + DAVINCI_MMCCTL) | 844 MMCCTL_WIDTH_4_BIT, 845 host->base + DAVINCI_MMCCTL); 846 break; 847 case MMC_BUS_WIDTH_1: 848 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 849 if (host->version == MMC_CTLR_VERSION_2) 850 writel(readl(host->base + DAVINCI_MMCCTL) & 851 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 852 host->base + DAVINCI_MMCCTL); 853 else 854 writel(readl(host->base + DAVINCI_MMCCTL) & 855 ~MMCCTL_WIDTH_4_BIT, 856 host->base + DAVINCI_MMCCTL); 857 break; 858 } 859 860 calculate_clk_divider(mmc, ios); 861 862 host->bus_mode = ios->bus_mode; 863 if (ios->power_mode == MMC_POWER_UP) { 864 unsigned long timeout = jiffies + msecs_to_jiffies(50); 865 bool lose = true; 866 867 /* Send clock cycles, poll completion */ 868 writel(0, host->base + DAVINCI_MMCARGHL); 869 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 870 while (time_before(jiffies, timeout)) { 871 u32 tmp = readl(host->base + DAVINCI_MMCST0); 872 873 if (tmp & MMCST0_RSPDNE) { 874 lose = false; 875 break; 876 } 877 cpu_relax(); 878 } 879 if (lose) 880 dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 881 } 882 883 /* FIXME on power OFF, reset things ... */ 884 } 885 886 static void 887 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 888 { 889 host->data = NULL; 890 891 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 892 /* 893 * SDIO Interrupt Detection work-around as suggested by 894 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 895 * 2.1.6): Signal SDIO interrupt only if it is enabled by core 896 */ 897 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 898 SDIOST0_DAT1_HI)) { 899 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 900 mmc_signal_sdio_irq(host->mmc); 901 } 902 } 903 904 if (host->do_dma) { 905 davinci_abort_dma(host); 906 907 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 908 (data->flags & MMC_DATA_WRITE) 909 ? DMA_TO_DEVICE 910 : DMA_FROM_DEVICE); 911 host->do_dma = false; 912 } 913 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 914 915 if (!data->stop || (host->cmd && host->cmd->error)) { 916 mmc_request_done(host->mmc, data->mrq); 917 writel(0, host->base + DAVINCI_MMCIM); 918 } else 919 mmc_davinci_start_command(host, data->stop); 920 } 921 922 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 923 struct mmc_command *cmd) 924 { 925 host->cmd = NULL; 926 927 if (cmd->flags & MMC_RSP_PRESENT) { 928 if (cmd->flags & MMC_RSP_136) { 929 /* response type 2 */ 930 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 931 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 932 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 933 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 934 } else { 935 /* response types 1, 1b, 3, 4, 5, 6 */ 936 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 937 } 938 } 939 940 if (host->data == NULL || cmd->error) { 941 if (cmd->error == -ETIMEDOUT) 942 cmd->mrq->cmd->retries = 0; 943 mmc_request_done(host->mmc, cmd->mrq); 944 writel(0, host->base + DAVINCI_MMCIM); 945 } 946 } 947 948 static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 949 int val) 950 { 951 u32 temp; 952 953 temp = readl(host->base + DAVINCI_MMCCTL); 954 if (val) /* reset */ 955 temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 956 else /* enable */ 957 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 958 959 writel(temp, host->base + DAVINCI_MMCCTL); 960 udelay(10); 961 } 962 963 static void 964 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 965 { 966 mmc_davinci_reset_ctrl(host, 1); 967 mmc_davinci_reset_ctrl(host, 0); 968 } 969 970 static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 971 { 972 struct mmc_davinci_host *host = dev_id; 973 unsigned int status; 974 975 status = readl(host->base + DAVINCI_SDIOIST); 976 if (status & SDIOIST_IOINT) { 977 dev_dbg(mmc_dev(host->mmc), 978 "SDIO interrupt status %x\n", status); 979 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 980 mmc_signal_sdio_irq(host->mmc); 981 } 982 return IRQ_HANDLED; 983 } 984 985 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 986 { 987 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 988 unsigned int status, qstatus; 989 int end_command = 0; 990 int end_transfer = 0; 991 struct mmc_data *data = host->data; 992 993 if (host->cmd == NULL && host->data == NULL) { 994 status = readl(host->base + DAVINCI_MMCST0); 995 dev_dbg(mmc_dev(host->mmc), 996 "Spurious interrupt 0x%04x\n", status); 997 /* Disable the interrupt from mmcsd */ 998 writel(0, host->base + DAVINCI_MMCIM); 999 return IRQ_NONE; 1000 } 1001 1002 status = readl(host->base + DAVINCI_MMCST0); 1003 qstatus = status; 1004 1005 /* handle FIFO first when using PIO for data. 1006 * bytes_left will decrease to zero as I/O progress and status will 1007 * read zero over iteration because this controller status 1008 * register(MMCST0) reports any status only once and it is cleared 1009 * by read. So, it is not unbouned loop even in the case of 1010 * non-dma. 1011 */ 1012 while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 1013 davinci_fifo_data_trans(host, rw_threshold); 1014 status = readl(host->base + DAVINCI_MMCST0); 1015 if (!status) 1016 break; 1017 qstatus |= status; 1018 } 1019 1020 if (qstatus & MMCST0_DATDNE) { 1021 /* All blocks sent/received, and CRC checks passed */ 1022 if (data != NULL) { 1023 if ((host->do_dma == 0) && (host->bytes_left > 0)) { 1024 /* if datasize < rw_threshold 1025 * no RX ints are generated 1026 */ 1027 davinci_fifo_data_trans(host, host->bytes_left); 1028 } 1029 end_transfer = 1; 1030 data->bytes_xfered = data->blocks * data->blksz; 1031 } else { 1032 dev_err(mmc_dev(host->mmc), 1033 "DATDNE with no host->data\n"); 1034 } 1035 } 1036 1037 if (qstatus & MMCST0_TOUTRD) { 1038 /* Read data timeout */ 1039 data->error = -ETIMEDOUT; 1040 end_transfer = 1; 1041 1042 dev_dbg(mmc_dev(host->mmc), 1043 "read data timeout, status %x\n", 1044 qstatus); 1045 1046 davinci_abort_data(host, data); 1047 } 1048 1049 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 1050 /* Data CRC error */ 1051 data->error = -EILSEQ; 1052 end_transfer = 1; 1053 1054 /* NOTE: this controller uses CRCWR to report both CRC 1055 * errors and timeouts (on writes). MMCDRSP values are 1056 * only weakly documented, but 0x9f was clearly a timeout 1057 * case and the two three-bit patterns in various SD specs 1058 * (101, 010) aren't part of it ... 1059 */ 1060 if (qstatus & MMCST0_CRCWR) { 1061 u32 temp = readb(host->base + DAVINCI_MMCDRSP); 1062 1063 if (temp == 0x9f) 1064 data->error = -ETIMEDOUT; 1065 } 1066 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 1067 (qstatus & MMCST0_CRCWR) ? "write" : "read", 1068 (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 1069 1070 davinci_abort_data(host, data); 1071 } 1072 1073 if (qstatus & MMCST0_TOUTRS) { 1074 /* Command timeout */ 1075 if (host->cmd) { 1076 dev_dbg(mmc_dev(host->mmc), 1077 "CMD%d timeout, status %x\n", 1078 host->cmd->opcode, qstatus); 1079 host->cmd->error = -ETIMEDOUT; 1080 if (data) { 1081 end_transfer = 1; 1082 davinci_abort_data(host, data); 1083 } else 1084 end_command = 1; 1085 } 1086 } 1087 1088 if (qstatus & MMCST0_CRCRS) { 1089 /* Command CRC error */ 1090 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1091 if (host->cmd) { 1092 host->cmd->error = -EILSEQ; 1093 end_command = 1; 1094 } 1095 } 1096 1097 if (qstatus & MMCST0_RSPDNE) { 1098 /* End of command phase */ 1099 end_command = (int) host->cmd; 1100 } 1101 1102 if (end_command) 1103 mmc_davinci_cmd_done(host, host->cmd); 1104 if (end_transfer) 1105 mmc_davinci_xfer_done(host, data); 1106 return IRQ_HANDLED; 1107 } 1108 1109 static int mmc_davinci_get_cd(struct mmc_host *mmc) 1110 { 1111 struct platform_device *pdev = to_platform_device(mmc->parent); 1112 struct davinci_mmc_config *config = pdev->dev.platform_data; 1113 1114 if (!config || !config->get_cd) 1115 return -ENOSYS; 1116 return config->get_cd(pdev->id); 1117 } 1118 1119 static int mmc_davinci_get_ro(struct mmc_host *mmc) 1120 { 1121 struct platform_device *pdev = to_platform_device(mmc->parent); 1122 struct davinci_mmc_config *config = pdev->dev.platform_data; 1123 1124 if (!config || !config->get_ro) 1125 return -ENOSYS; 1126 return config->get_ro(pdev->id); 1127 } 1128 1129 static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1130 { 1131 struct mmc_davinci_host *host = mmc_priv(mmc); 1132 1133 if (enable) { 1134 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1135 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1136 mmc_signal_sdio_irq(host->mmc); 1137 } else { 1138 host->sdio_int = true; 1139 writel(readl(host->base + DAVINCI_SDIOIEN) | 1140 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1141 } 1142 } else { 1143 host->sdio_int = false; 1144 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1145 host->base + DAVINCI_SDIOIEN); 1146 } 1147 } 1148 1149 static struct mmc_host_ops mmc_davinci_ops = { 1150 .request = mmc_davinci_request, 1151 .set_ios = mmc_davinci_set_ios, 1152 .get_cd = mmc_davinci_get_cd, 1153 .get_ro = mmc_davinci_get_ro, 1154 .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1155 }; 1156 1157 /*----------------------------------------------------------------------*/ 1158 1159 #ifdef CONFIG_CPU_FREQ 1160 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 1161 unsigned long val, void *data) 1162 { 1163 struct mmc_davinci_host *host; 1164 unsigned int mmc_pclk; 1165 struct mmc_host *mmc; 1166 unsigned long flags; 1167 1168 host = container_of(nb, struct mmc_davinci_host, freq_transition); 1169 mmc = host->mmc; 1170 mmc_pclk = clk_get_rate(host->clk); 1171 1172 if (val == CPUFREQ_POSTCHANGE) { 1173 spin_lock_irqsave(&mmc->lock, flags); 1174 host->mmc_input_clk = mmc_pclk; 1175 calculate_clk_divider(mmc, &mmc->ios); 1176 spin_unlock_irqrestore(&mmc->lock, flags); 1177 } 1178 1179 return 0; 1180 } 1181 1182 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1183 { 1184 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 1185 1186 return cpufreq_register_notifier(&host->freq_transition, 1187 CPUFREQ_TRANSITION_NOTIFIER); 1188 } 1189 1190 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1191 { 1192 cpufreq_unregister_notifier(&host->freq_transition, 1193 CPUFREQ_TRANSITION_NOTIFIER); 1194 } 1195 #else 1196 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1197 { 1198 return 0; 1199 } 1200 1201 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1202 { 1203 } 1204 #endif 1205 static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1206 { 1207 1208 mmc_davinci_reset_ctrl(host, 1); 1209 1210 writel(0, host->base + DAVINCI_MMCCLK); 1211 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1212 1213 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1214 writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1215 1216 mmc_davinci_reset_ctrl(host, 0); 1217 } 1218 1219 static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1220 { 1221 struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1222 struct mmc_davinci_host *host = NULL; 1223 struct mmc_host *mmc = NULL; 1224 struct resource *r, *mem = NULL; 1225 int ret = 0, irq = 0; 1226 size_t mem_size; 1227 1228 /* REVISIT: when we're fully converted, fail if pdata is NULL */ 1229 1230 ret = -ENODEV; 1231 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1232 irq = platform_get_irq(pdev, 0); 1233 if (!r || irq == NO_IRQ) 1234 goto out; 1235 1236 ret = -EBUSY; 1237 mem_size = resource_size(r); 1238 mem = request_mem_region(r->start, mem_size, pdev->name); 1239 if (!mem) 1240 goto out; 1241 1242 ret = -ENOMEM; 1243 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1244 if (!mmc) 1245 goto out; 1246 1247 host = mmc_priv(mmc); 1248 host->mmc = mmc; /* Important */ 1249 1250 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1251 if (!r) 1252 goto out; 1253 host->rxdma = r->start; 1254 1255 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1256 if (!r) 1257 goto out; 1258 host->txdma = r->start; 1259 1260 host->mem_res = mem; 1261 host->base = ioremap(mem->start, mem_size); 1262 if (!host->base) 1263 goto out; 1264 1265 ret = -ENXIO; 1266 host->clk = clk_get(&pdev->dev, "MMCSDCLK"); 1267 if (IS_ERR(host->clk)) { 1268 ret = PTR_ERR(host->clk); 1269 goto out; 1270 } 1271 clk_enable(host->clk); 1272 host->mmc_input_clk = clk_get_rate(host->clk); 1273 1274 init_mmcsd_host(host); 1275 1276 if (pdata->nr_sg) 1277 host->nr_sg = pdata->nr_sg - 1; 1278 1279 if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1280 host->nr_sg = MAX_NR_SG; 1281 1282 host->use_dma = use_dma; 1283 host->mmc_irq = irq; 1284 host->sdio_irq = platform_get_irq(pdev, 1); 1285 1286 if (host->use_dma && davinci_acquire_dma_channels(host) != 0) 1287 host->use_dma = 0; 1288 1289 /* REVISIT: someday, support IRQ-driven card detection. */ 1290 mmc->caps |= MMC_CAP_NEEDS_POLL; 1291 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1292 1293 if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1294 mmc->caps |= MMC_CAP_4_BIT_DATA; 1295 1296 if (pdata && (pdata->wires == 8)) 1297 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1298 1299 host->version = pdata->version; 1300 1301 mmc->ops = &mmc_davinci_ops; 1302 mmc->f_min = 312500; 1303 mmc->f_max = 25000000; 1304 if (pdata && pdata->max_freq) 1305 mmc->f_max = pdata->max_freq; 1306 if (pdata && pdata->caps) 1307 mmc->caps |= pdata->caps; 1308 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1309 1310 /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1311 * Each hw_seg uses one EDMA parameter RAM slot, always one 1312 * channel and then usually some linked slots. 1313 */ 1314 mmc->max_segs = 1 + host->n_link; 1315 1316 /* EDMA limit per hw segment (one or two MBytes) */ 1317 mmc->max_seg_size = MAX_CCNT * rw_threshold; 1318 1319 /* MMC/SD controller limits for multiblock requests */ 1320 mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1321 mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1322 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1323 1324 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1325 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1326 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1327 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1328 1329 platform_set_drvdata(pdev, host); 1330 1331 ret = mmc_davinci_cpufreq_register(host); 1332 if (ret) { 1333 dev_err(&pdev->dev, "failed to register cpufreq\n"); 1334 goto cpu_freq_fail; 1335 } 1336 1337 ret = mmc_add_host(mmc); 1338 if (ret < 0) 1339 goto out; 1340 1341 ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); 1342 if (ret) 1343 goto out; 1344 1345 if (host->sdio_irq >= 0) { 1346 ret = request_irq(host->sdio_irq, mmc_davinci_sdio_irq, 0, 1347 mmc_hostname(mmc), host); 1348 if (!ret) 1349 mmc->caps |= MMC_CAP_SDIO_IRQ; 1350 } 1351 1352 rename_region(mem, mmc_hostname(mmc)); 1353 1354 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1355 host->use_dma ? "DMA" : "PIO", 1356 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1357 1358 return 0; 1359 1360 out: 1361 mmc_davinci_cpufreq_deregister(host); 1362 cpu_freq_fail: 1363 if (host) { 1364 davinci_release_dma_channels(host); 1365 1366 if (host->clk) { 1367 clk_disable(host->clk); 1368 clk_put(host->clk); 1369 } 1370 1371 if (host->base) 1372 iounmap(host->base); 1373 } 1374 1375 if (mmc) 1376 mmc_free_host(mmc); 1377 1378 if (mem) 1379 release_resource(mem); 1380 1381 dev_dbg(&pdev->dev, "probe err %d\n", ret); 1382 1383 return ret; 1384 } 1385 1386 static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1387 { 1388 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1389 1390 platform_set_drvdata(pdev, NULL); 1391 if (host) { 1392 mmc_davinci_cpufreq_deregister(host); 1393 1394 mmc_remove_host(host->mmc); 1395 free_irq(host->mmc_irq, host); 1396 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 1397 free_irq(host->sdio_irq, host); 1398 1399 davinci_release_dma_channels(host); 1400 1401 clk_disable(host->clk); 1402 clk_put(host->clk); 1403 1404 iounmap(host->base); 1405 1406 release_resource(host->mem_res); 1407 1408 mmc_free_host(host->mmc); 1409 } 1410 1411 return 0; 1412 } 1413 1414 #ifdef CONFIG_PM 1415 static int davinci_mmcsd_suspend(struct device *dev) 1416 { 1417 struct platform_device *pdev = to_platform_device(dev); 1418 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1419 int ret; 1420 1421 mmc_host_enable(host->mmc); 1422 ret = mmc_suspend_host(host->mmc); 1423 if (!ret) { 1424 writel(0, host->base + DAVINCI_MMCIM); 1425 mmc_davinci_reset_ctrl(host, 1); 1426 mmc_host_disable(host->mmc); 1427 clk_disable(host->clk); 1428 host->suspended = 1; 1429 } else { 1430 host->suspended = 0; 1431 mmc_host_disable(host->mmc); 1432 } 1433 1434 return ret; 1435 } 1436 1437 static int davinci_mmcsd_resume(struct device *dev) 1438 { 1439 struct platform_device *pdev = to_platform_device(dev); 1440 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1441 int ret; 1442 1443 if (!host->suspended) 1444 return 0; 1445 1446 clk_enable(host->clk); 1447 mmc_host_enable(host->mmc); 1448 1449 mmc_davinci_reset_ctrl(host, 0); 1450 ret = mmc_resume_host(host->mmc); 1451 if (!ret) 1452 host->suspended = 0; 1453 1454 return ret; 1455 } 1456 1457 static const struct dev_pm_ops davinci_mmcsd_pm = { 1458 .suspend = davinci_mmcsd_suspend, 1459 .resume = davinci_mmcsd_resume, 1460 }; 1461 1462 #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1463 #else 1464 #define davinci_mmcsd_pm_ops NULL 1465 #endif 1466 1467 static struct platform_driver davinci_mmcsd_driver = { 1468 .driver = { 1469 .name = "davinci_mmc", 1470 .owner = THIS_MODULE, 1471 .pm = davinci_mmcsd_pm_ops, 1472 }, 1473 .remove = __exit_p(davinci_mmcsd_remove), 1474 }; 1475 1476 static int __init davinci_mmcsd_init(void) 1477 { 1478 return platform_driver_probe(&davinci_mmcsd_driver, 1479 davinci_mmcsd_probe); 1480 } 1481 module_init(davinci_mmcsd_init); 1482 1483 static void __exit davinci_mmcsd_exit(void) 1484 { 1485 platform_driver_unregister(&davinci_mmcsd_driver); 1486 } 1487 module_exit(davinci_mmcsd_exit); 1488 1489 MODULE_AUTHOR("Texas Instruments India"); 1490 MODULE_LICENSE("GPL"); 1491 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 1492 1493