1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CQHCI crypto engine (inline encryption) support 4 * 5 * Copyright 2020 Google LLC 6 */ 7 8 #include <linux/blk-crypto.h> 9 #include <linux/blk-crypto-profile.h> 10 #include <linux/mmc/host.h> 11 12 #include "cqhci-crypto.h" 13 14 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */ 15 static const struct cqhci_crypto_alg_entry { 16 enum cqhci_crypto_alg alg; 17 enum cqhci_crypto_key_size key_size; 18 } cqhci_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = { 19 [BLK_ENCRYPTION_MODE_AES_256_XTS] = { 20 .alg = CQHCI_CRYPTO_ALG_AES_XTS, 21 .key_size = CQHCI_CRYPTO_KEY_SIZE_256, 22 }, 23 }; 24 25 static inline struct cqhci_host * 26 cqhci_host_from_crypto_profile(struct blk_crypto_profile *profile) 27 { 28 return mmc_from_crypto_profile(profile)->cqe_private; 29 } 30 31 static void cqhci_crypto_program_key(struct cqhci_host *cq_host, 32 const union cqhci_crypto_cfg_entry *cfg, 33 int slot) 34 { 35 u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); 36 int i; 37 38 /* Clear CFGE */ 39 cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); 40 41 /* Write the key */ 42 for (i = 0; i < 16; i++) { 43 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]), 44 slot_offset + i * sizeof(cfg->reg_val[0])); 45 } 46 /* Write dword 17 */ 47 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]), 48 slot_offset + 17 * sizeof(cfg->reg_val[0])); 49 /* Write dword 16, which includes the new value of CFGE */ 50 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]), 51 slot_offset + 16 * sizeof(cfg->reg_val[0])); 52 } 53 54 static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile, 55 const struct blk_crypto_key *key, 56 unsigned int slot) 57 58 { 59 struct cqhci_host *cq_host = cqhci_host_from_crypto_profile(profile); 60 const union cqhci_crypto_cap_entry *ccap_array = 61 cq_host->crypto_cap_array; 62 const struct cqhci_crypto_alg_entry *alg = 63 &cqhci_crypto_algs[key->crypto_cfg.crypto_mode]; 64 u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512; 65 int i; 66 int cap_idx = -1; 67 union cqhci_crypto_cfg_entry cfg = {}; 68 69 BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0); 70 for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) { 71 if (ccap_array[i].algorithm_id == alg->alg && 72 ccap_array[i].key_size == alg->key_size && 73 (ccap_array[i].sdus_mask & data_unit_mask)) { 74 cap_idx = i; 75 break; 76 } 77 } 78 if (WARN_ON(cap_idx < 0)) 79 return -EOPNOTSUPP; 80 81 cfg.data_unit_size = data_unit_mask; 82 cfg.crypto_cap_idx = cap_idx; 83 cfg.config_enable = CQHCI_CRYPTO_CONFIGURATION_ENABLE; 84 85 if (ccap_array[cap_idx].algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS) { 86 /* In XTS mode, the blk_crypto_key's size is already doubled */ 87 memcpy(cfg.crypto_key, key->raw, key->size/2); 88 memcpy(cfg.crypto_key + CQHCI_CRYPTO_KEY_MAX_SIZE/2, 89 key->raw + key->size/2, key->size/2); 90 } else { 91 memcpy(cfg.crypto_key, key->raw, key->size); 92 } 93 94 cqhci_crypto_program_key(cq_host, &cfg, slot); 95 96 memzero_explicit(&cfg, sizeof(cfg)); 97 return 0; 98 } 99 100 static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot) 101 { 102 /* 103 * Clear the crypto cfg on the device. Clearing CFGE 104 * might not be sufficient, so just clear the entire cfg. 105 */ 106 union cqhci_crypto_cfg_entry cfg = {}; 107 108 cqhci_crypto_program_key(cq_host, &cfg, slot); 109 return 0; 110 } 111 112 static int cqhci_crypto_keyslot_evict(struct blk_crypto_profile *profile, 113 const struct blk_crypto_key *key, 114 unsigned int slot) 115 { 116 struct cqhci_host *cq_host = cqhci_host_from_crypto_profile(profile); 117 118 return cqhci_crypto_clear_keyslot(cq_host, slot); 119 } 120 121 /* 122 * The keyslot management operations for CQHCI crypto. 123 * 124 * Note that the block layer ensures that these are never called while the host 125 * controller is runtime-suspended. However, the CQE won't necessarily be 126 * "enabled" when these are called, i.e. CQHCI_ENABLE might not be set in the 127 * CQHCI_CFG register. But the hardware allows that. 128 */ 129 static const struct blk_crypto_ll_ops cqhci_crypto_ops = { 130 .keyslot_program = cqhci_crypto_keyslot_program, 131 .keyslot_evict = cqhci_crypto_keyslot_evict, 132 }; 133 134 static enum blk_crypto_mode_num 135 cqhci_find_blk_crypto_mode(union cqhci_crypto_cap_entry cap) 136 { 137 int i; 138 139 for (i = 0; i < ARRAY_SIZE(cqhci_crypto_algs); i++) { 140 BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0); 141 if (cqhci_crypto_algs[i].alg == cap.algorithm_id && 142 cqhci_crypto_algs[i].key_size == cap.key_size) 143 return i; 144 } 145 return BLK_ENCRYPTION_MODE_INVALID; 146 } 147 148 /** 149 * cqhci_crypto_init - initialize CQHCI crypto support 150 * @cq_host: a cqhci host 151 * 152 * If the driver previously set MMC_CAP2_CRYPTO and the CQE declares 153 * CQHCI_CAP_CS, initialize the crypto support. This involves reading the 154 * crypto capability registers, initializing the blk_crypto_profile, clearing 155 * all keyslots, and enabling 128-bit task descriptors. 156 * 157 * Return: 0 if crypto was initialized or isn't supported; whether 158 * MMC_CAP2_CRYPTO remains set indicates which one of those cases it is. 159 * Also can return a negative errno value on unexpected error. 160 */ 161 int cqhci_crypto_init(struct cqhci_host *cq_host) 162 { 163 struct mmc_host *mmc = cq_host->mmc; 164 struct device *dev = mmc_dev(mmc); 165 struct blk_crypto_profile *profile = &mmc->crypto_profile; 166 unsigned int cap_idx; 167 enum blk_crypto_mode_num blk_mode_num; 168 unsigned int slot; 169 int err = 0; 170 171 if (!(mmc->caps2 & MMC_CAP2_CRYPTO) || 172 !(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS)) 173 goto out; 174 175 if (cq_host->ops->uses_custom_crypto_profile) 176 goto profile_initialized; 177 178 cq_host->crypto_capabilities.reg_val = 179 cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP)); 180 181 cq_host->crypto_cfg_register = 182 (u32)cq_host->crypto_capabilities.config_array_ptr * 0x100; 183 184 cq_host->crypto_cap_array = 185 devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap, 186 sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL); 187 if (!cq_host->crypto_cap_array) { 188 err = -ENOMEM; 189 goto out; 190 } 191 192 /* 193 * CCAP.CFGC is off by one, so the actual number of crypto 194 * configurations (a.k.a. keyslots) is CCAP.CFGC + 1. 195 */ 196 err = devm_blk_crypto_profile_init( 197 dev, profile, cq_host->crypto_capabilities.config_count + 1); 198 if (err) 199 goto out; 200 201 profile->ll_ops = cqhci_crypto_ops; 202 profile->dev = dev; 203 204 /* Unfortunately, CQHCI crypto only supports 32 DUN bits. */ 205 profile->max_dun_bytes_supported = 4; 206 207 /* 208 * Cache all the crypto capabilities and advertise the supported crypto 209 * modes and data unit sizes to the block layer. 210 */ 211 for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap; 212 cap_idx++) { 213 cq_host->crypto_cap_array[cap_idx].reg_val = 214 cpu_to_le32(cqhci_readl(cq_host, 215 CQHCI_CRYPTOCAP + 216 cap_idx * sizeof(__le32))); 217 blk_mode_num = cqhci_find_blk_crypto_mode( 218 cq_host->crypto_cap_array[cap_idx]); 219 if (blk_mode_num == BLK_ENCRYPTION_MODE_INVALID) 220 continue; 221 profile->modes_supported[blk_mode_num] |= 222 cq_host->crypto_cap_array[cap_idx].sdus_mask * 512; 223 } 224 225 profile_initialized: 226 227 /* Clear all the keyslots so that we start in a known state. */ 228 for (slot = 0; slot < profile->num_slots; slot++) 229 profile->ll_ops.keyslot_evict(profile, NULL, slot); 230 231 /* CQHCI crypto requires the use of 128-bit task descriptors. */ 232 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 233 234 return 0; 235 236 out: 237 mmc->caps2 &= ~MMC_CAP2_CRYPTO; 238 return err; 239 } 240