1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Linaro Ltd 4 * Author: Ulf Hansson <ulf.hansson@linaro.org> 5 * 6 * Copyright (C) 2014 Intel Corp, All Rights Reserved. 7 * Author: Yi Sun <yi.y.sun@intel.com> 8 * 9 * Copyright (C) 2020 Genesys Logic, Inc. 10 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 11 * 12 * Copyright (C) 2020 Linaro Limited 13 * Author: AKASHI Takahiro <takahiro.akashi@linaro.org> 14 * 15 * Copyright (C) 2022 Genesys Logic, Inc. 16 * Authors: Jason Lai <jason.lai@genesyslogic.com.tw> 17 * 18 * Copyright (C) 2023 Genesys Logic, Inc. 19 * Authors: Victor Shih <victor.shih@genesyslogic.com.tw> 20 * 21 * Support for SD UHS-II cards 22 */ 23 #include <linux/err.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/sd.h> 30 #include <linux/mmc/sd_uhs2.h> 31 32 #include "card.h" 33 #include "core.h" 34 #include "bus.h" 35 #include "sd.h" 36 #include "sd_ops.h" 37 #include "mmc_ops.h" 38 39 #define UHS2_WAIT_CFG_COMPLETE_PERIOD_US (1 * 1000) 40 #define UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS 100 41 42 static const unsigned int sd_uhs2_freqs[] = { 52000000, 26000000 }; 43 44 struct sd_uhs2_wait_active_state_data { 45 struct mmc_host *host; 46 struct mmc_command *cmd; 47 }; 48 49 static int sd_uhs2_power_up(struct mmc_host *host) 50 { 51 if (host->ios.power_mode == MMC_POWER_ON) 52 return 0; 53 54 host->ios.vdd = fls(host->ocr_avail) - 1; 55 host->ios.clock = host->f_init; 56 host->ios.timing = MMC_TIMING_UHS2_SPEED_A; 57 host->ios.power_mode = MMC_POWER_ON; 58 59 return host->ops->uhs2_control(host, UHS2_SET_IOS); 60 } 61 62 static int sd_uhs2_power_off(struct mmc_host *host) 63 { 64 int err; 65 66 if (host->ios.power_mode == MMC_POWER_OFF) 67 return 0; 68 69 host->ios.vdd = 0; 70 host->ios.clock = 0; 71 host->ios.power_mode = MMC_POWER_OFF; 72 host->uhs2_sd_tran = false; 73 74 err = host->ops->uhs2_control(host, UHS2_SET_IOS); 75 if (err) 76 return err; 77 78 /* For consistency, let's restore the initial timing. */ 79 host->ios.timing = MMC_TIMING_LEGACY; 80 return 0; 81 } 82 83 /* 84 * Run the phy initialization sequence, which mainly relies on the UHS-II host 85 * to check that we reach the expected electrical state, between the host and 86 * the card. 87 */ 88 static int sd_uhs2_phy_init(struct mmc_host *host) 89 { 90 int err; 91 92 err = host->ops->uhs2_control(host, UHS2_PHY_INIT); 93 if (err) { 94 pr_err("%s: failed to initial phy for UHS-II!\n", 95 mmc_hostname(host)); 96 } 97 98 return err; 99 } 100 101 /* 102 * sd_uhs2_cmd_assemble() - build up UHS-II command packet which is embedded in 103 * mmc_command structure 104 * @cmd: MMC command to executed 105 * @uhs2_cmd: UHS2 command corresponded to MMC command 106 * @header: Header field of UHS-II command cxpacket 107 * @arg: Argument field of UHS-II command packet 108 * @payload: Payload field of UHS-II command packet 109 * @plen: Payload length 110 * @resp: Response buffer is allocated by caller and it is used to keep 111 * the response of CM-TRAN command. For SD-TRAN command, uhs2_resp 112 * should be null and SD-TRAN command response should be stored in 113 * resp of mmc_command. 114 * @resp_len: Response buffer length 115 * 116 * The uhs2_command structure contains message packets which are transmited/ 117 * received on UHS-II bus. This function fills in the contents of uhs2_command 118 * structure and embededs UHS2 command into mmc_command structure, which is used 119 * in legacy SD operation functions. 120 * 121 */ 122 static void sd_uhs2_cmd_assemble(struct mmc_command *cmd, 123 struct uhs2_command *uhs2_cmd, 124 u8 plen, u8 resp_len) 125 { 126 uhs2_cmd->payload_len = plen * sizeof(u32); 127 uhs2_cmd->packet_len = uhs2_cmd->payload_len + 4; 128 129 cmd->uhs2_cmd = uhs2_cmd; 130 cmd->uhs2_cmd->uhs2_resp_len = resp_len; 131 } 132 133 /* 134 * Do the early initialization of the card, by sending the device init broadcast 135 * command and wait for the process to be completed. 136 */ 137 static int sd_uhs2_dev_init(struct mmc_host *host) 138 { 139 struct mmc_command cmd = {0}; 140 struct uhs2_command uhs2_cmd = {}; 141 u32 cnt; 142 u32 dap, gap, resp_gap; 143 u32 payload0; 144 u8 gd = 0; 145 int err; 146 147 dap = host->uhs2_caps.dap; 148 gap = host->uhs2_caps.gap; 149 150 /* 151 * Refer to UHS-II Addendum Version 1.02 Figure 6-21 to see DEVICE_INIT CCMD format. 152 * Head: 153 * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). 154 * - IOADR = CMD_BASE + 002h 155 * Payload: 156 * - bit [3:0] : GAP(Group Allocated Power) 157 * - bit [7:4] : GD(Group Descriptor) 158 * - bit [11] : Complete Flag 159 * - bit [15:12]: DAP(Device Allocated Power) 160 */ 161 uhs2_cmd.header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; 162 uhs2_cmd.arg = ((UHS2_DEV_CMD_DEVICE_INIT & 0xFF) << 8) | 163 UHS2_NATIVE_CMD_WRITE | 164 UHS2_NATIVE_CMD_PLEN_4B | 165 (UHS2_DEV_CMD_DEVICE_INIT >> 8); 166 167 /* 168 * Refer to UHS-II Addendum Version 1.02 section 6.3.1. 169 * Max. time from DEVICE_INIT CCMD EOP reception on Device 170 * Rx to its SOP transmission on Device Tx(Tfwd_init_cmd) is 171 * 1 second. 172 */ 173 cmd.busy_timeout = 1000; 174 175 /* 176 * Refer to UHS-II Addendum Version 1.02 section 6.2.6.3. 177 * Let's retry the DEVICE_INIT command no more than 30 times. 178 */ 179 for (cnt = 0; cnt < 30; cnt++) { 180 payload0 = ((dap & 0xF) << 12) | 181 UHS2_DEV_INIT_COMPLETE_FLAG | 182 ((gd & 0xF) << 4) | 183 (gap & 0xF); 184 uhs2_cmd.payload[0] = (__force __be32)payload0; 185 186 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_DEV_INIT_PAYLOAD_LEN, 187 UHS2_DEV_INIT_RESP_LEN); 188 189 err = mmc_wait_for_cmd(host, &cmd, 0); 190 191 if (err) { 192 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 193 mmc_hostname(host), __func__, err); 194 continue; 195 } 196 197 if (uhs2_cmd.uhs2_resp[3] != (UHS2_DEV_CMD_DEVICE_INIT & 0xFF)) { 198 pr_err("%s: DEVICE_INIT response is wrong!\n", 199 mmc_hostname(host)); 200 return -EIO; 201 } 202 203 if (uhs2_cmd.uhs2_resp[5] & 0x8) { 204 host->uhs2_caps.group_desc = gd; 205 return 0; 206 } 207 resp_gap = uhs2_cmd.uhs2_resp[4] & 0x0F; 208 if (gap == resp_gap) 209 gd++; 210 } 211 212 if (err) { 213 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 214 mmc_hostname(host), __func__, err); 215 return err; 216 } 217 218 return 0; 219 } 220 221 /* 222 * Run the enumeration process by sending the enumerate command to the card. 223 * Note that, we currently support only the point to point connection, which 224 * means only one card can be attached per host/slot. 225 */ 226 static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) 227 { 228 struct mmc_command cmd = {0}; 229 struct uhs2_command uhs2_cmd = {}; 230 u32 payload0; 231 u8 id_f = 0xF, id_l = 0x0; 232 int err; 233 234 /* 235 * Refer to UHS-II Addendum Version 1.02 Figure 6-28 to see ENUMERATE CCMD format. 236 * Header: 237 * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). 238 * - IOADR = CMD_BASE + 003h 239 * Payload: 240 * - bit [3:0]: ID_L(Last Node ID) 241 * - bit [7:4]: ID_F(First Node ID) 242 */ 243 uhs2_cmd.header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; 244 uhs2_cmd.arg = ((UHS2_DEV_CMD_ENUMERATE & 0xFF) << 8) | 245 UHS2_NATIVE_CMD_WRITE | 246 UHS2_NATIVE_CMD_PLEN_4B | 247 (UHS2_DEV_CMD_ENUMERATE >> 8); 248 249 payload0 = (id_f << 4) | id_l; 250 uhs2_cmd.payload[0] = cpu_to_be32(payload0); 251 252 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_DEV_ENUM_PAYLOAD_LEN, UHS2_DEV_ENUM_RESP_LEN); 253 254 err = mmc_wait_for_cmd(host, &cmd, 0); 255 if (err) { 256 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 257 mmc_hostname(host), __func__, err); 258 return err; 259 } 260 261 if (uhs2_cmd.uhs2_resp[3] != (UHS2_DEV_CMD_ENUMERATE & 0xFF)) { 262 pr_err("%s: ENUMERATE response is wrong!\n", 263 mmc_hostname(host)); 264 return -EIO; 265 } 266 267 id_f = (uhs2_cmd.uhs2_resp[4] >> 4) & 0xF; 268 id_l = uhs2_cmd.uhs2_resp[4] & 0xF; 269 *node_id = id_f; 270 271 return 0; 272 } 273 274 /* 275 * Read the UHS-II configuration registers (CFG_REG) of the card, by sending it 276 * commands and by parsing the responses. Store a copy of the relevant data in 277 * card->uhs2_config. 278 */ 279 static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *card) 280 { 281 struct mmc_command cmd = {0}; 282 struct uhs2_command uhs2_cmd = {}; 283 u32 cap; 284 int err; 285 286 /* 287 * Use Control Read CCMD to read Generic Capability from Configuration Register. 288 * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). 289 * - IOADR = Generic Capability Register(CFG_BASE + 000h) 290 */ 291 uhs2_cmd.header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uhs2_config.node_id; 292 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_GEN_CAPS & 0xFF) << 8) | 293 UHS2_NATIVE_CMD_READ | 294 UHS2_NATIVE_CMD_PLEN_4B | 295 (UHS2_DEV_CONFIG_GEN_CAPS >> 8); 296 297 /* 298 * There is no payload because per spec, there should be 299 * no payload field for read CCMD. 300 * Plen is set in arg. Per spec, plen for read CCMD 301 * represents the len of read data which is assigned in payload 302 * of following RES (p136). 303 */ 304 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); 305 306 err = mmc_wait_for_cmd(host, &cmd, 0); 307 if (err) { 308 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 309 mmc_hostname(host), __func__, err); 310 return err; 311 } 312 313 /* 314 * Generic Capability Register: 315 * bit [7:0] : Reserved 316 * bit [13:8] : Device-Specific Number of Lanes and Functionality 317 * bit 8: 2L-HD 318 * bit 9: 2D-1U FD 319 * bit 10: 1D-2U FD 320 * bit 11: 2D-2U FD 321 * Others: Reserved 322 * bit [14] : DADR Length 323 * 0: 4 bytes 324 * 1: Reserved 325 * bit [23:16]: Application Type 326 * bit 16: 0=Non-SD memory, 1=SD memory 327 * bit 17: 0=Non-SDIO, 1=SDIO 328 * bit 18: 0=Card, 1=Embedded 329 * bit [63:24]: Reserved 330 */ 331 cap = cmd.resp[0]; 332 card->uhs2_config.n_lanes = 333 (cap >> UHS2_DEV_CONFIG_N_LANES_POS) & 334 UHS2_DEV_CONFIG_N_LANES_MASK; 335 card->uhs2_config.dadr_len = 336 (cap >> UHS2_DEV_CONFIG_DADR_POS) & 337 UHS2_DEV_CONFIG_DADR_MASK; 338 card->uhs2_config.app_type = 339 (cap >> UHS2_DEV_CONFIG_APP_POS) & 340 UHS2_DEV_CONFIG_APP_MASK; 341 342 /* 343 * Use Control Read CCMD to read PHY Capability from Configuration Register. 344 * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). 345 * - IOADR = PHY Capability Register(CFG_BASE + 002h) 346 */ 347 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_PHY_CAPS & 0xFF) << 8) | 348 UHS2_NATIVE_CMD_READ | 349 UHS2_NATIVE_CMD_PLEN_8B | 350 (UHS2_DEV_CONFIG_PHY_CAPS >> 8); 351 352 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); 353 354 err = mmc_wait_for_cmd(host, &cmd, 0); 355 if (err) { 356 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 357 mmc_hostname(host), __func__, err); 358 return err; 359 } 360 361 /* 362 * PHY Capability Register: 363 * bit [3:0] : PHY Minor Revision 364 * bit [5:4] : PHY Major Revision 365 * bit [15] : Support Hibernate Mode 366 * 0: Not support Hibernate Mode 367 * 1: Support Hibernate Mode 368 * bit [31:16]: Reserved 369 * bit [35:32]: Device-Specific N_LSS_SYN 370 * bit [39:36]: Device-Specific N_LSS_DIR 371 * bit [63:40]: Reserved 372 */ 373 cap = cmd.resp[0]; 374 card->uhs2_config.phy_minor_rev = 375 cap & UHS2_DEV_CONFIG_PHY_MINOR_MASK; 376 card->uhs2_config.phy_major_rev = 377 (cap >> UHS2_DEV_CONFIG_PHY_MAJOR_POS) & 378 UHS2_DEV_CONFIG_PHY_MAJOR_MASK; 379 card->uhs2_config.can_hibernate = 380 (cap >> UHS2_DEV_CONFIG_CAN_HIBER_POS) & 381 UHS2_DEV_CONFIG_CAN_HIBER_MASK; 382 383 cap = cmd.resp[1]; 384 card->uhs2_config.n_lss_sync = 385 cap & UHS2_DEV_CONFIG_N_LSS_SYN_MASK; 386 card->uhs2_config.n_lss_dir = 387 (cap >> UHS2_DEV_CONFIG_N_LSS_DIR_POS) & 388 UHS2_DEV_CONFIG_N_LSS_DIR_MASK; 389 if (card->uhs2_config.n_lss_sync == 0) 390 card->uhs2_config.n_lss_sync = 16 << 2; 391 else 392 card->uhs2_config.n_lss_sync <<= 2; 393 394 if (card->uhs2_config.n_lss_dir == 0) 395 card->uhs2_config.n_lss_dir = 16 << 3; 396 else 397 card->uhs2_config.n_lss_dir <<= 3; 398 399 /* 400 * Use Control Read CCMD to read LINK/TRAN Capability from Configuration Register. 401 * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). 402 * - IOADR = LINK/TRAN Capability Register(CFG_BASE + 004h) 403 */ 404 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_LINK_TRAN_CAPS & 0xFF) << 8) | 405 UHS2_NATIVE_CMD_READ | 406 UHS2_NATIVE_CMD_PLEN_8B | 407 (UHS2_DEV_CONFIG_LINK_TRAN_CAPS >> 8); 408 409 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); 410 411 err = mmc_wait_for_cmd(host, &cmd, 0); 412 if (err) { 413 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 414 mmc_hostname(host), __func__, err); 415 return err; 416 } 417 418 /* 419 * LINK/TRAN Capability Register: 420 * bit [3:0] : LINK_TRAN Minor Revision 421 * bit [5:4] : LINK/TRAN Major Revision 422 * bit [7:6] : Reserved 423 * bit [15:8] : Device-Specific N_FCU 424 * bit [18:16]: Device Type 425 * 001b=Host 426 * 010b=Device 427 * 011b=Reserved for CMD issuable Device 428 * bit [19] : Reserved 429 * bit [31:20]: Device-Specific MAX_BLKLEN 430 * bit [39:32]: Device-Specific N_DATA_GAP 431 * bit [63:40]: Reserved 432 */ 433 cap = cmd.resp[0]; 434 card->uhs2_config.link_minor_rev = 435 cap & UHS2_DEV_CONFIG_LT_MINOR_MASK; 436 card->uhs2_config.link_major_rev = 437 (cap >> UHS2_DEV_CONFIG_LT_MAJOR_POS) & 438 UHS2_DEV_CONFIG_LT_MAJOR_MASK; 439 card->uhs2_config.n_fcu = 440 (cap >> UHS2_DEV_CONFIG_N_FCU_POS) & 441 UHS2_DEV_CONFIG_N_FCU_MASK; 442 card->uhs2_config.dev_type = 443 (cap >> UHS2_DEV_CONFIG_DEV_TYPE_POS) & 444 UHS2_DEV_CONFIG_DEV_TYPE_MASK; 445 card->uhs2_config.maxblk_len = 446 (cap >> UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) & 447 UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK; 448 449 cap = cmd.resp[1]; 450 card->uhs2_config.n_data_gap = 451 cap & UHS2_DEV_CONFIG_N_DATA_GAP_MASK; 452 if (card->uhs2_config.n_fcu == 0) 453 card->uhs2_config.n_fcu = 256; 454 455 return 0; 456 } 457 458 /* 459 * Based on the card's and host's UHS-II capabilities, let's update the 460 * configuration of the card and the host. This may also include to move to a 461 * greater speed range/mode. Depending on the updated configuration, we may need 462 * to do a soft reset of the card via sending it a GO_DORMANT_STATE command. 463 * 464 * In the final step, let's check if the card signals "config completion", which 465 * indicates that the card has moved from config state into active state. 466 */ 467 static int sd_uhs2_config_write(struct mmc_host *host, struct mmc_card *card) 468 { 469 struct mmc_command cmd = {0}; 470 struct uhs2_command uhs2_cmd = {}; 471 u32 payload0, payload1; 472 u8 nMinDataGap; 473 int err; 474 475 /* 476 * Use Control Write CCMD to set Generic Setting in Configuration Register. 477 * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). 478 * - IOADR = Generic Setting Register(CFG_BASE + 008h) 479 * - Payload = New contents to be written to Generic Setting Register 480 */ 481 uhs2_cmd.header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uhs2_config.node_id; 482 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | 483 UHS2_NATIVE_CMD_WRITE | 484 UHS2_NATIVE_CMD_PLEN_8B | 485 (UHS2_DEV_CONFIG_GEN_SET >> 8); 486 487 /* 488 * Most UHS-II cards only support FD and 2L-HD mode. Other lane numbers 489 * defined in UHS-II addendem Ver1.01 are optional. 490 */ 491 host->uhs2_caps.n_lanes_set = UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; 492 card->uhs2_config.n_lanes_set = UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; 493 494 payload0 = card->uhs2_config.n_lanes_set << UHS2_DEV_CONFIG_N_LANES_POS; 495 payload1 = 0; 496 uhs2_cmd.payload[0] = cpu_to_be32(payload0); 497 uhs2_cmd.payload[1] = cpu_to_be32(payload1); 498 499 /* 500 * There is no payload because per spec, there should be 501 * no payload field for read CCMD. 502 * Plen is set in arg. Per spec, plen for read CCMD 503 * represents the len of read data which is assigned in payload 504 * of following RES (p136). 505 */ 506 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, 0); 507 508 err = mmc_wait_for_cmd(host, &cmd, 0); 509 if (err) { 510 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 511 mmc_hostname(host), __func__, err); 512 return err; 513 } 514 515 /* 516 * Use Control Write CCMD to set PHY Setting in Configuration Register. 517 * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). 518 * - IOADR = PHY Setting Register(CFG_BASE + 00Ah) 519 * - Payload = New contents to be written to PHY Setting Register 520 */ 521 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_PHY_SET & 0xFF) << 8) | 522 UHS2_NATIVE_CMD_WRITE | 523 UHS2_NATIVE_CMD_PLEN_8B | 524 (UHS2_DEV_CONFIG_PHY_SET >> 8); 525 526 if (host->uhs2_caps.speed_range == UHS2_DEV_CONFIG_PHY_SET_SPEED_B) { 527 if (card->uhs2_config.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD && 528 host->uhs2_caps.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD) { 529 /* Support HD */ 530 host->ios.timing = MMC_TIMING_UHS2_SPEED_B_HD; 531 nMinDataGap = 1; 532 } else { 533 /* Only support 2L-FD so far */ 534 host->ios.timing = MMC_TIMING_UHS2_SPEED_B; 535 nMinDataGap = 3; 536 } 537 card->uhs2_config.speed_range_set = UHS2_DEV_CONFIG_PHY_SET_SPEED_B; 538 } else { 539 if (card->uhs2_config.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD && 540 host->uhs2_caps.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD) { 541 /* Support HD */ 542 host->ios.timing = MMC_TIMING_UHS2_SPEED_A_HD; 543 nMinDataGap = 1; 544 } else { 545 /* Only support 2L-FD so far */ 546 host->ios.timing = MMC_TIMING_UHS2_SPEED_A; 547 nMinDataGap = 3; 548 } 549 card->uhs2_config.speed_range_set = UHS2_DEV_CONFIG_PHY_SET_SPEED_A; 550 } 551 552 payload0 = card->uhs2_config.speed_range_set << UHS2_DEV_CONFIG_PHY_SET_SPEED_POS; 553 554 card->uhs2_config.n_lss_sync_set = (max(card->uhs2_config.n_lss_sync, 555 host->uhs2_caps.n_lss_sync) >> 2) & 556 UHS2_DEV_CONFIG_N_LSS_SYN_MASK; 557 host->uhs2_caps.n_lss_sync_set = card->uhs2_config.n_lss_sync_set; 558 559 card->uhs2_config.n_lss_dir_set = (max(card->uhs2_config.n_lss_dir, 560 host->uhs2_caps.n_lss_dir) >> 3) & 561 UHS2_DEV_CONFIG_N_LSS_DIR_MASK; 562 host->uhs2_caps.n_lss_dir_set = card->uhs2_config.n_lss_dir_set; 563 564 payload1 = (card->uhs2_config.n_lss_dir_set << UHS2_DEV_CONFIG_N_LSS_DIR_POS) | 565 card->uhs2_config.n_lss_sync_set; 566 uhs2_cmd.payload[0] = cpu_to_be32(payload0); 567 uhs2_cmd.payload[1] = cpu_to_be32(payload1); 568 569 memset(uhs2_cmd.uhs2_resp, 0, sizeof(uhs2_cmd.uhs2_resp)); 570 571 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, 572 UHS2_CFG_WRITE_PHY_SET_RESP_LEN); 573 574 err = mmc_wait_for_cmd(host, &cmd, 0); 575 if (err) { 576 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 577 mmc_hostname(host), __func__, err); 578 return err; 579 } 580 581 if ((uhs2_cmd.uhs2_resp[2] & 0x80)) { 582 pr_err("%s: %s: UHS2 CMD not accepted, resp= 0x%x!\n", 583 mmc_hostname(host), __func__, uhs2_cmd.uhs2_resp[2]); 584 return -EIO; 585 } 586 587 /* 588 * Use Control Write CCMD to set LINK/TRAN Setting in Configuration Register. 589 * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). 590 * - IOADR = LINK/TRAN Setting Register(CFG_BASE + 00Ch) 591 * - Payload = New contents to be written to LINK/TRAN Setting Register 592 */ 593 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_LINK_TRAN_SET & 0xFF) << 8) | 594 UHS2_NATIVE_CMD_WRITE | 595 UHS2_NATIVE_CMD_PLEN_8B | 596 (UHS2_DEV_CONFIG_LINK_TRAN_SET >> 8); 597 598 if (card->uhs2_config.app_type == UHS2_DEV_CONFIG_APP_SD_MEM) 599 card->uhs2_config.maxblk_len_set = UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN; 600 else 601 card->uhs2_config.maxblk_len_set = min(card->uhs2_config.maxblk_len, 602 host->uhs2_caps.maxblk_len); 603 host->uhs2_caps.maxblk_len_set = card->uhs2_config.maxblk_len_set; 604 605 card->uhs2_config.n_fcu_set = min(card->uhs2_config.n_fcu, host->uhs2_caps.n_fcu); 606 host->uhs2_caps.n_fcu_set = card->uhs2_config.n_fcu_set; 607 608 card->uhs2_config.n_data_gap_set = max(nMinDataGap, card->uhs2_config.n_data_gap); 609 host->uhs2_caps.n_data_gap_set = card->uhs2_config.n_data_gap_set; 610 611 host->uhs2_caps.max_retry_set = 3; 612 card->uhs2_config.max_retry_set = host->uhs2_caps.max_retry_set; 613 614 payload0 = (card->uhs2_config.maxblk_len_set << UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) | 615 (card->uhs2_config.max_retry_set << UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_POS) | 616 (card->uhs2_config.n_fcu_set << UHS2_DEV_CONFIG_N_FCU_POS); 617 payload1 = card->uhs2_config.n_data_gap_set; 618 uhs2_cmd.payload[0] = cpu_to_be32(payload0); 619 uhs2_cmd.payload[1] = cpu_to_be32(payload1); 620 621 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, 0); 622 623 err = mmc_wait_for_cmd(host, &cmd, 0); 624 if (err) { 625 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 626 mmc_hostname(host), __func__, err); 627 return err; 628 } 629 630 /* 631 * Use Control Write CCMD to set Config Completion(payload bit 63) in Generic Setting 632 * Register. 633 * Header: 634 * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). 635 * - IOADR = PGeneric Setting Register(CFG_BASE + 008h) 636 * Payload: 637 * - bit [63]: Config Completion 638 * 639 * DLSM transits to Active state immediately when Config Completion is set to 1. 640 */ 641 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | 642 UHS2_NATIVE_CMD_WRITE | 643 UHS2_NATIVE_CMD_PLEN_8B | 644 (UHS2_DEV_CONFIG_GEN_SET >> 8); 645 646 payload0 = 0; 647 payload1 = UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE; 648 uhs2_cmd.payload[0] = cpu_to_be32(payload0); 649 uhs2_cmd.payload[1] = cpu_to_be32(payload1); 650 651 memset(uhs2_cmd.uhs2_resp, 0, sizeof(uhs2_cmd.uhs2_resp)); 652 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, 653 UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN); 654 655 err = mmc_wait_for_cmd(host, &cmd, 0); 656 if (err) { 657 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 658 mmc_hostname(host), __func__, err); 659 return err; 660 } 661 662 /* Set host Config Setting registers */ 663 err = host->ops->uhs2_control(host, UHS2_SET_CONFIG); 664 if (err) { 665 pr_err("%s: %s: UHS2 SET_CONFIG fail!\n", mmc_hostname(host), __func__); 666 return err; 667 } 668 669 return 0; 670 } 671 672 static int sd_uhs2_go_dormant(struct mmc_host *host, u32 node_id) 673 { 674 struct mmc_command cmd = {0}; 675 struct uhs2_command uhs2_cmd = {}; 676 int err; 677 678 /* Disable Normal INT */ 679 err = host->ops->uhs2_control(host, UHS2_DISABLE_INT); 680 if (err) { 681 pr_err("%s: %s: UHS2 DISABLE_INT fail!\n", 682 mmc_hostname(host), __func__); 683 return err; 684 } 685 686 /* 687 * Refer to UHS-II Addendum Version 1.02 Figure 6-17 to see GO_DORMANT_STATE CCMD format. 688 * Header: 689 * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). 690 * - IOADR = CMD_BASE + 001h 691 * Payload: 692 * - bit [7]: HBR(Entry to Hibernate Mode) 693 * 1: Host intends to enter Hibernate mode during Dormant state. 694 * The default setting is 0 because hibernate is currently not supported. 695 */ 696 uhs2_cmd.header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; 697 uhs2_cmd.arg = ((UHS2_DEV_CMD_GO_DORMANT_STATE & 0xFF) << 8) | 698 UHS2_NATIVE_CMD_WRITE | 699 UHS2_NATIVE_CMD_PLEN_4B | 700 (UHS2_DEV_CMD_GO_DORMANT_STATE >> 8); 701 702 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_GO_DORMANT_PAYLOAD_LEN, 0); 703 704 err = mmc_wait_for_cmd(host, &cmd, 0); 705 if (err) { 706 pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", 707 mmc_hostname(host), __func__, err); 708 return err; 709 } 710 711 /* Check Dormant State in Present */ 712 err = host->ops->uhs2_control(host, UHS2_CHECK_DORMANT); 713 if (err) 714 return err; 715 716 /* Disable UHS2 card clock */ 717 err = host->ops->uhs2_control(host, UHS2_DISABLE_CLK); 718 if (err) 719 return err; 720 721 /* Restore sd clock */ 722 mmc_delay(5); 723 err = host->ops->uhs2_control(host, UHS2_ENABLE_CLK); 724 if (err) 725 return err; 726 727 /* Enable Normal INT */ 728 err = host->ops->uhs2_control(host, UHS2_ENABLE_INT); 729 if (err) 730 return err; 731 732 /* Detect UHS2 */ 733 err = host->ops->uhs2_control(host, UHS2_PHY_INIT); 734 if (err) 735 return err; 736 737 return 0; 738 } 739 740 static int sd_uhs2_wait_active_state_cb(void *cb_data, bool *busy) 741 { 742 struct sd_uhs2_wait_active_state_data *data = cb_data; 743 struct mmc_host *host = data->host; 744 struct mmc_command *cmd = data->cmd; 745 int err; 746 747 err = mmc_wait_for_cmd(host, cmd, 0); 748 if (err) 749 return err; 750 751 if (cmd->resp[1] & UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE) 752 *busy = false; 753 else 754 *busy = true; 755 756 return 0; 757 } 758 759 static int sd_uhs2_go_dormant_state(struct mmc_host *host, u32 node_id) 760 { 761 struct mmc_command cmd = {0}; 762 struct uhs2_command uhs2_cmd = {}; 763 int err; 764 struct sd_uhs2_wait_active_state_data cb_data = { 765 .host = host, 766 .cmd = &cmd 767 }; 768 769 err = sd_uhs2_go_dormant(host, node_id); 770 if (err) { 771 pr_err("%s: %s: UHS2 GO_DORMANT_STATE fail, err= 0x%x!\n", 772 mmc_hostname(host), __func__, err); 773 return err; 774 } 775 776 /* 777 * Use Control Read CCMD to check Config Completion(bit 63) in Generic Setting Register. 778 * - Control Read(R/W=0) with 8-Byte payload(PLEN=10b). 779 * - IOADR = Generic Setting Register(CFG_BASE + 008h) 780 * 781 * When UHS-II card been switched to new speed mode, it will set Config Completion to 1. 782 */ 783 uhs2_cmd.header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; 784 uhs2_cmd.arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | 785 UHS2_NATIVE_CMD_READ | 786 UHS2_NATIVE_CMD_PLEN_8B | 787 (UHS2_DEV_CONFIG_GEN_SET >> 8); 788 789 sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); 790 err = __mmc_poll_for_busy(host, UHS2_WAIT_CFG_COMPLETE_PERIOD_US, 791 UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS, 792 &sd_uhs2_wait_active_state_cb, &cb_data); 793 if (err) { 794 pr_err("%s: %s: Not switch to Active in 100 ms\n", mmc_hostname(host), __func__); 795 return err; 796 } 797 798 return 0; 799 } 800 801 /* 802 * Allocate the data structure for the mmc_card and run the UHS-II specific 803 * initialization sequence. 804 */ 805 static int sd_uhs2_init_card(struct mmc_host *host, struct mmc_card *oldcard) 806 { 807 struct mmc_card *card; 808 u32 node_id = 0; 809 int err; 810 811 err = sd_uhs2_dev_init(host); 812 if (err) 813 return err; 814 815 err = sd_uhs2_enum(host, &node_id); 816 if (err) 817 return err; 818 819 if (oldcard) { 820 card = oldcard; 821 } else { 822 card = mmc_alloc_card(host, &sd_type); 823 if (IS_ERR(card)) 824 return PTR_ERR(card); 825 } 826 827 card->uhs2_config.node_id = node_id; 828 card->type = MMC_TYPE_SD; 829 830 err = sd_uhs2_config_read(host, card); 831 if (err) 832 goto err; 833 834 err = sd_uhs2_config_write(host, card); 835 if (err) 836 goto err; 837 838 /* If change speed to Range B, need to GO_DORMANT_STATE */ 839 if (host->ios.timing == MMC_TIMING_UHS2_SPEED_B || 840 host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD) { 841 err = sd_uhs2_go_dormant_state(host, node_id); 842 if (err) 843 goto err; 844 } 845 846 host->uhs2_sd_tran = true; 847 host->card = card; 848 return 0; 849 850 err: 851 if (!oldcard) 852 mmc_remove_card(card); 853 return err; 854 } 855 856 /* 857 * Initialize the UHS-II card through the SD-TRAN transport layer. This enables 858 * commands/requests to be backwards compatible through the legacy SD protocol. 859 * UHS-II cards has a specific power limit specified for VDD1/VDD2, that should 860 * be set through a legacy CMD6. Note that, the power limit that becomes set, 861 * survives a soft reset through the GO_DORMANT_STATE command. 862 */ 863 static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *card, 864 bool reinit) 865 { 866 int err; 867 u32 cid[4]; 868 u32 ocr; 869 u32 rocr; 870 u8 *status; 871 int ro; 872 873 /* Send CMD0 to reset SD card */ 874 err = __mmc_go_idle(host); 875 if (err) 876 return err; 877 878 mmc_delay(1); 879 880 /* Send CMD8 to communicate SD interface operation condition */ 881 err = mmc_send_if_cond(host, host->ocr_avail); 882 if (err) 883 return err; 884 885 /* 886 * Probe SD card working voltage. 887 */ 888 err = mmc_send_app_op_cond(host, 0, &ocr); 889 if (err) 890 return err; 891 892 card->ocr = ocr; 893 894 /* 895 * Some SD cards claims an out of spec VDD voltage range. Let's treat 896 * these bits as being in-valid and especially also bit7. 897 */ 898 ocr &= ~0x7FFF; 899 rocr = mmc_select_voltage(host, ocr); 900 /* 901 * Some cards have zero value of rocr in UHS-II mode. Assign host's 902 * ocr value to rocr. 903 */ 904 if (!rocr) 905 rocr = host->ocr_avail; 906 907 rocr |= (SD_OCR_CCS | SD_OCR_XPC); 908 909 /* Wait SD power on ready */ 910 ocr = rocr; 911 912 err = mmc_send_app_op_cond(host, ocr, &rocr); 913 if (err) 914 return err; 915 916 err = mmc_send_cid(host, cid); 917 if (err) 918 return err; 919 920 if (reinit) { 921 if (memcmp(cid, card->raw_cid, sizeof(cid)) != 0) { 922 pr_debug("%s: Perhaps the card was replaced\n", 923 mmc_hostname(host)); 924 return -ENOENT; 925 } 926 } else { 927 memcpy(card->raw_cid, cid, sizeof(card->raw_cid)); 928 mmc_decode_cid(card); 929 } 930 931 /* 932 * For native busses: get card RCA and quit open drain mode. 933 */ 934 err = mmc_send_relative_addr(host, &card->rca); 935 if (err) 936 return err; 937 938 err = mmc_sd_get_csd(card, false); 939 if (err) 940 return err; 941 942 /* 943 * Select card, as all following commands rely on that. 944 */ 945 err = mmc_select_card(card); 946 if (err) 947 return err; 948 949 /* 950 * Fetch SCR from card. 951 */ 952 err = mmc_app_send_scr(card); 953 if (err) 954 return err; 955 956 err = mmc_decode_scr(card); 957 if (err) 958 return err; 959 960 /* 961 * Switch to high power consumption mode. 962 * Even switch failed, sd card can still work at lower power consumption mode, but 963 * performance will be lower than high power consumption mode. 964 */ 965 status = kmalloc(64, GFP_KERNEL); 966 if (!status) 967 return -ENOMEM; 968 969 if (!(card->csd.cmdclass & CCC_SWITCH)) { 970 pr_warn("%s: card lacks mandatory switch function, performance might suffer\n", 971 mmc_hostname(card->host)); 972 } else { 973 /* 974 * Send CMD6 to set Maximum Power Consumption to get better 975 * performance. Ignore errors and continue. 976 */ 977 err = mmc_sd_switch(card, 0, 3, SD4_SET_POWER_LIMIT_1_80W, status); 978 if (!err) 979 mmc_sd_switch(card, 1, 3, SD4_SET_POWER_LIMIT_1_80W, status); 980 } 981 982 /* 983 * Check if read-only switch is active. 984 */ 985 ro = mmc_sd_get_ro(host); 986 if (ro < 0) 987 pr_warn("%s: host does not support read-only switch, assuming write-enable\n", 988 mmc_hostname(host)); 989 else if (ro > 0) 990 mmc_card_set_readonly(card); 991 992 kfree(status); 993 return 0; 994 } 995 996 static int sd_uhs2_reinit(struct mmc_host *host) 997 { 998 struct mmc_card *card = host->card; 999 int err; 1000 1001 err = sd_uhs2_power_up(host); 1002 if (err) 1003 return err; 1004 1005 err = sd_uhs2_phy_init(host); 1006 if (err) 1007 return err; 1008 1009 err = sd_uhs2_init_card(host, card); 1010 if (err) 1011 return err; 1012 1013 return sd_uhs2_legacy_init(host, card, true); 1014 } 1015 1016 static void sd_uhs2_remove(struct mmc_host *host) 1017 { 1018 mmc_remove_card(host->card); 1019 host->card = NULL; 1020 } 1021 1022 static int sd_uhs2_alive(struct mmc_host *host) 1023 { 1024 return mmc_send_status(host->card, NULL); 1025 } 1026 1027 static void sd_uhs2_detect(struct mmc_host *host) 1028 { 1029 int err; 1030 1031 mmc_get_card(host->card, NULL); 1032 err = _mmc_detect_card_removed(host); 1033 mmc_put_card(host->card, NULL); 1034 1035 if (err) { 1036 sd_uhs2_remove(host); 1037 1038 mmc_claim_host(host); 1039 mmc_detach_bus(host); 1040 sd_uhs2_power_off(host); 1041 mmc_release_host(host); 1042 } 1043 } 1044 1045 static int _sd_uhs2_suspend(struct mmc_host *host) 1046 { 1047 struct mmc_card *card = host->card; 1048 1049 mmc_claim_host(host); 1050 1051 if (mmc_card_suspended(card)) 1052 goto out; 1053 1054 sd_uhs2_power_off(host); 1055 mmc_card_set_suspended(card); 1056 1057 out: 1058 mmc_release_host(host); 1059 return 0; 1060 } 1061 1062 /* 1063 * Callback for suspend 1064 */ 1065 static int sd_uhs2_suspend(struct mmc_host *host) 1066 { 1067 int err; 1068 1069 err = _sd_uhs2_suspend(host); 1070 if (!err) { 1071 pm_runtime_disable(&host->card->dev); 1072 pm_runtime_set_suspended(&host->card->dev); 1073 } 1074 1075 return err; 1076 } 1077 1078 /* 1079 * This function tries to determine if the same card is still present 1080 * and, if so, restore all state to it. 1081 */ 1082 static int _mmc_sd_uhs2_resume(struct mmc_host *host) 1083 { 1084 int err = 0; 1085 1086 mmc_claim_host(host); 1087 1088 if (!mmc_card_suspended(host->card)) 1089 goto out; 1090 1091 /* Power up UHS2 SD card and re-initialize it. */ 1092 err = sd_uhs2_reinit(host); 1093 mmc_card_clr_suspended(host->card); 1094 1095 out: 1096 mmc_release_host(host); 1097 return err; 1098 } 1099 1100 /* 1101 * Callback for resume 1102 */ 1103 static int sd_uhs2_resume(struct mmc_host *host) 1104 { 1105 pm_runtime_enable(&host->card->dev); 1106 return 0; 1107 } 1108 1109 /* 1110 * Callback for runtime_suspend. 1111 */ 1112 static int sd_uhs2_runtime_suspend(struct mmc_host *host) 1113 { 1114 int err; 1115 1116 if (!(host->caps & MMC_CAP_AGGRESSIVE_PM)) 1117 return 0; 1118 1119 err = _sd_uhs2_suspend(host); 1120 if (err) 1121 pr_err("%s: error %d doing aggressive suspend\n", mmc_hostname(host), err); 1122 1123 return err; 1124 } 1125 1126 static int sd_uhs2_runtime_resume(struct mmc_host *host) 1127 { 1128 int err; 1129 1130 err = _mmc_sd_uhs2_resume(host); 1131 if (err && err != -ENOMEDIUM) 1132 pr_err("%s: error %d doing runtime resume\n", mmc_hostname(host), err); 1133 1134 return err; 1135 } 1136 1137 static int sd_uhs2_hw_reset(struct mmc_host *host) 1138 { 1139 sd_uhs2_power_off(host); 1140 /* Wait at least 1 ms according to SD spec */ 1141 mmc_delay(1); 1142 1143 return sd_uhs2_reinit(host); 1144 } 1145 1146 static const struct mmc_bus_ops sd_uhs2_ops = { 1147 .remove = sd_uhs2_remove, 1148 .alive = sd_uhs2_alive, 1149 .detect = sd_uhs2_detect, 1150 .suspend = sd_uhs2_suspend, 1151 .resume = sd_uhs2_resume, 1152 .runtime_suspend = sd_uhs2_runtime_suspend, 1153 .runtime_resume = sd_uhs2_runtime_resume, 1154 .shutdown = sd_uhs2_suspend, 1155 .hw_reset = sd_uhs2_hw_reset, 1156 }; 1157 1158 static int sd_uhs2_attach(struct mmc_host *host) 1159 { 1160 int err; 1161 1162 err = sd_uhs2_power_up(host); 1163 if (err) 1164 goto err; 1165 1166 err = sd_uhs2_phy_init(host); 1167 if (err) 1168 goto err; 1169 1170 err = sd_uhs2_init_card(host, NULL); 1171 if (err) 1172 goto err; 1173 1174 err = sd_uhs2_legacy_init(host, host->card, false); 1175 if (err) 1176 goto remove_card; 1177 1178 mmc_attach_bus(host, &sd_uhs2_ops); 1179 1180 mmc_release_host(host); 1181 1182 err = mmc_add_card(host->card); 1183 if (err) 1184 goto remove_card; 1185 1186 mmc_claim_host(host); 1187 return 0; 1188 1189 remove_card: 1190 sd_uhs2_remove(host); 1191 mmc_claim_host(host); 1192 err: 1193 mmc_detach_bus(host); 1194 sd_uhs2_power_off(host); 1195 return err; 1196 } 1197 1198 /** 1199 * mmc_attach_sd_uhs2 - select UHS2 interface 1200 * @host: MMC host 1201 * 1202 * Try to select UHS2 interface and initialize the bus for a given 1203 * frequency, @freq. 1204 * 1205 * Return: 0 on success, non-zero error on failure 1206 */ 1207 int mmc_attach_sd_uhs2(struct mmc_host *host) 1208 { 1209 int i, err; 1210 1211 if (!(host->caps2 & MMC_CAP2_SD_UHS2)) 1212 return -EOPNOTSUPP; 1213 1214 /* Turn off the legacy SD interface before trying with UHS-II. */ 1215 mmc_power_off(host); 1216 1217 /* 1218 * Start UHS-II initialization at 52MHz and possibly make a retry at 1219 * 26MHz according to the spec. It's required that the host driver 1220 * validates ios->clock, to set a rate within the correct range. 1221 */ 1222 for (i = 0; i < ARRAY_SIZE(sd_uhs2_freqs); i++) { 1223 host->f_init = sd_uhs2_freqs[i]; 1224 pr_debug("%s: %s: trying to init UHS-II card at %u Hz\n", 1225 mmc_hostname(host), __func__, host->f_init); 1226 err = sd_uhs2_attach(host); 1227 if (!err) 1228 break; 1229 } 1230 1231 return err; 1232 } 1233 1234 /* 1235 * mmc_uhs2_prepare_cmd - prepare for SD command packet 1236 * @host: MMC host 1237 * @mrq: MMC request 1238 * 1239 * Initialize and fill in a header and a payload of SD command packet. 1240 * The caller should allocate uhs2_command in host->cmd->uhs2_cmd in 1241 * advance. 1242 * 1243 * Return: 0 on success, non-zero error on failure 1244 */ 1245 void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq) 1246 { 1247 struct mmc_command *cmd; 1248 struct uhs2_command *uhs2_cmd; 1249 u8 plen; 1250 1251 cmd = mrq->cmd; 1252 cmd->uhs2_cmd = &mrq->uhs2_cmd; 1253 uhs2_cmd = cmd->uhs2_cmd; 1254 uhs2_cmd->header = host->card->uhs2_config.node_id; 1255 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) 1256 uhs2_cmd->header |= UHS2_PACKET_TYPE_DCMD; 1257 else 1258 uhs2_cmd->header |= UHS2_PACKET_TYPE_CCMD; 1259 1260 uhs2_cmd->arg = cmd->opcode << UHS2_SD_CMD_INDEX_POS; 1261 if (host->uhs2_app_cmd) { 1262 uhs2_cmd->arg |= UHS2_SD_CMD_APP; 1263 host->uhs2_app_cmd = false; 1264 } 1265 1266 /* 1267 * UHS-II Addendum 7.2.1.2 1268 * Host may set DM to 1 for DCMD which supports multi-block read/write regardless of 1269 * data transfer length (e.g., CMD18, CMD25). Otherwise, it shall not set DM to 1. 1270 * (e.g., CMD6, CMD17, CMD24). These rules are also applied to other multi-block read/write 1271 * commands defined in other Part of SD specifications (for example, Host may set DM to 1 1272 * for ACMD18 or ACMD25). 1273 */ 1274 if (mmc_op_multi(cmd->opcode)) 1275 cmd->uhs2_cmd->tmode_half_duplex = mmc_card_uhs2_hd_mode(host); 1276 else 1277 cmd->uhs2_cmd->tmode_half_duplex = 0; 1278 1279 uhs2_cmd = cmd->uhs2_cmd; 1280 plen = 2; /* at the maximum */ 1281 1282 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC && 1283 cmd->uhs2_cmd->tmode_half_duplex) { 1284 if (mmc_card_uhs2_hd_mode(host)) 1285 uhs2_cmd->arg |= UHS2_DCMD_2L_HD_MODE; 1286 1287 uhs2_cmd->arg |= UHS2_DCMD_LM_TLEN_EXIST; 1288 1289 if (cmd->data->blocks == 1 && 1290 cmd->data->blksz != 512 && 1291 cmd->opcode != MMC_READ_SINGLE_BLOCK && 1292 cmd->opcode != MMC_WRITE_BLOCK) { 1293 uhs2_cmd->arg |= UHS2_DCMD_TLUM_BYTE_MODE; 1294 uhs2_cmd->payload[1] = cpu_to_be32(cmd->data->blksz); 1295 } else { 1296 uhs2_cmd->payload[1] = cpu_to_be32(cmd->data->blocks); 1297 } 1298 } else { 1299 plen = 1; 1300 } 1301 1302 uhs2_cmd->payload[0] = cpu_to_be32(cmd->arg); 1303 sd_uhs2_cmd_assemble(cmd, uhs2_cmd, plen, 0); 1304 } 1305