1 /* 2 * SN Platform GRU Driver 3 * 4 * GRU HANDLE DEFINITION 5 * 6 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #ifndef __GRUHANDLES_H__ 24 #define __GRUHANDLES_H__ 25 #include "gru_instructions.h" 26 27 /* 28 * Manifest constants for GRU Memory Map 29 */ 30 #define GRU_GSEG0_BASE 0 31 #define GRU_MCS_BASE (64 * 1024 * 1024) 32 #define GRU_SIZE (128UL * 1024 * 1024) 33 34 /* Handle & resource counts */ 35 #define GRU_NUM_CB 128 36 #define GRU_NUM_DSR_BYTES (32 * 1024) 37 #define GRU_NUM_TFM 16 38 #define GRU_NUM_TGH 24 39 #define GRU_NUM_CBE 128 40 #define GRU_NUM_TFH 128 41 #define GRU_NUM_CCH 16 42 43 /* Maximum resource counts that can be reserved by user programs */ 44 #define GRU_NUM_USER_CBR GRU_NUM_CBE 45 #define GRU_NUM_USER_DSR_BYTES GRU_NUM_DSR_BYTES 46 47 /* Bytes per handle & handle stride. Code assumes all cb, tfh, cbe handles 48 * are the same */ 49 #define GRU_HANDLE_BYTES 64 50 #define GRU_HANDLE_STRIDE 256 51 52 /* Base addresses of handles */ 53 #define GRU_TFM_BASE (GRU_MCS_BASE + 0x00000) 54 #define GRU_TGH_BASE (GRU_MCS_BASE + 0x08000) 55 #define GRU_CBE_BASE (GRU_MCS_BASE + 0x10000) 56 #define GRU_TFH_BASE (GRU_MCS_BASE + 0x18000) 57 #define GRU_CCH_BASE (GRU_MCS_BASE + 0x20000) 58 59 /* User gseg constants */ 60 #define GRU_GSEG_STRIDE (4 * 1024 * 1024) 61 #define GSEG_BASE(a) ((a) & ~(GRU_GSEG_PAGESIZE - 1)) 62 63 /* Data segment constants */ 64 #define GRU_DSR_AU_BYTES 1024 65 #define GRU_DSR_CL (GRU_NUM_DSR_BYTES / GRU_CACHE_LINE_BYTES) 66 #define GRU_DSR_AU_CL (GRU_DSR_AU_BYTES / GRU_CACHE_LINE_BYTES) 67 #define GRU_DSR_AU (GRU_NUM_DSR_BYTES / GRU_DSR_AU_BYTES) 68 69 /* Control block constants */ 70 #define GRU_CBR_AU_SIZE 2 71 #define GRU_CBR_AU (GRU_NUM_CBE / GRU_CBR_AU_SIZE) 72 73 /* Convert resource counts to the number of AU */ 74 #define GRU_DS_BYTES_TO_AU(n) DIV_ROUND_UP(n, GRU_DSR_AU_BYTES) 75 #define GRU_CB_COUNT_TO_AU(n) DIV_ROUND_UP(n, GRU_CBR_AU_SIZE) 76 77 /* UV limits */ 78 #define GRU_CHIPLETS_PER_HUB 2 79 #define GRU_HUBS_PER_BLADE 1 80 #define GRU_CHIPLETS_PER_BLADE (GRU_HUBS_PER_BLADE * GRU_CHIPLETS_PER_HUB) 81 82 /* User GRU Gseg offsets */ 83 #define GRU_CB_BASE 0 84 #define GRU_CB_LIMIT (GRU_CB_BASE + GRU_HANDLE_STRIDE * GRU_NUM_CBE) 85 #define GRU_DS_BASE 0x20000 86 #define GRU_DS_LIMIT (GRU_DS_BASE + GRU_NUM_DSR_BYTES) 87 88 /* Convert a GRU physical address to the chiplet offset */ 89 #define GSEGPOFF(h) ((h) & (GRU_SIZE - 1)) 90 91 /* Convert an arbitrary handle address to the beginning of the GRU segment */ 92 #define GRUBASE(h) ((void *)((unsigned long)(h) & ~(GRU_SIZE - 1))) 93 94 /* Test a valid handle address to determine the type */ 95 #define TYPE_IS(hn, h) ((h) >= GRU_##hn##_BASE && (h) < \ 96 GRU_##hn##_BASE + GRU_NUM_##hn * GRU_HANDLE_STRIDE && \ 97 (((h) & (GRU_HANDLE_STRIDE - 1)) == 0)) 98 99 100 /* General addressing macros. */ 101 static inline void *get_gseg_base_address(void *base, int ctxnum) 102 { 103 return (void *)(base + GRU_GSEG0_BASE + GRU_GSEG_STRIDE * ctxnum); 104 } 105 106 static inline void *get_gseg_base_address_cb(void *base, int ctxnum, int line) 107 { 108 return (void *)(get_gseg_base_address(base, ctxnum) + 109 GRU_CB_BASE + GRU_HANDLE_STRIDE * line); 110 } 111 112 static inline void *get_gseg_base_address_ds(void *base, int ctxnum, int line) 113 { 114 return (void *)(get_gseg_base_address(base, ctxnum) + GRU_DS_BASE + 115 GRU_CACHE_LINE_BYTES * line); 116 } 117 118 static inline struct gru_tlb_fault_map *get_tfm(void *base, int ctxnum) 119 { 120 return (struct gru_tlb_fault_map *)(base + GRU_TFM_BASE + 121 ctxnum * GRU_HANDLE_STRIDE); 122 } 123 124 static inline struct gru_tlb_global_handle *get_tgh(void *base, int ctxnum) 125 { 126 return (struct gru_tlb_global_handle *)(base + GRU_TGH_BASE + 127 ctxnum * GRU_HANDLE_STRIDE); 128 } 129 130 static inline struct gru_control_block_extended *get_cbe(void *base, int ctxnum) 131 { 132 return (struct gru_control_block_extended *)(base + GRU_CBE_BASE + 133 ctxnum * GRU_HANDLE_STRIDE); 134 } 135 136 static inline struct gru_tlb_fault_handle *get_tfh(void *base, int ctxnum) 137 { 138 return (struct gru_tlb_fault_handle *)(base + GRU_TFH_BASE + 139 ctxnum * GRU_HANDLE_STRIDE); 140 } 141 142 static inline struct gru_context_configuration_handle *get_cch(void *base, 143 int ctxnum) 144 { 145 return (struct gru_context_configuration_handle *)(base + 146 GRU_CCH_BASE + ctxnum * GRU_HANDLE_STRIDE); 147 } 148 149 static inline unsigned long get_cb_number(void *cb) 150 { 151 return (((unsigned long)cb - GRU_CB_BASE) % GRU_GSEG_PAGESIZE) / 152 GRU_HANDLE_STRIDE; 153 } 154 155 /* byte offset to a specific GRU chiplet. (p=pnode, c=chiplet (0 or 1)*/ 156 static inline unsigned long gru_chiplet_paddr(unsigned long paddr, int pnode, 157 int chiplet) 158 { 159 return paddr + GRU_SIZE * (2 * pnode + chiplet); 160 } 161 162 static inline void *gru_chiplet_vaddr(void *vaddr, int pnode, int chiplet) 163 { 164 return vaddr + GRU_SIZE * (2 * pnode + chiplet); 165 } 166 167 static inline struct gru_control_block_extended *gru_tfh_to_cbe( 168 struct gru_tlb_fault_handle *tfh) 169 { 170 unsigned long cbe; 171 172 cbe = (unsigned long)tfh - GRU_TFH_BASE + GRU_CBE_BASE; 173 return (struct gru_control_block_extended*)cbe; 174 } 175 176 177 178 179 /* 180 * Global TLB Fault Map 181 * Bitmap of outstanding TLB misses needing interrupt/polling service. 182 * 183 */ 184 struct gru_tlb_fault_map { 185 unsigned long fault_bits[BITS_TO_LONGS(GRU_NUM_CBE)]; 186 unsigned long fill0[2]; 187 unsigned long done_bits[BITS_TO_LONGS(GRU_NUM_CBE)]; 188 unsigned long fill1[2]; 189 }; 190 191 /* 192 * TGH - TLB Global Handle 193 * Used for TLB flushing. 194 * 195 */ 196 struct gru_tlb_global_handle { 197 unsigned int cmd:1; /* DW 0 */ 198 unsigned int delresp:1; 199 unsigned int opc:1; 200 unsigned int fill1:5; 201 202 unsigned int fill2:8; 203 204 unsigned int status:2; 205 unsigned long fill3:2; 206 unsigned int state:3; 207 unsigned long fill4:1; 208 209 unsigned int cause:3; 210 unsigned long fill5:37; 211 212 unsigned long vaddr:64; /* DW 1 */ 213 214 unsigned int asid:24; /* DW 2 */ 215 unsigned int fill6:8; 216 217 unsigned int pagesize:5; 218 unsigned int fill7:11; 219 220 unsigned int global:1; 221 unsigned int fill8:15; 222 223 unsigned long vaddrmask:39; /* DW 3 */ 224 unsigned int fill9:9; 225 unsigned int n:10; 226 unsigned int fill10:6; 227 228 unsigned int ctxbitmap:16; /* DW4 */ 229 unsigned long fill11[3]; 230 }; 231 232 enum gru_tgh_cmd { 233 TGHCMD_START 234 }; 235 236 enum gru_tgh_opc { 237 TGHOP_TLBNOP, 238 TGHOP_TLBINV 239 }; 240 241 enum gru_tgh_status { 242 TGHSTATUS_IDLE, 243 TGHSTATUS_EXCEPTION, 244 TGHSTATUS_ACTIVE 245 }; 246 247 enum gru_tgh_state { 248 TGHSTATE_IDLE, 249 TGHSTATE_PE_INVAL, 250 TGHSTATE_INTERRUPT_INVAL, 251 TGHSTATE_WAITDONE, 252 TGHSTATE_RESTART_CTX, 253 }; 254 255 /* 256 * TFH - TLB Global Handle 257 * Used for TLB dropins into the GRU TLB. 258 * 259 */ 260 struct gru_tlb_fault_handle { 261 unsigned int cmd:1; /* DW 0 - low 32*/ 262 unsigned int delresp:1; 263 unsigned int fill0:2; 264 unsigned int opc:3; 265 unsigned int fill1:9; 266 267 unsigned int status:2; 268 unsigned int fill2:2; 269 unsigned int state:3; 270 unsigned int fill3:1; 271 272 unsigned int cause:6; 273 unsigned int cb_int:1; 274 unsigned int fill4:1; 275 276 unsigned int indexway:12; /* DW 0 - high 32 */ 277 unsigned int fill5:4; 278 279 unsigned int ctxnum:4; 280 unsigned int fill6:12; 281 282 unsigned long missvaddr:64; /* DW 1 */ 283 284 unsigned int missasid:24; /* DW 2 */ 285 unsigned int fill7:8; 286 unsigned int fillasid:24; 287 unsigned int dirty:1; 288 unsigned int gaa:2; 289 unsigned long fill8:5; 290 291 unsigned long pfn:41; /* DW 3 */ 292 unsigned int fill9:7; 293 unsigned int pagesize:5; 294 unsigned int fill10:11; 295 296 unsigned long fillvaddr:64; /* DW 4 */ 297 298 unsigned long fill11[3]; 299 }; 300 301 enum gru_tfh_opc { 302 TFHOP_NOOP, 303 TFHOP_RESTART, 304 TFHOP_WRITE_ONLY, 305 TFHOP_WRITE_RESTART, 306 TFHOP_EXCEPTION, 307 TFHOP_USER_POLLING_MODE = 7, 308 }; 309 310 enum tfh_status { 311 TFHSTATUS_IDLE, 312 TFHSTATUS_EXCEPTION, 313 TFHSTATUS_ACTIVE, 314 }; 315 316 enum tfh_state { 317 TFHSTATE_INACTIVE, 318 TFHSTATE_IDLE, 319 TFHSTATE_MISS_UPM, 320 TFHSTATE_MISS_FMM, 321 TFHSTATE_HW_ERR, 322 TFHSTATE_WRITE_TLB, 323 TFHSTATE_RESTART_CBR, 324 }; 325 326 /* TFH cause bits */ 327 enum tfh_cause { 328 TFHCAUSE_NONE, 329 TFHCAUSE_TLB_MISS, 330 TFHCAUSE_TLB_MOD, 331 TFHCAUSE_HW_ERROR_RR, 332 TFHCAUSE_HW_ERROR_MAIN_ARRAY, 333 TFHCAUSE_HW_ERROR_VALID, 334 TFHCAUSE_HW_ERROR_PAGESIZE, 335 TFHCAUSE_INSTRUCTION_EXCEPTION, 336 TFHCAUSE_UNCORRECTIBLE_ERROR, 337 }; 338 339 /* GAA values */ 340 #define GAA_RAM 0x0 341 #define GAA_NCRAM 0x2 342 #define GAA_MMIO 0x1 343 #define GAA_REGISTER 0x3 344 345 /* GRU paddr shift for pfn. (NOTE: shift is NOT by actual pagesize) */ 346 #define GRU_PADDR_SHIFT 12 347 348 /* 349 * Context Configuration handle 350 * Used to allocate resources to a GSEG context. 351 * 352 */ 353 struct gru_context_configuration_handle { 354 unsigned int cmd:1; /* DW0 */ 355 unsigned int delresp:1; 356 unsigned int opc:3; 357 unsigned int unmap_enable:1; 358 unsigned int req_slice_set_enable:1; 359 unsigned int req_slice:2; 360 unsigned int cb_int_enable:1; 361 unsigned int tlb_int_enable:1; 362 unsigned int tfm_fault_bit_enable:1; 363 unsigned int tlb_int_select:4; 364 365 unsigned int status:2; 366 unsigned int state:2; 367 unsigned int reserved2:4; 368 369 unsigned int cause:4; 370 unsigned int tfm_done_bit_enable:1; 371 unsigned int unused:3; 372 373 unsigned int dsr_allocation_map; 374 375 unsigned long cbr_allocation_map; /* DW1 */ 376 377 unsigned int asid[8]; /* DW 2 - 5 */ 378 unsigned short sizeavail[8]; /* DW 6 - 7 */ 379 } __attribute__ ((packed)); 380 381 enum gru_cch_opc { 382 CCHOP_START = 1, 383 CCHOP_ALLOCATE, 384 CCHOP_INTERRUPT, 385 CCHOP_DEALLOCATE, 386 CCHOP_INTERRUPT_SYNC, 387 }; 388 389 enum gru_cch_status { 390 CCHSTATUS_IDLE, 391 CCHSTATUS_EXCEPTION, 392 CCHSTATUS_ACTIVE, 393 }; 394 395 enum gru_cch_state { 396 CCHSTATE_INACTIVE, 397 CCHSTATE_MAPPED, 398 CCHSTATE_ACTIVE, 399 CCHSTATE_INTERRUPTED, 400 }; 401 402 /* CCH Exception cause */ 403 enum gru_cch_cause { 404 CCHCAUSE_REGION_REGISTER_WRITE_ERROR = 1, 405 CCHCAUSE_ILLEGAL_OPCODE = 2, 406 CCHCAUSE_INVALID_START_REQUEST = 3, 407 CCHCAUSE_INVALID_ALLOCATION_REQUEST = 4, 408 CCHCAUSE_INVALID_DEALLOCATION_REQUEST = 5, 409 CCHCAUSE_INVALID_INTERRUPT_REQUEST = 6, 410 CCHCAUSE_CCH_BUSY = 7, 411 CCHCAUSE_NO_CBRS_TO_ALLOCATE = 8, 412 CCHCAUSE_BAD_TFM_CONFIG = 9, 413 CCHCAUSE_CBR_RESOURCES_OVERSUBSCRIPED = 10, 414 CCHCAUSE_DSR_RESOURCES_OVERSUBSCRIPED = 11, 415 CCHCAUSE_CBR_DEALLOCATION_ERROR = 12, 416 }; 417 /* 418 * CBE - Control Block Extended 419 * Maintains internal GRU state for active CBs. 420 * 421 */ 422 struct gru_control_block_extended { 423 unsigned int reserved0:1; /* DW 0 - low */ 424 unsigned int imacpy:3; 425 unsigned int reserved1:4; 426 unsigned int xtypecpy:3; 427 unsigned int iaa0cpy:2; 428 unsigned int iaa1cpy:2; 429 unsigned int reserved2:1; 430 unsigned int opccpy:8; 431 unsigned int exopccpy:8; 432 433 unsigned int idef2cpy:22; /* DW 0 - high */ 434 unsigned int reserved3:10; 435 436 unsigned int idef4cpy:22; /* DW 1 */ 437 unsigned int reserved4:10; 438 unsigned int idef4upd:22; 439 unsigned int reserved5:10; 440 441 unsigned long idef1upd:64; /* DW 2 */ 442 443 unsigned long idef5cpy:64; /* DW 3 */ 444 445 unsigned long idef6cpy:64; /* DW 4 */ 446 447 unsigned long idef3upd:64; /* DW 5 */ 448 449 unsigned long idef5upd:64; /* DW 6 */ 450 451 unsigned int idef2upd:22; /* DW 7 */ 452 unsigned int reserved6:10; 453 454 unsigned int ecause:20; 455 unsigned int cbrstate:4; 456 unsigned int cbrexecstatus:8; 457 }; 458 459 /* CBE fields for active BCOPY instructions */ 460 #define cbe_baddr0 idef1upd 461 #define cbe_baddr1 idef3upd 462 #define cbe_src_cl idef6cpy 463 #define cbe_nelemcur idef5upd 464 465 enum gru_cbr_state { 466 CBRSTATE_INACTIVE, 467 CBRSTATE_IDLE, 468 CBRSTATE_PE_CHECK, 469 CBRSTATE_QUEUED, 470 CBRSTATE_WAIT_RESPONSE, 471 CBRSTATE_INTERRUPTED, 472 CBRSTATE_INTERRUPTED_MISS_FMM, 473 CBRSTATE_BUSY_INTERRUPT_MISS_FMM, 474 CBRSTATE_INTERRUPTED_MISS_UPM, 475 CBRSTATE_BUSY_INTERRUPTED_MISS_UPM, 476 CBRSTATE_REQUEST_ISSUE, 477 CBRSTATE_BUSY_INTERRUPT, 478 }; 479 480 /* CBE cbrexecstatus bits - defined in gru_instructions.h*/ 481 /* CBE ecause bits - defined in gru_instructions.h */ 482 483 /* 484 * Convert a processor pagesize into the strange encoded pagesize used by the 485 * GRU. Processor pagesize is encoded as log of bytes per page. (or PAGE_SHIFT) 486 * pagesize log pagesize grupagesize 487 * 4k 12 0 488 * 16k 14 1 489 * 64k 16 2 490 * 256k 18 3 491 * 1m 20 4 492 * 2m 21 5 493 * 4m 22 6 494 * 16m 24 7 495 * 64m 26 8 496 * ... 497 */ 498 #define GRU_PAGESIZE(sh) ((((sh) > 20 ? (sh) + 2 : (sh)) >> 1) - 6) 499 #define GRU_SIZEAVAIL(sh) (1UL << GRU_PAGESIZE(sh)) 500 501 /* minimum TLB purge count to ensure a full purge */ 502 #define GRUMAXINVAL 1024UL 503 504 int cch_allocate(struct gru_context_configuration_handle *cch); 505 int cch_start(struct gru_context_configuration_handle *cch); 506 int cch_interrupt(struct gru_context_configuration_handle *cch); 507 int cch_deallocate(struct gru_context_configuration_handle *cch); 508 int cch_interrupt_sync(struct gru_context_configuration_handle *cch); 509 int tgh_invalidate(struct gru_tlb_global_handle *tgh, unsigned long vaddr, 510 unsigned long vaddrmask, int asid, int pagesize, int global, int n, 511 unsigned short ctxbitmap); 512 int tfh_write_only(struct gru_tlb_fault_handle *tfh, unsigned long paddr, 513 int gaa, unsigned long vaddr, int asid, int dirty, int pagesize); 514 void tfh_write_restart(struct gru_tlb_fault_handle *tfh, unsigned long paddr, 515 int gaa, unsigned long vaddr, int asid, int dirty, int pagesize); 516 void tfh_restart(struct gru_tlb_fault_handle *tfh); 517 void tfh_user_polling_mode(struct gru_tlb_fault_handle *tfh); 518 void tfh_exception(struct gru_tlb_fault_handle *tfh); 519 520 #endif /* __GRUHANDLES_H__ */ 521