xref: /linux/drivers/misc/sgi-gru/grufile.c (revision b889fcf63cb62e7fdb7816565e28f44dbe4a76a5)
1 /*
2  * SN Platform GRU Driver
3  *
4  *              FILE OPERATIONS & DRIVER INITIALIZATION
5  *
6  * This file supports the user system call for file open, close, mmap, etc.
7  * This also incudes the driver initialization code.
8  *
9  *  Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
10  *
11  *  This program is free software; you can redistribute it and/or modify
12  *  it under the terms of the GNU General Public License as published by
13  *  the Free Software Foundation; either version 2 of the License, or
14  *  (at your option) any later version.
15  *
16  *  This program is distributed in the hope that it will be useful,
17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *  GNU General Public License for more details.
20  *
21  *  You should have received a copy of the GNU General Public License
22  *  along with this program; if not, write to the Free Software
23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
24  */
25 
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/errno.h>
29 #include <linux/slab.h>
30 #include <linux/mm.h>
31 #include <linux/io.h>
32 #include <linux/spinlock.h>
33 #include <linux/device.h>
34 #include <linux/miscdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/proc_fs.h>
37 #include <linux/uaccess.h>
38 #ifdef CONFIG_X86_64
39 #include <asm/uv/uv_irq.h>
40 #endif
41 #include <asm/uv/uv.h>
42 #include "gru.h"
43 #include "grulib.h"
44 #include "grutables.h"
45 
46 #include <asm/uv/uv_hub.h>
47 #include <asm/uv/uv_mmrs.h>
48 
49 struct gru_blade_state *gru_base[GRU_MAX_BLADES] __read_mostly;
50 unsigned long gru_start_paddr __read_mostly;
51 void *gru_start_vaddr __read_mostly;
52 unsigned long gru_end_paddr __read_mostly;
53 unsigned int gru_max_gids __read_mostly;
54 struct gru_stats_s gru_stats;
55 
56 /* Guaranteed user available resources on each node */
57 static int max_user_cbrs, max_user_dsr_bytes;
58 
59 static struct miscdevice gru_miscdev;
60 
61 
62 /*
63  * gru_vma_close
64  *
65  * Called when unmapping a device mapping. Frees all gru resources
66  * and tables belonging to the vma.
67  */
68 static void gru_vma_close(struct vm_area_struct *vma)
69 {
70 	struct gru_vma_data *vdata;
71 	struct gru_thread_state *gts;
72 	struct list_head *entry, *next;
73 
74 	if (!vma->vm_private_data)
75 		return;
76 
77 	vdata = vma->vm_private_data;
78 	vma->vm_private_data = NULL;
79 	gru_dbg(grudev, "vma %p, file %p, vdata %p\n", vma, vma->vm_file,
80 				vdata);
81 	list_for_each_safe(entry, next, &vdata->vd_head) {
82 		gts =
83 		    list_entry(entry, struct gru_thread_state, ts_next);
84 		list_del(&gts->ts_next);
85 		mutex_lock(&gts->ts_ctxlock);
86 		if (gts->ts_gru)
87 			gru_unload_context(gts, 0);
88 		mutex_unlock(&gts->ts_ctxlock);
89 		gts_drop(gts);
90 	}
91 	kfree(vdata);
92 	STAT(vdata_free);
93 }
94 
95 /*
96  * gru_file_mmap
97  *
98  * Called when mmapping the device.  Initializes the vma with a fault handler
99  * and private data structure necessary to allocate, track, and free the
100  * underlying pages.
101  */
102 static int gru_file_mmap(struct file *file, struct vm_area_struct *vma)
103 {
104 	if ((vma->vm_flags & (VM_SHARED | VM_WRITE)) != (VM_SHARED | VM_WRITE))
105 		return -EPERM;
106 
107 	if (vma->vm_start & (GRU_GSEG_PAGESIZE - 1) ||
108 				vma->vm_end & (GRU_GSEG_PAGESIZE - 1))
109 		return -EINVAL;
110 
111 	vma->vm_flags |= VM_IO | VM_PFNMAP | VM_LOCKED |
112 			 VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP;
113 	vma->vm_page_prot = PAGE_SHARED;
114 	vma->vm_ops = &gru_vm_ops;
115 
116 	vma->vm_private_data = gru_alloc_vma_data(vma, 0);
117 	if (!vma->vm_private_data)
118 		return -ENOMEM;
119 
120 	gru_dbg(grudev, "file %p, vaddr 0x%lx, vma %p, vdata %p\n",
121 		file, vma->vm_start, vma, vma->vm_private_data);
122 	return 0;
123 }
124 
125 /*
126  * Create a new GRU context
127  */
128 static int gru_create_new_context(unsigned long arg)
129 {
130 	struct gru_create_context_req req;
131 	struct vm_area_struct *vma;
132 	struct gru_vma_data *vdata;
133 	int ret = -EINVAL;
134 
135 	if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
136 		return -EFAULT;
137 
138 	if (req.data_segment_bytes > max_user_dsr_bytes)
139 		return -EINVAL;
140 	if (req.control_blocks > max_user_cbrs || !req.maximum_thread_count)
141 		return -EINVAL;
142 
143 	if (!(req.options & GRU_OPT_MISS_MASK))
144 		req.options |= GRU_OPT_MISS_FMM_INTR;
145 
146 	down_write(&current->mm->mmap_sem);
147 	vma = gru_find_vma(req.gseg);
148 	if (vma) {
149 		vdata = vma->vm_private_data;
150 		vdata->vd_user_options = req.options;
151 		vdata->vd_dsr_au_count =
152 		    GRU_DS_BYTES_TO_AU(req.data_segment_bytes);
153 		vdata->vd_cbr_au_count = GRU_CB_COUNT_TO_AU(req.control_blocks);
154 		vdata->vd_tlb_preload_count = req.tlb_preload_count;
155 		ret = 0;
156 	}
157 	up_write(&current->mm->mmap_sem);
158 
159 	return ret;
160 }
161 
162 /*
163  * Get GRU configuration info (temp - for emulator testing)
164  */
165 static long gru_get_config_info(unsigned long arg)
166 {
167 	struct gru_config_info info;
168 	int nodesperblade;
169 
170 	if (num_online_nodes() > 1 &&
171 			(uv_node_to_blade_id(1) == uv_node_to_blade_id(0)))
172 		nodesperblade = 2;
173 	else
174 		nodesperblade = 1;
175 	info.cpus = num_online_cpus();
176 	info.nodes = num_online_nodes();
177 	info.blades = info.nodes / nodesperblade;
178 	info.chiplets = GRU_CHIPLETS_PER_BLADE * info.blades;
179 
180 	if (copy_to_user((void __user *)arg, &info, sizeof(info)))
181 		return -EFAULT;
182 	return 0;
183 }
184 
185 /*
186  * gru_file_unlocked_ioctl
187  *
188  * Called to update file attributes via IOCTL calls.
189  */
190 static long gru_file_unlocked_ioctl(struct file *file, unsigned int req,
191 				    unsigned long arg)
192 {
193 	int err = -EBADRQC;
194 
195 	gru_dbg(grudev, "file %p, req 0x%x, 0x%lx\n", file, req, arg);
196 
197 	switch (req) {
198 	case GRU_CREATE_CONTEXT:
199 		err = gru_create_new_context(arg);
200 		break;
201 	case GRU_SET_CONTEXT_OPTION:
202 		err = gru_set_context_option(arg);
203 		break;
204 	case GRU_USER_GET_EXCEPTION_DETAIL:
205 		err = gru_get_exception_detail(arg);
206 		break;
207 	case GRU_USER_UNLOAD_CONTEXT:
208 		err = gru_user_unload_context(arg);
209 		break;
210 	case GRU_USER_FLUSH_TLB:
211 		err = gru_user_flush_tlb(arg);
212 		break;
213 	case GRU_USER_CALL_OS:
214 		err = gru_handle_user_call_os(arg);
215 		break;
216 	case GRU_GET_GSEG_STATISTICS:
217 		err = gru_get_gseg_statistics(arg);
218 		break;
219 	case GRU_KTEST:
220 		err = gru_ktest(arg);
221 		break;
222 	case GRU_GET_CONFIG_INFO:
223 		err = gru_get_config_info(arg);
224 		break;
225 	case GRU_DUMP_CHIPLET_STATE:
226 		err = gru_dump_chiplet_request(arg);
227 		break;
228 	}
229 	return err;
230 }
231 
232 /*
233  * Called at init time to build tables for all GRUs that are present in the
234  * system.
235  */
236 static void gru_init_chiplet(struct gru_state *gru, unsigned long paddr,
237 			     void *vaddr, int blade_id, int chiplet_id)
238 {
239 	spin_lock_init(&gru->gs_lock);
240 	spin_lock_init(&gru->gs_asid_lock);
241 	gru->gs_gru_base_paddr = paddr;
242 	gru->gs_gru_base_vaddr = vaddr;
243 	gru->gs_gid = blade_id * GRU_CHIPLETS_PER_BLADE + chiplet_id;
244 	gru->gs_blade = gru_base[blade_id];
245 	gru->gs_blade_id = blade_id;
246 	gru->gs_chiplet_id = chiplet_id;
247 	gru->gs_cbr_map = (GRU_CBR_AU == 64) ? ~0 : (1UL << GRU_CBR_AU) - 1;
248 	gru->gs_dsr_map = (1UL << GRU_DSR_AU) - 1;
249 	gru->gs_asid_limit = MAX_ASID;
250 	gru_tgh_flush_init(gru);
251 	if (gru->gs_gid >= gru_max_gids)
252 		gru_max_gids = gru->gs_gid + 1;
253 	gru_dbg(grudev, "bid %d, gid %d, vaddr %p (0x%lx)\n",
254 		blade_id, gru->gs_gid, gru->gs_gru_base_vaddr,
255 		gru->gs_gru_base_paddr);
256 }
257 
258 static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
259 {
260 	int pnode, nid, bid, chip;
261 	int cbrs, dsrbytes, n;
262 	int order = get_order(sizeof(struct gru_blade_state));
263 	struct page *page;
264 	struct gru_state *gru;
265 	unsigned long paddr;
266 	void *vaddr;
267 
268 	max_user_cbrs = GRU_NUM_CB;
269 	max_user_dsr_bytes = GRU_NUM_DSR_BYTES;
270 	for_each_possible_blade(bid) {
271 		pnode = uv_blade_to_pnode(bid);
272 		nid = uv_blade_to_memory_nid(bid);/* -1 if no memory on blade */
273 		page = alloc_pages_node(nid, GFP_KERNEL, order);
274 		if (!page)
275 			goto fail;
276 		gru_base[bid] = page_address(page);
277 		memset(gru_base[bid], 0, sizeof(struct gru_blade_state));
278 		gru_base[bid]->bs_lru_gru = &gru_base[bid]->bs_grus[0];
279 		spin_lock_init(&gru_base[bid]->bs_lock);
280 		init_rwsem(&gru_base[bid]->bs_kgts_sema);
281 
282 		dsrbytes = 0;
283 		cbrs = 0;
284 		for (gru = gru_base[bid]->bs_grus, chip = 0;
285 				chip < GRU_CHIPLETS_PER_BLADE;
286 				chip++, gru++) {
287 			paddr = gru_chiplet_paddr(gru_base_paddr, pnode, chip);
288 			vaddr = gru_chiplet_vaddr(gru_base_vaddr, pnode, chip);
289 			gru_init_chiplet(gru, paddr, vaddr, bid, chip);
290 			n = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
291 			cbrs = max(cbrs, n);
292 			n = hweight64(gru->gs_dsr_map) * GRU_DSR_AU_BYTES;
293 			dsrbytes = max(dsrbytes, n);
294 		}
295 		max_user_cbrs = min(max_user_cbrs, cbrs);
296 		max_user_dsr_bytes = min(max_user_dsr_bytes, dsrbytes);
297 	}
298 
299 	return 0;
300 
301 fail:
302 	for (bid--; bid >= 0; bid--)
303 		free_pages((unsigned long)gru_base[bid], order);
304 	return -ENOMEM;
305 }
306 
307 static void gru_free_tables(void)
308 {
309 	int bid;
310 	int order = get_order(sizeof(struct gru_state) *
311 			      GRU_CHIPLETS_PER_BLADE);
312 
313 	for (bid = 0; bid < GRU_MAX_BLADES; bid++)
314 		free_pages((unsigned long)gru_base[bid], order);
315 }
316 
317 static unsigned long gru_chiplet_cpu_to_mmr(int chiplet, int cpu, int *corep)
318 {
319 	unsigned long mmr = 0;
320 	int core;
321 
322 	/*
323 	 * We target the cores of a blade and not the hyperthreads themselves.
324 	 * There is a max of 8 cores per socket and 2 sockets per blade,
325 	 * making for a max total of 16 cores (i.e., 16 CPUs without
326 	 * hyperthreading and 32 CPUs with hyperthreading).
327 	 */
328 	core = uv_cpu_core_number(cpu) + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
329 	if (core >= GRU_NUM_TFM || uv_cpu_ht_number(cpu))
330 		return 0;
331 
332 	if (chiplet == 0) {
333 		mmr = UVH_GR0_TLB_INT0_CONFIG +
334 		    core * (UVH_GR0_TLB_INT1_CONFIG - UVH_GR0_TLB_INT0_CONFIG);
335 	} else if (chiplet == 1) {
336 		mmr = UVH_GR1_TLB_INT0_CONFIG +
337 		    core * (UVH_GR1_TLB_INT1_CONFIG - UVH_GR1_TLB_INT0_CONFIG);
338 	} else {
339 		BUG();
340 	}
341 
342 	*corep = core;
343 	return mmr;
344 }
345 
346 #ifdef CONFIG_IA64
347 
348 static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];
349 
350 static void gru_noop(struct irq_data *d)
351 {
352 }
353 
354 static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
355 	[0 ... GRU_CHIPLETS_PER_BLADE - 1] {
356 		.irq_mask	= gru_noop,
357 		.irq_unmask	= gru_noop,
358 		.irq_ack	= gru_noop
359 	}
360 };
361 
362 static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
363 			irq_handler_t irq_handler, int cpu, int blade)
364 {
365 	unsigned long mmr;
366 	int irq = IRQ_GRU + chiplet;
367 	int ret, core;
368 
369 	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
370 	if (mmr == 0)
371 		return 0;
372 
373 	if (gru_irq_count[chiplet] == 0) {
374 		gru_chip[chiplet].name = irq_name;
375 		ret = irq_set_chip(irq, &gru_chip[chiplet]);
376 		if (ret) {
377 			printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
378 			       GRU_DRIVER_ID_STR, -ret);
379 			return ret;
380 		}
381 
382 		ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
383 		if (ret) {
384 			printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
385 			       GRU_DRIVER_ID_STR, -ret);
386 			return ret;
387 		}
388 	}
389 	gru_irq_count[chiplet]++;
390 
391 	return 0;
392 }
393 
394 static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
395 {
396 	unsigned long mmr;
397 	int core, irq = IRQ_GRU + chiplet;
398 
399 	if (gru_irq_count[chiplet] == 0)
400 		return;
401 
402 	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
403 	if (mmr == 0)
404 		return;
405 
406 	if (--gru_irq_count[chiplet] == 0)
407 		free_irq(irq, NULL);
408 }
409 
410 #elif defined CONFIG_X86_64
411 
412 static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
413 			irq_handler_t irq_handler, int cpu, int blade)
414 {
415 	unsigned long mmr;
416 	int irq, core;
417 	int ret;
418 
419 	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
420 	if (mmr == 0)
421 		return 0;
422 
423 	irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
424 	if (irq < 0) {
425 		printk(KERN_ERR "%s: uv_setup_irq failed, errno=%d\n",
426 		       GRU_DRIVER_ID_STR, -irq);
427 		return irq;
428 	}
429 
430 	ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
431 	if (ret) {
432 		uv_teardown_irq(irq);
433 		printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
434 		       GRU_DRIVER_ID_STR, -ret);
435 		return ret;
436 	}
437 	gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
438 	return 0;
439 }
440 
441 static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
442 {
443 	int irq, core;
444 	unsigned long mmr;
445 
446 	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
447 	if (mmr) {
448 		irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
449 		if (irq) {
450 			free_irq(irq, NULL);
451 			uv_teardown_irq(irq);
452 		}
453 	}
454 }
455 
456 #endif
457 
458 static void gru_teardown_tlb_irqs(void)
459 {
460 	int blade;
461 	int cpu;
462 
463 	for_each_online_cpu(cpu) {
464 		blade = uv_cpu_to_blade_id(cpu);
465 		gru_chiplet_teardown_tlb_irq(0, cpu, blade);
466 		gru_chiplet_teardown_tlb_irq(1, cpu, blade);
467 	}
468 	for_each_possible_blade(blade) {
469 		if (uv_blade_nr_possible_cpus(blade))
470 			continue;
471 		gru_chiplet_teardown_tlb_irq(0, 0, blade);
472 		gru_chiplet_teardown_tlb_irq(1, 0, blade);
473 	}
474 }
475 
476 static int gru_setup_tlb_irqs(void)
477 {
478 	int blade;
479 	int cpu;
480 	int ret;
481 
482 	for_each_online_cpu(cpu) {
483 		blade = uv_cpu_to_blade_id(cpu);
484 		ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
485 		if (ret != 0)
486 			goto exit1;
487 
488 		ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
489 		if (ret != 0)
490 			goto exit1;
491 	}
492 	for_each_possible_blade(blade) {
493 		if (uv_blade_nr_possible_cpus(blade))
494 			continue;
495 		ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
496 		if (ret != 0)
497 			goto exit1;
498 
499 		ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);
500 		if (ret != 0)
501 			goto exit1;
502 	}
503 
504 	return 0;
505 
506 exit1:
507 	gru_teardown_tlb_irqs();
508 	return ret;
509 }
510 
511 /*
512  * gru_init
513  *
514  * Called at boot or module load time to initialize the GRUs.
515  */
516 static int __init gru_init(void)
517 {
518 	int ret;
519 
520 	if (!is_uv_system())
521 		return 0;
522 
523 #if defined CONFIG_IA64
524 	gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
525 #else
526 	gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR) &
527 				0x7fffffffffffUL;
528 #endif
529 	gru_start_vaddr = __va(gru_start_paddr);
530 	gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
531 	printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
532 	       gru_start_paddr, gru_end_paddr);
533 	ret = misc_register(&gru_miscdev);
534 	if (ret) {
535 		printk(KERN_ERR "%s: misc_register failed\n",
536 		       GRU_DRIVER_ID_STR);
537 		goto exit0;
538 	}
539 
540 	ret = gru_proc_init();
541 	if (ret) {
542 		printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
543 		goto exit1;
544 	}
545 
546 	ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
547 	if (ret) {
548 		printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
549 		goto exit2;
550 	}
551 
552 	ret = gru_setup_tlb_irqs();
553 	if (ret != 0)
554 		goto exit3;
555 
556 	gru_kservices_init();
557 
558 	printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
559 	       GRU_DRIVER_VERSION_STR);
560 	return 0;
561 
562 exit3:
563 	gru_free_tables();
564 exit2:
565 	gru_proc_exit();
566 exit1:
567 	misc_deregister(&gru_miscdev);
568 exit0:
569 	return ret;
570 
571 }
572 
573 static void __exit gru_exit(void)
574 {
575 	if (!is_uv_system())
576 		return;
577 
578 	gru_teardown_tlb_irqs();
579 	gru_kservices_exit();
580 	gru_free_tables();
581 	misc_deregister(&gru_miscdev);
582 	gru_proc_exit();
583 }
584 
585 static const struct file_operations gru_fops = {
586 	.owner		= THIS_MODULE,
587 	.unlocked_ioctl	= gru_file_unlocked_ioctl,
588 	.mmap		= gru_file_mmap,
589 	.llseek		= noop_llseek,
590 };
591 
592 static struct miscdevice gru_miscdev = {
593 	.minor		= MISC_DYNAMIC_MINOR,
594 	.name		= "gru",
595 	.fops		= &gru_fops,
596 };
597 
598 const struct vm_operations_struct gru_vm_ops = {
599 	.close		= gru_vma_close,
600 	.fault		= gru_fault,
601 };
602 
603 #ifndef MODULE
604 fs_initcall(gru_init);
605 #else
606 module_init(gru_init);
607 #endif
608 module_exit(gru_exit);
609 
610 module_param(gru_options, ulong, 0644);
611 MODULE_PARM_DESC(gru_options, "Various debug options");
612 
613 MODULE_AUTHOR("Silicon Graphics, Inc.");
614 MODULE_LICENSE("GPL");
615 MODULE_DESCRIPTION(GRU_DRIVER_ID_STR GRU_DRIVER_VERSION_STR);
616 MODULE_VERSION(GRU_DRIVER_VERSION_STR);
617 
618