1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2025 Raspberry Pi Ltd. 4 * 5 * All rights reserved. 6 */ 7 8 #include <linux/err.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/module.h> 14 #include <linux/msi.h> 15 #include <linux/of_platform.h> 16 #include <linux/pci.h> 17 #include <linux/platform_device.h> 18 19 #define RP1_HW_IRQ_MASK GENMASK(5, 0) 20 21 #define REG_SET 0x800 22 #define REG_CLR 0xc00 23 24 /* MSI-X CFG registers start at 0x8 */ 25 #define MSIX_CFG(x) (0x8 + (4 * (x))) 26 27 #define MSIX_CFG_IACK_EN BIT(3) 28 #define MSIX_CFG_IACK BIT(2) 29 #define MSIX_CFG_ENABLE BIT(0) 30 31 /* Address map */ 32 #define RP1_PCIE_APBS_BASE 0x108000 33 34 /* Interrupts */ 35 #define RP1_INT_END 61 36 37 /* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */ 38 extern char __dtbo_rp1_pci_begin[]; 39 extern char __dtbo_rp1_pci_end[]; 40 41 struct rp1_dev { 42 struct pci_dev *pdev; 43 struct irq_domain *domain; 44 struct irq_data *pcie_irqds[64]; 45 void __iomem *bar1; 46 int ovcs_id; /* overlay changeset id */ 47 bool level_triggered_irq[RP1_INT_END]; 48 }; 49 50 static void msix_cfg_set(struct rp1_dev *rp1, unsigned int hwirq, u32 value) 51 { 52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq)); 53 } 54 55 static void msix_cfg_clr(struct rp1_dev *rp1, unsigned int hwirq, u32 value) 56 { 57 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); 58 } 59 60 static void rp1_mask_irq(struct irq_data *irqd) 61 { 62 struct rp1_dev *rp1 = irqd->domain->host_data; 63 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq]; 64 65 pci_msi_mask_irq(pcie_irqd); 66 } 67 68 static void rp1_unmask_irq(struct irq_data *irqd) 69 { 70 struct rp1_dev *rp1 = irqd->domain->host_data; 71 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq]; 72 73 pci_msi_unmask_irq(pcie_irqd); 74 } 75 76 static int rp1_irq_set_type(struct irq_data *irqd, unsigned int type) 77 { 78 struct rp1_dev *rp1 = irqd->domain->host_data; 79 unsigned int hwirq = (unsigned int)irqd->hwirq; 80 81 switch (type) { 82 case IRQ_TYPE_LEVEL_HIGH: 83 dev_dbg(&rp1->pdev->dev, "MSIX IACK EN for IRQ %u\n", hwirq); 84 msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN); 85 rp1->level_triggered_irq[hwirq] = true; 86 break; 87 case IRQ_TYPE_EDGE_RISING: 88 msix_cfg_clr(rp1, hwirq, MSIX_CFG_IACK_EN); 89 rp1->level_triggered_irq[hwirq] = false; 90 break; 91 default: 92 return -EINVAL; 93 } 94 95 return 0; 96 } 97 98 static struct irq_chip rp1_irq_chip = { 99 .name = "rp1_irq_chip", 100 .irq_mask = rp1_mask_irq, 101 .irq_unmask = rp1_unmask_irq, 102 .irq_set_type = rp1_irq_set_type, 103 }; 104 105 static void rp1_chained_handle_irq(struct irq_desc *desc) 106 { 107 unsigned int hwirq = desc->irq_data.hwirq & RP1_HW_IRQ_MASK; 108 struct rp1_dev *rp1 = irq_desc_get_handler_data(desc); 109 struct irq_chip *chip = irq_desc_get_chip(desc); 110 unsigned int virq; 111 112 chained_irq_enter(chip, desc); 113 114 virq = irq_find_mapping(rp1->domain, hwirq); 115 generic_handle_irq(virq); 116 if (rp1->level_triggered_irq[hwirq]) 117 msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK); 118 119 chained_irq_exit(chip, desc); 120 } 121 122 static int rp1_irq_xlate(struct irq_domain *d, struct device_node *node, 123 const u32 *intspec, unsigned int intsize, 124 unsigned long *out_hwirq, unsigned int *out_type) 125 { 126 struct rp1_dev *rp1 = d->host_data; 127 struct irq_data *pcie_irqd; 128 unsigned long hwirq; 129 int pcie_irq; 130 int ret; 131 132 ret = irq_domain_xlate_twocell(d, node, intspec, intsize, 133 &hwirq, out_type); 134 if (ret) 135 return ret; 136 137 pcie_irq = pci_irq_vector(rp1->pdev, hwirq); 138 pcie_irqd = irq_get_irq_data(pcie_irq); 139 rp1->pcie_irqds[hwirq] = pcie_irqd; 140 *out_hwirq = hwirq; 141 142 return 0; 143 } 144 145 static int rp1_irq_activate(struct irq_domain *d, struct irq_data *irqd, 146 bool reserve) 147 { 148 struct rp1_dev *rp1 = d->host_data; 149 150 msix_cfg_set(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE); 151 152 return 0; 153 } 154 155 static void rp1_irq_deactivate(struct irq_domain *d, struct irq_data *irqd) 156 { 157 struct rp1_dev *rp1 = d->host_data; 158 159 msix_cfg_clr(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE); 160 } 161 162 static const struct irq_domain_ops rp1_domain_ops = { 163 .xlate = rp1_irq_xlate, 164 .activate = rp1_irq_activate, 165 .deactivate = rp1_irq_deactivate, 166 }; 167 168 static void rp1_unregister_interrupts(struct pci_dev *pdev) 169 { 170 struct rp1_dev *rp1 = pci_get_drvdata(pdev); 171 int irq, i; 172 173 if (rp1->domain) { 174 for (i = 0; i < RP1_INT_END; i++) { 175 irq = irq_find_mapping(rp1->domain, i); 176 irq_dispose_mapping(irq); 177 } 178 179 irq_domain_remove(rp1->domain); 180 } 181 182 pci_free_irq_vectors(pdev); 183 } 184 185 static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id) 186 { 187 u32 dtbo_size = __dtbo_rp1_pci_end - __dtbo_rp1_pci_begin; 188 void *dtbo_start = __dtbo_rp1_pci_begin; 189 struct device *dev = &pdev->dev; 190 struct device_node *rp1_node; 191 bool skip_ovl = true; 192 struct rp1_dev *rp1; 193 int err = 0; 194 int i; 195 196 /* 197 * Either use rp1_nexus node if already present in DT, or 198 * set a flag to load it from overlay at runtime 199 */ 200 rp1_node = of_find_node_by_name(NULL, "rp1_nexus"); 201 if (!rp1_node) { 202 rp1_node = dev_of_node(dev); 203 skip_ovl = false; 204 } 205 206 if (!rp1_node) { 207 dev_err(dev, "Missing of_node for device\n"); 208 err = -EINVAL; 209 goto err_put_node; 210 } 211 212 rp1 = devm_kzalloc(&pdev->dev, sizeof(*rp1), GFP_KERNEL); 213 if (!rp1) { 214 err = -ENOMEM; 215 goto err_put_node; 216 } 217 218 rp1->pdev = pdev; 219 220 if (pci_resource_len(pdev, 1) <= 0x10000) { 221 dev_err(&pdev->dev, 222 "Not initialized - is the firmware running?\n"); 223 err = -EINVAL; 224 goto err_put_node; 225 } 226 227 err = pcim_enable_device(pdev); 228 if (err < 0) { 229 err = dev_err_probe(&pdev->dev, err, 230 "Enabling PCI device has failed"); 231 goto err_put_node; 232 } 233 234 rp1->bar1 = pcim_iomap(pdev, 1, 0); 235 if (!rp1->bar1) { 236 dev_err(&pdev->dev, "Cannot map PCI BAR\n"); 237 err = -EIO; 238 goto err_put_node; 239 } 240 241 pci_set_master(pdev); 242 243 err = pci_alloc_irq_vectors(pdev, RP1_INT_END, RP1_INT_END, 244 PCI_IRQ_MSIX); 245 if (err < 0) { 246 err = dev_err_probe(&pdev->dev, err, 247 "Failed to allocate MSI-X vectors\n"); 248 goto err_put_node; 249 } else if (err != RP1_INT_END) { 250 dev_err(&pdev->dev, "Cannot allocate enough interrupts\n"); 251 err = -EINVAL; 252 goto err_put_node; 253 } 254 255 pci_set_drvdata(pdev, rp1); 256 rp1->domain = irq_domain_add_linear(rp1_node, RP1_INT_END, 257 &rp1_domain_ops, rp1); 258 if (!rp1->domain) { 259 dev_err(&pdev->dev, "Error creating IRQ domain\n"); 260 err = -ENOMEM; 261 goto err_unregister_interrupts; 262 } 263 264 for (i = 0; i < RP1_INT_END; i++) { 265 unsigned int irq = irq_create_mapping(rp1->domain, i); 266 267 if (!irq) { 268 dev_err(&pdev->dev, "Failed to create IRQ mapping\n"); 269 err = -EINVAL; 270 goto err_unregister_interrupts; 271 } 272 273 irq_set_chip_and_handler(irq, &rp1_irq_chip, handle_level_irq); 274 irq_set_probe(irq); 275 irq_set_chained_handler_and_data(pci_irq_vector(pdev, i), 276 rp1_chained_handle_irq, rp1); 277 } 278 279 if (!skip_ovl) { 280 err = of_overlay_fdt_apply(dtbo_start, dtbo_size, &rp1->ovcs_id, 281 rp1_node); 282 if (err) 283 goto err_unregister_interrupts; 284 } 285 286 err = of_platform_default_populate(rp1_node, NULL, dev); 287 if (err) { 288 dev_err_probe(&pdev->dev, err, "Error populating devicetree\n"); 289 goto err_unload_overlay; 290 } 291 292 return 0; 293 294 err_unload_overlay: 295 of_overlay_remove(&rp1->ovcs_id); 296 err_unregister_interrupts: 297 rp1_unregister_interrupts(pdev); 298 err_put_node: 299 if (skip_ovl) 300 of_node_put(rp1_node); 301 302 return err; 303 } 304 305 static void rp1_remove(struct pci_dev *pdev) 306 { 307 struct rp1_dev *rp1 = pci_get_drvdata(pdev); 308 struct device *dev = &pdev->dev; 309 310 of_platform_depopulate(dev); 311 of_overlay_remove(&rp1->ovcs_id); 312 rp1_unregister_interrupts(pdev); 313 } 314 315 static const struct pci_device_id dev_id_table[] = { 316 { PCI_DEVICE(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0), }, 317 { } 318 }; 319 MODULE_DEVICE_TABLE(pci, dev_id_table); 320 321 static struct pci_driver rp1_driver = { 322 .name = KBUILD_MODNAME, 323 .id_table = dev_id_table, 324 .probe = rp1_probe, 325 .remove = rp1_remove, 326 }; 327 328 module_pci_driver(rp1_driver); 329 330 MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>"); 331 MODULE_AUTHOR("Andrea della Porta <andrea.porta@suse.com>"); 332 MODULE_DESCRIPTION("RaspberryPi RP1 misc device"); 333 MODULE_LICENSE("GPL"); 334