1 /* 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/types.h> 21 #include <linux/fs.h> 22 #include <linux/uaccess.h> 23 #include <linux/string.h> 24 #include <linux/pci.h> 25 #include <linux/io.h> 26 #include <linux/delay.h> 27 #include <linux/mutex.h> 28 #include <linux/if_ether.h> 29 #include <linux/ctype.h> 30 #include <linux/dmi.h> 31 32 #define PHUB_STATUS 0x00 /* Status Register offset */ 33 #define PHUB_CONTROL 0x04 /* Control Register offset */ 34 #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */ 35 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */ 36 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */ 37 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address 38 offset */ 39 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address 40 offset */ 41 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset 42 (Intel EG20T PCH)*/ 43 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address 44 offset(LAPIS Semicon ML7213) 45 */ 46 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address 47 offset(LAPIS Semicon ML7223) 48 */ 49 50 /* MAX number of INT_REDUCE_CONTROL registers */ 51 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128 52 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801 53 #define PCH_MINOR_NOS 1 54 #define CLKCFG_CAN_50MHZ 0x12000000 55 #define CLKCFG_CANCLK_MASK 0xFF000000 56 #define CLKCFG_UART_MASK 0xFFFFFF 57 58 /* CM-iTC */ 59 #define CLKCFG_UART_48MHZ (1 << 16) 60 #define CLKCFG_BAUDDIV (2 << 20) 61 #define CLKCFG_PLL2VCO (8 << 9) 62 #define CLKCFG_UARTCLKSEL (1 << 18) 63 64 /* Macros for ML7213 */ 65 #define PCI_VENDOR_ID_ROHM 0x10db 66 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 67 68 /* Macros for ML7223 */ 69 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */ 70 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */ 71 72 /* Macros for ML7831 */ 73 #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801 74 75 /* SROM ACCESS Macro */ 76 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1)) 77 78 /* Registers address offset */ 79 #define PCH_PHUB_ID_REG 0x0000 80 #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004 81 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008 82 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C 83 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010 84 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014 85 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018 86 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020 87 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024 88 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028 89 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C 90 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040 91 #define CLKCFG_REG_OFFSET 0x500 92 #define FUNCSEL_REG_OFFSET 0x508 93 94 #define PCH_PHUB_OROM_SIZE 15360 95 96 /** 97 * struct pch_phub_reg - PHUB register structure 98 * @phub_id_reg: PHUB_ID register val 99 * @q_pri_val_reg: QUEUE_PRI_VAL register val 100 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val 101 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val 102 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val 103 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val 104 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val 105 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val 106 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val 107 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val 108 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val 109 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val 110 * @clkcfg_reg: CLK CFG register val 111 * @funcsel_reg: Function select register value 112 * @pch_phub_base_address: Register base address 113 * @pch_phub_extrom_base_address: external rom base address 114 * @pch_mac_start_address: MAC address area start address 115 * @pch_opt_rom_start_address: Option ROM start address 116 * @ioh_type: Save IOH type 117 * @pdev: pointer to pci device struct 118 */ 119 struct pch_phub_reg { 120 u32 phub_id_reg; 121 u32 q_pri_val_reg; 122 u32 rc_q_maxsize_reg; 123 u32 bri_q_maxsize_reg; 124 u32 comp_resp_timeout_reg; 125 u32 bus_slave_control_reg; 126 u32 deadlock_avoid_type_reg; 127 u32 intpin_reg_wpermit_reg0; 128 u32 intpin_reg_wpermit_reg1; 129 u32 intpin_reg_wpermit_reg2; 130 u32 intpin_reg_wpermit_reg3; 131 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG]; 132 u32 clkcfg_reg; 133 u32 funcsel_reg; 134 void __iomem *pch_phub_base_address; 135 void __iomem *pch_phub_extrom_base_address; 136 u32 pch_mac_start_address; 137 u32 pch_opt_rom_start_address; 138 int ioh_type; 139 struct pci_dev *pdev; 140 }; 141 142 /* SROM SPEC for MAC address assignment offset */ 143 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa}; 144 145 static DEFINE_MUTEX(pch_phub_mutex); 146 147 /** 148 * pch_phub_read_modify_write_reg() - Reading modifying and writing register 149 * @reg_addr_offset: Register offset address value. 150 * @data: Writing value. 151 * @mask: Mask value. 152 */ 153 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip, 154 unsigned int reg_addr_offset, 155 unsigned int data, unsigned int mask) 156 { 157 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; 158 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); 159 } 160 161 /* pch_phub_save_reg_conf - saves register configuration */ 162 static void pch_phub_save_reg_conf(struct pci_dev *pdev) 163 { 164 unsigned int i; 165 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 166 167 void __iomem *p = chip->pch_phub_base_address; 168 169 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); 170 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); 171 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 172 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 173 chip->comp_resp_timeout_reg = 174 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 175 chip->bus_slave_control_reg = 176 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 177 chip->deadlock_avoid_type_reg = 178 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 179 chip->intpin_reg_wpermit_reg0 = 180 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 181 chip->intpin_reg_wpermit_reg1 = 182 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 183 chip->intpin_reg_wpermit_reg2 = 184 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 185 chip->intpin_reg_wpermit_reg3 = 186 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 187 dev_dbg(&pdev->dev, "%s : " 188 "chip->phub_id_reg=%x, " 189 "chip->q_pri_val_reg=%x, " 190 "chip->rc_q_maxsize_reg=%x, " 191 "chip->bri_q_maxsize_reg=%x, " 192 "chip->comp_resp_timeout_reg=%x, " 193 "chip->bus_slave_control_reg=%x, " 194 "chip->deadlock_avoid_type_reg=%x, " 195 "chip->intpin_reg_wpermit_reg0=%x, " 196 "chip->intpin_reg_wpermit_reg1=%x, " 197 "chip->intpin_reg_wpermit_reg2=%x, " 198 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 199 chip->phub_id_reg, 200 chip->q_pri_val_reg, 201 chip->rc_q_maxsize_reg, 202 chip->bri_q_maxsize_reg, 203 chip->comp_resp_timeout_reg, 204 chip->bus_slave_control_reg, 205 chip->deadlock_avoid_type_reg, 206 chip->intpin_reg_wpermit_reg0, 207 chip->intpin_reg_wpermit_reg1, 208 chip->intpin_reg_wpermit_reg2, 209 chip->intpin_reg_wpermit_reg3); 210 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 211 chip->int_reduce_control_reg[i] = 212 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 213 dev_dbg(&pdev->dev, "%s : " 214 "chip->int_reduce_control_reg[%d]=%x\n", 215 __func__, i, chip->int_reduce_control_reg[i]); 216 } 217 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET); 218 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 219 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET); 220 } 221 222 /* pch_phub_restore_reg_conf - restore register configuration */ 223 static void pch_phub_restore_reg_conf(struct pci_dev *pdev) 224 { 225 unsigned int i; 226 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 227 void __iomem *p; 228 p = chip->pch_phub_base_address; 229 230 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG); 231 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG); 232 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 233 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 234 iowrite32(chip->comp_resp_timeout_reg, 235 p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 236 iowrite32(chip->bus_slave_control_reg, 237 p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 238 iowrite32(chip->deadlock_avoid_type_reg, 239 p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 240 iowrite32(chip->intpin_reg_wpermit_reg0, 241 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 242 iowrite32(chip->intpin_reg_wpermit_reg1, 243 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 244 iowrite32(chip->intpin_reg_wpermit_reg2, 245 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 246 iowrite32(chip->intpin_reg_wpermit_reg3, 247 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 248 dev_dbg(&pdev->dev, "%s : " 249 "chip->phub_id_reg=%x, " 250 "chip->q_pri_val_reg=%x, " 251 "chip->rc_q_maxsize_reg=%x, " 252 "chip->bri_q_maxsize_reg=%x, " 253 "chip->comp_resp_timeout_reg=%x, " 254 "chip->bus_slave_control_reg=%x, " 255 "chip->deadlock_avoid_type_reg=%x, " 256 "chip->intpin_reg_wpermit_reg0=%x, " 257 "chip->intpin_reg_wpermit_reg1=%x, " 258 "chip->intpin_reg_wpermit_reg2=%x, " 259 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 260 chip->phub_id_reg, 261 chip->q_pri_val_reg, 262 chip->rc_q_maxsize_reg, 263 chip->bri_q_maxsize_reg, 264 chip->comp_resp_timeout_reg, 265 chip->bus_slave_control_reg, 266 chip->deadlock_avoid_type_reg, 267 chip->intpin_reg_wpermit_reg0, 268 chip->intpin_reg_wpermit_reg1, 269 chip->intpin_reg_wpermit_reg2, 270 chip->intpin_reg_wpermit_reg3); 271 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 272 iowrite32(chip->int_reduce_control_reg[i], 273 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 274 dev_dbg(&pdev->dev, "%s : " 275 "chip->int_reduce_control_reg[%d]=%x\n", 276 __func__, i, chip->int_reduce_control_reg[i]); 277 } 278 279 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET); 280 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 281 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET); 282 } 283 284 /** 285 * pch_phub_read_serial_rom() - Reading Serial ROM 286 * @offset_address: Serial ROM offset address to read. 287 * @data: Read buffer for specified Serial ROM value. 288 */ 289 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip, 290 unsigned int offset_address, u8 *data) 291 { 292 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 293 offset_address; 294 295 *data = ioread8(mem_addr); 296 } 297 298 /** 299 * pch_phub_write_serial_rom() - Writing Serial ROM 300 * @offset_address: Serial ROM offset address. 301 * @data: Serial ROM value to write. 302 */ 303 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip, 304 unsigned int offset_address, u8 data) 305 { 306 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 307 (offset_address & PCH_WORD_ADDR_MASK); 308 int i; 309 unsigned int word_data; 310 unsigned int pos; 311 unsigned int mask; 312 pos = (offset_address % 4) * 8; 313 mask = ~(0xFF << pos); 314 315 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE, 316 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 317 318 word_data = ioread32(mem_addr); 319 iowrite32((word_data & mask) | (u32)data << pos, mem_addr); 320 321 i = 0; 322 while (ioread8(chip->pch_phub_extrom_base_address + 323 PHUB_STATUS) != 0x00) { 324 msleep(1); 325 if (i == PHUB_TIMEOUT) 326 return -ETIMEDOUT; 327 i++; 328 } 329 330 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE, 331 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 332 333 return 0; 334 } 335 336 /** 337 * pch_phub_read_serial_rom_val() - Read Serial ROM value 338 * @offset_address: Serial ROM address offset value. 339 * @data: Serial ROM value to read. 340 */ 341 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip, 342 unsigned int offset_address, u8 *data) 343 { 344 unsigned int mem_addr; 345 346 mem_addr = chip->pch_mac_start_address + 347 pch_phub_mac_offset[offset_address]; 348 349 pch_phub_read_serial_rom(chip, mem_addr, data); 350 } 351 352 /** 353 * pch_phub_write_serial_rom_val() - writing Serial ROM value 354 * @offset_address: Serial ROM address offset value. 355 * @data: Serial ROM value. 356 */ 357 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip, 358 unsigned int offset_address, u8 data) 359 { 360 int retval; 361 unsigned int mem_addr; 362 363 mem_addr = chip->pch_mac_start_address + 364 pch_phub_mac_offset[offset_address]; 365 366 retval = pch_phub_write_serial_rom(chip, mem_addr, data); 367 368 return retval; 369 } 370 371 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration 372 * for Gigabit Ethernet MAC address 373 */ 374 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip) 375 { 376 int retval; 377 378 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc); 379 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10); 380 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01); 381 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02); 382 383 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00); 384 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00); 385 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00); 386 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80); 387 388 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc); 389 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10); 390 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01); 391 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18); 392 393 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc); 394 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10); 395 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01); 396 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19); 397 398 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc); 399 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10); 400 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01); 401 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a); 402 403 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01); 404 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00); 405 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00); 406 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00); 407 408 return retval; 409 } 410 411 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration 412 * for Gigabit Ethernet MAC address 413 */ 414 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip) 415 { 416 int retval; 417 u32 offset_addr; 418 419 offset_addr = 0x200; 420 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc); 421 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00); 422 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40); 423 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02); 424 425 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00); 426 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00); 427 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00); 428 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80); 429 430 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc); 431 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00); 432 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40); 433 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18); 434 435 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc); 436 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00); 437 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40); 438 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19); 439 440 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc); 441 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00); 442 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40); 443 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a); 444 445 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01); 446 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00); 447 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00); 448 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00); 449 450 return retval; 451 } 452 453 /** 454 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address 455 * @offset_address: Gigabit Ethernet MAC address offset value. 456 * @data: Buffer of the Gigabit Ethernet MAC address value. 457 */ 458 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 459 { 460 int i; 461 for (i = 0; i < ETH_ALEN; i++) 462 pch_phub_read_serial_rom_val(chip, i, &data[i]); 463 } 464 465 /** 466 * pch_phub_write_gbe_mac_addr() - Write MAC address 467 * @offset_address: Gigabit Ethernet MAC address offset value. 468 * @data: Gigabit Ethernet MAC address value. 469 */ 470 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 471 { 472 int retval; 473 int i; 474 475 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/ 476 retval = pch_phub_gbe_serial_rom_conf(chip); 477 else /* ML7223 */ 478 retval = pch_phub_gbe_serial_rom_conf_mp(chip); 479 if (retval) 480 return retval; 481 482 for (i = 0; i < ETH_ALEN; i++) { 483 retval = pch_phub_write_serial_rom_val(chip, i, data[i]); 484 if (retval) 485 return retval; 486 } 487 488 return retval; 489 } 490 491 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj, 492 struct bin_attribute *attr, char *buf, 493 loff_t off, size_t count) 494 { 495 unsigned int rom_signature; 496 unsigned char rom_length; 497 unsigned int tmp; 498 unsigned int addr_offset; 499 unsigned int orom_size; 500 int ret; 501 int err; 502 ssize_t rom_size; 503 504 struct pch_phub_reg *chip = 505 dev_get_drvdata(container_of(kobj, struct device, kobj)); 506 507 ret = mutex_lock_interruptible(&pch_phub_mutex); 508 if (ret) { 509 err = -ERESTARTSYS; 510 goto return_err_nomutex; 511 } 512 513 /* Get Rom signature */ 514 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 515 if (!chip->pch_phub_extrom_base_address) 516 goto exrom_map_err; 517 518 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address, 519 (unsigned char *)&rom_signature); 520 rom_signature &= 0xff; 521 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1, 522 (unsigned char *)&tmp); 523 rom_signature |= (tmp & 0xff) << 8; 524 if (rom_signature == 0xAA55) { 525 pch_phub_read_serial_rom(chip, 526 chip->pch_opt_rom_start_address + 2, 527 &rom_length); 528 orom_size = rom_length * 512; 529 if (orom_size < off) { 530 addr_offset = 0; 531 goto return_ok; 532 } 533 if (orom_size < count) { 534 addr_offset = 0; 535 goto return_ok; 536 } 537 538 for (addr_offset = 0; addr_offset < count; addr_offset++) { 539 pch_phub_read_serial_rom(chip, 540 chip->pch_opt_rom_start_address + addr_offset + off, 541 &buf[addr_offset]); 542 } 543 } else { 544 err = -ENODATA; 545 goto return_err; 546 } 547 return_ok: 548 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 549 mutex_unlock(&pch_phub_mutex); 550 return addr_offset; 551 552 return_err: 553 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 554 exrom_map_err: 555 mutex_unlock(&pch_phub_mutex); 556 return_err_nomutex: 557 return err; 558 } 559 560 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj, 561 struct bin_attribute *attr, 562 char *buf, loff_t off, size_t count) 563 { 564 int err; 565 unsigned int addr_offset; 566 int ret; 567 ssize_t rom_size; 568 struct pch_phub_reg *chip = 569 dev_get_drvdata(container_of(kobj, struct device, kobj)); 570 571 ret = mutex_lock_interruptible(&pch_phub_mutex); 572 if (ret) 573 return -ERESTARTSYS; 574 575 if (off > PCH_PHUB_OROM_SIZE) { 576 addr_offset = 0; 577 goto return_ok; 578 } 579 if (count > PCH_PHUB_OROM_SIZE) { 580 addr_offset = 0; 581 goto return_ok; 582 } 583 584 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 585 if (!chip->pch_phub_extrom_base_address) { 586 err = -ENOMEM; 587 goto exrom_map_err; 588 } 589 590 for (addr_offset = 0; addr_offset < count; addr_offset++) { 591 if (PCH_PHUB_OROM_SIZE < off + addr_offset) 592 goto return_ok; 593 594 ret = pch_phub_write_serial_rom(chip, 595 chip->pch_opt_rom_start_address + addr_offset + off, 596 buf[addr_offset]); 597 if (ret) { 598 err = ret; 599 goto return_err; 600 } 601 } 602 603 return_ok: 604 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 605 mutex_unlock(&pch_phub_mutex); 606 return addr_offset; 607 608 return_err: 609 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 610 611 exrom_map_err: 612 mutex_unlock(&pch_phub_mutex); 613 return err; 614 } 615 616 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr, 617 char *buf) 618 { 619 u8 mac[8]; 620 struct pch_phub_reg *chip = dev_get_drvdata(dev); 621 ssize_t rom_size; 622 623 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 624 if (!chip->pch_phub_extrom_base_address) 625 return -ENOMEM; 626 627 pch_phub_read_gbe_mac_addr(chip, mac); 628 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 629 630 return sprintf(buf, "%pM\n", mac); 631 } 632 633 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr, 634 const char *buf, size_t count) 635 { 636 u8 mac[6]; 637 ssize_t rom_size; 638 struct pch_phub_reg *chip = dev_get_drvdata(dev); 639 640 if (count != 18) 641 return -EINVAL; 642 643 sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", 644 (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3], 645 (u32 *)&mac[4], (u32 *)&mac[5]); 646 647 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 648 if (!chip->pch_phub_extrom_base_address) 649 return -ENOMEM; 650 651 pch_phub_write_gbe_mac_addr(chip, mac); 652 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 653 654 return count; 655 } 656 657 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac); 658 659 static struct bin_attribute pch_bin_attr = { 660 .attr = { 661 .name = "pch_firmware", 662 .mode = S_IRUGO | S_IWUSR, 663 }, 664 .size = PCH_PHUB_OROM_SIZE + 1, 665 .read = pch_phub_bin_read, 666 .write = pch_phub_bin_write, 667 }; 668 669 static int __devinit pch_phub_probe(struct pci_dev *pdev, 670 const struct pci_device_id *id) 671 { 672 int retval; 673 674 int ret; 675 struct pch_phub_reg *chip; 676 677 chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL); 678 if (chip == NULL) 679 return -ENOMEM; 680 681 ret = pci_enable_device(pdev); 682 if (ret) { 683 dev_err(&pdev->dev, 684 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret); 685 goto err_pci_enable_dev; 686 } 687 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, 688 ret); 689 690 ret = pci_request_regions(pdev, KBUILD_MODNAME); 691 if (ret) { 692 dev_err(&pdev->dev, 693 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret); 694 goto err_req_regions; 695 } 696 dev_dbg(&pdev->dev, "%s : " 697 "pci_request_regions returns %d\n", __func__, ret); 698 699 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); 700 701 702 if (chip->pch_phub_base_address == NULL) { 703 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); 704 ret = -ENOMEM; 705 goto err_pci_iomap; 706 } 707 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " 708 "in pch_phub_base_address variable is %p\n", __func__, 709 chip->pch_phub_base_address); 710 711 chip->pdev = pdev; /* Save pci device struct */ 712 713 if (id->driver_data == 1) { /* EG20T PCH */ 714 const char *board_name; 715 716 retval = sysfs_create_file(&pdev->dev.kobj, 717 &dev_attr_pch_mac.attr); 718 if (retval) 719 goto err_sysfs_create; 720 721 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 722 if (retval) 723 goto exit_bin_attr; 724 725 pch_phub_read_modify_write_reg(chip, 726 (unsigned int)CLKCFG_REG_OFFSET, 727 CLKCFG_CAN_50MHZ, 728 CLKCFG_CANCLK_MASK); 729 730 /* quirk for CM-iTC board */ 731 board_name = dmi_get_system_info(DMI_BOARD_NAME); 732 if (board_name && strstr(board_name, "CM-iTC")) 733 pch_phub_read_modify_write_reg(chip, 734 (unsigned int)CLKCFG_REG_OFFSET, 735 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV | 736 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL, 737 CLKCFG_UART_MASK); 738 739 /* set the prefech value */ 740 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 741 /* set the interrupt delay value */ 742 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 743 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 744 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 745 } else if (id->driver_data == 2) { /* ML7213 IOH */ 746 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 747 if (retval) 748 goto err_sysfs_create; 749 /* set the prefech value 750 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a 751 * Device4(SDIO #0,1,2):f 752 * Device6(SATA 2):f 753 * Device8(USB OHCI #0/ USB EHCI #0):a 754 */ 755 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); 756 chip->pch_opt_rom_start_address =\ 757 PCH_PHUB_ROM_START_ADDR_ML7213; 758 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/ 759 /* set the prefech value 760 * Device8(GbE) 761 */ 762 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14); 763 /* set the interrupt delay value */ 764 iowrite32(0x25, chip->pch_phub_base_address + 0x140); 765 chip->pch_opt_rom_start_address =\ 766 PCH_PHUB_ROM_START_ADDR_ML7223; 767 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 768 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/ 769 retval = sysfs_create_file(&pdev->dev.kobj, 770 &dev_attr_pch_mac.attr); 771 if (retval) 772 goto err_sysfs_create; 773 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 774 if (retval) 775 goto exit_bin_attr; 776 /* set the prefech value 777 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a 778 * Device4(SDIO #0,1):f 779 * Device6(SATA 2):f 780 */ 781 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14); 782 chip->pch_opt_rom_start_address =\ 783 PCH_PHUB_ROM_START_ADDR_ML7223; 784 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 785 } else if (id->driver_data == 5) { /* ML7831 */ 786 retval = sysfs_create_file(&pdev->dev.kobj, 787 &dev_attr_pch_mac.attr); 788 if (retval) 789 goto err_sysfs_create; 790 791 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 792 if (retval) 793 goto exit_bin_attr; 794 795 /* set the prefech value */ 796 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 797 /* set the interrupt delay value */ 798 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 799 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 800 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 801 } 802 803 chip->ioh_type = id->driver_data; 804 pci_set_drvdata(pdev, chip); 805 806 return 0; 807 exit_bin_attr: 808 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 809 810 err_sysfs_create: 811 pci_iounmap(pdev, chip->pch_phub_base_address); 812 err_pci_iomap: 813 pci_release_regions(pdev); 814 err_req_regions: 815 pci_disable_device(pdev); 816 err_pci_enable_dev: 817 kfree(chip); 818 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); 819 return ret; 820 } 821 822 static void __devexit pch_phub_remove(struct pci_dev *pdev) 823 { 824 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 825 826 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 827 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); 828 pci_iounmap(pdev, chip->pch_phub_base_address); 829 pci_release_regions(pdev); 830 pci_disable_device(pdev); 831 kfree(chip); 832 } 833 834 #ifdef CONFIG_PM 835 836 static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state) 837 { 838 int ret; 839 840 pch_phub_save_reg_conf(pdev); 841 ret = pci_save_state(pdev); 842 if (ret) { 843 dev_err(&pdev->dev, 844 " %s -pci_save_state returns %d\n", __func__, ret); 845 return ret; 846 } 847 pci_enable_wake(pdev, PCI_D3hot, 0); 848 pci_disable_device(pdev); 849 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 850 851 return 0; 852 } 853 854 static int pch_phub_resume(struct pci_dev *pdev) 855 { 856 int ret; 857 858 pci_set_power_state(pdev, PCI_D0); 859 pci_restore_state(pdev); 860 ret = pci_enable_device(pdev); 861 if (ret) { 862 dev_err(&pdev->dev, 863 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 864 return ret; 865 } 866 867 pci_enable_wake(pdev, PCI_D3hot, 0); 868 pch_phub_restore_reg_conf(pdev); 869 870 return 0; 871 } 872 #else 873 #define pch_phub_suspend NULL 874 #define pch_phub_resume NULL 875 #endif /* CONFIG_PM */ 876 877 static struct pci_device_id pch_phub_pcidev_id[] = { 878 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, }, 879 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, }, 880 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, }, 881 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, }, 882 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5, }, 883 { } 884 }; 885 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id); 886 887 static struct pci_driver pch_phub_driver = { 888 .name = "pch_phub", 889 .id_table = pch_phub_pcidev_id, 890 .probe = pch_phub_probe, 891 .remove = __devexit_p(pch_phub_remove), 892 .suspend = pch_phub_suspend, 893 .resume = pch_phub_resume 894 }; 895 896 module_pci_driver(pch_phub_driver); 897 898 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB"); 899 MODULE_LICENSE("GPL"); 900