1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2019, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/moduleparam.h> 9 #include <linux/kernel.h> 10 #include <linux/device.h> 11 #include <linux/fs.h> 12 #include <linux/errno.h> 13 #include <linux/types.h> 14 #include <linux/fcntl.h> 15 #include <linux/pci.h> 16 #include <linux/poll.h> 17 #include <linux/ioctl.h> 18 #include <linux/cdev.h> 19 #include <linux/sched.h> 20 #include <linux/uuid.h> 21 #include <linux/compat.h> 22 #include <linux/jiffies.h> 23 #include <linux/interrupt.h> 24 25 #include <linux/pm_domain.h> 26 #include <linux/pm_runtime.h> 27 28 #include <linux/mei.h> 29 30 #include "mei_dev.h" 31 #include "client.h" 32 #include "hw-me-regs.h" 33 #include "hw-me.h" 34 35 /* mei_pci_tbl - PCI Device ID Table */ 36 static const struct pci_device_id mei_me_pci_tbl[] = { 37 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 39 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 40 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 48 49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 58 59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 63 64 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 68 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)}, 69 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 77 78 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 79 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 80 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 81 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 82 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)}, 83 84 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 86 87 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 88 89 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 90 91 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 92 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 93 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)}, 98 99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 100 101 /* required last entry */ 102 {0, } 103 }; 104 105 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 106 107 #ifdef CONFIG_PM 108 static inline void mei_me_set_pm_domain(struct mei_device *dev); 109 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 110 #else 111 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 112 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 113 #endif /* CONFIG_PM */ 114 115 /** 116 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 117 * 118 * @pdev: PCI device structure 119 * @cfg: per generation config 120 * 121 * Return: true if ME Interface is valid, false otherwise 122 */ 123 static bool mei_me_quirk_probe(struct pci_dev *pdev, 124 const struct mei_cfg *cfg) 125 { 126 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 127 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 128 return false; 129 } 130 131 return true; 132 } 133 134 /** 135 * mei_me_probe - Device Initialization Routine 136 * 137 * @pdev: PCI device structure 138 * @ent: entry in kcs_pci_tbl 139 * 140 * Return: 0 on success, <0 on failure. 141 */ 142 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 143 { 144 const struct mei_cfg *cfg; 145 struct mei_device *dev; 146 struct mei_me_hw *hw; 147 unsigned int irqflags; 148 int err; 149 150 cfg = mei_me_get_cfg(ent->driver_data); 151 if (!cfg) 152 return -ENODEV; 153 154 if (!mei_me_quirk_probe(pdev, cfg)) 155 return -ENODEV; 156 157 /* enable pci dev */ 158 err = pcim_enable_device(pdev); 159 if (err) { 160 dev_err(&pdev->dev, "failed to enable pci device.\n"); 161 goto end; 162 } 163 /* set PCI host mastering */ 164 pci_set_master(pdev); 165 /* pci request regions and mapping IO device memory for mei driver */ 166 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 167 if (err) { 168 dev_err(&pdev->dev, "failed to get pci regions.\n"); 169 goto end; 170 } 171 172 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 173 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 174 175 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 176 if (err) 177 err = dma_set_coherent_mask(&pdev->dev, 178 DMA_BIT_MASK(32)); 179 } 180 if (err) { 181 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 182 goto end; 183 } 184 185 /* allocates and initializes the mei dev structure */ 186 dev = mei_me_dev_init(pdev, cfg); 187 if (!dev) { 188 err = -ENOMEM; 189 goto end; 190 } 191 hw = to_me_hw(dev); 192 hw->mem_addr = pcim_iomap_table(pdev)[0]; 193 194 pci_enable_msi(pdev); 195 196 /* request and enable interrupt */ 197 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 198 199 err = request_threaded_irq(pdev->irq, 200 mei_me_irq_quick_handler, 201 mei_me_irq_thread_handler, 202 irqflags, KBUILD_MODNAME, dev); 203 if (err) { 204 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 205 pdev->irq); 206 goto end; 207 } 208 209 if (mei_start(dev)) { 210 dev_err(&pdev->dev, "init hw failure.\n"); 211 err = -ENODEV; 212 goto release_irq; 213 } 214 215 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 216 pm_runtime_use_autosuspend(&pdev->dev); 217 218 err = mei_register(dev, &pdev->dev); 219 if (err) 220 goto stop; 221 222 pci_set_drvdata(pdev, dev); 223 224 /* 225 * MEI requires to resume from runtime suspend mode 226 * in order to perform link reset flow upon system suspend. 227 */ 228 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 229 230 /* 231 * ME maps runtime suspend/resume to D0i states, 232 * hence we need to go around native PCI runtime service which 233 * eventually brings the device into D3cold/hot state, 234 * but the mei device cannot wake up from D3 unlike from D0i3. 235 * To get around the PCI device native runtime pm, 236 * ME uses runtime pm domain handlers which take precedence 237 * over the driver's pm handlers. 238 */ 239 mei_me_set_pm_domain(dev); 240 241 if (mei_pg_is_enabled(dev)) { 242 pm_runtime_put_noidle(&pdev->dev); 243 if (hw->d0i3_supported) 244 pm_runtime_allow(&pdev->dev); 245 } 246 247 dev_dbg(&pdev->dev, "initialization successful.\n"); 248 249 return 0; 250 251 stop: 252 mei_stop(dev); 253 release_irq: 254 mei_cancel_work(dev); 255 mei_disable_interrupts(dev); 256 free_irq(pdev->irq, dev); 257 end: 258 dev_err(&pdev->dev, "initialization failed.\n"); 259 return err; 260 } 261 262 /** 263 * mei_me_shutdown - Device Removal Routine 264 * 265 * @pdev: PCI device structure 266 * 267 * mei_me_shutdown is called from the reboot notifier 268 * it's a simplified version of remove so we go down 269 * faster. 270 */ 271 static void mei_me_shutdown(struct pci_dev *pdev) 272 { 273 struct mei_device *dev; 274 275 dev = pci_get_drvdata(pdev); 276 if (!dev) 277 return; 278 279 dev_dbg(&pdev->dev, "shutdown\n"); 280 mei_stop(dev); 281 282 mei_me_unset_pm_domain(dev); 283 284 mei_disable_interrupts(dev); 285 free_irq(pdev->irq, dev); 286 } 287 288 /** 289 * mei_me_remove - Device Removal Routine 290 * 291 * @pdev: PCI device structure 292 * 293 * mei_me_remove is called by the PCI subsystem to alert the driver 294 * that it should release a PCI device. 295 */ 296 static void mei_me_remove(struct pci_dev *pdev) 297 { 298 struct mei_device *dev; 299 300 dev = pci_get_drvdata(pdev); 301 if (!dev) 302 return; 303 304 if (mei_pg_is_enabled(dev)) 305 pm_runtime_get_noresume(&pdev->dev); 306 307 dev_dbg(&pdev->dev, "stop\n"); 308 mei_stop(dev); 309 310 mei_me_unset_pm_domain(dev); 311 312 mei_disable_interrupts(dev); 313 314 free_irq(pdev->irq, dev); 315 316 mei_deregister(dev); 317 } 318 319 #ifdef CONFIG_PM_SLEEP 320 static int mei_me_pci_suspend(struct device *device) 321 { 322 struct pci_dev *pdev = to_pci_dev(device); 323 struct mei_device *dev = pci_get_drvdata(pdev); 324 325 if (!dev) 326 return -ENODEV; 327 328 dev_dbg(&pdev->dev, "suspend\n"); 329 330 mei_stop(dev); 331 332 mei_disable_interrupts(dev); 333 334 free_irq(pdev->irq, dev); 335 pci_disable_msi(pdev); 336 337 return 0; 338 } 339 340 static int mei_me_pci_resume(struct device *device) 341 { 342 struct pci_dev *pdev = to_pci_dev(device); 343 struct mei_device *dev; 344 unsigned int irqflags; 345 int err; 346 347 dev = pci_get_drvdata(pdev); 348 if (!dev) 349 return -ENODEV; 350 351 pci_enable_msi(pdev); 352 353 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 354 355 /* request and enable interrupt */ 356 err = request_threaded_irq(pdev->irq, 357 mei_me_irq_quick_handler, 358 mei_me_irq_thread_handler, 359 irqflags, KBUILD_MODNAME, dev); 360 361 if (err) { 362 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 363 pdev->irq); 364 return err; 365 } 366 367 err = mei_restart(dev); 368 if (err) 369 return err; 370 371 /* Start timer if stopped in suspend */ 372 schedule_delayed_work(&dev->timer_work, HZ); 373 374 return 0; 375 } 376 #endif /* CONFIG_PM_SLEEP */ 377 378 #ifdef CONFIG_PM 379 static int mei_me_pm_runtime_idle(struct device *device) 380 { 381 struct pci_dev *pdev = to_pci_dev(device); 382 struct mei_device *dev; 383 384 dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n"); 385 386 dev = pci_get_drvdata(pdev); 387 if (!dev) 388 return -ENODEV; 389 if (mei_write_is_idle(dev)) 390 pm_runtime_autosuspend(device); 391 392 return -EBUSY; 393 } 394 395 static int mei_me_pm_runtime_suspend(struct device *device) 396 { 397 struct pci_dev *pdev = to_pci_dev(device); 398 struct mei_device *dev; 399 int ret; 400 401 dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n"); 402 403 dev = pci_get_drvdata(pdev); 404 if (!dev) 405 return -ENODEV; 406 407 mutex_lock(&dev->device_lock); 408 409 if (mei_write_is_idle(dev)) 410 ret = mei_me_pg_enter_sync(dev); 411 else 412 ret = -EAGAIN; 413 414 mutex_unlock(&dev->device_lock); 415 416 dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret); 417 418 if (ret && ret != -EAGAIN) 419 schedule_work(&dev->reset_work); 420 421 return ret; 422 } 423 424 static int mei_me_pm_runtime_resume(struct device *device) 425 { 426 struct pci_dev *pdev = to_pci_dev(device); 427 struct mei_device *dev; 428 int ret; 429 430 dev_dbg(&pdev->dev, "rpm: me: runtime resume\n"); 431 432 dev = pci_get_drvdata(pdev); 433 if (!dev) 434 return -ENODEV; 435 436 mutex_lock(&dev->device_lock); 437 438 ret = mei_me_pg_exit_sync(dev); 439 440 mutex_unlock(&dev->device_lock); 441 442 dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret); 443 444 if (ret) 445 schedule_work(&dev->reset_work); 446 447 return ret; 448 } 449 450 /** 451 * mei_me_set_pm_domain - fill and set pm domain structure for device 452 * 453 * @dev: mei_device 454 */ 455 static inline void mei_me_set_pm_domain(struct mei_device *dev) 456 { 457 struct pci_dev *pdev = to_pci_dev(dev->dev); 458 459 if (pdev->dev.bus && pdev->dev.bus->pm) { 460 dev->pg_domain.ops = *pdev->dev.bus->pm; 461 462 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 463 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 464 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 465 466 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 467 } 468 } 469 470 /** 471 * mei_me_unset_pm_domain - clean pm domain structure for device 472 * 473 * @dev: mei_device 474 */ 475 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 476 { 477 /* stop using pm callbacks if any */ 478 dev_pm_domain_set(dev->dev, NULL); 479 } 480 481 static const struct dev_pm_ops mei_me_pm_ops = { 482 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 483 mei_me_pci_resume) 484 SET_RUNTIME_PM_OPS( 485 mei_me_pm_runtime_suspend, 486 mei_me_pm_runtime_resume, 487 mei_me_pm_runtime_idle) 488 }; 489 490 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 491 #else 492 #define MEI_ME_PM_OPS NULL 493 #endif /* CONFIG_PM */ 494 /* 495 * PCI driver structure 496 */ 497 static struct pci_driver mei_me_driver = { 498 .name = KBUILD_MODNAME, 499 .id_table = mei_me_pci_tbl, 500 .probe = mei_me_probe, 501 .remove = mei_me_remove, 502 .shutdown = mei_me_shutdown, 503 .driver.pm = MEI_ME_PM_OPS, 504 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 505 }; 506 507 module_pci_driver(mei_me_driver); 508 509 MODULE_AUTHOR("Intel Corporation"); 510 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 511 MODULE_LICENSE("GPL v2"); 512