1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 16 #include <linux/pm_domain.h> 17 #include <linux/pm_runtime.h> 18 19 #include <linux/mei.h> 20 21 #include "mei_dev.h" 22 #include "client.h" 23 #include "hw-me-regs.h" 24 #include "hw-me.h" 25 26 /* mei_pci_tbl - PCI Device ID Table */ 27 static const struct pci_device_id mei_me_pci_tbl[] = { 28 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 39 40 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 49 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 54 55 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 68 69 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_CFG)}, 74 75 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 77 78 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 79 80 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 81 82 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 83 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 84 85 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 86 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)}, 87 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH8_CFG)}, 89 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 91 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, 92 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)}, 95 96 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 97 98 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 99 100 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 101 102 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 103 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 104 105 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 106 107 /* required last entry */ 108 {0, } 109 }; 110 111 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 112 113 #ifdef CONFIG_PM 114 static inline void mei_me_set_pm_domain(struct mei_device *dev); 115 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 116 #else 117 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 118 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 119 #endif /* CONFIG_PM */ 120 121 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 122 { 123 struct pci_dev *pdev = to_pci_dev(dev->dev); 124 125 return pci_read_config_dword(pdev, where, val); 126 } 127 128 /** 129 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 130 * 131 * @pdev: PCI device structure 132 * @cfg: per generation config 133 * 134 * Return: true if ME Interface is valid, false otherwise 135 */ 136 static bool mei_me_quirk_probe(struct pci_dev *pdev, 137 const struct mei_cfg *cfg) 138 { 139 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 140 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 141 return false; 142 } 143 144 return true; 145 } 146 147 /** 148 * mei_me_probe - Device Initialization Routine 149 * 150 * @pdev: PCI device structure 151 * @ent: entry in kcs_pci_tbl 152 * 153 * Return: 0 on success, <0 on failure. 154 */ 155 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 156 { 157 const struct mei_cfg *cfg; 158 struct mei_device *dev; 159 struct mei_me_hw *hw; 160 unsigned int irqflags; 161 int err; 162 163 cfg = mei_me_get_cfg(ent->driver_data); 164 if (!cfg) 165 return -ENODEV; 166 167 if (!mei_me_quirk_probe(pdev, cfg)) 168 return -ENODEV; 169 170 /* enable pci dev */ 171 err = pcim_enable_device(pdev); 172 if (err) { 173 dev_err(&pdev->dev, "failed to enable pci device.\n"); 174 goto end; 175 } 176 /* set PCI host mastering */ 177 pci_set_master(pdev); 178 /* pci request regions and mapping IO device memory for mei driver */ 179 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 180 if (err) { 181 dev_err(&pdev->dev, "failed to get pci regions.\n"); 182 goto end; 183 } 184 185 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 186 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 187 188 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 189 if (err) 190 err = dma_set_coherent_mask(&pdev->dev, 191 DMA_BIT_MASK(32)); 192 } 193 if (err) { 194 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 195 goto end; 196 } 197 198 /* allocates and initializes the mei dev structure */ 199 dev = mei_me_dev_init(&pdev->dev, cfg); 200 if (!dev) { 201 err = -ENOMEM; 202 goto end; 203 } 204 hw = to_me_hw(dev); 205 hw->mem_addr = pcim_iomap_table(pdev)[0]; 206 hw->read_fws = mei_me_read_fws; 207 208 pci_enable_msi(pdev); 209 210 hw->irq = pdev->irq; 211 212 /* request and enable interrupt */ 213 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 214 215 err = request_threaded_irq(pdev->irq, 216 mei_me_irq_quick_handler, 217 mei_me_irq_thread_handler, 218 irqflags, KBUILD_MODNAME, dev); 219 if (err) { 220 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 221 pdev->irq); 222 goto end; 223 } 224 225 if (mei_start(dev)) { 226 dev_err(&pdev->dev, "init hw failure.\n"); 227 err = -ENODEV; 228 goto release_irq; 229 } 230 231 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 232 pm_runtime_use_autosuspend(&pdev->dev); 233 234 err = mei_register(dev, &pdev->dev); 235 if (err) 236 goto stop; 237 238 pci_set_drvdata(pdev, dev); 239 240 /* 241 * MEI requires to resume from runtime suspend mode 242 * in order to perform link reset flow upon system suspend. 243 */ 244 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 245 246 /* 247 * ME maps runtime suspend/resume to D0i states, 248 * hence we need to go around native PCI runtime service which 249 * eventually brings the device into D3cold/hot state, 250 * but the mei device cannot wake up from D3 unlike from D0i3. 251 * To get around the PCI device native runtime pm, 252 * ME uses runtime pm domain handlers which take precedence 253 * over the driver's pm handlers. 254 */ 255 mei_me_set_pm_domain(dev); 256 257 if (mei_pg_is_enabled(dev)) { 258 pm_runtime_put_noidle(&pdev->dev); 259 if (hw->d0i3_supported) 260 pm_runtime_allow(&pdev->dev); 261 } 262 263 dev_dbg(&pdev->dev, "initialization successful.\n"); 264 265 return 0; 266 267 stop: 268 mei_stop(dev); 269 release_irq: 270 mei_cancel_work(dev); 271 mei_disable_interrupts(dev); 272 free_irq(pdev->irq, dev); 273 end: 274 dev_err(&pdev->dev, "initialization failed.\n"); 275 return err; 276 } 277 278 /** 279 * mei_me_shutdown - Device Removal Routine 280 * 281 * @pdev: PCI device structure 282 * 283 * mei_me_shutdown is called from the reboot notifier 284 * it's a simplified version of remove so we go down 285 * faster. 286 */ 287 static void mei_me_shutdown(struct pci_dev *pdev) 288 { 289 struct mei_device *dev; 290 291 dev = pci_get_drvdata(pdev); 292 if (!dev) 293 return; 294 295 dev_dbg(&pdev->dev, "shutdown\n"); 296 mei_stop(dev); 297 298 mei_me_unset_pm_domain(dev); 299 300 mei_disable_interrupts(dev); 301 free_irq(pdev->irq, dev); 302 } 303 304 /** 305 * mei_me_remove - Device Removal Routine 306 * 307 * @pdev: PCI device structure 308 * 309 * mei_me_remove is called by the PCI subsystem to alert the driver 310 * that it should release a PCI device. 311 */ 312 static void mei_me_remove(struct pci_dev *pdev) 313 { 314 struct mei_device *dev; 315 316 dev = pci_get_drvdata(pdev); 317 if (!dev) 318 return; 319 320 if (mei_pg_is_enabled(dev)) 321 pm_runtime_get_noresume(&pdev->dev); 322 323 dev_dbg(&pdev->dev, "stop\n"); 324 mei_stop(dev); 325 326 mei_me_unset_pm_domain(dev); 327 328 mei_disable_interrupts(dev); 329 330 free_irq(pdev->irq, dev); 331 332 mei_deregister(dev); 333 } 334 335 #ifdef CONFIG_PM_SLEEP 336 static int mei_me_pci_suspend(struct device *device) 337 { 338 struct pci_dev *pdev = to_pci_dev(device); 339 struct mei_device *dev = pci_get_drvdata(pdev); 340 341 if (!dev) 342 return -ENODEV; 343 344 dev_dbg(&pdev->dev, "suspend\n"); 345 346 mei_stop(dev); 347 348 mei_disable_interrupts(dev); 349 350 free_irq(pdev->irq, dev); 351 pci_disable_msi(pdev); 352 353 return 0; 354 } 355 356 static int mei_me_pci_resume(struct device *device) 357 { 358 struct pci_dev *pdev = to_pci_dev(device); 359 struct mei_device *dev; 360 unsigned int irqflags; 361 int err; 362 363 dev = pci_get_drvdata(pdev); 364 if (!dev) 365 return -ENODEV; 366 367 pci_enable_msi(pdev); 368 369 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 370 371 /* request and enable interrupt */ 372 err = request_threaded_irq(pdev->irq, 373 mei_me_irq_quick_handler, 374 mei_me_irq_thread_handler, 375 irqflags, KBUILD_MODNAME, dev); 376 377 if (err) { 378 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 379 pdev->irq); 380 return err; 381 } 382 383 err = mei_restart(dev); 384 if (err) 385 return err; 386 387 /* Start timer if stopped in suspend */ 388 schedule_delayed_work(&dev->timer_work, HZ); 389 390 return 0; 391 } 392 #endif /* CONFIG_PM_SLEEP */ 393 394 #ifdef CONFIG_PM 395 static int mei_me_pm_runtime_idle(struct device *device) 396 { 397 struct mei_device *dev; 398 399 dev_dbg(device, "rpm: me: runtime_idle\n"); 400 401 dev = dev_get_drvdata(device); 402 if (!dev) 403 return -ENODEV; 404 if (mei_write_is_idle(dev)) 405 pm_runtime_autosuspend(device); 406 407 return -EBUSY; 408 } 409 410 static int mei_me_pm_runtime_suspend(struct device *device) 411 { 412 struct mei_device *dev; 413 int ret; 414 415 dev_dbg(device, "rpm: me: runtime suspend\n"); 416 417 dev = dev_get_drvdata(device); 418 if (!dev) 419 return -ENODEV; 420 421 mutex_lock(&dev->device_lock); 422 423 if (mei_write_is_idle(dev)) 424 ret = mei_me_pg_enter_sync(dev); 425 else 426 ret = -EAGAIN; 427 428 mutex_unlock(&dev->device_lock); 429 430 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 431 432 if (ret && ret != -EAGAIN) 433 schedule_work(&dev->reset_work); 434 435 return ret; 436 } 437 438 static int mei_me_pm_runtime_resume(struct device *device) 439 { 440 struct mei_device *dev; 441 int ret; 442 443 dev_dbg(device, "rpm: me: runtime resume\n"); 444 445 dev = dev_get_drvdata(device); 446 if (!dev) 447 return -ENODEV; 448 449 mutex_lock(&dev->device_lock); 450 451 ret = mei_me_pg_exit_sync(dev); 452 453 mutex_unlock(&dev->device_lock); 454 455 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 456 457 if (ret) 458 schedule_work(&dev->reset_work); 459 460 return ret; 461 } 462 463 /** 464 * mei_me_set_pm_domain - fill and set pm domain structure for device 465 * 466 * @dev: mei_device 467 */ 468 static inline void mei_me_set_pm_domain(struct mei_device *dev) 469 { 470 struct pci_dev *pdev = to_pci_dev(dev->dev); 471 472 if (pdev->dev.bus && pdev->dev.bus->pm) { 473 dev->pg_domain.ops = *pdev->dev.bus->pm; 474 475 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 476 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 477 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 478 479 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 480 } 481 } 482 483 /** 484 * mei_me_unset_pm_domain - clean pm domain structure for device 485 * 486 * @dev: mei_device 487 */ 488 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 489 { 490 /* stop using pm callbacks if any */ 491 dev_pm_domain_set(dev->dev, NULL); 492 } 493 494 static const struct dev_pm_ops mei_me_pm_ops = { 495 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 496 mei_me_pci_resume) 497 SET_RUNTIME_PM_OPS( 498 mei_me_pm_runtime_suspend, 499 mei_me_pm_runtime_resume, 500 mei_me_pm_runtime_idle) 501 }; 502 503 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 504 #else 505 #define MEI_ME_PM_OPS NULL 506 #endif /* CONFIG_PM */ 507 /* 508 * PCI driver structure 509 */ 510 static struct pci_driver mei_me_driver = { 511 .name = KBUILD_MODNAME, 512 .id_table = mei_me_pci_tbl, 513 .probe = mei_me_probe, 514 .remove = mei_me_remove, 515 .shutdown = mei_me_shutdown, 516 .driver.pm = MEI_ME_PM_OPS, 517 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 518 }; 519 520 module_pci_driver(mei_me_driver); 521 522 MODULE_AUTHOR("Intel Corporation"); 523 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 524 MODULE_LICENSE("GPL v2"); 525