1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/sched.h> 15 #include <linux/interrupt.h> 16 17 #include <linux/pm_domain.h> 18 #include <linux/pm_runtime.h> 19 20 #include <linux/mei.h> 21 22 #include "mei_dev.h" 23 #include "client.h" 24 #include "hw-me-regs.h" 25 #include "hw-me.h" 26 #include "mei-trace.h" 27 28 /* mei_pci_tbl - PCI Device ID Table */ 29 static const struct pci_device_id mei_me_pci_tbl[] = { 30 {PCI_DEVICE_DATA(INTEL, MEI_82946GZ, MEI_ME_ICH_CFG)}, 31 {PCI_DEVICE_DATA(INTEL, MEI_82G35, MEI_ME_ICH_CFG)}, 32 {PCI_DEVICE_DATA(INTEL, MEI_82Q965, MEI_ME_ICH_CFG)}, 33 {PCI_DEVICE_DATA(INTEL, MEI_82G965, MEI_ME_ICH_CFG)}, 34 {PCI_DEVICE_DATA(INTEL, MEI_82GM965, MEI_ME_ICH_CFG)}, 35 {PCI_DEVICE_DATA(INTEL, MEI_82GME965, MEI_ME_ICH_CFG)}, 36 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_82Q35, MEI_ME_ICH_CFG)}, 37 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_82G33, MEI_ME_ICH_CFG)}, 38 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_82Q33, MEI_ME_ICH_CFG)}, 39 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_82X38, MEI_ME_ICH_CFG)}, 40 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_3200, MEI_ME_ICH_CFG)}, 41 42 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_6, MEI_ME_ICH_CFG)}, 43 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_7, MEI_ME_ICH_CFG)}, 44 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_8, MEI_ME_ICH_CFG)}, 45 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_9, MEI_ME_ICH_CFG)}, 46 {PCI_DEVICE_DATA(INTEL, MEI_ICH9_10, MEI_ME_ICH_CFG)}, 47 {PCI_DEVICE_DATA(INTEL, MEI_ICH9M_1, MEI_ME_ICH_CFG)}, 48 {PCI_DEVICE_DATA(INTEL, MEI_ICH9M_2, MEI_ME_ICH_CFG)}, 49 {PCI_DEVICE_DATA(INTEL, MEI_ICH9M_3, MEI_ME_ICH_CFG)}, 50 {PCI_DEVICE_DATA(INTEL, MEI_ICH9M_4, MEI_ME_ICH_CFG)}, 51 52 {PCI_DEVICE_DATA(INTEL, MEI_ICH10_1, MEI_ME_ICH10_CFG)}, 53 {PCI_DEVICE_DATA(INTEL, MEI_ICH10_2, MEI_ME_ICH10_CFG)}, 54 {PCI_DEVICE_DATA(INTEL, MEI_ICH10_3, MEI_ME_ICH10_CFG)}, 55 {PCI_DEVICE_DATA(INTEL, MEI_ICH10_4, MEI_ME_ICH10_CFG)}, 56 57 {PCI_DEVICE_DATA(INTEL, MEI_IBXPK_1, MEI_ME_PCH6_CFG)}, 58 {PCI_DEVICE_DATA(INTEL, MEI_IBXPK_2, MEI_ME_PCH6_CFG)}, 59 {PCI_DEVICE_DATA(INTEL, MEI_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 60 {PCI_DEVICE_DATA(INTEL, MEI_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 61 {PCI_DEVICE_DATA(INTEL, MEI_PPT_1, MEI_ME_PCH7_CFG)}, 62 {PCI_DEVICE_DATA(INTEL, MEI_PPT_2, MEI_ME_PCH7_CFG)}, 63 {PCI_DEVICE_DATA(INTEL, MEI_PPT_3, MEI_ME_PCH7_CFG)}, 64 {PCI_DEVICE_DATA(INTEL, MEI_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 65 {PCI_DEVICE_DATA(INTEL, MEI_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 66 {PCI_DEVICE_DATA(INTEL, MEI_LPT_LP, MEI_ME_PCH8_CFG)}, 67 {PCI_DEVICE_DATA(INTEL, MEI_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 68 {PCI_DEVICE_DATA(INTEL, MEI_WPT_LP, MEI_ME_PCH8_CFG)}, 69 {PCI_DEVICE_DATA(INTEL, MEI_WPT_LP_2, MEI_ME_PCH8_CFG)}, 70 71 {PCI_DEVICE_DATA(INTEL, MEI_SPT, MEI_ME_PCH8_CFG)}, 72 {PCI_DEVICE_DATA(INTEL, MEI_SPT_2, MEI_ME_PCH8_CFG)}, 73 {PCI_DEVICE_DATA(INTEL, MEI_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, 74 {PCI_DEVICE_DATA(INTEL, MEI_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 75 {PCI_DEVICE_DATA(INTEL, MEI_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 76 {PCI_DEVICE_DATA(INTEL, MEI_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 77 78 {PCI_DEVICE_DATA(INTEL, MEI_BXT_M, MEI_ME_PCH8_CFG)}, 79 {PCI_DEVICE_DATA(INTEL, MEI_APL_I, MEI_ME_PCH8_CFG)}, 80 81 {PCI_DEVICE_DATA(INTEL, MEI_DNV_IE, MEI_ME_PCH8_CFG)}, 82 83 {PCI_DEVICE_DATA(INTEL, MEI_GLK, MEI_ME_PCH8_CFG)}, 84 85 {PCI_DEVICE_DATA(INTEL, MEI_KBP, MEI_ME_PCH8_CFG)}, 86 {PCI_DEVICE_DATA(INTEL, MEI_KBP_2, MEI_ME_PCH8_CFG)}, 87 {PCI_DEVICE_DATA(INTEL, MEI_KBP_3, MEI_ME_PCH8_CFG)}, 88 89 {PCI_DEVICE_DATA(INTEL, MEI_CNP_LP, MEI_ME_PCH12_CFG)}, 90 {PCI_DEVICE_DATA(INTEL, MEI_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 91 {PCI_DEVICE_DATA(INTEL, MEI_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 92 {PCI_DEVICE_DATA(INTEL, MEI_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, 93 94 {PCI_DEVICE_DATA(INTEL, MEI_CMP_LP, MEI_ME_PCH12_CFG)}, 95 {PCI_DEVICE_DATA(INTEL, MEI_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 96 {PCI_DEVICE_DATA(INTEL, MEI_CMP_V, MEI_ME_PCH12_CFG)}, 97 {PCI_DEVICE_DATA(INTEL, MEI_CMP_H, MEI_ME_PCH12_CFG)}, 98 {PCI_DEVICE_DATA(INTEL, MEI_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, 99 100 {PCI_DEVICE_DATA(INTEL, MEI_ICP_LP, MEI_ME_PCH12_CFG)}, 101 {PCI_DEVICE_DATA(INTEL, MEI_ICP_N, MEI_ME_PCH12_CFG)}, 102 103 {PCI_DEVICE_DATA(INTEL, MEI_TGP_LP, MEI_ME_PCH15_CFG)}, 104 {PCI_DEVICE_DATA(INTEL, MEI_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 105 106 {PCI_DEVICE_DATA(INTEL, MEI_JSP_N, MEI_ME_PCH15_CFG)}, 107 108 {PCI_DEVICE_DATA(INTEL, MEI_MCC, MEI_ME_PCH15_CFG)}, 109 {PCI_DEVICE_DATA(INTEL, MEI_MCC_4, MEI_ME_PCH8_CFG)}, 110 111 {PCI_DEVICE_DATA(INTEL, MEI_CDF, MEI_ME_PCH8_CFG)}, 112 113 {PCI_DEVICE_DATA(INTEL, MEI_EBG, MEI_ME_PCH15_SPS_CFG)}, 114 115 {PCI_DEVICE_DATA(INTEL, MEI_ADP_S, MEI_ME_PCH15_CFG)}, 116 {PCI_DEVICE_DATA(INTEL, MEI_ADP_LP, MEI_ME_PCH15_CFG)}, 117 {PCI_DEVICE_DATA(INTEL, MEI_ADP_P, MEI_ME_PCH15_CFG)}, 118 {PCI_DEVICE_DATA(INTEL, MEI_ADP_N, MEI_ME_PCH15_CFG)}, 119 120 {PCI_DEVICE_DATA(INTEL, MEI_RPL_S, MEI_ME_PCH15_SPS_CFG)}, 121 122 {PCI_DEVICE_DATA(INTEL, MEI_MTL_M, MEI_ME_PCH15_CFG)}, 123 {PCI_DEVICE_DATA(INTEL, MEI_ARL_S, MEI_ME_PCH15_CFG)}, 124 {PCI_DEVICE_DATA(INTEL, MEI_ARL_H, MEI_ME_PCH15_CFG)}, 125 126 {PCI_DEVICE_DATA(INTEL, MEI_LNL_M, MEI_ME_PCH15_CFG)}, 127 128 {PCI_DEVICE_DATA(INTEL, MEI_PTL_H, MEI_ME_PCH15_CFG)}, 129 {PCI_DEVICE_DATA(INTEL, MEI_PTL_P, MEI_ME_PCH15_CFG)}, 130 131 {PCI_DEVICE_DATA(INTEL, MEI_WCL_P, MEI_ME_PCH15_CFG)}, 132 133 {PCI_DEVICE_DATA(INTEL, MEI_NVL_S, MEI_ME_PCH15_CFG)}, 134 {PCI_DEVICE_DATA(INTEL, MEI_NVL_H, MEI_ME_PCH15_CFG)}, 135 136 /* required last entry */ 137 {0, } 138 }; 139 140 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 141 142 #ifdef CONFIG_PM 143 static inline void mei_me_set_pm_domain(struct mei_device *dev); 144 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 145 #else 146 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 147 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 148 #endif /* CONFIG_PM */ 149 150 static int mei_me_read_fws(const struct mei_device *dev, int where, const char *name, u32 *val) 151 { 152 struct pci_dev *pdev = to_pci_dev(dev->parent); 153 int ret; 154 155 ret = pci_read_config_dword(pdev, where, val); 156 trace_mei_pci_cfg_read(&dev->dev, name, where, *val, ret); 157 return pcibios_err_to_errno(ret); 158 } 159 160 /** 161 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 162 * 163 * @pdev: PCI device structure 164 * @cfg: per generation config 165 * 166 * Return: true if ME Interface is valid, false otherwise 167 */ 168 static bool mei_me_quirk_probe(struct pci_dev *pdev, 169 const struct mei_cfg *cfg) 170 { 171 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 172 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 173 return false; 174 } 175 176 return true; 177 } 178 179 /** 180 * mei_me_probe - Device Initialization Routine 181 * 182 * @pdev: PCI device structure 183 * @ent: entry in kcs_pci_tbl 184 * 185 * Return: 0 on success, <0 on failure. 186 */ 187 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 188 { 189 const struct mei_cfg *cfg; 190 struct mei_device *dev; 191 struct mei_me_hw *hw; 192 unsigned int irqflags; 193 int err; 194 195 cfg = mei_me_get_cfg(ent->driver_data); 196 if (!cfg) 197 return -ENODEV; 198 199 if (!mei_me_quirk_probe(pdev, cfg)) 200 return -ENODEV; 201 202 /* enable pci dev */ 203 err = pcim_enable_device(pdev); 204 if (err) { 205 dev_err(&pdev->dev, "failed to enable pci device.\n"); 206 goto end; 207 } 208 /* set PCI host mastering */ 209 pci_set_master(pdev); 210 /* pci request regions and mapping IO device memory for mei driver */ 211 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 212 if (err) { 213 dev_err(&pdev->dev, "failed to get pci regions.\n"); 214 goto end; 215 } 216 217 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 218 if (err) { 219 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 220 goto end; 221 } 222 223 /* allocates and initializes the mei dev structure */ 224 dev = mei_me_dev_init(&pdev->dev, cfg, false); 225 if (!dev) { 226 err = -ENOMEM; 227 goto end; 228 } 229 hw = to_me_hw(dev); 230 hw->mem_addr = pcim_iomap_table(pdev)[0]; 231 hw->read_fws = mei_me_read_fws; 232 233 err = mei_register(dev, &pdev->dev); 234 if (err) 235 goto end; 236 237 pci_enable_msi(pdev); 238 239 hw->irq = pdev->irq; 240 241 /* request and enable interrupt */ 242 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 243 244 err = request_threaded_irq(pdev->irq, 245 mei_me_irq_quick_handler, 246 mei_me_irq_thread_handler, 247 irqflags, KBUILD_MODNAME, dev); 248 if (err) { 249 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 250 pdev->irq); 251 goto deregister; 252 } 253 254 if (mei_start(dev)) { 255 dev_err(&pdev->dev, "init hw failure.\n"); 256 err = -ENODEV; 257 goto deregister; 258 } 259 260 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 261 pm_runtime_use_autosuspend(&pdev->dev); 262 263 pci_set_drvdata(pdev, dev); 264 265 /* 266 * MEI requires to resume from runtime suspend mode 267 * in order to perform link reset flow upon system suspend. 268 */ 269 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 270 271 /* 272 * ME maps runtime suspend/resume to D0i states, 273 * hence we need to go around native PCI runtime service which 274 * eventually brings the device into D3cold/hot state, 275 * but the mei device cannot wake up from D3 unlike from D0i3. 276 * To get around the PCI device native runtime pm, 277 * ME uses runtime pm domain handlers which take precedence 278 * over the driver's pm handlers. 279 */ 280 mei_me_set_pm_domain(dev); 281 282 if (mei_pg_is_enabled(dev)) { 283 pm_runtime_put_noidle(&pdev->dev); 284 if (hw->d0i3_supported) 285 pm_runtime_allow(&pdev->dev); 286 } 287 288 dev_dbg(&pdev->dev, "initialization successful.\n"); 289 290 return 0; 291 292 deregister: 293 mei_cancel_work(dev); 294 mei_disable_interrupts(dev); 295 free_irq(pdev->irq, dev); 296 mei_deregister(dev); 297 end: 298 dev_err(&pdev->dev, "initialization failed.\n"); 299 return err; 300 } 301 302 /** 303 * mei_me_shutdown - Device Removal Routine 304 * 305 * @pdev: PCI device structure 306 * 307 * mei_me_shutdown is called from the reboot notifier 308 * it's a simplified version of remove so we go down 309 * faster. 310 */ 311 static void mei_me_shutdown(struct pci_dev *pdev) 312 { 313 struct mei_device *dev = pci_get_drvdata(pdev); 314 315 dev_dbg(&pdev->dev, "shutdown\n"); 316 mei_stop(dev); 317 318 mei_me_unset_pm_domain(dev); 319 320 mei_disable_interrupts(dev); 321 free_irq(pdev->irq, dev); 322 } 323 324 /** 325 * mei_me_remove - Device Removal Routine 326 * 327 * @pdev: PCI device structure 328 * 329 * mei_me_remove is called by the PCI subsystem to alert the driver 330 * that it should release a PCI device. 331 */ 332 static void mei_me_remove(struct pci_dev *pdev) 333 { 334 struct mei_device *dev = pci_get_drvdata(pdev); 335 336 if (mei_pg_is_enabled(dev)) 337 pm_runtime_get_noresume(&pdev->dev); 338 339 dev_dbg(&pdev->dev, "stop\n"); 340 mei_stop(dev); 341 342 mei_me_unset_pm_domain(dev); 343 344 mei_disable_interrupts(dev); 345 346 free_irq(pdev->irq, dev); 347 348 mei_deregister(dev); 349 } 350 351 #ifdef CONFIG_PM_SLEEP 352 static int mei_me_pci_prepare(struct device *device) 353 { 354 pm_runtime_resume(device); 355 return 0; 356 } 357 358 static int mei_me_pci_suspend(struct device *device) 359 { 360 struct pci_dev *pdev = to_pci_dev(device); 361 struct mei_device *dev = pci_get_drvdata(pdev); 362 363 dev_dbg(&pdev->dev, "suspend\n"); 364 365 mei_stop(dev); 366 367 mei_disable_interrupts(dev); 368 369 free_irq(pdev->irq, dev); 370 pci_disable_msi(pdev); 371 372 return 0; 373 } 374 375 static int mei_me_pci_resume(struct device *device) 376 { 377 struct pci_dev *pdev = to_pci_dev(device); 378 struct mei_device *dev = pci_get_drvdata(pdev); 379 unsigned int irqflags; 380 int err; 381 382 pci_enable_msi(pdev); 383 384 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 385 386 /* request and enable interrupt */ 387 err = request_threaded_irq(pdev->irq, 388 mei_me_irq_quick_handler, 389 mei_me_irq_thread_handler, 390 irqflags, KBUILD_MODNAME, dev); 391 392 if (err) { 393 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 394 pdev->irq); 395 return err; 396 } 397 398 err = mei_restart(dev); 399 if (err) { 400 free_irq(pdev->irq, dev); 401 return err; 402 } 403 404 /* Start timer if stopped in suspend */ 405 schedule_delayed_work(&dev->timer_work, HZ); 406 407 return 0; 408 } 409 410 static void mei_me_pci_complete(struct device *device) 411 { 412 pm_runtime_suspend(device); 413 } 414 #else /* CONFIG_PM_SLEEP */ 415 416 #define mei_me_pci_prepare NULL 417 #define mei_me_pci_complete NULL 418 419 #endif /* !CONFIG_PM_SLEEP */ 420 421 #ifdef CONFIG_PM 422 static int mei_me_pm_runtime_idle(struct device *device) 423 { 424 struct mei_device *dev = dev_get_drvdata(device); 425 426 dev_dbg(device, "rpm: me: runtime_idle\n"); 427 428 if (mei_write_is_idle(dev)) 429 pm_runtime_autosuspend(device); 430 431 return -EBUSY; 432 } 433 434 static int mei_me_pm_runtime_suspend(struct device *device) 435 { 436 struct mei_device *dev = dev_get_drvdata(device); 437 int ret; 438 439 dev_dbg(device, "rpm: me: runtime suspend\n"); 440 441 mutex_lock(&dev->device_lock); 442 443 if (mei_write_is_idle(dev)) 444 ret = mei_me_pg_enter_sync(dev); 445 else 446 ret = -EAGAIN; 447 448 mutex_unlock(&dev->device_lock); 449 450 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 451 452 if (ret && ret != -EAGAIN) 453 schedule_work(&dev->reset_work); 454 455 return ret; 456 } 457 458 static int mei_me_pm_runtime_resume(struct device *device) 459 { 460 struct mei_device *dev = dev_get_drvdata(device); 461 int ret; 462 463 dev_dbg(device, "rpm: me: runtime resume\n"); 464 465 mutex_lock(&dev->device_lock); 466 467 ret = mei_me_pg_exit_sync(dev); 468 469 mutex_unlock(&dev->device_lock); 470 471 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 472 473 if (ret) 474 schedule_work(&dev->reset_work); 475 476 return ret; 477 } 478 479 /** 480 * mei_me_set_pm_domain - fill and set pm domain structure for device 481 * 482 * @dev: mei_device 483 */ 484 static inline void mei_me_set_pm_domain(struct mei_device *dev) 485 { 486 struct pci_dev *pdev = to_pci_dev(dev->parent); 487 488 if (pdev->dev.bus && pdev->dev.bus->pm) { 489 dev->pg_domain.ops = *pdev->dev.bus->pm; 490 491 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 492 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 493 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 494 495 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 496 } 497 } 498 499 /** 500 * mei_me_unset_pm_domain - clean pm domain structure for device 501 * 502 * @dev: mei_device 503 */ 504 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 505 { 506 /* stop using pm callbacks if any */ 507 dev_pm_domain_set(dev->parent, NULL); 508 } 509 510 static const struct dev_pm_ops mei_me_pm_ops = { 511 .prepare = mei_me_pci_prepare, 512 .complete = mei_me_pci_complete, 513 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 514 mei_me_pci_resume) 515 SET_RUNTIME_PM_OPS( 516 mei_me_pm_runtime_suspend, 517 mei_me_pm_runtime_resume, 518 mei_me_pm_runtime_idle) 519 }; 520 521 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 522 #else 523 #define MEI_ME_PM_OPS NULL 524 #endif /* CONFIG_PM */ 525 /* 526 * PCI driver structure 527 */ 528 static struct pci_driver mei_me_driver = { 529 .name = KBUILD_MODNAME, 530 .id_table = mei_me_pci_tbl, 531 .probe = mei_me_probe, 532 .remove = mei_me_remove, 533 .shutdown = mei_me_shutdown, 534 .driver.pm = MEI_ME_PM_OPS, 535 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 536 }; 537 538 module_pci_driver(mei_me_driver); 539 540 MODULE_AUTHOR("Intel Corporation"); 541 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 542 MODULE_LICENSE("GPL v2"); 543