1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 16 #include <linux/pm_domain.h> 17 #include <linux/pm_runtime.h> 18 19 #include <linux/mei.h> 20 21 #include "mei_dev.h" 22 #include "client.h" 23 #include "hw-me-regs.h" 24 #include "hw-me.h" 25 26 /* mei_pci_tbl - PCI Device ID Table */ 27 static const struct pci_device_id mei_me_pci_tbl[] = { 28 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 39 40 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 49 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 54 55 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 68 69 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 75 76 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 77 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 78 79 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 80 81 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 82 83 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, 86 87 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, 91 92 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, 97 98 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 99 100 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 101 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 102 103 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 104 105 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 106 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 107 108 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 109 110 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, 111 112 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, 113 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, 114 115 /* required last entry */ 116 {0, } 117 }; 118 119 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 120 121 #ifdef CONFIG_PM 122 static inline void mei_me_set_pm_domain(struct mei_device *dev); 123 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 124 #else 125 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 126 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 127 #endif /* CONFIG_PM */ 128 129 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 130 { 131 struct pci_dev *pdev = to_pci_dev(dev->dev); 132 133 return pci_read_config_dword(pdev, where, val); 134 } 135 136 /** 137 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 138 * 139 * @pdev: PCI device structure 140 * @cfg: per generation config 141 * 142 * Return: true if ME Interface is valid, false otherwise 143 */ 144 static bool mei_me_quirk_probe(struct pci_dev *pdev, 145 const struct mei_cfg *cfg) 146 { 147 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 148 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 149 return false; 150 } 151 152 return true; 153 } 154 155 /** 156 * mei_me_probe - Device Initialization Routine 157 * 158 * @pdev: PCI device structure 159 * @ent: entry in kcs_pci_tbl 160 * 161 * Return: 0 on success, <0 on failure. 162 */ 163 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 164 { 165 const struct mei_cfg *cfg; 166 struct mei_device *dev; 167 struct mei_me_hw *hw; 168 unsigned int irqflags; 169 int err; 170 171 cfg = mei_me_get_cfg(ent->driver_data); 172 if (!cfg) 173 return -ENODEV; 174 175 if (!mei_me_quirk_probe(pdev, cfg)) 176 return -ENODEV; 177 178 /* enable pci dev */ 179 err = pcim_enable_device(pdev); 180 if (err) { 181 dev_err(&pdev->dev, "failed to enable pci device.\n"); 182 goto end; 183 } 184 /* set PCI host mastering */ 185 pci_set_master(pdev); 186 /* pci request regions and mapping IO device memory for mei driver */ 187 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 188 if (err) { 189 dev_err(&pdev->dev, "failed to get pci regions.\n"); 190 goto end; 191 } 192 193 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 194 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 195 196 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 197 if (err) 198 err = dma_set_coherent_mask(&pdev->dev, 199 DMA_BIT_MASK(32)); 200 } 201 if (err) { 202 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 203 goto end; 204 } 205 206 /* allocates and initializes the mei dev structure */ 207 dev = mei_me_dev_init(&pdev->dev, cfg); 208 if (!dev) { 209 err = -ENOMEM; 210 goto end; 211 } 212 hw = to_me_hw(dev); 213 hw->mem_addr = pcim_iomap_table(pdev)[0]; 214 hw->read_fws = mei_me_read_fws; 215 216 pci_enable_msi(pdev); 217 218 hw->irq = pdev->irq; 219 220 /* request and enable interrupt */ 221 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 222 223 err = request_threaded_irq(pdev->irq, 224 mei_me_irq_quick_handler, 225 mei_me_irq_thread_handler, 226 irqflags, KBUILD_MODNAME, dev); 227 if (err) { 228 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 229 pdev->irq); 230 goto end; 231 } 232 233 if (mei_start(dev)) { 234 dev_err(&pdev->dev, "init hw failure.\n"); 235 err = -ENODEV; 236 goto release_irq; 237 } 238 239 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 240 pm_runtime_use_autosuspend(&pdev->dev); 241 242 err = mei_register(dev, &pdev->dev); 243 if (err) 244 goto stop; 245 246 pci_set_drvdata(pdev, dev); 247 248 /* 249 * MEI requires to resume from runtime suspend mode 250 * in order to perform link reset flow upon system suspend. 251 */ 252 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 253 254 /* 255 * ME maps runtime suspend/resume to D0i states, 256 * hence we need to go around native PCI runtime service which 257 * eventually brings the device into D3cold/hot state, 258 * but the mei device cannot wake up from D3 unlike from D0i3. 259 * To get around the PCI device native runtime pm, 260 * ME uses runtime pm domain handlers which take precedence 261 * over the driver's pm handlers. 262 */ 263 mei_me_set_pm_domain(dev); 264 265 if (mei_pg_is_enabled(dev)) { 266 pm_runtime_put_noidle(&pdev->dev); 267 if (hw->d0i3_supported) 268 pm_runtime_allow(&pdev->dev); 269 } 270 271 dev_dbg(&pdev->dev, "initialization successful.\n"); 272 273 return 0; 274 275 stop: 276 mei_stop(dev); 277 release_irq: 278 mei_cancel_work(dev); 279 mei_disable_interrupts(dev); 280 free_irq(pdev->irq, dev); 281 end: 282 dev_err(&pdev->dev, "initialization failed.\n"); 283 return err; 284 } 285 286 /** 287 * mei_me_shutdown - Device Removal Routine 288 * 289 * @pdev: PCI device structure 290 * 291 * mei_me_shutdown is called from the reboot notifier 292 * it's a simplified version of remove so we go down 293 * faster. 294 */ 295 static void mei_me_shutdown(struct pci_dev *pdev) 296 { 297 struct mei_device *dev; 298 299 dev = pci_get_drvdata(pdev); 300 if (!dev) 301 return; 302 303 dev_dbg(&pdev->dev, "shutdown\n"); 304 mei_stop(dev); 305 306 mei_me_unset_pm_domain(dev); 307 308 mei_disable_interrupts(dev); 309 free_irq(pdev->irq, dev); 310 } 311 312 /** 313 * mei_me_remove - Device Removal Routine 314 * 315 * @pdev: PCI device structure 316 * 317 * mei_me_remove is called by the PCI subsystem to alert the driver 318 * that it should release a PCI device. 319 */ 320 static void mei_me_remove(struct pci_dev *pdev) 321 { 322 struct mei_device *dev; 323 324 dev = pci_get_drvdata(pdev); 325 if (!dev) 326 return; 327 328 if (mei_pg_is_enabled(dev)) 329 pm_runtime_get_noresume(&pdev->dev); 330 331 dev_dbg(&pdev->dev, "stop\n"); 332 mei_stop(dev); 333 334 mei_me_unset_pm_domain(dev); 335 336 mei_disable_interrupts(dev); 337 338 free_irq(pdev->irq, dev); 339 340 mei_deregister(dev); 341 } 342 343 #ifdef CONFIG_PM_SLEEP 344 static int mei_me_pci_suspend(struct device *device) 345 { 346 struct pci_dev *pdev = to_pci_dev(device); 347 struct mei_device *dev = pci_get_drvdata(pdev); 348 349 if (!dev) 350 return -ENODEV; 351 352 dev_dbg(&pdev->dev, "suspend\n"); 353 354 mei_stop(dev); 355 356 mei_disable_interrupts(dev); 357 358 free_irq(pdev->irq, dev); 359 pci_disable_msi(pdev); 360 361 return 0; 362 } 363 364 static int mei_me_pci_resume(struct device *device) 365 { 366 struct pci_dev *pdev = to_pci_dev(device); 367 struct mei_device *dev; 368 unsigned int irqflags; 369 int err; 370 371 dev = pci_get_drvdata(pdev); 372 if (!dev) 373 return -ENODEV; 374 375 pci_enable_msi(pdev); 376 377 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 378 379 /* request and enable interrupt */ 380 err = request_threaded_irq(pdev->irq, 381 mei_me_irq_quick_handler, 382 mei_me_irq_thread_handler, 383 irqflags, KBUILD_MODNAME, dev); 384 385 if (err) { 386 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 387 pdev->irq); 388 return err; 389 } 390 391 err = mei_restart(dev); 392 if (err) 393 return err; 394 395 /* Start timer if stopped in suspend */ 396 schedule_delayed_work(&dev->timer_work, HZ); 397 398 return 0; 399 } 400 #endif /* CONFIG_PM_SLEEP */ 401 402 #ifdef CONFIG_PM 403 static int mei_me_pm_runtime_idle(struct device *device) 404 { 405 struct mei_device *dev; 406 407 dev_dbg(device, "rpm: me: runtime_idle\n"); 408 409 dev = dev_get_drvdata(device); 410 if (!dev) 411 return -ENODEV; 412 if (mei_write_is_idle(dev)) 413 pm_runtime_autosuspend(device); 414 415 return -EBUSY; 416 } 417 418 static int mei_me_pm_runtime_suspend(struct device *device) 419 { 420 struct mei_device *dev; 421 int ret; 422 423 dev_dbg(device, "rpm: me: runtime suspend\n"); 424 425 dev = dev_get_drvdata(device); 426 if (!dev) 427 return -ENODEV; 428 429 mutex_lock(&dev->device_lock); 430 431 if (mei_write_is_idle(dev)) 432 ret = mei_me_pg_enter_sync(dev); 433 else 434 ret = -EAGAIN; 435 436 mutex_unlock(&dev->device_lock); 437 438 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 439 440 if (ret && ret != -EAGAIN) 441 schedule_work(&dev->reset_work); 442 443 return ret; 444 } 445 446 static int mei_me_pm_runtime_resume(struct device *device) 447 { 448 struct mei_device *dev; 449 int ret; 450 451 dev_dbg(device, "rpm: me: runtime resume\n"); 452 453 dev = dev_get_drvdata(device); 454 if (!dev) 455 return -ENODEV; 456 457 mutex_lock(&dev->device_lock); 458 459 ret = mei_me_pg_exit_sync(dev); 460 461 mutex_unlock(&dev->device_lock); 462 463 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 464 465 if (ret) 466 schedule_work(&dev->reset_work); 467 468 return ret; 469 } 470 471 /** 472 * mei_me_set_pm_domain - fill and set pm domain structure for device 473 * 474 * @dev: mei_device 475 */ 476 static inline void mei_me_set_pm_domain(struct mei_device *dev) 477 { 478 struct pci_dev *pdev = to_pci_dev(dev->dev); 479 480 if (pdev->dev.bus && pdev->dev.bus->pm) { 481 dev->pg_domain.ops = *pdev->dev.bus->pm; 482 483 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 484 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 485 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 486 487 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 488 } 489 } 490 491 /** 492 * mei_me_unset_pm_domain - clean pm domain structure for device 493 * 494 * @dev: mei_device 495 */ 496 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 497 { 498 /* stop using pm callbacks if any */ 499 dev_pm_domain_set(dev->dev, NULL); 500 } 501 502 static const struct dev_pm_ops mei_me_pm_ops = { 503 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 504 mei_me_pci_resume) 505 SET_RUNTIME_PM_OPS( 506 mei_me_pm_runtime_suspend, 507 mei_me_pm_runtime_resume, 508 mei_me_pm_runtime_idle) 509 }; 510 511 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 512 #else 513 #define MEI_ME_PM_OPS NULL 514 #endif /* CONFIG_PM */ 515 /* 516 * PCI driver structure 517 */ 518 static struct pci_driver mei_me_driver = { 519 .name = KBUILD_MODNAME, 520 .id_table = mei_me_pci_tbl, 521 .probe = mei_me_probe, 522 .remove = mei_me_remove, 523 .shutdown = mei_me_shutdown, 524 .driver.pm = MEI_ME_PM_OPS, 525 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 526 }; 527 528 module_pci_driver(mei_me_driver); 529 530 MODULE_AUTHOR("Intel Corporation"); 531 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 532 MODULE_LICENSE("GPL v2"); 533