1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/sched.h> 15 #include <linux/interrupt.h> 16 17 #include <linux/pm_domain.h> 18 #include <linux/pm_runtime.h> 19 20 #include <linux/mei.h> 21 22 #include "mei_dev.h" 23 #include "client.h" 24 #include "hw-me-regs.h" 25 #include "hw-me.h" 26 27 /* mei_pci_tbl - PCI Device ID Table */ 28 static const struct pci_device_id mei_me_pci_tbl[] = { 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 40 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 50 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 55 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 69 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 76 77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 79 80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 81 82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 83 84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, 87 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, 92 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, 98 99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)}, 101 102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 104 105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 106 107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 109 110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 111 112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, 113 114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, 115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, 116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)}, 117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)}, 118 119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)}, 120 121 {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)}, 122 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)}, 123 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)}, 124 125 {MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)}, 126 127 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_H, MEI_ME_PCH15_CFG)}, 128 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_P, MEI_ME_PCH15_CFG)}, 129 130 {MEI_PCI_DEVICE(MEI_DEV_ID_WCL_P, MEI_ME_PCH15_CFG)}, 131 132 /* required last entry */ 133 {0, } 134 }; 135 136 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 137 138 #ifdef CONFIG_PM 139 static inline void mei_me_set_pm_domain(struct mei_device *dev); 140 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 141 #else 142 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 143 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 144 #endif /* CONFIG_PM */ 145 146 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 147 { 148 struct pci_dev *pdev = to_pci_dev(dev->parent); 149 150 return pci_read_config_dword(pdev, where, val); 151 } 152 153 /** 154 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 155 * 156 * @pdev: PCI device structure 157 * @cfg: per generation config 158 * 159 * Return: true if ME Interface is valid, false otherwise 160 */ 161 static bool mei_me_quirk_probe(struct pci_dev *pdev, 162 const struct mei_cfg *cfg) 163 { 164 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 165 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 166 return false; 167 } 168 169 return true; 170 } 171 172 /** 173 * mei_me_probe - Device Initialization Routine 174 * 175 * @pdev: PCI device structure 176 * @ent: entry in kcs_pci_tbl 177 * 178 * Return: 0 on success, <0 on failure. 179 */ 180 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 181 { 182 const struct mei_cfg *cfg; 183 struct mei_device *dev; 184 struct mei_me_hw *hw; 185 unsigned int irqflags; 186 int err; 187 188 cfg = mei_me_get_cfg(ent->driver_data); 189 if (!cfg) 190 return -ENODEV; 191 192 if (!mei_me_quirk_probe(pdev, cfg)) 193 return -ENODEV; 194 195 /* enable pci dev */ 196 err = pcim_enable_device(pdev); 197 if (err) { 198 dev_err(&pdev->dev, "failed to enable pci device.\n"); 199 goto end; 200 } 201 /* set PCI host mastering */ 202 pci_set_master(pdev); 203 /* pci request regions and mapping IO device memory for mei driver */ 204 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 205 if (err) { 206 dev_err(&pdev->dev, "failed to get pci regions.\n"); 207 goto end; 208 } 209 210 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 211 if (err) { 212 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 213 goto end; 214 } 215 216 /* allocates and initializes the mei dev structure */ 217 dev = mei_me_dev_init(&pdev->dev, cfg, false); 218 if (!dev) { 219 err = -ENOMEM; 220 goto end; 221 } 222 hw = to_me_hw(dev); 223 hw->mem_addr = pcim_iomap_table(pdev)[0]; 224 hw->read_fws = mei_me_read_fws; 225 226 pci_enable_msi(pdev); 227 228 hw->irq = pdev->irq; 229 230 /* request and enable interrupt */ 231 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 232 233 err = request_threaded_irq(pdev->irq, 234 mei_me_irq_quick_handler, 235 mei_me_irq_thread_handler, 236 irqflags, KBUILD_MODNAME, dev); 237 if (err) { 238 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 239 pdev->irq); 240 goto end; 241 } 242 243 err = mei_register(dev, &pdev->dev); 244 if (err) 245 goto release_irq; 246 247 if (mei_start(dev)) { 248 dev_err(&pdev->dev, "init hw failure.\n"); 249 err = -ENODEV; 250 goto deregister; 251 } 252 253 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 254 pm_runtime_use_autosuspend(&pdev->dev); 255 256 pci_set_drvdata(pdev, dev); 257 258 /* 259 * MEI requires to resume from runtime suspend mode 260 * in order to perform link reset flow upon system suspend. 261 */ 262 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 263 264 /* 265 * ME maps runtime suspend/resume to D0i states, 266 * hence we need to go around native PCI runtime service which 267 * eventually brings the device into D3cold/hot state, 268 * but the mei device cannot wake up from D3 unlike from D0i3. 269 * To get around the PCI device native runtime pm, 270 * ME uses runtime pm domain handlers which take precedence 271 * over the driver's pm handlers. 272 */ 273 mei_me_set_pm_domain(dev); 274 275 if (mei_pg_is_enabled(dev)) { 276 pm_runtime_put_noidle(&pdev->dev); 277 if (hw->d0i3_supported) 278 pm_runtime_allow(&pdev->dev); 279 } 280 281 dev_dbg(&pdev->dev, "initialization successful.\n"); 282 283 return 0; 284 285 deregister: 286 mei_deregister(dev); 287 release_irq: 288 mei_cancel_work(dev); 289 mei_disable_interrupts(dev); 290 free_irq(pdev->irq, dev); 291 end: 292 dev_err(&pdev->dev, "initialization failed.\n"); 293 return err; 294 } 295 296 /** 297 * mei_me_shutdown - Device Removal Routine 298 * 299 * @pdev: PCI device structure 300 * 301 * mei_me_shutdown is called from the reboot notifier 302 * it's a simplified version of remove so we go down 303 * faster. 304 */ 305 static void mei_me_shutdown(struct pci_dev *pdev) 306 { 307 struct mei_device *dev = pci_get_drvdata(pdev); 308 309 dev_dbg(&pdev->dev, "shutdown\n"); 310 mei_stop(dev); 311 312 mei_me_unset_pm_domain(dev); 313 314 mei_disable_interrupts(dev); 315 free_irq(pdev->irq, dev); 316 } 317 318 /** 319 * mei_me_remove - Device Removal Routine 320 * 321 * @pdev: PCI device structure 322 * 323 * mei_me_remove is called by the PCI subsystem to alert the driver 324 * that it should release a PCI device. 325 */ 326 static void mei_me_remove(struct pci_dev *pdev) 327 { 328 struct mei_device *dev = pci_get_drvdata(pdev); 329 330 if (mei_pg_is_enabled(dev)) 331 pm_runtime_get_noresume(&pdev->dev); 332 333 dev_dbg(&pdev->dev, "stop\n"); 334 mei_stop(dev); 335 336 mei_me_unset_pm_domain(dev); 337 338 mei_disable_interrupts(dev); 339 340 free_irq(pdev->irq, dev); 341 342 mei_deregister(dev); 343 } 344 345 #ifdef CONFIG_PM_SLEEP 346 static int mei_me_pci_prepare(struct device *device) 347 { 348 pm_runtime_resume(device); 349 return 0; 350 } 351 352 static int mei_me_pci_suspend(struct device *device) 353 { 354 struct pci_dev *pdev = to_pci_dev(device); 355 struct mei_device *dev = pci_get_drvdata(pdev); 356 357 dev_dbg(&pdev->dev, "suspend\n"); 358 359 mei_stop(dev); 360 361 mei_disable_interrupts(dev); 362 363 free_irq(pdev->irq, dev); 364 pci_disable_msi(pdev); 365 366 return 0; 367 } 368 369 static int mei_me_pci_resume(struct device *device) 370 { 371 struct pci_dev *pdev = to_pci_dev(device); 372 struct mei_device *dev = pci_get_drvdata(pdev); 373 unsigned int irqflags; 374 int err; 375 376 pci_enable_msi(pdev); 377 378 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 379 380 /* request and enable interrupt */ 381 err = request_threaded_irq(pdev->irq, 382 mei_me_irq_quick_handler, 383 mei_me_irq_thread_handler, 384 irqflags, KBUILD_MODNAME, dev); 385 386 if (err) { 387 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 388 pdev->irq); 389 return err; 390 } 391 392 err = mei_restart(dev); 393 if (err) { 394 free_irq(pdev->irq, dev); 395 return err; 396 } 397 398 /* Start timer if stopped in suspend */ 399 schedule_delayed_work(&dev->timer_work, HZ); 400 401 return 0; 402 } 403 404 static void mei_me_pci_complete(struct device *device) 405 { 406 pm_runtime_suspend(device); 407 } 408 #else /* CONFIG_PM_SLEEP */ 409 410 #define mei_me_pci_prepare NULL 411 #define mei_me_pci_complete NULL 412 413 #endif /* !CONFIG_PM_SLEEP */ 414 415 #ifdef CONFIG_PM 416 static int mei_me_pm_runtime_idle(struct device *device) 417 { 418 struct mei_device *dev = dev_get_drvdata(device); 419 420 dev_dbg(device, "rpm: me: runtime_idle\n"); 421 422 if (mei_write_is_idle(dev)) 423 pm_runtime_autosuspend(device); 424 425 return -EBUSY; 426 } 427 428 static int mei_me_pm_runtime_suspend(struct device *device) 429 { 430 struct mei_device *dev = dev_get_drvdata(device); 431 int ret; 432 433 dev_dbg(device, "rpm: me: runtime suspend\n"); 434 435 mutex_lock(&dev->device_lock); 436 437 if (mei_write_is_idle(dev)) 438 ret = mei_me_pg_enter_sync(dev); 439 else 440 ret = -EAGAIN; 441 442 mutex_unlock(&dev->device_lock); 443 444 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 445 446 if (ret && ret != -EAGAIN) 447 schedule_work(&dev->reset_work); 448 449 return ret; 450 } 451 452 static int mei_me_pm_runtime_resume(struct device *device) 453 { 454 struct mei_device *dev = dev_get_drvdata(device); 455 int ret; 456 457 dev_dbg(device, "rpm: me: runtime resume\n"); 458 459 mutex_lock(&dev->device_lock); 460 461 ret = mei_me_pg_exit_sync(dev); 462 463 mutex_unlock(&dev->device_lock); 464 465 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 466 467 if (ret) 468 schedule_work(&dev->reset_work); 469 470 return ret; 471 } 472 473 /** 474 * mei_me_set_pm_domain - fill and set pm domain structure for device 475 * 476 * @dev: mei_device 477 */ 478 static inline void mei_me_set_pm_domain(struct mei_device *dev) 479 { 480 struct pci_dev *pdev = to_pci_dev(dev->parent); 481 482 if (pdev->dev.bus && pdev->dev.bus->pm) { 483 dev->pg_domain.ops = *pdev->dev.bus->pm; 484 485 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 486 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 487 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 488 489 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 490 } 491 } 492 493 /** 494 * mei_me_unset_pm_domain - clean pm domain structure for device 495 * 496 * @dev: mei_device 497 */ 498 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 499 { 500 /* stop using pm callbacks if any */ 501 dev_pm_domain_set(dev->parent, NULL); 502 } 503 504 static const struct dev_pm_ops mei_me_pm_ops = { 505 .prepare = mei_me_pci_prepare, 506 .complete = mei_me_pci_complete, 507 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 508 mei_me_pci_resume) 509 SET_RUNTIME_PM_OPS( 510 mei_me_pm_runtime_suspend, 511 mei_me_pm_runtime_resume, 512 mei_me_pm_runtime_idle) 513 }; 514 515 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 516 #else 517 #define MEI_ME_PM_OPS NULL 518 #endif /* CONFIG_PM */ 519 /* 520 * PCI driver structure 521 */ 522 static struct pci_driver mei_me_driver = { 523 .name = KBUILD_MODNAME, 524 .id_table = mei_me_pci_tbl, 525 .probe = mei_me_probe, 526 .remove = mei_me_remove, 527 .shutdown = mei_me_shutdown, 528 .driver.pm = MEI_ME_PM_OPS, 529 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 530 }; 531 532 module_pci_driver(mei_me_driver); 533 534 MODULE_AUTHOR("Intel Corporation"); 535 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 536 MODULE_LICENSE("GPL v2"); 537