1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2013-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/pci.h> 8 #include <linux/jiffies.h> 9 #include <linux/ktime.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/interrupt.h> 13 #include <linux/pm_runtime.h> 14 15 #include <linux/mei.h> 16 17 #include "mei_dev.h" 18 #include "hw-txe.h" 19 #include "client.h" 20 #include "hbm.h" 21 22 #include "mei-trace.h" 23 24 #define TXE_HBUF_DEPTH (PAYLOAD_SIZE / MEI_SLOT_SIZE) 25 26 /** 27 * mei_txe_reg_read - Reads 32bit data from the txe device 28 * 29 * @base_addr: registers base address 30 * @offset: register offset 31 * 32 * Return: register value 33 */ 34 static inline u32 mei_txe_reg_read(void __iomem *base_addr, 35 unsigned long offset) 36 { 37 return ioread32(base_addr + offset); 38 } 39 40 /** 41 * mei_txe_reg_write - Writes 32bit data to the txe device 42 * 43 * @base_addr: registers base address 44 * @offset: register offset 45 * @value: the value to write 46 */ 47 static inline void mei_txe_reg_write(void __iomem *base_addr, 48 unsigned long offset, u32 value) 49 { 50 iowrite32(value, base_addr + offset); 51 } 52 53 /** 54 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR 55 * 56 * @hw: the txe hardware structure 57 * @offset: register offset 58 * 59 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR 60 * 61 * Return: register value 62 */ 63 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, 64 unsigned long offset) 65 { 66 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); 67 } 68 69 /** 70 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR 71 * 72 * @hw: the txe hardware structure 73 * @offset: register offset 74 * 75 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set 76 * 77 * Return: register value 78 */ 79 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, 80 unsigned long offset) 81 { 82 WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); 83 return mei_txe_sec_reg_read_silent(hw, offset); 84 } 85 /** 86 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR 87 * doesn't check for aliveness 88 * 89 * @hw: the txe hardware structure 90 * @offset: register offset 91 * @value: value to write 92 * 93 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR 94 */ 95 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, 96 unsigned long offset, u32 value) 97 { 98 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); 99 } 100 101 /** 102 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR 103 * 104 * @hw: the txe hardware structure 105 * @offset: register offset 106 * @value: value to write 107 * 108 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set 109 */ 110 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, 111 unsigned long offset, u32 value) 112 { 113 WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); 114 mei_txe_sec_reg_write_silent(hw, offset, value); 115 } 116 /** 117 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR 118 * 119 * @hw: the txe hardware structure 120 * @offset: offset from which to read the data 121 * 122 * Return: the byte read. 123 */ 124 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, 125 unsigned long offset) 126 { 127 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); 128 } 129 130 /** 131 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR 132 * 133 * @hw: the txe hardware structure 134 * @offset: offset from which to write the data 135 * @value: the byte to write 136 */ 137 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, 138 unsigned long offset, u32 value) 139 { 140 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); 141 } 142 143 /** 144 * mei_txe_aliveness_set - request for aliveness change 145 * 146 * @dev: the device structure 147 * @req: requested aliveness value 148 * 149 * Request for aliveness change and returns true if the change is 150 * really needed and false if aliveness is already 151 * in the requested state 152 * 153 * Locking: called under "dev->device_lock" lock 154 * 155 * Return: true if request was send 156 */ 157 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req) 158 { 159 160 struct mei_txe_hw *hw = to_txe_hw(dev); 161 bool do_req = hw->aliveness != req; 162 163 dev_dbg(dev->dev, "Aliveness current=%d request=%d\n", 164 hw->aliveness, req); 165 if (do_req) { 166 dev->pg_event = MEI_PG_EVENT_WAIT; 167 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); 168 } 169 return do_req; 170 } 171 172 173 /** 174 * mei_txe_aliveness_req_get - get aliveness requested register value 175 * 176 * @dev: the device structure 177 * 178 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from 179 * from HICR_HOST_ALIVENESS_REQ register value 180 * 181 * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value 182 */ 183 static u32 mei_txe_aliveness_req_get(struct mei_device *dev) 184 { 185 struct mei_txe_hw *hw = to_txe_hw(dev); 186 u32 reg; 187 188 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); 189 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; 190 } 191 192 /** 193 * mei_txe_aliveness_get - get aliveness response register value 194 * 195 * @dev: the device structure 196 * 197 * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP 198 * register 199 */ 200 static u32 mei_txe_aliveness_get(struct mei_device *dev) 201 { 202 struct mei_txe_hw *hw = to_txe_hw(dev); 203 u32 reg; 204 205 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); 206 return reg & HICR_HOST_ALIVENESS_RESP_ACK; 207 } 208 209 /** 210 * mei_txe_aliveness_poll - waits for aliveness to settle 211 * 212 * @dev: the device structure 213 * @expected: expected aliveness value 214 * 215 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 216 * 217 * Return: 0 if the expected value was received, -ETIME otherwise 218 */ 219 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected) 220 { 221 struct mei_txe_hw *hw = to_txe_hw(dev); 222 ktime_t stop, start; 223 224 start = ktime_get(); 225 stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT)); 226 do { 227 hw->aliveness = mei_txe_aliveness_get(dev); 228 if (hw->aliveness == expected) { 229 dev->pg_event = MEI_PG_EVENT_IDLE; 230 dev_dbg(dev->dev, "aliveness settled after %lld usecs\n", 231 ktime_to_us(ktime_sub(ktime_get(), start))); 232 return 0; 233 } 234 usleep_range(20, 50); 235 } while (ktime_before(ktime_get(), stop)); 236 237 dev->pg_event = MEI_PG_EVENT_IDLE; 238 dev_err(dev->dev, "aliveness timed out\n"); 239 return -ETIME; 240 } 241 242 /** 243 * mei_txe_aliveness_wait - waits for aliveness to settle 244 * 245 * @dev: the device structure 246 * @expected: expected aliveness value 247 * 248 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 249 * 250 * Return: 0 on success and < 0 otherwise 251 */ 252 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected) 253 { 254 struct mei_txe_hw *hw = to_txe_hw(dev); 255 const unsigned long timeout = 256 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT); 257 long err; 258 int ret; 259 260 hw->aliveness = mei_txe_aliveness_get(dev); 261 if (hw->aliveness == expected) 262 return 0; 263 264 mutex_unlock(&dev->device_lock); 265 err = wait_event_timeout(hw->wait_aliveness_resp, 266 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 267 mutex_lock(&dev->device_lock); 268 269 hw->aliveness = mei_txe_aliveness_get(dev); 270 ret = hw->aliveness == expected ? 0 : -ETIME; 271 272 if (ret) 273 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", 274 err, hw->aliveness, dev->pg_event); 275 else 276 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", 277 jiffies_to_msecs(timeout - err), 278 hw->aliveness, dev->pg_event); 279 280 dev->pg_event = MEI_PG_EVENT_IDLE; 281 return ret; 282 } 283 284 /** 285 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete 286 * 287 * @dev: the device structure 288 * @req: requested aliveness value 289 * 290 * Return: 0 on success and < 0 otherwise 291 */ 292 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req) 293 { 294 if (mei_txe_aliveness_set(dev, req)) 295 return mei_txe_aliveness_wait(dev, req); 296 return 0; 297 } 298 299 /** 300 * mei_txe_pg_in_transition - is device now in pg transition 301 * 302 * @dev: the device structure 303 * 304 * Return: true if in pg transition, false otherwise 305 */ 306 static bool mei_txe_pg_in_transition(struct mei_device *dev) 307 { 308 return dev->pg_event == MEI_PG_EVENT_WAIT; 309 } 310 311 /** 312 * mei_txe_pg_is_enabled - detect if PG is supported by HW 313 * 314 * @dev: the device structure 315 * 316 * Return: true is pg supported, false otherwise 317 */ 318 static bool mei_txe_pg_is_enabled(struct mei_device *dev) 319 { 320 return true; 321 } 322 323 /** 324 * mei_txe_pg_state - translate aliveness register value 325 * to the mei power gating state 326 * 327 * @dev: the device structure 328 * 329 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise 330 */ 331 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev) 332 { 333 struct mei_txe_hw *hw = to_txe_hw(dev); 334 335 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; 336 } 337 338 /** 339 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt 340 * 341 * @dev: the device structure 342 */ 343 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev) 344 { 345 struct mei_txe_hw *hw = to_txe_hw(dev); 346 u32 hintmsk; 347 /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */ 348 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); 349 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY; 350 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); 351 } 352 353 /** 354 * mei_txe_input_doorbell_set - sets bit 0 in 355 * SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL. 356 * 357 * @hw: the txe hardware structure 358 */ 359 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) 360 { 361 /* Clear the interrupt cause */ 362 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); 363 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); 364 } 365 366 /** 367 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1 368 * 369 * @hw: the txe hardware structure 370 */ 371 static void mei_txe_output_ready_set(struct mei_txe_hw *hw) 372 { 373 mei_txe_br_reg_write(hw, 374 SICR_SEC_IPC_OUTPUT_STATUS_REG, 375 SEC_IPC_OUTPUT_STATUS_RDY); 376 } 377 378 /** 379 * mei_txe_is_input_ready - check if TXE is ready for receiving data 380 * 381 * @dev: the device structure 382 * 383 * Return: true if INPUT STATUS READY bit is set 384 */ 385 static bool mei_txe_is_input_ready(struct mei_device *dev) 386 { 387 struct mei_txe_hw *hw = to_txe_hw(dev); 388 u32 status; 389 390 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); 391 return !!(SEC_IPC_INPUT_STATUS_RDY & status); 392 } 393 394 /** 395 * mei_txe_intr_clear - clear all interrupts 396 * 397 * @dev: the device structure 398 */ 399 static inline void mei_txe_intr_clear(struct mei_device *dev) 400 { 401 struct mei_txe_hw *hw = to_txe_hw(dev); 402 403 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, 404 SEC_IPC_HOST_INT_STATUS_PENDING); 405 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); 406 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); 407 } 408 409 /** 410 * mei_txe_intr_disable - disable all interrupts 411 * 412 * @dev: the device structure 413 */ 414 static void mei_txe_intr_disable(struct mei_device *dev) 415 { 416 struct mei_txe_hw *hw = to_txe_hw(dev); 417 418 mei_txe_br_reg_write(hw, HHIER_REG, 0); 419 mei_txe_br_reg_write(hw, HIER_REG, 0); 420 } 421 /** 422 * mei_txe_intr_enable - enable all interrupts 423 * 424 * @dev: the device structure 425 */ 426 static void mei_txe_intr_enable(struct mei_device *dev) 427 { 428 struct mei_txe_hw *hw = to_txe_hw(dev); 429 430 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); 431 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); 432 } 433 434 /** 435 * mei_txe_synchronize_irq - wait for pending IRQ handlers 436 * 437 * @dev: the device structure 438 */ 439 static void mei_txe_synchronize_irq(struct mei_device *dev) 440 { 441 struct pci_dev *pdev = to_pci_dev(dev->dev); 442 443 synchronize_irq(pdev->irq); 444 } 445 446 /** 447 * mei_txe_pending_interrupts - check if there are pending interrupts 448 * only Aliveness, Input ready, and output doorbell are of relevance 449 * 450 * @dev: the device structure 451 * 452 * Checks if there are pending interrupts 453 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant 454 * 455 * Return: true if there are pending interrupts 456 */ 457 static bool mei_txe_pending_interrupts(struct mei_device *dev) 458 { 459 460 struct mei_txe_hw *hw = to_txe_hw(dev); 461 bool ret = (hw->intr_cause & (TXE_INTR_READINESS | 462 TXE_INTR_ALIVENESS | 463 TXE_INTR_IN_READY | 464 TXE_INTR_OUT_DB)); 465 466 if (ret) { 467 dev_dbg(dev->dev, 468 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n", 469 !!(hw->intr_cause & TXE_INTR_IN_READY), 470 !!(hw->intr_cause & TXE_INTR_READINESS), 471 !!(hw->intr_cause & TXE_INTR_ALIVENESS), 472 !!(hw->intr_cause & TXE_INTR_OUT_DB)); 473 } 474 return ret; 475 } 476 477 /** 478 * mei_txe_input_payload_write - write a dword to the host buffer 479 * at offset idx 480 * 481 * @dev: the device structure 482 * @idx: index in the host buffer 483 * @value: value 484 */ 485 static void mei_txe_input_payload_write(struct mei_device *dev, 486 unsigned long idx, u32 value) 487 { 488 struct mei_txe_hw *hw = to_txe_hw(dev); 489 490 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + 491 (idx * sizeof(u32)), value); 492 } 493 494 /** 495 * mei_txe_out_data_read - read dword from the device buffer 496 * at offset idx 497 * 498 * @dev: the device structure 499 * @idx: index in the device buffer 500 * 501 * Return: register value at index 502 */ 503 static u32 mei_txe_out_data_read(const struct mei_device *dev, 504 unsigned long idx) 505 { 506 struct mei_txe_hw *hw = to_txe_hw(dev); 507 508 return mei_txe_br_reg_read(hw, 509 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32))); 510 } 511 512 /* Readiness */ 513 514 /** 515 * mei_txe_readiness_set_host_rdy - set host readiness bit 516 * 517 * @dev: the device structure 518 */ 519 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev) 520 { 521 struct mei_txe_hw *hw = to_txe_hw(dev); 522 523 mei_txe_br_reg_write(hw, 524 SICR_HOST_IPC_READINESS_REQ_REG, 525 SICR_HOST_IPC_READINESS_HOST_RDY); 526 } 527 528 /** 529 * mei_txe_readiness_clear - clear host readiness bit 530 * 531 * @dev: the device structure 532 */ 533 static void mei_txe_readiness_clear(struct mei_device *dev) 534 { 535 struct mei_txe_hw *hw = to_txe_hw(dev); 536 537 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, 538 SICR_HOST_IPC_READINESS_RDY_CLR); 539 } 540 /** 541 * mei_txe_readiness_get - Reads and returns 542 * the HICR_SEC_IPC_READINESS register value 543 * 544 * @dev: the device structure 545 * 546 * Return: the HICR_SEC_IPC_READINESS register value 547 */ 548 static u32 mei_txe_readiness_get(struct mei_device *dev) 549 { 550 struct mei_txe_hw *hw = to_txe_hw(dev); 551 552 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 553 } 554 555 556 /** 557 * mei_txe_readiness_is_sec_rdy - check readiness 558 * for HICR_SEC_IPC_READINESS_SEC_RDY 559 * 560 * @readiness: cached readiness state 561 * 562 * Return: true if readiness bit is set 563 */ 564 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness) 565 { 566 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY); 567 } 568 569 /** 570 * mei_txe_hw_is_ready - check if the hw is ready 571 * 572 * @dev: the device structure 573 * 574 * Return: true if sec is ready 575 */ 576 static bool mei_txe_hw_is_ready(struct mei_device *dev) 577 { 578 u32 readiness = mei_txe_readiness_get(dev); 579 580 return mei_txe_readiness_is_sec_rdy(readiness); 581 } 582 583 /** 584 * mei_txe_host_is_ready - check if the host is ready 585 * 586 * @dev: the device structure 587 * 588 * Return: true if host is ready 589 */ 590 static inline bool mei_txe_host_is_ready(struct mei_device *dev) 591 { 592 struct mei_txe_hw *hw = to_txe_hw(dev); 593 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 594 595 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); 596 } 597 598 /** 599 * mei_txe_readiness_wait - wait till readiness settles 600 * 601 * @dev: the device structure 602 * 603 * Return: 0 on success and -ETIME on timeout 604 */ 605 static int mei_txe_readiness_wait(struct mei_device *dev) 606 { 607 if (mei_txe_hw_is_ready(dev)) 608 return 0; 609 610 mutex_unlock(&dev->device_lock); 611 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, 612 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT)); 613 mutex_lock(&dev->device_lock); 614 if (!dev->recvd_hw_ready) { 615 dev_err(dev->dev, "wait for readiness failed\n"); 616 return -ETIME; 617 } 618 619 dev->recvd_hw_ready = false; 620 return 0; 621 } 622 623 static const struct mei_fw_status mei_txe_fw_sts = { 624 .count = 2, 625 .status[0] = PCI_CFG_TXE_FW_STS0, 626 .status[1] = PCI_CFG_TXE_FW_STS1 627 }; 628 629 /** 630 * mei_txe_fw_status - read fw status register from pci config space 631 * 632 * @dev: mei device 633 * @fw_status: fw status register values 634 * 635 * Return: 0 on success, error otherwise 636 */ 637 static int mei_txe_fw_status(struct mei_device *dev, 638 struct mei_fw_status *fw_status) 639 { 640 const struct mei_fw_status *fw_src = &mei_txe_fw_sts; 641 struct pci_dev *pdev = to_pci_dev(dev->dev); 642 int ret; 643 int i; 644 645 if (!fw_status) 646 return -EINVAL; 647 648 fw_status->count = fw_src->count; 649 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { 650 ret = pci_read_config_dword(pdev, fw_src->status[i], 651 &fw_status->status[i]); 652 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", 653 fw_src->status[i], 654 fw_status->status[i]); 655 if (ret) 656 return ret; 657 } 658 659 return 0; 660 } 661 662 /** 663 * mei_txe_hw_config - configure hardware at the start of the devices 664 * 665 * @dev: the device structure 666 * 667 * Configure hardware at the start of the device should be done only 668 * once at the device probe time 669 * 670 * Return: always 0 671 */ 672 static int mei_txe_hw_config(struct mei_device *dev) 673 { 674 675 struct mei_txe_hw *hw = to_txe_hw(dev); 676 677 hw->aliveness = mei_txe_aliveness_get(dev); 678 hw->readiness = mei_txe_readiness_get(dev); 679 680 dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", 681 hw->aliveness, hw->readiness); 682 683 return 0; 684 } 685 686 /** 687 * mei_txe_write - writes a message to device. 688 * 689 * @dev: the device structure 690 * @hdr: header of message 691 * @hdr_len: header length in bytes - must multiplication of a slot (4bytes) 692 * @data: payload 693 * @data_len: paylead length in bytes 694 * 695 * Return: 0 if success, < 0 - otherwise. 696 */ 697 static int mei_txe_write(struct mei_device *dev, 698 const void *hdr, size_t hdr_len, 699 const void *data, size_t data_len) 700 { 701 struct mei_txe_hw *hw = to_txe_hw(dev); 702 unsigned long rem; 703 const u32 *reg_buf; 704 u32 slots = TXE_HBUF_DEPTH; 705 u32 dw_cnt; 706 unsigned long i, j; 707 708 if (WARN_ON(!hdr || !data || hdr_len & 0x3)) 709 return -EINVAL; 710 711 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); 712 713 dw_cnt = mei_data2slots(hdr_len + data_len); 714 if (dw_cnt > slots) 715 return -EMSGSIZE; 716 717 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) 718 return -EAGAIN; 719 720 /* Enable Input Ready Interrupt. */ 721 mei_txe_input_ready_interrupt_enable(dev); 722 723 if (!mei_txe_is_input_ready(dev)) { 724 char fw_sts_str[MEI_FW_STATUS_STR_SZ]; 725 726 mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ); 727 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str); 728 return -EAGAIN; 729 } 730 731 reg_buf = hdr; 732 for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++) 733 mei_txe_input_payload_write(dev, i, reg_buf[i]); 734 735 reg_buf = data; 736 for (j = 0; j < data_len / MEI_SLOT_SIZE; j++) 737 mei_txe_input_payload_write(dev, i + j, reg_buf[j]); 738 739 rem = data_len & 0x3; 740 if (rem > 0) { 741 u32 reg = 0; 742 743 memcpy(®, (const u8 *)data + data_len - rem, rem); 744 mei_txe_input_payload_write(dev, i + j, reg); 745 } 746 747 /* after each write the whole buffer is consumed */ 748 hw->slots = 0; 749 750 /* Set Input-Doorbell */ 751 mei_txe_input_doorbell_set(hw); 752 753 return 0; 754 } 755 756 /** 757 * mei_txe_hbuf_depth - mimics the me hbuf circular buffer 758 * 759 * @dev: the device structure 760 * 761 * Return: the TXE_HBUF_DEPTH 762 */ 763 static u32 mei_txe_hbuf_depth(const struct mei_device *dev) 764 { 765 return TXE_HBUF_DEPTH; 766 } 767 768 /** 769 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer 770 * 771 * @dev: the device structure 772 * 773 * Return: always TXE_HBUF_DEPTH 774 */ 775 static int mei_txe_hbuf_empty_slots(struct mei_device *dev) 776 { 777 struct mei_txe_hw *hw = to_txe_hw(dev); 778 779 return hw->slots; 780 } 781 782 /** 783 * mei_txe_count_full_read_slots - mimics the me device circular buffer 784 * 785 * @dev: the device structure 786 * 787 * Return: always buffer size in dwords count 788 */ 789 static int mei_txe_count_full_read_slots(struct mei_device *dev) 790 { 791 /* read buffers has static size */ 792 return TXE_HBUF_DEPTH; 793 } 794 795 /** 796 * mei_txe_read_hdr - read message header which is always in 4 first bytes 797 * 798 * @dev: the device structure 799 * 800 * Return: mei message header 801 */ 802 803 static u32 mei_txe_read_hdr(const struct mei_device *dev) 804 { 805 return mei_txe_out_data_read(dev, 0); 806 } 807 /** 808 * mei_txe_read - reads a message from the txe device. 809 * 810 * @dev: the device structure 811 * @buf: message buffer will be written 812 * @len: message size will be read 813 * 814 * Return: -EINVAL on error wrong argument and 0 on success 815 */ 816 static int mei_txe_read(struct mei_device *dev, 817 unsigned char *buf, unsigned long len) 818 { 819 820 struct mei_txe_hw *hw = to_txe_hw(dev); 821 u32 *reg_buf, reg; 822 u32 rem; 823 u32 i; 824 825 if (WARN_ON(!buf || !len)) 826 return -EINVAL; 827 828 reg_buf = (u32 *)buf; 829 rem = len & 0x3; 830 831 dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n", 832 len, mei_txe_out_data_read(dev, 0)); 833 834 for (i = 0; i < len / MEI_SLOT_SIZE; i++) { 835 /* skip header: index starts from 1 */ 836 reg = mei_txe_out_data_read(dev, i + 1); 837 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg); 838 *reg_buf++ = reg; 839 } 840 841 if (rem) { 842 reg = mei_txe_out_data_read(dev, i + 1); 843 memcpy(reg_buf, ®, rem); 844 } 845 846 mei_txe_output_ready_set(hw); 847 return 0; 848 } 849 850 /** 851 * mei_txe_hw_reset - resets host and fw. 852 * 853 * @dev: the device structure 854 * @intr_enable: if interrupt should be enabled after reset. 855 * 856 * Return: 0 on success and < 0 in case of error 857 */ 858 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable) 859 { 860 struct mei_txe_hw *hw = to_txe_hw(dev); 861 862 u32 aliveness_req; 863 /* 864 * read input doorbell to ensure consistency between Bridge and SeC 865 * return value might be garbage return 866 */ 867 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); 868 869 aliveness_req = mei_txe_aliveness_req_get(dev); 870 hw->aliveness = mei_txe_aliveness_get(dev); 871 872 /* Disable interrupts in this stage we will poll */ 873 mei_txe_intr_disable(dev); 874 875 /* 876 * If Aliveness Request and Aliveness Response are not equal then 877 * wait for them to be equal 878 * Since we might have interrupts disabled - poll for it 879 */ 880 if (aliveness_req != hw->aliveness) 881 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) { 882 dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n"); 883 return -EIO; 884 } 885 886 /* 887 * If Aliveness Request and Aliveness Response are set then clear them 888 */ 889 if (aliveness_req) { 890 mei_txe_aliveness_set(dev, 0); 891 if (mei_txe_aliveness_poll(dev, 0) < 0) { 892 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); 893 return -EIO; 894 } 895 } 896 897 /* 898 * Set readiness RDY_CLR bit 899 */ 900 mei_txe_readiness_clear(dev); 901 902 return 0; 903 } 904 905 /** 906 * mei_txe_hw_start - start the hardware after reset 907 * 908 * @dev: the device structure 909 * 910 * Return: 0 on success an error code otherwise 911 */ 912 static int mei_txe_hw_start(struct mei_device *dev) 913 { 914 struct mei_txe_hw *hw = to_txe_hw(dev); 915 int ret; 916 917 u32 hisr; 918 919 /* bring back interrupts */ 920 mei_txe_intr_enable(dev); 921 922 ret = mei_txe_readiness_wait(dev); 923 if (ret < 0) { 924 dev_err(dev->dev, "waiting for readiness failed\n"); 925 return ret; 926 } 927 928 /* 929 * If HISR.INT2_STS interrupt status bit is set then clear it. 930 */ 931 hisr = mei_txe_br_reg_read(hw, HISR_REG); 932 if (hisr & HISR_INT_2_STS) 933 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); 934 935 /* Clear the interrupt cause of OutputDoorbell */ 936 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); 937 938 ret = mei_txe_aliveness_set_sync(dev, 1); 939 if (ret < 0) { 940 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); 941 return ret; 942 } 943 944 pm_runtime_set_active(dev->dev); 945 946 /* enable input ready interrupts: 947 * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK 948 */ 949 mei_txe_input_ready_interrupt_enable(dev); 950 951 952 /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */ 953 mei_txe_output_ready_set(hw); 954 955 /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY 956 */ 957 mei_txe_readiness_set_host_rdy(dev); 958 959 return 0; 960 } 961 962 /** 963 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into 964 * single bit mask and acknowledge the interrupts 965 * 966 * @dev: the device structure 967 * @do_ack: acknowledge interrupts 968 * 969 * Return: true if found interrupts to process. 970 */ 971 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack) 972 { 973 struct mei_txe_hw *hw = to_txe_hw(dev); 974 u32 hisr; 975 u32 hhisr; 976 u32 ipc_isr; 977 u32 aliveness; 978 bool generated; 979 980 /* read interrupt registers */ 981 hhisr = mei_txe_br_reg_read(hw, HHISR_REG); 982 generated = (hhisr & IPC_HHIER_MSK); 983 if (!generated) 984 goto out; 985 986 hisr = mei_txe_br_reg_read(hw, HISR_REG); 987 988 aliveness = mei_txe_aliveness_get(dev); 989 if (hhisr & IPC_HHIER_SEC && aliveness) { 990 ipc_isr = mei_txe_sec_reg_read_silent(hw, 991 SEC_IPC_HOST_INT_STATUS_REG); 992 } else { 993 ipc_isr = 0; 994 hhisr &= ~IPC_HHIER_SEC; 995 } 996 997 generated = generated || 998 (hisr & HISR_INT_STS_MSK) || 999 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING); 1000 1001 if (generated && do_ack) { 1002 /* Save the interrupt causes */ 1003 hw->intr_cause |= hisr & HISR_INT_STS_MSK; 1004 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY) 1005 hw->intr_cause |= TXE_INTR_IN_READY; 1006 1007 1008 mei_txe_intr_disable(dev); 1009 /* Clear the interrupts in hierarchy: 1010 * IPC and Bridge, than the High Level */ 1011 mei_txe_sec_reg_write_silent(hw, 1012 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr); 1013 mei_txe_br_reg_write(hw, HISR_REG, hisr); 1014 mei_txe_br_reg_write(hw, HHISR_REG, hhisr); 1015 } 1016 1017 out: 1018 return generated; 1019 } 1020 1021 /** 1022 * mei_txe_irq_quick_handler - The ISR of the MEI device 1023 * 1024 * @irq: The irq number 1025 * @dev_id: pointer to the device structure 1026 * 1027 * Return: IRQ_WAKE_THREAD if interrupt is designed for the device 1028 * IRQ_NONE otherwise 1029 */ 1030 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id) 1031 { 1032 struct mei_device *dev = dev_id; 1033 1034 if (mei_txe_check_and_ack_intrs(dev, true)) 1035 return IRQ_WAKE_THREAD; 1036 return IRQ_NONE; 1037 } 1038 1039 1040 /** 1041 * mei_txe_irq_thread_handler - txe interrupt thread 1042 * 1043 * @irq: The irq number 1044 * @dev_id: pointer to the device structure 1045 * 1046 * Return: IRQ_HANDLED 1047 */ 1048 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id) 1049 { 1050 struct mei_device *dev = (struct mei_device *) dev_id; 1051 struct mei_txe_hw *hw = to_txe_hw(dev); 1052 struct list_head cmpl_list; 1053 s32 slots; 1054 int rets = 0; 1055 1056 dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", 1057 mei_txe_br_reg_read(hw, HHISR_REG), 1058 mei_txe_br_reg_read(hw, HISR_REG), 1059 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); 1060 1061 1062 /* initialize our complete list */ 1063 mutex_lock(&dev->device_lock); 1064 INIT_LIST_HEAD(&cmpl_list); 1065 1066 if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) 1067 mei_txe_check_and_ack_intrs(dev, true); 1068 1069 /* show irq events */ 1070 mei_txe_pending_interrupts(dev); 1071 1072 hw->aliveness = mei_txe_aliveness_get(dev); 1073 hw->readiness = mei_txe_readiness_get(dev); 1074 1075 /* Readiness: 1076 * Detection of TXE driver going through reset 1077 * or TXE driver resetting the HECI interface. 1078 */ 1079 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { 1080 dev_dbg(dev->dev, "Readiness Interrupt was received...\n"); 1081 1082 /* Check if SeC is going through reset */ 1083 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { 1084 dev_dbg(dev->dev, "we need to start the dev.\n"); 1085 dev->recvd_hw_ready = true; 1086 } else { 1087 dev->recvd_hw_ready = false; 1088 if (dev->dev_state != MEI_DEV_RESETTING) { 1089 1090 dev_warn(dev->dev, "FW not ready: resetting.\n"); 1091 schedule_work(&dev->reset_work); 1092 goto end; 1093 1094 } 1095 } 1096 wake_up(&dev->wait_hw_ready); 1097 } 1098 1099 /************************************************************/ 1100 /* Check interrupt cause: 1101 * Aliveness: Detection of SeC acknowledge of host request that 1102 * it remain alive or host cancellation of that request. 1103 */ 1104 1105 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { 1106 /* Clear the interrupt cause */ 1107 dev_dbg(dev->dev, 1108 "Aliveness Interrupt: Status: %d\n", hw->aliveness); 1109 dev->pg_event = MEI_PG_EVENT_RECEIVED; 1110 if (waitqueue_active(&hw->wait_aliveness_resp)) 1111 wake_up(&hw->wait_aliveness_resp); 1112 } 1113 1114 1115 /* Output Doorbell: 1116 * Detection of SeC having sent output to host 1117 */ 1118 slots = mei_count_full_read_slots(dev); 1119 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { 1120 /* Read from TXE */ 1121 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); 1122 if (rets && 1123 (dev->dev_state != MEI_DEV_RESETTING && 1124 dev->dev_state != MEI_DEV_POWER_DOWN)) { 1125 dev_err(dev->dev, 1126 "mei_irq_read_handler ret = %d.\n", rets); 1127 1128 schedule_work(&dev->reset_work); 1129 goto end; 1130 } 1131 } 1132 /* Input Ready: Detection if host can write to SeC */ 1133 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { 1134 dev->hbuf_is_ready = true; 1135 hw->slots = TXE_HBUF_DEPTH; 1136 } 1137 1138 if (hw->aliveness && dev->hbuf_is_ready) { 1139 /* get the real register value */ 1140 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1141 rets = mei_irq_write_handler(dev, &cmpl_list); 1142 if (rets && rets != -EMSGSIZE) 1143 dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n", 1144 rets); 1145 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1146 } 1147 1148 mei_irq_compl_handler(dev, &cmpl_list); 1149 1150 end: 1151 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); 1152 1153 mutex_unlock(&dev->device_lock); 1154 1155 mei_enable_interrupts(dev); 1156 return IRQ_HANDLED; 1157 } 1158 1159 static const struct mei_hw_ops mei_txe_hw_ops = { 1160 1161 .host_is_ready = mei_txe_host_is_ready, 1162 1163 .fw_status = mei_txe_fw_status, 1164 .pg_state = mei_txe_pg_state, 1165 1166 .hw_is_ready = mei_txe_hw_is_ready, 1167 .hw_reset = mei_txe_hw_reset, 1168 .hw_config = mei_txe_hw_config, 1169 .hw_start = mei_txe_hw_start, 1170 1171 .pg_in_transition = mei_txe_pg_in_transition, 1172 .pg_is_enabled = mei_txe_pg_is_enabled, 1173 1174 .intr_clear = mei_txe_intr_clear, 1175 .intr_enable = mei_txe_intr_enable, 1176 .intr_disable = mei_txe_intr_disable, 1177 .synchronize_irq = mei_txe_synchronize_irq, 1178 1179 .hbuf_free_slots = mei_txe_hbuf_empty_slots, 1180 .hbuf_is_ready = mei_txe_is_input_ready, 1181 .hbuf_depth = mei_txe_hbuf_depth, 1182 1183 .write = mei_txe_write, 1184 1185 .rdbuf_full_slots = mei_txe_count_full_read_slots, 1186 .read_hdr = mei_txe_read_hdr, 1187 1188 .read = mei_txe_read, 1189 1190 }; 1191 1192 /** 1193 * mei_txe_dev_init - allocates and initializes txe hardware specific structure 1194 * 1195 * @pdev: pci device 1196 * 1197 * Return: struct mei_device * on success or NULL 1198 */ 1199 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev) 1200 { 1201 struct mei_device *dev; 1202 struct mei_txe_hw *hw; 1203 1204 dev = devm_kzalloc(&pdev->dev, sizeof(*dev) + sizeof(*hw), GFP_KERNEL); 1205 if (!dev) 1206 return NULL; 1207 1208 mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); 1209 1210 hw = to_txe_hw(dev); 1211 1212 init_waitqueue_head(&hw->wait_aliveness_resp); 1213 1214 return dev; 1215 } 1216 1217 /** 1218 * mei_txe_setup_satt2 - SATT2 configuration for DMA support. 1219 * 1220 * @dev: the device structure 1221 * @addr: physical address start of the range 1222 * @range: physical range size 1223 * 1224 * Return: 0 on success an error code otherwise 1225 */ 1226 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range) 1227 { 1228 struct mei_txe_hw *hw = to_txe_hw(dev); 1229 1230 u32 lo32 = lower_32_bits(addr); 1231 u32 hi32 = upper_32_bits(addr); 1232 u32 ctrl; 1233 1234 /* SATT is limited to 36 Bits */ 1235 if (hi32 & ~0xF) 1236 return -EINVAL; 1237 1238 /* SATT has to be 16Byte aligned */ 1239 if (lo32 & 0xF) 1240 return -EINVAL; 1241 1242 /* SATT range has to be 4Bytes aligned */ 1243 if (range & 0x4) 1244 return -EINVAL; 1245 1246 /* SATT is limited to 32 MB range*/ 1247 if (range > SATT_RANGE_MAX) 1248 return -EINVAL; 1249 1250 ctrl = SATT2_CTRL_VALID_MSK; 1251 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT; 1252 1253 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); 1254 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); 1255 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); 1256 dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", 1257 range, lo32, ctrl); 1258 1259 return 0; 1260 } 1261