1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2013-2014, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/jiffies.h> 19 #include <linux/delay.h> 20 #include <linux/kthread.h> 21 #include <linux/irqreturn.h> 22 23 #include <linux/mei.h> 24 25 #include "mei_dev.h" 26 #include "hw-txe.h" 27 #include "client.h" 28 #include "hbm.h" 29 30 /** 31 * mei_txe_reg_read - Reads 32bit data from the device 32 * 33 * @base_addr: registers base address 34 * @offset: register offset 35 * 36 */ 37 static inline u32 mei_txe_reg_read(void __iomem *base_addr, 38 unsigned long offset) 39 { 40 return ioread32(base_addr + offset); 41 } 42 43 /** 44 * mei_txe_reg_write - Writes 32bit data to the device 45 * 46 * @base_addr: registers base address 47 * @offset: register offset 48 * @value: the value to write 49 */ 50 static inline void mei_txe_reg_write(void __iomem *base_addr, 51 unsigned long offset, u32 value) 52 { 53 iowrite32(value, base_addr + offset); 54 } 55 56 /** 57 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR 58 * 59 * @dev: the device structure 60 * @offset: register offset 61 * 62 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR 63 */ 64 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, 65 unsigned long offset) 66 { 67 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); 68 } 69 70 /** 71 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR 72 * 73 * @dev: the device structure 74 * @offset: register offset 75 * 76 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set 77 */ 78 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, 79 unsigned long offset) 80 { 81 WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); 82 return mei_txe_sec_reg_read_silent(hw, offset); 83 } 84 /** 85 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR 86 * doesn't check for aliveness 87 * 88 * @dev: the device structure 89 * @offset: register offset 90 * @value: value to write 91 * 92 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR 93 */ 94 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, 95 unsigned long offset, u32 value) 96 { 97 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); 98 } 99 100 /** 101 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR 102 * 103 * @dev: the device structure 104 * @offset: register offset 105 * @value: value to write 106 * 107 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set 108 */ 109 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, 110 unsigned long offset, u32 value) 111 { 112 WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); 113 mei_txe_sec_reg_write_silent(hw, offset, value); 114 } 115 /** 116 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR 117 * 118 * @hw: the device structure 119 * @offset: offset from which to read the data 120 * 121 */ 122 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, 123 unsigned long offset) 124 { 125 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); 126 } 127 128 /** 129 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR 130 * 131 * @hw: the device structure 132 * @offset: offset from which to write the data 133 * @value: the byte to write 134 */ 135 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, 136 unsigned long offset, u32 value) 137 { 138 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); 139 } 140 141 /** 142 * mei_txe_aliveness_set - request for aliveness change 143 * 144 * @dev: the device structure 145 * @req: requested aliveness value 146 * 147 * Request for aliveness change and returns true if the change is 148 * really needed and false if aliveness is already 149 * in the requested state 150 * Requires device lock to be held 151 */ 152 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req) 153 { 154 155 struct mei_txe_hw *hw = to_txe_hw(dev); 156 bool do_req = hw->aliveness != req; 157 158 dev_dbg(&dev->pdev->dev, "Aliveness current=%d request=%d\n", 159 hw->aliveness, req); 160 if (do_req) { 161 hw->recvd_aliveness = false; 162 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); 163 } 164 return do_req; 165 } 166 167 168 /** 169 * mei_txe_aliveness_req_get - get aliveness requested register value 170 * 171 * @dev: the device structure 172 * 173 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from 174 * from HICR_HOST_ALIVENESS_REQ register value 175 */ 176 static u32 mei_txe_aliveness_req_get(struct mei_device *dev) 177 { 178 struct mei_txe_hw *hw = to_txe_hw(dev); 179 u32 reg; 180 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); 181 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; 182 } 183 184 /** 185 * mei_txe_aliveness_get - get aliveness response register value 186 * @dev: the device structure 187 * 188 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit 189 * from HICR_HOST_ALIVENESS_RESP register value 190 */ 191 static u32 mei_txe_aliveness_get(struct mei_device *dev) 192 { 193 struct mei_txe_hw *hw = to_txe_hw(dev); 194 u32 reg; 195 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); 196 return reg & HICR_HOST_ALIVENESS_RESP_ACK; 197 } 198 199 /** 200 * mei_txe_aliveness_poll - waits for aliveness to settle 201 * 202 * @dev: the device structure 203 * @expected: expected aliveness value 204 * 205 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 206 * returns > 0 if the expected value was received, -ETIME otherwise 207 */ 208 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected) 209 { 210 struct mei_txe_hw *hw = to_txe_hw(dev); 211 int t = 0; 212 213 do { 214 hw->aliveness = mei_txe_aliveness_get(dev); 215 if (hw->aliveness == expected) { 216 dev_dbg(&dev->pdev->dev, 217 "aliveness settled after %d msecs\n", t); 218 return t; 219 } 220 mutex_unlock(&dev->device_lock); 221 msleep(MSEC_PER_SEC / 5); 222 mutex_lock(&dev->device_lock); 223 t += MSEC_PER_SEC / 5; 224 } while (t < SEC_ALIVENESS_WAIT_TIMEOUT); 225 226 dev_err(&dev->pdev->dev, "aliveness timed out\n"); 227 return -ETIME; 228 } 229 230 /** 231 * mei_txe_aliveness_wait - waits for aliveness to settle 232 * 233 * @dev: the device structure 234 * @expected: expected aliveness value 235 * 236 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set 237 * returns returns 0 on success and < 0 otherwise 238 */ 239 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected) 240 { 241 struct mei_txe_hw *hw = to_txe_hw(dev); 242 const unsigned long timeout = 243 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT); 244 long err; 245 int ret; 246 247 hw->aliveness = mei_txe_aliveness_get(dev); 248 if (hw->aliveness == expected) 249 return 0; 250 251 mutex_unlock(&dev->device_lock); 252 err = wait_event_timeout(hw->wait_aliveness, 253 hw->recvd_aliveness, timeout); 254 mutex_lock(&dev->device_lock); 255 256 hw->aliveness = mei_txe_aliveness_get(dev); 257 ret = hw->aliveness == expected ? 0 : -ETIME; 258 259 if (ret) 260 dev_err(&dev->pdev->dev, "aliveness timed out"); 261 else 262 dev_dbg(&dev->pdev->dev, "aliveness settled after %d msecs\n", 263 jiffies_to_msecs(timeout - err)); 264 hw->recvd_aliveness = false; 265 return ret; 266 } 267 268 /** 269 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete 270 * 271 * @dev: the device structure 272 * 273 * returns returns 0 on success and < 0 otherwise 274 */ 275 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req) 276 { 277 if (mei_txe_aliveness_set(dev, req)) 278 return mei_txe_aliveness_wait(dev, req); 279 return 0; 280 } 281 282 /** 283 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt 284 * 285 * @dev: the device structure 286 */ 287 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev) 288 { 289 struct mei_txe_hw *hw = to_txe_hw(dev); 290 u32 hintmsk; 291 /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */ 292 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); 293 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY; 294 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); 295 } 296 297 /** 298 * mei_txe_input_doorbell_set 299 * - Sets bit 0 in SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL. 300 * @dev: the device structure 301 */ 302 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) 303 { 304 /* Clear the interrupt cause */ 305 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); 306 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); 307 } 308 309 /** 310 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1 311 * 312 * @dev: the device structure 313 */ 314 static void mei_txe_output_ready_set(struct mei_txe_hw *hw) 315 { 316 mei_txe_br_reg_write(hw, 317 SICR_SEC_IPC_OUTPUT_STATUS_REG, 318 SEC_IPC_OUTPUT_STATUS_RDY); 319 } 320 321 /** 322 * mei_txe_is_input_ready - check if TXE is ready for receiving data 323 * 324 * @dev: the device structure 325 */ 326 static bool mei_txe_is_input_ready(struct mei_device *dev) 327 { 328 struct mei_txe_hw *hw = to_txe_hw(dev); 329 u32 status; 330 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); 331 return !!(SEC_IPC_INPUT_STATUS_RDY & status); 332 } 333 334 /** 335 * mei_txe_intr_clear - clear all interrupts 336 * 337 * @dev: the device structure 338 */ 339 static inline void mei_txe_intr_clear(struct mei_device *dev) 340 { 341 struct mei_txe_hw *hw = to_txe_hw(dev); 342 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, 343 SEC_IPC_HOST_INT_STATUS_PENDING); 344 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); 345 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); 346 } 347 348 /** 349 * mei_txe_intr_disable - disable all interrupts 350 * 351 * @dev: the device structure 352 */ 353 static void mei_txe_intr_disable(struct mei_device *dev) 354 { 355 struct mei_txe_hw *hw = to_txe_hw(dev); 356 mei_txe_br_reg_write(hw, HHIER_REG, 0); 357 mei_txe_br_reg_write(hw, HIER_REG, 0); 358 } 359 /** 360 * mei_txe_intr_disable - enable all interrupts 361 * 362 * @dev: the device structure 363 */ 364 static void mei_txe_intr_enable(struct mei_device *dev) 365 { 366 struct mei_txe_hw *hw = to_txe_hw(dev); 367 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); 368 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); 369 } 370 371 /** 372 * mei_txe_pending_interrupts - check if there are pending interrupts 373 * only Aliveness, Input ready, and output doorbell are of relevance 374 * 375 * @dev: the device structure 376 * 377 * Checks if there are pending interrupts 378 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant 379 */ 380 static bool mei_txe_pending_interrupts(struct mei_device *dev) 381 { 382 383 struct mei_txe_hw *hw = to_txe_hw(dev); 384 bool ret = (hw->intr_cause & (TXE_INTR_READINESS | 385 TXE_INTR_ALIVENESS | 386 TXE_INTR_IN_READY | 387 TXE_INTR_OUT_DB)); 388 389 if (ret) { 390 dev_dbg(&dev->pdev->dev, 391 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n", 392 !!(hw->intr_cause & TXE_INTR_IN_READY), 393 !!(hw->intr_cause & TXE_INTR_READINESS), 394 !!(hw->intr_cause & TXE_INTR_ALIVENESS), 395 !!(hw->intr_cause & TXE_INTR_OUT_DB)); 396 } 397 return ret; 398 } 399 400 /** 401 * mei_txe_input_payload_write - write a dword to the host buffer 402 * at offset idx 403 * 404 * @dev: the device structure 405 * @idx: index in the host buffer 406 * @value: value 407 */ 408 static void mei_txe_input_payload_write(struct mei_device *dev, 409 unsigned long idx, u32 value) 410 { 411 struct mei_txe_hw *hw = to_txe_hw(dev); 412 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + 413 (idx * sizeof(u32)), value); 414 } 415 416 /** 417 * mei_txe_out_data_read - read dword from the device buffer 418 * at offset idx 419 * 420 * @dev: the device structure 421 * @idx: index in the device buffer 422 * 423 * returns register value at index 424 */ 425 static u32 mei_txe_out_data_read(const struct mei_device *dev, 426 unsigned long idx) 427 { 428 struct mei_txe_hw *hw = to_txe_hw(dev); 429 return mei_txe_br_reg_read(hw, 430 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32))); 431 } 432 433 /* Readiness */ 434 435 /** 436 * mei_txe_readiness_set_host_rdy 437 * 438 * @dev: the device structure 439 */ 440 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev) 441 { 442 struct mei_txe_hw *hw = to_txe_hw(dev); 443 mei_txe_br_reg_write(hw, 444 SICR_HOST_IPC_READINESS_REQ_REG, 445 SICR_HOST_IPC_READINESS_HOST_RDY); 446 } 447 448 /** 449 * mei_txe_readiness_clear 450 * 451 * @dev: the device structure 452 */ 453 static void mei_txe_readiness_clear(struct mei_device *dev) 454 { 455 struct mei_txe_hw *hw = to_txe_hw(dev); 456 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, 457 SICR_HOST_IPC_READINESS_RDY_CLR); 458 } 459 /** 460 * mei_txe_readiness_get - Reads and returns 461 * the HICR_SEC_IPC_READINESS register value 462 * 463 * @dev: the device structure 464 */ 465 static u32 mei_txe_readiness_get(struct mei_device *dev) 466 { 467 struct mei_txe_hw *hw = to_txe_hw(dev); 468 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 469 } 470 471 472 /** 473 * mei_txe_readiness_is_sec_rdy - check readiness 474 * for HICR_SEC_IPC_READINESS_SEC_RDY 475 * 476 * @readiness - cached readiness state 477 */ 478 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness) 479 { 480 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY); 481 } 482 483 /** 484 * mei_txe_hw_is_ready - check if the hw is ready 485 * 486 * @dev: the device structure 487 */ 488 static bool mei_txe_hw_is_ready(struct mei_device *dev) 489 { 490 u32 readiness = mei_txe_readiness_get(dev); 491 return mei_txe_readiness_is_sec_rdy(readiness); 492 } 493 494 /** 495 * mei_txe_host_is_ready - check if the host is ready 496 * 497 * @dev: the device structure 498 */ 499 static inline bool mei_txe_host_is_ready(struct mei_device *dev) 500 { 501 struct mei_txe_hw *hw = to_txe_hw(dev); 502 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); 503 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); 504 } 505 506 /** 507 * mei_txe_readiness_wait - wait till readiness settles 508 * 509 * @dev: the device structure 510 * 511 * returns 0 on success and -ETIME on timeout 512 */ 513 static int mei_txe_readiness_wait(struct mei_device *dev) 514 { 515 if (mei_txe_hw_is_ready(dev)) 516 return 0; 517 518 mutex_unlock(&dev->device_lock); 519 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, 520 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT)); 521 mutex_lock(&dev->device_lock); 522 if (!dev->recvd_hw_ready) { 523 dev_err(&dev->pdev->dev, "wait for readiness failed\n"); 524 return -ETIME; 525 } 526 527 dev->recvd_hw_ready = false; 528 return 0; 529 } 530 531 /** 532 * mei_txe_hw_config - configure hardware at the start of the devices 533 * 534 * @dev: the device structure 535 * 536 * Configure hardware at the start of the device should be done only 537 * once at the device probe time 538 */ 539 static void mei_txe_hw_config(struct mei_device *dev) 540 { 541 542 struct mei_txe_hw *hw = to_txe_hw(dev); 543 /* Doesn't change in runtime */ 544 dev->hbuf_depth = PAYLOAD_SIZE / 4; 545 546 hw->aliveness = mei_txe_aliveness_get(dev); 547 hw->readiness = mei_txe_readiness_get(dev); 548 549 dev_dbg(&dev->pdev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", 550 hw->aliveness, hw->readiness); 551 } 552 553 554 /** 555 * mei_txe_write - writes a message to device. 556 * 557 * @dev: the device structure 558 * @header: header of message 559 * @buf: message buffer will be written 560 * returns 1 if success, 0 - otherwise. 561 */ 562 563 static int mei_txe_write(struct mei_device *dev, 564 struct mei_msg_hdr *header, unsigned char *buf) 565 { 566 struct mei_txe_hw *hw = to_txe_hw(dev); 567 unsigned long rem; 568 unsigned long length; 569 int slots = dev->hbuf_depth; 570 u32 *reg_buf = (u32 *)buf; 571 u32 dw_cnt; 572 int i; 573 574 if (WARN_ON(!header || !buf)) 575 return -EINVAL; 576 577 length = header->length; 578 579 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); 580 581 dw_cnt = mei_data2slots(length); 582 if (dw_cnt > slots) 583 return -EMSGSIZE; 584 585 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) 586 return -EAGAIN; 587 588 /* Enable Input Ready Interrupt. */ 589 mei_txe_input_ready_interrupt_enable(dev); 590 591 if (!mei_txe_is_input_ready(dev)) { 592 dev_err(&dev->pdev->dev, "Input is not ready"); 593 return -EAGAIN; 594 } 595 596 mei_txe_input_payload_write(dev, 0, *((u32 *)header)); 597 598 for (i = 0; i < length / 4; i++) 599 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]); 600 601 rem = length & 0x3; 602 if (rem > 0) { 603 u32 reg = 0; 604 memcpy(®, &buf[length - rem], rem); 605 mei_txe_input_payload_write(dev, i + 1, reg); 606 } 607 608 /* after each write the whole buffer is consumed */ 609 hw->slots = 0; 610 611 /* Set Input-Doorbell */ 612 mei_txe_input_doorbell_set(hw); 613 614 return 0; 615 } 616 617 /** 618 * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer 619 * 620 * @dev: the device structure 621 * 622 * returns the PAYLOAD_SIZE - 4 623 */ 624 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev) 625 { 626 return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr); 627 } 628 629 /** 630 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer 631 * 632 * @dev: the device structure 633 * 634 * returns always hbuf_depth 635 */ 636 static int mei_txe_hbuf_empty_slots(struct mei_device *dev) 637 { 638 struct mei_txe_hw *hw = to_txe_hw(dev); 639 return hw->slots; 640 } 641 642 /** 643 * mei_txe_count_full_read_slots - mimics the me device circular buffer 644 * 645 * @dev: the device structure 646 * 647 * returns always buffer size in dwords count 648 */ 649 static int mei_txe_count_full_read_slots(struct mei_device *dev) 650 { 651 /* read buffers has static size */ 652 return PAYLOAD_SIZE / 4; 653 } 654 655 /** 656 * mei_txe_read_hdr - read message header which is always in 4 first bytes 657 * 658 * @dev: the device structure 659 * 660 * returns mei message header 661 */ 662 663 static u32 mei_txe_read_hdr(const struct mei_device *dev) 664 { 665 return mei_txe_out_data_read(dev, 0); 666 } 667 /** 668 * mei_txe_read - reads a message from the txe device. 669 * 670 * @dev: the device structure 671 * @buf: message buffer will be written 672 * @len: message size will be read 673 * 674 * returns -EINVAL on error wrong argument and 0 on success 675 */ 676 static int mei_txe_read(struct mei_device *dev, 677 unsigned char *buf, unsigned long len) 678 { 679 680 struct mei_txe_hw *hw = to_txe_hw(dev); 681 u32 i; 682 u32 *reg_buf = (u32 *)buf; 683 u32 rem = len & 0x3; 684 685 if (WARN_ON(!buf || !len)) 686 return -EINVAL; 687 688 dev_dbg(&dev->pdev->dev, 689 "buffer-length = %lu buf[0]0x%08X\n", 690 len, mei_txe_out_data_read(dev, 0)); 691 692 for (i = 0; i < len / 4; i++) { 693 /* skip header: index starts from 1 */ 694 u32 reg = mei_txe_out_data_read(dev, i + 1); 695 dev_dbg(&dev->pdev->dev, "buf[%d] = 0x%08X\n", i, reg); 696 *reg_buf++ = reg; 697 } 698 699 if (rem) { 700 u32 reg = mei_txe_out_data_read(dev, i + 1); 701 memcpy(reg_buf, ®, rem); 702 } 703 704 mei_txe_output_ready_set(hw); 705 return 0; 706 } 707 708 /** 709 * mei_txe_hw_reset - resets host and fw. 710 * 711 * @dev: the device structure 712 * @intr_enable: if interrupt should be enabled after reset. 713 * 714 * returns 0 on success and < 0 in case of error 715 */ 716 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable) 717 { 718 struct mei_txe_hw *hw = to_txe_hw(dev); 719 720 u32 aliveness_req; 721 /* 722 * read input doorbell to ensure consistency between Bridge and SeC 723 * return value might be garbage return 724 */ 725 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); 726 727 aliveness_req = mei_txe_aliveness_req_get(dev); 728 hw->aliveness = mei_txe_aliveness_get(dev); 729 730 /* Disable interrupts in this stage we will poll */ 731 mei_txe_intr_disable(dev); 732 733 /* 734 * If Aliveness Request and Aliveness Response are not equal then 735 * wait for them to be equal 736 * Since we might have interrupts disabled - poll for it 737 */ 738 if (aliveness_req != hw->aliveness) 739 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) { 740 dev_err(&dev->pdev->dev, 741 "wait for aliveness settle failed ... bailing out\n"); 742 return -EIO; 743 } 744 745 /* 746 * If Aliveness Request and Aliveness Response are set then clear them 747 */ 748 if (aliveness_req) { 749 mei_txe_aliveness_set(dev, 0); 750 if (mei_txe_aliveness_poll(dev, 0) < 0) { 751 dev_err(&dev->pdev->dev, 752 "wait for aliveness failed ... bailing out\n"); 753 return -EIO; 754 } 755 } 756 757 /* 758 * Set rediness RDY_CLR bit 759 */ 760 mei_txe_readiness_clear(dev); 761 762 return 0; 763 } 764 765 /** 766 * mei_txe_hw_start - start the hardware after reset 767 * 768 * @dev: the device structure 769 * 770 * returns 0 on success and < 0 in case of error 771 */ 772 static int mei_txe_hw_start(struct mei_device *dev) 773 { 774 struct mei_txe_hw *hw = to_txe_hw(dev); 775 int ret; 776 777 u32 hisr; 778 779 /* bring back interrupts */ 780 mei_txe_intr_enable(dev); 781 782 ret = mei_txe_readiness_wait(dev); 783 if (ret < 0) { 784 dev_err(&dev->pdev->dev, "wating for readiness failed\n"); 785 return ret; 786 } 787 788 /* 789 * If HISR.INT2_STS interrupt status bit is set then clear it. 790 */ 791 hisr = mei_txe_br_reg_read(hw, HISR_REG); 792 if (hisr & HISR_INT_2_STS) 793 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); 794 795 /* Clear the interrupt cause of OutputDoorbell */ 796 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); 797 798 ret = mei_txe_aliveness_set_sync(dev, 1); 799 if (ret < 0) { 800 dev_err(&dev->pdev->dev, "wait for aliveness failed ... bailing out\n"); 801 return ret; 802 } 803 804 /* enable input ready interrupts: 805 * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK 806 */ 807 mei_txe_input_ready_interrupt_enable(dev); 808 809 810 /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */ 811 mei_txe_output_ready_set(hw); 812 813 /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY 814 */ 815 mei_txe_readiness_set_host_rdy(dev); 816 817 return 0; 818 } 819 820 /** 821 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into 822 * single bit mask and acknowledge the interrupts 823 * 824 * @dev: the device structure 825 * @do_ack: acknowledge interrupts 826 */ 827 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack) 828 { 829 struct mei_txe_hw *hw = to_txe_hw(dev); 830 u32 hisr; 831 u32 hhisr; 832 u32 ipc_isr; 833 u32 aliveness; 834 bool generated; 835 836 /* read interrupt registers */ 837 hhisr = mei_txe_br_reg_read(hw, HHISR_REG); 838 generated = (hhisr & IPC_HHIER_MSK); 839 if (!generated) 840 goto out; 841 842 hisr = mei_txe_br_reg_read(hw, HISR_REG); 843 844 aliveness = mei_txe_aliveness_get(dev); 845 if (hhisr & IPC_HHIER_SEC && aliveness) 846 ipc_isr = mei_txe_sec_reg_read_silent(hw, 847 SEC_IPC_HOST_INT_STATUS_REG); 848 else 849 ipc_isr = 0; 850 851 generated = generated || 852 (hisr & HISR_INT_STS_MSK) || 853 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING); 854 855 if (generated && do_ack) { 856 /* Save the interrupt causes */ 857 hw->intr_cause |= hisr & HISR_INT_STS_MSK; 858 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY) 859 hw->intr_cause |= TXE_INTR_IN_READY; 860 861 862 mei_txe_intr_disable(dev); 863 /* Clear the interrupts in hierarchy: 864 * IPC and Bridge, than the High Level */ 865 mei_txe_sec_reg_write_silent(hw, 866 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr); 867 mei_txe_br_reg_write(hw, HISR_REG, hisr); 868 mei_txe_br_reg_write(hw, HHISR_REG, hhisr); 869 } 870 871 out: 872 return generated; 873 } 874 875 /** 876 * mei_txe_irq_quick_handler - The ISR of the MEI device 877 * 878 * @irq: The irq number 879 * @dev_id: pointer to the device structure 880 * 881 * returns irqreturn_t 882 */ 883 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id) 884 { 885 struct mei_device *dev = dev_id; 886 887 if (mei_txe_check_and_ack_intrs(dev, true)) 888 return IRQ_WAKE_THREAD; 889 return IRQ_NONE; 890 } 891 892 893 /** 894 * mei_txe_irq_thread_handler - txe interrupt thread 895 * 896 * @irq: The irq number 897 * @dev_id: pointer to the device structure 898 * 899 * returns irqreturn_t 900 * 901 */ 902 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id) 903 { 904 struct mei_device *dev = (struct mei_device *) dev_id; 905 struct mei_txe_hw *hw = to_txe_hw(dev); 906 struct mei_cl_cb complete_list; 907 s32 slots; 908 int rets = 0; 909 910 dev_dbg(&dev->pdev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", 911 mei_txe_br_reg_read(hw, HHISR_REG), 912 mei_txe_br_reg_read(hw, HISR_REG), 913 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); 914 915 916 /* initialize our complete list */ 917 mutex_lock(&dev->device_lock); 918 mei_io_list_init(&complete_list); 919 920 if (pci_dev_msi_enabled(dev->pdev)) 921 mei_txe_check_and_ack_intrs(dev, true); 922 923 /* show irq events */ 924 mei_txe_pending_interrupts(dev); 925 926 hw->aliveness = mei_txe_aliveness_get(dev); 927 hw->readiness = mei_txe_readiness_get(dev); 928 929 /* Readiness: 930 * Detection of TXE driver going through reset 931 * or TXE driver resetting the HECI interface. 932 */ 933 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { 934 dev_dbg(&dev->pdev->dev, "Readiness Interrupt was received...\n"); 935 936 /* Check if SeC is going through reset */ 937 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { 938 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n"); 939 dev->recvd_hw_ready = true; 940 } else { 941 dev->recvd_hw_ready = false; 942 if (dev->dev_state != MEI_DEV_RESETTING) { 943 944 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n"); 945 schedule_work(&dev->reset_work); 946 goto end; 947 948 } 949 } 950 wake_up(&dev->wait_hw_ready); 951 } 952 953 /************************************************************/ 954 /* Check interrupt cause: 955 * Aliveness: Detection of SeC acknowledge of host request that 956 * it remain alive or host cancellation of that request. 957 */ 958 959 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { 960 /* Clear the interrupt cause */ 961 dev_dbg(&dev->pdev->dev, 962 "Aliveness Interrupt: Status: %d\n", hw->aliveness); 963 hw->recvd_aliveness = true; 964 if (waitqueue_active(&hw->wait_aliveness)) 965 wake_up(&hw->wait_aliveness); 966 } 967 968 969 /* Output Doorbell: 970 * Detection of SeC having sent output to host 971 */ 972 slots = mei_count_full_read_slots(dev); 973 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { 974 /* Read from TXE */ 975 rets = mei_irq_read_handler(dev, &complete_list, &slots); 976 if (rets && dev->dev_state != MEI_DEV_RESETTING) { 977 dev_err(&dev->pdev->dev, 978 "mei_irq_read_handler ret = %d.\n", rets); 979 980 schedule_work(&dev->reset_work); 981 goto end; 982 } 983 } 984 /* Input Ready: Detection if host can write to SeC */ 985 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { 986 dev->hbuf_is_ready = true; 987 hw->slots = dev->hbuf_depth; 988 } 989 990 if (hw->aliveness && dev->hbuf_is_ready) { 991 /* get the real register value */ 992 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 993 rets = mei_irq_write_handler(dev, &complete_list); 994 if (rets && rets != -EMSGSIZE) 995 dev_err(&dev->pdev->dev, "mei_irq_write_handler ret = %d.\n", 996 rets); 997 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 998 } 999 1000 mei_irq_compl_handler(dev, &complete_list); 1001 1002 end: 1003 dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets); 1004 1005 mutex_unlock(&dev->device_lock); 1006 1007 mei_enable_interrupts(dev); 1008 return IRQ_HANDLED; 1009 } 1010 1011 static const struct mei_hw_ops mei_txe_hw_ops = { 1012 1013 .host_is_ready = mei_txe_host_is_ready, 1014 1015 .hw_is_ready = mei_txe_hw_is_ready, 1016 .hw_reset = mei_txe_hw_reset, 1017 .hw_config = mei_txe_hw_config, 1018 .hw_start = mei_txe_hw_start, 1019 1020 .intr_clear = mei_txe_intr_clear, 1021 .intr_enable = mei_txe_intr_enable, 1022 .intr_disable = mei_txe_intr_disable, 1023 1024 .hbuf_free_slots = mei_txe_hbuf_empty_slots, 1025 .hbuf_is_ready = mei_txe_is_input_ready, 1026 .hbuf_max_len = mei_txe_hbuf_max_len, 1027 1028 .write = mei_txe_write, 1029 1030 .rdbuf_full_slots = mei_txe_count_full_read_slots, 1031 .read_hdr = mei_txe_read_hdr, 1032 1033 .read = mei_txe_read, 1034 1035 }; 1036 1037 /** 1038 * mei_txe_dev_init - allocates and initializes txe hardware specific structure 1039 * 1040 * @pdev - pci device 1041 * returns struct mei_device * on success or NULL; 1042 * 1043 */ 1044 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev) 1045 { 1046 struct mei_device *dev; 1047 struct mei_txe_hw *hw; 1048 1049 dev = kzalloc(sizeof(struct mei_device) + 1050 sizeof(struct mei_txe_hw), GFP_KERNEL); 1051 if (!dev) 1052 return NULL; 1053 1054 mei_device_init(dev); 1055 1056 hw = to_txe_hw(dev); 1057 1058 init_waitqueue_head(&hw->wait_aliveness); 1059 1060 dev->ops = &mei_txe_hw_ops; 1061 1062 dev->pdev = pdev; 1063 return dev; 1064 } 1065 1066 /** 1067 * mei_txe_setup_satt2 - SATT2 configuration for DMA support. 1068 * 1069 * @dev: the device structure 1070 * @addr: physical address start of the range 1071 * @range: physical range size 1072 */ 1073 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range) 1074 { 1075 struct mei_txe_hw *hw = to_txe_hw(dev); 1076 1077 u32 lo32 = lower_32_bits(addr); 1078 u32 hi32 = upper_32_bits(addr); 1079 u32 ctrl; 1080 1081 /* SATT is limited to 36 Bits */ 1082 if (hi32 & ~0xF) 1083 return -EINVAL; 1084 1085 /* SATT has to be 16Byte aligned */ 1086 if (lo32 & 0xF) 1087 return -EINVAL; 1088 1089 /* SATT range has to be 4Bytes aligned */ 1090 if (range & 0x4) 1091 return -EINVAL; 1092 1093 /* SATT is limited to 32 MB range*/ 1094 if (range > SATT_RANGE_MAX) 1095 return -EINVAL; 1096 1097 ctrl = SATT2_CTRL_VALID_MSK; 1098 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT; 1099 1100 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); 1101 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); 1102 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); 1103 dev_dbg(&dev->pdev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", 1104 range, lo32, ctrl); 1105 1106 return 0; 1107 } 1108