1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #include <linux/pci.h> 18 19 #include <linux/kthread.h> 20 #include <linux/interrupt.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/sizes.h> 23 24 #include "mei_dev.h" 25 #include "hbm.h" 26 27 #include "hw-me.h" 28 #include "hw-me-regs.h" 29 30 #include "mei-trace.h" 31 32 /** 33 * mei_me_reg_read - Reads 32bit data from the mei device 34 * 35 * @hw: the me hardware structure 36 * @offset: offset from which to read the data 37 * 38 * Return: register value (u32) 39 */ 40 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, 41 unsigned long offset) 42 { 43 return ioread32(hw->mem_addr + offset); 44 } 45 46 47 /** 48 * mei_me_reg_write - Writes 32bit data to the mei device 49 * 50 * @hw: the me hardware structure 51 * @offset: offset from which to write the data 52 * @value: register value to write (u32) 53 */ 54 static inline void mei_me_reg_write(const struct mei_me_hw *hw, 55 unsigned long offset, u32 value) 56 { 57 iowrite32(value, hw->mem_addr + offset); 58 } 59 60 /** 61 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer 62 * read window register 63 * 64 * @dev: the device structure 65 * 66 * Return: ME_CB_RW register value (u32) 67 */ 68 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) 69 { 70 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); 71 } 72 73 /** 74 * mei_me_hcbww_write - write 32bit data to the host circular buffer 75 * 76 * @dev: the device structure 77 * @data: 32bit data to be written to the host circular buffer 78 */ 79 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) 80 { 81 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); 82 } 83 84 /** 85 * mei_me_mecsr_read - Reads 32bit data from the ME CSR 86 * 87 * @dev: the device structure 88 * 89 * Return: ME_CSR_HA register value (u32) 90 */ 91 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) 92 { 93 u32 reg; 94 95 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); 96 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); 97 98 return reg; 99 } 100 101 /** 102 * mei_hcsr_read - Reads 32bit data from the host CSR 103 * 104 * @dev: the device structure 105 * 106 * Return: H_CSR register value (u32) 107 */ 108 static inline u32 mei_hcsr_read(const struct mei_device *dev) 109 { 110 u32 reg; 111 112 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); 113 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); 114 115 return reg; 116 } 117 118 /** 119 * mei_hcsr_write - writes H_CSR register to the mei device 120 * 121 * @dev: the device structure 122 * @reg: new register value 123 */ 124 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) 125 { 126 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); 127 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); 128 } 129 130 /** 131 * mei_hcsr_set - writes H_CSR register to the mei device, 132 * and ignores the H_IS bit for it is write-one-to-zero. 133 * 134 * @dev: the device structure 135 * @reg: new register value 136 */ 137 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) 138 { 139 reg &= ~H_CSR_IS_MASK; 140 mei_hcsr_write(dev, reg); 141 } 142 143 /** 144 * mei_hcsr_set_hig - set host interrupt (set H_IG) 145 * 146 * @dev: the device structure 147 */ 148 static inline void mei_hcsr_set_hig(struct mei_device *dev) 149 { 150 u32 hcsr; 151 152 hcsr = mei_hcsr_read(dev) | H_IG; 153 mei_hcsr_set(dev, hcsr); 154 } 155 156 /** 157 * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register 158 * 159 * @dev: the device structure 160 * 161 * Return: H_D0I3C register value (u32) 162 */ 163 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) 164 { 165 u32 reg; 166 167 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); 168 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); 169 170 return reg; 171 } 172 173 /** 174 * mei_me_d0i3c_write - writes H_D0I3C register to device 175 * 176 * @dev: the device structure 177 * @reg: new register value 178 */ 179 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) 180 { 181 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); 182 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); 183 } 184 185 /** 186 * mei_me_fw_status - read fw status register from pci config space 187 * 188 * @dev: mei device 189 * @fw_status: fw status register values 190 * 191 * Return: 0 on success, error otherwise 192 */ 193 static int mei_me_fw_status(struct mei_device *dev, 194 struct mei_fw_status *fw_status) 195 { 196 struct pci_dev *pdev = to_pci_dev(dev->dev); 197 struct mei_me_hw *hw = to_me_hw(dev); 198 const struct mei_fw_status *fw_src = &hw->cfg->fw_status; 199 int ret; 200 int i; 201 202 if (!fw_status) 203 return -EINVAL; 204 205 fw_status->count = fw_src->count; 206 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { 207 ret = pci_read_config_dword(pdev, fw_src->status[i], 208 &fw_status->status[i]); 209 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", 210 fw_src->status[i], 211 fw_status->status[i]); 212 if (ret) 213 return ret; 214 } 215 216 return 0; 217 } 218 219 /** 220 * mei_me_hw_config - configure hw dependent settings 221 * 222 * @dev: mei device 223 */ 224 static void mei_me_hw_config(struct mei_device *dev) 225 { 226 struct pci_dev *pdev = to_pci_dev(dev->dev); 227 struct mei_me_hw *hw = to_me_hw(dev); 228 u32 hcsr, reg; 229 230 /* Doesn't change in runtime */ 231 hcsr = mei_hcsr_read(dev); 232 hw->hbuf_depth = (hcsr & H_CBD) >> 24; 233 234 reg = 0; 235 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); 236 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); 237 hw->d0i3_supported = 238 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK); 239 240 hw->pg_state = MEI_PG_OFF; 241 if (hw->d0i3_supported) { 242 reg = mei_me_d0i3c_read(dev); 243 if (reg & H_D0I3C_I3) 244 hw->pg_state = MEI_PG_ON; 245 } 246 } 247 248 /** 249 * mei_me_pg_state - translate internal pg state 250 * to the mei power gating state 251 * 252 * @dev: mei device 253 * 254 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise 255 */ 256 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) 257 { 258 struct mei_me_hw *hw = to_me_hw(dev); 259 260 return hw->pg_state; 261 } 262 263 static inline u32 me_intr_src(u32 hcsr) 264 { 265 return hcsr & H_CSR_IS_MASK; 266 } 267 268 /** 269 * me_intr_disable - disables mei device interrupts 270 * using supplied hcsr register value. 271 * 272 * @dev: the device structure 273 * @hcsr: supplied hcsr register value 274 */ 275 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) 276 { 277 hcsr &= ~H_CSR_IE_MASK; 278 mei_hcsr_set(dev, hcsr); 279 } 280 281 /** 282 * mei_me_intr_clear - clear and stop interrupts 283 * 284 * @dev: the device structure 285 * @hcsr: supplied hcsr register value 286 */ 287 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) 288 { 289 if (me_intr_src(hcsr)) 290 mei_hcsr_write(dev, hcsr); 291 } 292 293 /** 294 * mei_me_intr_clear - clear and stop interrupts 295 * 296 * @dev: the device structure 297 */ 298 static void mei_me_intr_clear(struct mei_device *dev) 299 { 300 u32 hcsr = mei_hcsr_read(dev); 301 302 me_intr_clear(dev, hcsr); 303 } 304 /** 305 * mei_me_intr_enable - enables mei device interrupts 306 * 307 * @dev: the device structure 308 */ 309 static void mei_me_intr_enable(struct mei_device *dev) 310 { 311 u32 hcsr = mei_hcsr_read(dev); 312 313 hcsr |= H_CSR_IE_MASK; 314 mei_hcsr_set(dev, hcsr); 315 } 316 317 /** 318 * mei_me_intr_disable - disables mei device interrupts 319 * 320 * @dev: the device structure 321 */ 322 static void mei_me_intr_disable(struct mei_device *dev) 323 { 324 u32 hcsr = mei_hcsr_read(dev); 325 326 me_intr_disable(dev, hcsr); 327 } 328 329 /** 330 * mei_me_synchronize_irq - wait for pending IRQ handlers 331 * 332 * @dev: the device structure 333 */ 334 static void mei_me_synchronize_irq(struct mei_device *dev) 335 { 336 struct pci_dev *pdev = to_pci_dev(dev->dev); 337 338 synchronize_irq(pdev->irq); 339 } 340 341 /** 342 * mei_me_hw_reset_release - release device from the reset 343 * 344 * @dev: the device structure 345 */ 346 static void mei_me_hw_reset_release(struct mei_device *dev) 347 { 348 u32 hcsr = mei_hcsr_read(dev); 349 350 hcsr |= H_IG; 351 hcsr &= ~H_RST; 352 mei_hcsr_set(dev, hcsr); 353 } 354 355 /** 356 * mei_me_host_set_ready - enable device 357 * 358 * @dev: mei device 359 */ 360 static void mei_me_host_set_ready(struct mei_device *dev) 361 { 362 u32 hcsr = mei_hcsr_read(dev); 363 364 hcsr |= H_CSR_IE_MASK | H_IG | H_RDY; 365 mei_hcsr_set(dev, hcsr); 366 } 367 368 /** 369 * mei_me_host_is_ready - check whether the host has turned ready 370 * 371 * @dev: mei device 372 * Return: bool 373 */ 374 static bool mei_me_host_is_ready(struct mei_device *dev) 375 { 376 u32 hcsr = mei_hcsr_read(dev); 377 378 return (hcsr & H_RDY) == H_RDY; 379 } 380 381 /** 382 * mei_me_hw_is_ready - check whether the me(hw) has turned ready 383 * 384 * @dev: mei device 385 * Return: bool 386 */ 387 static bool mei_me_hw_is_ready(struct mei_device *dev) 388 { 389 u32 mecsr = mei_me_mecsr_read(dev); 390 391 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; 392 } 393 394 /** 395 * mei_me_hw_is_resetting - check whether the me(hw) is in reset 396 * 397 * @dev: mei device 398 * Return: bool 399 */ 400 static bool mei_me_hw_is_resetting(struct mei_device *dev) 401 { 402 u32 mecsr = mei_me_mecsr_read(dev); 403 404 return (mecsr & ME_RST_HRA) == ME_RST_HRA; 405 } 406 407 /** 408 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready 409 * or timeout is reached 410 * 411 * @dev: mei device 412 * Return: 0 on success, error otherwise 413 */ 414 static int mei_me_hw_ready_wait(struct mei_device *dev) 415 { 416 mutex_unlock(&dev->device_lock); 417 wait_event_timeout(dev->wait_hw_ready, 418 dev->recvd_hw_ready, 419 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); 420 mutex_lock(&dev->device_lock); 421 if (!dev->recvd_hw_ready) { 422 dev_err(dev->dev, "wait hw ready failed\n"); 423 return -ETIME; 424 } 425 426 mei_me_hw_reset_release(dev); 427 dev->recvd_hw_ready = false; 428 return 0; 429 } 430 431 /** 432 * mei_me_hw_start - hw start routine 433 * 434 * @dev: mei device 435 * Return: 0 on success, error otherwise 436 */ 437 static int mei_me_hw_start(struct mei_device *dev) 438 { 439 int ret = mei_me_hw_ready_wait(dev); 440 441 if (ret) 442 return ret; 443 dev_dbg(dev->dev, "hw is ready\n"); 444 445 mei_me_host_set_ready(dev); 446 return ret; 447 } 448 449 450 /** 451 * mei_hbuf_filled_slots - gets number of device filled buffer slots 452 * 453 * @dev: the device structure 454 * 455 * Return: number of filled slots 456 */ 457 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) 458 { 459 u32 hcsr; 460 char read_ptr, write_ptr; 461 462 hcsr = mei_hcsr_read(dev); 463 464 read_ptr = (char) ((hcsr & H_CBRP) >> 8); 465 write_ptr = (char) ((hcsr & H_CBWP) >> 16); 466 467 return (unsigned char) (write_ptr - read_ptr); 468 } 469 470 /** 471 * mei_me_hbuf_is_empty - checks if host buffer is empty. 472 * 473 * @dev: the device structure 474 * 475 * Return: true if empty, false - otherwise. 476 */ 477 static bool mei_me_hbuf_is_empty(struct mei_device *dev) 478 { 479 return mei_hbuf_filled_slots(dev) == 0; 480 } 481 482 /** 483 * mei_me_hbuf_empty_slots - counts write empty slots. 484 * 485 * @dev: the device structure 486 * 487 * Return: -EOVERFLOW if overflow, otherwise empty slots count 488 */ 489 static int mei_me_hbuf_empty_slots(struct mei_device *dev) 490 { 491 struct mei_me_hw *hw = to_me_hw(dev); 492 unsigned char filled_slots, empty_slots; 493 494 filled_slots = mei_hbuf_filled_slots(dev); 495 empty_slots = hw->hbuf_depth - filled_slots; 496 497 /* check for overflow */ 498 if (filled_slots > hw->hbuf_depth) 499 return -EOVERFLOW; 500 501 return empty_slots; 502 } 503 504 /** 505 * mei_me_hbuf_depth - returns depth of the hw buffer. 506 * 507 * @dev: the device structure 508 * 509 * Return: size of hw buffer in slots 510 */ 511 static u32 mei_me_hbuf_depth(const struct mei_device *dev) 512 { 513 struct mei_me_hw *hw = to_me_hw(dev); 514 515 return hw->hbuf_depth; 516 } 517 518 /** 519 * mei_me_hbuf_write - writes a message to host hw buffer. 520 * 521 * @dev: the device structure 522 * @hdr: header of message 523 * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes) 524 * @data: payload 525 * @data_len: payload length in bytes 526 * 527 * Return: 0 if success, < 0 - otherwise. 528 */ 529 static int mei_me_hbuf_write(struct mei_device *dev, 530 const void *hdr, size_t hdr_len, 531 const void *data, size_t data_len) 532 { 533 unsigned long rem; 534 unsigned long i; 535 const u32 *reg_buf; 536 u32 dw_cnt; 537 int empty_slots; 538 539 if (WARN_ON(!hdr || !data || hdr_len & 0x3)) 540 return -EINVAL; 541 542 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); 543 544 empty_slots = mei_hbuf_empty_slots(dev); 545 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); 546 547 if (empty_slots < 0) 548 return -EOVERFLOW; 549 550 dw_cnt = mei_data2slots(hdr_len + data_len); 551 if (dw_cnt > (u32)empty_slots) 552 return -EMSGSIZE; 553 554 reg_buf = hdr; 555 for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++) 556 mei_me_hcbww_write(dev, reg_buf[i]); 557 558 reg_buf = data; 559 for (i = 0; i < data_len / MEI_SLOT_SIZE; i++) 560 mei_me_hcbww_write(dev, reg_buf[i]); 561 562 rem = data_len & 0x3; 563 if (rem > 0) { 564 u32 reg = 0; 565 566 memcpy(®, (const u8 *)data + data_len - rem, rem); 567 mei_me_hcbww_write(dev, reg); 568 } 569 570 mei_hcsr_set_hig(dev); 571 if (!mei_me_hw_is_ready(dev)) 572 return -EIO; 573 574 return 0; 575 } 576 577 /** 578 * mei_me_count_full_read_slots - counts read full slots. 579 * 580 * @dev: the device structure 581 * 582 * Return: -EOVERFLOW if overflow, otherwise filled slots count 583 */ 584 static int mei_me_count_full_read_slots(struct mei_device *dev) 585 { 586 u32 me_csr; 587 char read_ptr, write_ptr; 588 unsigned char buffer_depth, filled_slots; 589 590 me_csr = mei_me_mecsr_read(dev); 591 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); 592 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); 593 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); 594 filled_slots = (unsigned char) (write_ptr - read_ptr); 595 596 /* check for overflow */ 597 if (filled_slots > buffer_depth) 598 return -EOVERFLOW; 599 600 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); 601 return (int)filled_slots; 602 } 603 604 /** 605 * mei_me_read_slots - reads a message from mei device. 606 * 607 * @dev: the device structure 608 * @buffer: message buffer will be written 609 * @buffer_length: message size will be read 610 * 611 * Return: always 0 612 */ 613 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, 614 unsigned long buffer_length) 615 { 616 u32 *reg_buf = (u32 *)buffer; 617 618 for (; buffer_length >= MEI_SLOT_SIZE; buffer_length -= MEI_SLOT_SIZE) 619 *reg_buf++ = mei_me_mecbrw_read(dev); 620 621 if (buffer_length > 0) { 622 u32 reg = mei_me_mecbrw_read(dev); 623 624 memcpy(reg_buf, ®, buffer_length); 625 } 626 627 mei_hcsr_set_hig(dev); 628 return 0; 629 } 630 631 /** 632 * mei_me_pg_set - write pg enter register 633 * 634 * @dev: the device structure 635 */ 636 static void mei_me_pg_set(struct mei_device *dev) 637 { 638 struct mei_me_hw *hw = to_me_hw(dev); 639 u32 reg; 640 641 reg = mei_me_reg_read(hw, H_HPG_CSR); 642 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 643 644 reg |= H_HPG_CSR_PGI; 645 646 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 647 mei_me_reg_write(hw, H_HPG_CSR, reg); 648 } 649 650 /** 651 * mei_me_pg_unset - write pg exit register 652 * 653 * @dev: the device structure 654 */ 655 static void mei_me_pg_unset(struct mei_device *dev) 656 { 657 struct mei_me_hw *hw = to_me_hw(dev); 658 u32 reg; 659 660 reg = mei_me_reg_read(hw, H_HPG_CSR); 661 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 662 663 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); 664 665 reg |= H_HPG_CSR_PGIHEXR; 666 667 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); 668 mei_me_reg_write(hw, H_HPG_CSR, reg); 669 } 670 671 /** 672 * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure 673 * 674 * @dev: the device structure 675 * 676 * Return: 0 on success an error code otherwise 677 */ 678 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) 679 { 680 struct mei_me_hw *hw = to_me_hw(dev); 681 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); 682 int ret; 683 684 dev->pg_event = MEI_PG_EVENT_WAIT; 685 686 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); 687 if (ret) 688 return ret; 689 690 mutex_unlock(&dev->device_lock); 691 wait_event_timeout(dev->wait_pg, 692 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 693 mutex_lock(&dev->device_lock); 694 695 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { 696 mei_me_pg_set(dev); 697 ret = 0; 698 } else { 699 ret = -ETIME; 700 } 701 702 dev->pg_event = MEI_PG_EVENT_IDLE; 703 hw->pg_state = MEI_PG_ON; 704 705 return ret; 706 } 707 708 /** 709 * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure 710 * 711 * @dev: the device structure 712 * 713 * Return: 0 on success an error code otherwise 714 */ 715 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) 716 { 717 struct mei_me_hw *hw = to_me_hw(dev); 718 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); 719 int ret; 720 721 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) 722 goto reply; 723 724 dev->pg_event = MEI_PG_EVENT_WAIT; 725 726 mei_me_pg_unset(dev); 727 728 mutex_unlock(&dev->device_lock); 729 wait_event_timeout(dev->wait_pg, 730 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); 731 mutex_lock(&dev->device_lock); 732 733 reply: 734 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { 735 ret = -ETIME; 736 goto out; 737 } 738 739 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; 740 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); 741 if (ret) 742 return ret; 743 744 mutex_unlock(&dev->device_lock); 745 wait_event_timeout(dev->wait_pg, 746 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); 747 mutex_lock(&dev->device_lock); 748 749 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) 750 ret = 0; 751 else 752 ret = -ETIME; 753 754 out: 755 dev->pg_event = MEI_PG_EVENT_IDLE; 756 hw->pg_state = MEI_PG_OFF; 757 758 return ret; 759 } 760 761 /** 762 * mei_me_pg_in_transition - is device now in pg transition 763 * 764 * @dev: the device structure 765 * 766 * Return: true if in pg transition, false otherwise 767 */ 768 static bool mei_me_pg_in_transition(struct mei_device *dev) 769 { 770 return dev->pg_event >= MEI_PG_EVENT_WAIT && 771 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; 772 } 773 774 /** 775 * mei_me_pg_is_enabled - detect if PG is supported by HW 776 * 777 * @dev: the device structure 778 * 779 * Return: true is pg supported, false otherwise 780 */ 781 static bool mei_me_pg_is_enabled(struct mei_device *dev) 782 { 783 struct mei_me_hw *hw = to_me_hw(dev); 784 u32 reg = mei_me_mecsr_read(dev); 785 786 if (hw->d0i3_supported) 787 return true; 788 789 if ((reg & ME_PGIC_HRA) == 0) 790 goto notsupported; 791 792 if (!dev->hbm_f_pg_supported) 793 goto notsupported; 794 795 return true; 796 797 notsupported: 798 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", 799 hw->d0i3_supported, 800 !!(reg & ME_PGIC_HRA), 801 dev->version.major_version, 802 dev->version.minor_version, 803 HBM_MAJOR_VERSION_PGI, 804 HBM_MINOR_VERSION_PGI); 805 806 return false; 807 } 808 809 /** 810 * mei_me_d0i3_set - write d0i3 register bit on mei device. 811 * 812 * @dev: the device structure 813 * @intr: ask for interrupt 814 * 815 * Return: D0I3C register value 816 */ 817 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) 818 { 819 u32 reg = mei_me_d0i3c_read(dev); 820 821 reg |= H_D0I3C_I3; 822 if (intr) 823 reg |= H_D0I3C_IR; 824 else 825 reg &= ~H_D0I3C_IR; 826 mei_me_d0i3c_write(dev, reg); 827 /* read it to ensure HW consistency */ 828 reg = mei_me_d0i3c_read(dev); 829 return reg; 830 } 831 832 /** 833 * mei_me_d0i3_unset - clean d0i3 register bit on mei device. 834 * 835 * @dev: the device structure 836 * 837 * Return: D0I3C register value 838 */ 839 static u32 mei_me_d0i3_unset(struct mei_device *dev) 840 { 841 u32 reg = mei_me_d0i3c_read(dev); 842 843 reg &= ~H_D0I3C_I3; 844 reg |= H_D0I3C_IR; 845 mei_me_d0i3c_write(dev, reg); 846 /* read it to ensure HW consistency */ 847 reg = mei_me_d0i3c_read(dev); 848 return reg; 849 } 850 851 /** 852 * mei_me_d0i3_enter_sync - perform d0i3 entry procedure 853 * 854 * @dev: the device structure 855 * 856 * Return: 0 on success an error code otherwise 857 */ 858 static int mei_me_d0i3_enter_sync(struct mei_device *dev) 859 { 860 struct mei_me_hw *hw = to_me_hw(dev); 861 unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); 862 unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); 863 int ret; 864 u32 reg; 865 866 reg = mei_me_d0i3c_read(dev); 867 if (reg & H_D0I3C_I3) { 868 /* we are in d0i3, nothing to do */ 869 dev_dbg(dev->dev, "d0i3 set not needed\n"); 870 ret = 0; 871 goto on; 872 } 873 874 /* PGI entry procedure */ 875 dev->pg_event = MEI_PG_EVENT_WAIT; 876 877 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); 878 if (ret) 879 /* FIXME: should we reset here? */ 880 goto out; 881 882 mutex_unlock(&dev->device_lock); 883 wait_event_timeout(dev->wait_pg, 884 dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout); 885 mutex_lock(&dev->device_lock); 886 887 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { 888 ret = -ETIME; 889 goto out; 890 } 891 /* end PGI entry procedure */ 892 893 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; 894 895 reg = mei_me_d0i3_set(dev, true); 896 if (!(reg & H_D0I3C_CIP)) { 897 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); 898 ret = 0; 899 goto on; 900 } 901 902 mutex_unlock(&dev->device_lock); 903 wait_event_timeout(dev->wait_pg, 904 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); 905 mutex_lock(&dev->device_lock); 906 907 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { 908 reg = mei_me_d0i3c_read(dev); 909 if (!(reg & H_D0I3C_I3)) { 910 ret = -ETIME; 911 goto out; 912 } 913 } 914 915 ret = 0; 916 on: 917 hw->pg_state = MEI_PG_ON; 918 out: 919 dev->pg_event = MEI_PG_EVENT_IDLE; 920 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); 921 return ret; 922 } 923 924 /** 925 * mei_me_d0i3_enter - perform d0i3 entry procedure 926 * no hbm PG handshake 927 * no waiting for confirmation; runs with interrupts 928 * disabled 929 * 930 * @dev: the device structure 931 * 932 * Return: 0 on success an error code otherwise 933 */ 934 static int mei_me_d0i3_enter(struct mei_device *dev) 935 { 936 struct mei_me_hw *hw = to_me_hw(dev); 937 u32 reg; 938 939 reg = mei_me_d0i3c_read(dev); 940 if (reg & H_D0I3C_I3) { 941 /* we are in d0i3, nothing to do */ 942 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); 943 goto on; 944 } 945 946 mei_me_d0i3_set(dev, false); 947 on: 948 hw->pg_state = MEI_PG_ON; 949 dev->pg_event = MEI_PG_EVENT_IDLE; 950 dev_dbg(dev->dev, "d0i3 enter\n"); 951 return 0; 952 } 953 954 /** 955 * mei_me_d0i3_exit_sync - perform d0i3 exit procedure 956 * 957 * @dev: the device structure 958 * 959 * Return: 0 on success an error code otherwise 960 */ 961 static int mei_me_d0i3_exit_sync(struct mei_device *dev) 962 { 963 struct mei_me_hw *hw = to_me_hw(dev); 964 unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); 965 int ret; 966 u32 reg; 967 968 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; 969 970 reg = mei_me_d0i3c_read(dev); 971 if (!(reg & H_D0I3C_I3)) { 972 /* we are not in d0i3, nothing to do */ 973 dev_dbg(dev->dev, "d0i3 exit not needed\n"); 974 ret = 0; 975 goto off; 976 } 977 978 reg = mei_me_d0i3_unset(dev); 979 if (!(reg & H_D0I3C_CIP)) { 980 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); 981 ret = 0; 982 goto off; 983 } 984 985 mutex_unlock(&dev->device_lock); 986 wait_event_timeout(dev->wait_pg, 987 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); 988 mutex_lock(&dev->device_lock); 989 990 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { 991 reg = mei_me_d0i3c_read(dev); 992 if (reg & H_D0I3C_I3) { 993 ret = -ETIME; 994 goto out; 995 } 996 } 997 998 ret = 0; 999 off: 1000 hw->pg_state = MEI_PG_OFF; 1001 out: 1002 dev->pg_event = MEI_PG_EVENT_IDLE; 1003 1004 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); 1005 return ret; 1006 } 1007 1008 /** 1009 * mei_me_pg_legacy_intr - perform legacy pg processing 1010 * in interrupt thread handler 1011 * 1012 * @dev: the device structure 1013 */ 1014 static void mei_me_pg_legacy_intr(struct mei_device *dev) 1015 { 1016 struct mei_me_hw *hw = to_me_hw(dev); 1017 1018 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) 1019 return; 1020 1021 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; 1022 hw->pg_state = MEI_PG_OFF; 1023 if (waitqueue_active(&dev->wait_pg)) 1024 wake_up(&dev->wait_pg); 1025 } 1026 1027 /** 1028 * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler 1029 * 1030 * @dev: the device structure 1031 * @intr_source: interrupt source 1032 */ 1033 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) 1034 { 1035 struct mei_me_hw *hw = to_me_hw(dev); 1036 1037 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && 1038 (intr_source & H_D0I3C_IS)) { 1039 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; 1040 if (hw->pg_state == MEI_PG_ON) { 1041 hw->pg_state = MEI_PG_OFF; 1042 if (dev->hbm_state != MEI_HBM_IDLE) { 1043 /* 1044 * force H_RDY because it could be 1045 * wiped off during PG 1046 */ 1047 dev_dbg(dev->dev, "d0i3 set host ready\n"); 1048 mei_me_host_set_ready(dev); 1049 } 1050 } else { 1051 hw->pg_state = MEI_PG_ON; 1052 } 1053 1054 wake_up(&dev->wait_pg); 1055 } 1056 1057 if (hw->pg_state == MEI_PG_ON && (intr_source & H_IS)) { 1058 /* 1059 * HW sent some data and we are in D0i3, so 1060 * we got here because of HW initiated exit from D0i3. 1061 * Start runtime pm resume sequence to exit low power state. 1062 */ 1063 dev_dbg(dev->dev, "d0i3 want resume\n"); 1064 mei_hbm_pg_resume(dev); 1065 } 1066 } 1067 1068 /** 1069 * mei_me_pg_intr - perform pg processing in interrupt thread handler 1070 * 1071 * @dev: the device structure 1072 * @intr_source: interrupt source 1073 */ 1074 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) 1075 { 1076 struct mei_me_hw *hw = to_me_hw(dev); 1077 1078 if (hw->d0i3_supported) 1079 mei_me_d0i3_intr(dev, intr_source); 1080 else 1081 mei_me_pg_legacy_intr(dev); 1082 } 1083 1084 /** 1085 * mei_me_pg_enter_sync - perform runtime pm entry procedure 1086 * 1087 * @dev: the device structure 1088 * 1089 * Return: 0 on success an error code otherwise 1090 */ 1091 int mei_me_pg_enter_sync(struct mei_device *dev) 1092 { 1093 struct mei_me_hw *hw = to_me_hw(dev); 1094 1095 if (hw->d0i3_supported) 1096 return mei_me_d0i3_enter_sync(dev); 1097 else 1098 return mei_me_pg_legacy_enter_sync(dev); 1099 } 1100 1101 /** 1102 * mei_me_pg_exit_sync - perform runtime pm exit procedure 1103 * 1104 * @dev: the device structure 1105 * 1106 * Return: 0 on success an error code otherwise 1107 */ 1108 int mei_me_pg_exit_sync(struct mei_device *dev) 1109 { 1110 struct mei_me_hw *hw = to_me_hw(dev); 1111 1112 if (hw->d0i3_supported) 1113 return mei_me_d0i3_exit_sync(dev); 1114 else 1115 return mei_me_pg_legacy_exit_sync(dev); 1116 } 1117 1118 /** 1119 * mei_me_hw_reset - resets fw via mei csr register. 1120 * 1121 * @dev: the device structure 1122 * @intr_enable: if interrupt should be enabled after reset. 1123 * 1124 * Return: 0 on success an error code otherwise 1125 */ 1126 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) 1127 { 1128 struct mei_me_hw *hw = to_me_hw(dev); 1129 int ret; 1130 u32 hcsr; 1131 1132 if (intr_enable) { 1133 mei_me_intr_enable(dev); 1134 if (hw->d0i3_supported) { 1135 ret = mei_me_d0i3_exit_sync(dev); 1136 if (ret) 1137 return ret; 1138 } 1139 } 1140 1141 pm_runtime_set_active(dev->dev); 1142 1143 hcsr = mei_hcsr_read(dev); 1144 /* H_RST may be found lit before reset is started, 1145 * for example if preceding reset flow hasn't completed. 1146 * In that case asserting H_RST will be ignored, therefore 1147 * we need to clean H_RST bit to start a successful reset sequence. 1148 */ 1149 if ((hcsr & H_RST) == H_RST) { 1150 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); 1151 hcsr &= ~H_RST; 1152 mei_hcsr_set(dev, hcsr); 1153 hcsr = mei_hcsr_read(dev); 1154 } 1155 1156 hcsr |= H_RST | H_IG | H_CSR_IS_MASK; 1157 1158 if (!intr_enable) 1159 hcsr &= ~H_CSR_IE_MASK; 1160 1161 dev->recvd_hw_ready = false; 1162 mei_hcsr_write(dev, hcsr); 1163 1164 /* 1165 * Host reads the H_CSR once to ensure that the 1166 * posted write to H_CSR completes. 1167 */ 1168 hcsr = mei_hcsr_read(dev); 1169 1170 if ((hcsr & H_RST) == 0) 1171 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); 1172 1173 if ((hcsr & H_RDY) == H_RDY) 1174 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); 1175 1176 if (!intr_enable) { 1177 mei_me_hw_reset_release(dev); 1178 if (hw->d0i3_supported) { 1179 ret = mei_me_d0i3_enter(dev); 1180 if (ret) 1181 return ret; 1182 } 1183 } 1184 return 0; 1185 } 1186 1187 /** 1188 * mei_me_irq_quick_handler - The ISR of the MEI device 1189 * 1190 * @irq: The irq number 1191 * @dev_id: pointer to the device structure 1192 * 1193 * Return: irqreturn_t 1194 */ 1195 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) 1196 { 1197 struct mei_device *dev = (struct mei_device *)dev_id; 1198 u32 hcsr; 1199 1200 hcsr = mei_hcsr_read(dev); 1201 if (!me_intr_src(hcsr)) 1202 return IRQ_NONE; 1203 1204 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr)); 1205 1206 /* disable interrupts on device */ 1207 me_intr_disable(dev, hcsr); 1208 return IRQ_WAKE_THREAD; 1209 } 1210 1211 /** 1212 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt 1213 * processing. 1214 * 1215 * @irq: The irq number 1216 * @dev_id: pointer to the device structure 1217 * 1218 * Return: irqreturn_t 1219 * 1220 */ 1221 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) 1222 { 1223 struct mei_device *dev = (struct mei_device *) dev_id; 1224 struct list_head cmpl_list; 1225 s32 slots; 1226 u32 hcsr; 1227 int rets = 0; 1228 1229 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); 1230 /* initialize our complete list */ 1231 mutex_lock(&dev->device_lock); 1232 1233 hcsr = mei_hcsr_read(dev); 1234 me_intr_clear(dev, hcsr); 1235 1236 INIT_LIST_HEAD(&cmpl_list); 1237 1238 /* check if ME wants a reset */ 1239 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { 1240 dev_warn(dev->dev, "FW not ready: resetting.\n"); 1241 schedule_work(&dev->reset_work); 1242 goto end; 1243 } 1244 1245 if (mei_me_hw_is_resetting(dev)) 1246 mei_hcsr_set_hig(dev); 1247 1248 mei_me_pg_intr(dev, me_intr_src(hcsr)); 1249 1250 /* check if we need to start the dev */ 1251 if (!mei_host_is_ready(dev)) { 1252 if (mei_hw_is_ready(dev)) { 1253 dev_dbg(dev->dev, "we need to start the dev.\n"); 1254 dev->recvd_hw_ready = true; 1255 wake_up(&dev->wait_hw_ready); 1256 } else { 1257 dev_dbg(dev->dev, "Spurious Interrupt\n"); 1258 } 1259 goto end; 1260 } 1261 /* check slots available for reading */ 1262 slots = mei_count_full_read_slots(dev); 1263 while (slots > 0) { 1264 dev_dbg(dev->dev, "slots to read = %08x\n", slots); 1265 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); 1266 /* There is a race between ME write and interrupt delivery: 1267 * Not all data is always available immediately after the 1268 * interrupt, so try to read again on the next interrupt. 1269 */ 1270 if (rets == -ENODATA) 1271 break; 1272 1273 if (rets && 1274 (dev->dev_state != MEI_DEV_RESETTING && 1275 dev->dev_state != MEI_DEV_POWER_DOWN)) { 1276 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", 1277 rets); 1278 schedule_work(&dev->reset_work); 1279 goto end; 1280 } 1281 } 1282 1283 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1284 1285 /* 1286 * During PG handshake only allowed write is the replay to the 1287 * PG exit message, so block calling write function 1288 * if the pg event is in PG handshake 1289 */ 1290 if (dev->pg_event != MEI_PG_EVENT_WAIT && 1291 dev->pg_event != MEI_PG_EVENT_RECEIVED) { 1292 rets = mei_irq_write_handler(dev, &cmpl_list); 1293 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); 1294 } 1295 1296 mei_irq_compl_handler(dev, &cmpl_list); 1297 1298 end: 1299 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); 1300 mei_me_intr_enable(dev); 1301 mutex_unlock(&dev->device_lock); 1302 return IRQ_HANDLED; 1303 } 1304 1305 static const struct mei_hw_ops mei_me_hw_ops = { 1306 1307 .fw_status = mei_me_fw_status, 1308 .pg_state = mei_me_pg_state, 1309 1310 .host_is_ready = mei_me_host_is_ready, 1311 1312 .hw_is_ready = mei_me_hw_is_ready, 1313 .hw_reset = mei_me_hw_reset, 1314 .hw_config = mei_me_hw_config, 1315 .hw_start = mei_me_hw_start, 1316 1317 .pg_in_transition = mei_me_pg_in_transition, 1318 .pg_is_enabled = mei_me_pg_is_enabled, 1319 1320 .intr_clear = mei_me_intr_clear, 1321 .intr_enable = mei_me_intr_enable, 1322 .intr_disable = mei_me_intr_disable, 1323 .synchronize_irq = mei_me_synchronize_irq, 1324 1325 .hbuf_free_slots = mei_me_hbuf_empty_slots, 1326 .hbuf_is_ready = mei_me_hbuf_is_empty, 1327 .hbuf_depth = mei_me_hbuf_depth, 1328 1329 .write = mei_me_hbuf_write, 1330 1331 .rdbuf_full_slots = mei_me_count_full_read_slots, 1332 .read_hdr = mei_me_mecbrw_read, 1333 .read = mei_me_read_slots 1334 }; 1335 1336 static bool mei_me_fw_type_nm(struct pci_dev *pdev) 1337 { 1338 u32 reg; 1339 1340 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); 1341 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); 1342 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ 1343 return (reg & 0x600) == 0x200; 1344 } 1345 1346 #define MEI_CFG_FW_NM \ 1347 .quirk_probe = mei_me_fw_type_nm 1348 1349 static bool mei_me_fw_type_sps(struct pci_dev *pdev) 1350 { 1351 u32 reg; 1352 unsigned int devfn; 1353 1354 /* 1355 * Read ME FW Status register to check for SPS Firmware 1356 * The SPS FW is only signaled in pci function 0 1357 */ 1358 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); 1359 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®); 1360 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); 1361 /* if bits [19:16] = 15, running SPS Firmware */ 1362 return (reg & 0xf0000) == 0xf0000; 1363 } 1364 1365 #define MEI_CFG_FW_SPS \ 1366 .quirk_probe = mei_me_fw_type_sps 1367 1368 1369 #define MEI_CFG_ICH_HFS \ 1370 .fw_status.count = 0 1371 1372 #define MEI_CFG_ICH10_HFS \ 1373 .fw_status.count = 1, \ 1374 .fw_status.status[0] = PCI_CFG_HFS_1 1375 1376 #define MEI_CFG_PCH_HFS \ 1377 .fw_status.count = 2, \ 1378 .fw_status.status[0] = PCI_CFG_HFS_1, \ 1379 .fw_status.status[1] = PCI_CFG_HFS_2 1380 1381 #define MEI_CFG_PCH8_HFS \ 1382 .fw_status.count = 6, \ 1383 .fw_status.status[0] = PCI_CFG_HFS_1, \ 1384 .fw_status.status[1] = PCI_CFG_HFS_2, \ 1385 .fw_status.status[2] = PCI_CFG_HFS_3, \ 1386 .fw_status.status[3] = PCI_CFG_HFS_4, \ 1387 .fw_status.status[4] = PCI_CFG_HFS_5, \ 1388 .fw_status.status[5] = PCI_CFG_HFS_6 1389 1390 #define MEI_CFG_DMA_128 \ 1391 .dma_size[DMA_DSCR_HOST] = SZ_128K, \ 1392 .dma_size[DMA_DSCR_DEVICE] = SZ_128K, \ 1393 .dma_size[DMA_DSCR_CTRL] = PAGE_SIZE 1394 1395 /* ICH Legacy devices */ 1396 static const struct mei_cfg mei_me_ich_cfg = { 1397 MEI_CFG_ICH_HFS, 1398 }; 1399 1400 /* ICH devices */ 1401 static const struct mei_cfg mei_me_ich10_cfg = { 1402 MEI_CFG_ICH10_HFS, 1403 }; 1404 1405 /* PCH devices */ 1406 static const struct mei_cfg mei_me_pch_cfg = { 1407 MEI_CFG_PCH_HFS, 1408 }; 1409 1410 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ 1411 static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { 1412 MEI_CFG_PCH_HFS, 1413 MEI_CFG_FW_NM, 1414 }; 1415 1416 /* PCH8 Lynx Point and newer devices */ 1417 static const struct mei_cfg mei_me_pch8_cfg = { 1418 MEI_CFG_PCH8_HFS, 1419 }; 1420 1421 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ 1422 static const struct mei_cfg mei_me_pch8_sps_cfg = { 1423 MEI_CFG_PCH8_HFS, 1424 MEI_CFG_FW_SPS, 1425 }; 1426 1427 /* Cannon Lake and newer devices */ 1428 static const struct mei_cfg mei_me_pch12_cfg = { 1429 MEI_CFG_PCH8_HFS, 1430 MEI_CFG_DMA_128, 1431 }; 1432 1433 /* 1434 * mei_cfg_list - A list of platform platform specific configurations. 1435 * Note: has to be synchronized with enum mei_cfg_idx. 1436 */ 1437 static const struct mei_cfg *const mei_cfg_list[] = { 1438 [MEI_ME_UNDEF_CFG] = NULL, 1439 [MEI_ME_ICH_CFG] = &mei_me_ich_cfg, 1440 [MEI_ME_ICH10_CFG] = &mei_me_ich10_cfg, 1441 [MEI_ME_PCH_CFG] = &mei_me_pch_cfg, 1442 [MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg, 1443 [MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg, 1444 [MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg, 1445 [MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg, 1446 }; 1447 1448 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx) 1449 { 1450 BUILD_BUG_ON(ARRAY_SIZE(mei_cfg_list) != MEI_ME_NUM_CFG); 1451 1452 if (idx >= MEI_ME_NUM_CFG) 1453 return NULL; 1454 1455 return mei_cfg_list[idx]; 1456 }; 1457 1458 /** 1459 * mei_me_dev_init - allocates and initializes the mei device structure 1460 * 1461 * @pdev: The pci device structure 1462 * @cfg: per device generation config 1463 * 1464 * Return: The mei_device pointer on success, NULL on failure. 1465 */ 1466 struct mei_device *mei_me_dev_init(struct pci_dev *pdev, 1467 const struct mei_cfg *cfg) 1468 { 1469 struct mei_device *dev; 1470 struct mei_me_hw *hw; 1471 int i; 1472 1473 dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) + 1474 sizeof(struct mei_me_hw), GFP_KERNEL); 1475 if (!dev) 1476 return NULL; 1477 1478 hw = to_me_hw(dev); 1479 1480 for (i = 0; i < DMA_DSCR_NUM; i++) 1481 dev->dr_dscr[i].size = cfg->dma_size[i]; 1482 1483 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); 1484 hw->cfg = cfg; 1485 1486 return dev; 1487 } 1488 1489