19fff0425STomas Winkler /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 29fff0425STomas Winkler /* 3342e4c7eSTomas Winkler * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. 49dc64d6aSTomas Winkler * Intel Management Engine Interface (Intel MEI) Linux driver 59fff0425STomas Winkler */ 69dc64d6aSTomas Winkler #ifndef _MEI_HW_MEI_REGS_H_ 79dc64d6aSTomas Winkler #define _MEI_HW_MEI_REGS_H_ 89dc64d6aSTomas Winkler 99dc64d6aSTomas Winkler /* 109dc64d6aSTomas Winkler * MEI device IDs 119dc64d6aSTomas Winkler */ 129dc64d6aSTomas Winkler #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */ 139dc64d6aSTomas Winkler #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */ 149dc64d6aSTomas Winkler #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */ 159dc64d6aSTomas Winkler #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */ 169dc64d6aSTomas Winkler 179dc64d6aSTomas Winkler #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */ 189dc64d6aSTomas Winkler #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */ 199dc64d6aSTomas Winkler 209dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */ 219dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */ 229dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */ 239dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */ 249dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */ 259dc64d6aSTomas Winkler 269dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */ 279dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */ 289dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */ 299dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */ 309dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */ 319dc64d6aSTomas Winkler 329dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */ 339dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */ 349dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */ 359dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */ 369dc64d6aSTomas Winkler 379dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */ 389dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */ 399dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */ 409dc64d6aSTomas Winkler #define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */ 419dc64d6aSTomas Winkler 429dc64d6aSTomas Winkler #define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */ 439dc64d6aSTomas Winkler #define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */ 449dc64d6aSTomas Winkler 459dc64d6aSTomas Winkler #define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */ 469dc64d6aSTomas Winkler #define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */ 479dc64d6aSTomas Winkler 489dc64d6aSTomas Winkler #define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */ 499dc64d6aSTomas Winkler #define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */ 509dc64d6aSTomas Winkler #define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */ 519dc64d6aSTomas Winkler 5276a96359STomas Winkler #define MEI_DEV_ID_LPT_H 0x8C3A /* Lynx Point H */ 53838b3a6dSTomas Winkler #define MEI_DEV_ID_LPT_W 0x8D3A /* Lynx Point - Wellsburg */ 549dc64d6aSTomas Winkler #define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */ 5576a96359STomas Winkler #define MEI_DEV_ID_LPT_HR 0x8CBA /* Lynx Point H Refresh */ 5676a96359STomas Winkler 5776a96359STomas Winkler #define MEI_DEV_ID_WPT_LP 0x9CBA /* Wildcat Point LP */ 58d238a0ecSAlexander Usyskin #define MEI_DEV_ID_WPT_LP_2 0x9CBB /* Wildcat Point LP 2 */ 595e6533a6STomas Winkler 601625c7ecSTomas Winkler #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */ 611625c7ecSTomas Winkler #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */ 62372a8298STomas Winkler #define MEI_DEV_ID_SPT_3 0x9D3E /* Sunrise Point 3 (iToutch) */ 631625c7ecSTomas Winkler #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */ 641625c7ecSTomas Winkler #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */ 65dd16f6cdSTomas Winkler 669ff2007bSTomas Winkler #define MEI_DEV_ID_LBG 0xA1BA /* Lewisburg (SPT) */ 679ff2007bSTomas Winkler 68dd16f6cdSTomas Winkler #define MEI_DEV_ID_BXT_M 0x1A9A /* Broxton M */ 69dd16f6cdSTomas Winkler #define MEI_DEV_ID_APL_I 0x5A9A /* Apollo Lake I */ 70dd16f6cdSTomas Winkler 71f7ee8eadSTomas Winkler #define MEI_DEV_ID_DNV_IE 0x19E5 /* Denverton IE */ 72f7ee8eadSTomas Winkler 73688cb678STomas Winkler #define MEI_DEV_ID_GLK 0x319A /* Gemini Lake */ 74688cb678STomas Winkler 75ac182e8aSAlexander Usyskin #define MEI_DEV_ID_KBP 0xA2BA /* Kaby Point */ 76ac182e8aSAlexander Usyskin #define MEI_DEV_ID_KBP_2 0xA2BB /* Kaby Point 2 */ 774afc339eSTomas Winkler #define MEI_DEV_ID_KBP_3 0xA2BE /* Kaby Point 3 (iTouch) */ 78ac182e8aSAlexander Usyskin 79f8f4aa68SAlexander Usyskin #define MEI_DEV_ID_CNP_LP 0x9DE0 /* Cannon Point LP */ 80c23df7deSAlexander Usyskin #define MEI_DEV_ID_CNP_LP_3 0x9DE4 /* Cannon Point LP 3 (iTouch) */ 81f8f4aa68SAlexander Usyskin #define MEI_DEV_ID_CNP_H 0xA360 /* Cannon Point H */ 82c23df7deSAlexander Usyskin #define MEI_DEV_ID_CNP_H_3 0xA364 /* Cannon Point H 3 (iTouch) */ 83f8f4aa68SAlexander Usyskin 844d86dfd3STomas Winkler #define MEI_DEV_ID_CMP_LP 0x02e0 /* Comet Point LP */ 854d86dfd3STomas Winkler #define MEI_DEV_ID_CMP_LP_3 0x02e4 /* Comet Point LP 3 (iTouch) */ 86559e575aSTomas Winkler 8782b29b9fSAlexander Usyskin #define MEI_DEV_ID_CMP_V 0xA3BA /* Comet Point Lake V */ 884d86dfd3STomas Winkler 89559e575aSTomas Winkler #define MEI_DEV_ID_CMP_H 0x06e0 /* Comet Lake H */ 90559e575aSTomas Winkler #define MEI_DEV_ID_CMP_H_3 0x06e4 /* Comet Lake H 3 (iTouch) */ 91559e575aSTomas Winkler 9299397d33SAlexander Usyskin #define MEI_DEV_ID_CDF 0x18D3 /* Cedar Fork */ 9399397d33SAlexander Usyskin 94efe814e9STomas Winkler #define MEI_DEV_ID_ICP_LP 0x34E0 /* Ice Lake Point LP */ 9575c10c5eSAndy Shevchenko #define MEI_DEV_ID_ICP_N 0x38E0 /* Ice Lake Point N */ 96efe814e9STomas Winkler 970db4a15dSTomas Winkler #define MEI_DEV_ID_JSP_N 0x4DE0 /* Jasper Lake Point N */ 980db4a15dSTomas Winkler 99587f1740STomas Winkler #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */ 1008c289ea0SAlexander Usyskin #define MEI_DEV_ID_TGP_H 0x43E0 /* Tiger Lake Point H */ 101587f1740STomas Winkler 1021be8624aSAlexander Usyskin #define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */ 1031be8624aSAlexander Usyskin #define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */ 1041be8624aSAlexander Usyskin 105372726cbSTomas Winkler #define MEI_DEV_ID_EBG 0x1BE0 /* Emmitsburg WS */ 106372726cbSTomas Winkler 107f7545efaSAlexander Usyskin #define MEI_DEV_ID_ADP_S 0x7AE8 /* Alder Lake Point S */ 108930c922aSAlexander Usyskin #define MEI_DEV_ID_ADP_LP 0x7A60 /* Alder Lake Point LP */ 1090df74278STomas Winkler #define MEI_DEV_ID_ADP_P 0x51E0 /* Alder Lake Point P */ 1107bbbd084SAlexander Usyskin #define MEI_DEV_ID_ADP_N 0x54E0 /* Alder Lake Point N */ 111f7545efaSAlexander Usyskin 1123ed8c7d3SAlexander Usyskin #define MEI_DEV_ID_RPL_S 0x7A68 /* Raptor Lake Point S */ 1133ed8c7d3SAlexander Usyskin 1140c4d6826SAlexander Usyskin #define MEI_DEV_ID_MTL_M 0x7E70 /* Meteor Lake Point M */ 1157a9b9012SAlexander Usyskin #define MEI_DEV_ID_ARL_S 0x7F68 /* Arrow Lake Point S */ 1168436f258SAlexander Usyskin #define MEI_DEV_ID_ARL_H 0x7770 /* Arrow Lake Point H */ 1170c4d6826SAlexander Usyskin 118*4108a30fSAlexander Usyskin #define MEI_DEV_ID_LNL_M 0xA870 /* Lunar Lake Point M */ 119*4108a30fSAlexander Usyskin 1209dc64d6aSTomas Winkler /* 1219dc64d6aSTomas Winkler * MEI HW Section 1229dc64d6aSTomas Winkler */ 1239dc64d6aSTomas Winkler 124edca5ea3SAlexander Usyskin /* Host Firmware Status Registers in PCI Config Space */ 125edca5ea3SAlexander Usyskin #define PCI_CFG_HFS_1 0x40 126bb9f4d26SAlexander Usyskin # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000 1274d3c6c8eSTomas Winkler # define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */ 1284d3c6c8eSTomas Winkler # define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */ 129edca5ea3SAlexander Usyskin #define PCI_CFG_HFS_2 0x48 13034a674e9SVitaly Lubart # define PCI_CFG_HFS_2_PM_CMOFF_TO_CMX_ERROR 0x1000000 /* CMoff->CMx wake after an error */ 13134a674e9SVitaly Lubart # define PCI_CFG_HFS_2_PM_CM_RESET_ERROR 0x5000000 /* CME reset due to exception */ 13234a674e9SVitaly Lubart # define PCI_CFG_HFS_2_PM_EVENT_MASK 0xf000000 133edca5ea3SAlexander Usyskin #define PCI_CFG_HFS_3 0x60 134f76d77f5STomas Winkler # define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070 135ccdf6f80SAlexander Usyskin # define PCI_CFG_HFS_3_FW_SKU_IGN 0x00000000 136f76d77f5STomas Winkler # define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060 137edca5ea3SAlexander Usyskin #define PCI_CFG_HFS_4 0x64 138edca5ea3SAlexander Usyskin #define PCI_CFG_HFS_5 0x68 139342e4c7eSTomas Winkler # define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003 140342e4c7eSTomas Winkler # define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3 141edca5ea3SAlexander Usyskin #define PCI_CFG_HFS_6 0x6C 142edca5ea3SAlexander Usyskin 1439dc64d6aSTomas Winkler /* MEI registers */ 1449dc64d6aSTomas Winkler /* H_CB_WW - Host Circular Buffer (CB) Write Window register */ 1459dc64d6aSTomas Winkler #define H_CB_WW 0 1469dc64d6aSTomas Winkler /* H_CSR - Host Control Status register */ 1479dc64d6aSTomas Winkler #define H_CSR 4 1489dc64d6aSTomas Winkler /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */ 1499dc64d6aSTomas Winkler #define ME_CB_RW 8 1509dc64d6aSTomas Winkler /* ME_CSR_HA - ME Control Status Host Access register (read only) */ 1519dc64d6aSTomas Winkler #define ME_CSR_HA 0xC 152ad4d355bSTomas Winkler /* H_HGC_CSR - PGI register */ 153ad4d355bSTomas Winkler #define H_HPG_CSR 0x10 15411830486STomas Winkler /* H_D0I3C - D0I3 Control */ 15511830486STomas Winkler #define H_D0I3C 0x800 1569dc64d6aSTomas Winkler 157342e4c7eSTomas Winkler #define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100 158342e4c7eSTomas Winkler #define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104 159342e4c7eSTomas Winkler #define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108 160342e4c7eSTomas Winkler #define GSC_EXT_OP_MEM_VALID BIT(31) 161342e4c7eSTomas Winkler 1629dc64d6aSTomas Winkler /* register bits of H_CSR (Host Control Status register) */ 1639dc64d6aSTomas Winkler /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ 1649dc64d6aSTomas Winkler #define H_CBD 0xFF000000 1659dc64d6aSTomas Winkler /* Host Circular Buffer Write Pointer */ 1669dc64d6aSTomas Winkler #define H_CBWP 0x00FF0000 1679dc64d6aSTomas Winkler /* Host Circular Buffer Read Pointer */ 1689dc64d6aSTomas Winkler #define H_CBRP 0x0000FF00 1699dc64d6aSTomas Winkler /* Host Reset */ 1709dc64d6aSTomas Winkler #define H_RST 0x00000010 1719dc64d6aSTomas Winkler /* Host Ready */ 1729dc64d6aSTomas Winkler #define H_RDY 0x00000008 1739dc64d6aSTomas Winkler /* Host Interrupt Generate */ 1749dc64d6aSTomas Winkler #define H_IG 0x00000004 1759dc64d6aSTomas Winkler /* Host Interrupt Status */ 1769dc64d6aSTomas Winkler #define H_IS 0x00000002 1779dc64d6aSTomas Winkler /* Host Interrupt Enable */ 1789dc64d6aSTomas Winkler #define H_IE 0x00000001 17911830486STomas Winkler /* Host D0I3 Interrupt Enable */ 18011830486STomas Winkler #define H_D0I3C_IE 0x00000020 18111830486STomas Winkler /* Host D0I3 Interrupt Status */ 18211830486STomas Winkler #define H_D0I3C_IS 0x00000040 1839dc64d6aSTomas Winkler 1841fa55b4eSAlexander Usyskin /* H_CSR masks */ 1851fa55b4eSAlexander Usyskin #define H_CSR_IE_MASK (H_IE | H_D0I3C_IE) 1861fa55b4eSAlexander Usyskin #define H_CSR_IS_MASK (H_IS | H_D0I3C_IS) 1871fa55b4eSAlexander Usyskin 1889dc64d6aSTomas Winkler /* register bits of ME_CSR_HA (ME Control Status Host Access register) */ 1899dc64d6aSTomas Winkler /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only 1909dc64d6aSTomas Winkler access to ME_CBD */ 1919dc64d6aSTomas Winkler #define ME_CBD_HRA 0xFF000000 1929dc64d6aSTomas Winkler /* ME CB Write Pointer HRA - host read only access to ME_CBWP */ 1939dc64d6aSTomas Winkler #define ME_CBWP_HRA 0x00FF0000 1949dc64d6aSTomas Winkler /* ME CB Read Pointer HRA - host read only access to ME_CBRP */ 1959dc64d6aSTomas Winkler #define ME_CBRP_HRA 0x0000FF00 196ad4d355bSTomas Winkler /* ME Power Gate Isolation Capability HRA - host ready only access */ 197ad4d355bSTomas Winkler #define ME_PGIC_HRA 0x00000040 1989dc64d6aSTomas Winkler /* ME Reset HRA - host read only access to ME_RST */ 1999dc64d6aSTomas Winkler #define ME_RST_HRA 0x00000010 2009dc64d6aSTomas Winkler /* ME Ready HRA - host read only access to ME_RDY */ 2019dc64d6aSTomas Winkler #define ME_RDY_HRA 0x00000008 2029dc64d6aSTomas Winkler /* ME Interrupt Generate HRA - host read only access to ME_IG */ 2039dc64d6aSTomas Winkler #define ME_IG_HRA 0x00000004 2049dc64d6aSTomas Winkler /* ME Interrupt Status HRA - host read only access to ME_IS */ 2059dc64d6aSTomas Winkler #define ME_IS_HRA 0x00000002 2069dc64d6aSTomas Winkler /* ME Interrupt Enable HRA - host read only access to ME_IE */ 2079dc64d6aSTomas Winkler #define ME_IE_HRA 0x00000001 20852f6efdfSAlexander Usyskin /* TRC control shadow register */ 20952f6efdfSAlexander Usyskin #define ME_TRC 0x00000030 210ad4d355bSTomas Winkler 21111830486STomas Winkler /* H_HPG_CSR register bits */ 212ad4d355bSTomas Winkler #define H_HPG_CSR_PGIHEXR 0x00000001 213ad4d355bSTomas Winkler #define H_HPG_CSR_PGI 0x00000002 214ad4d355bSTomas Winkler 21511830486STomas Winkler /* H_D0I3C register bits */ 21611830486STomas Winkler #define H_D0I3C_CIP 0x00000001 21711830486STomas Winkler #define H_D0I3C_IR 0x00000002 21811830486STomas Winkler #define H_D0I3C_I3 0x00000004 21911830486STomas Winkler #define H_D0I3C_RR 0x00000008 22011830486STomas Winkler 2219dc64d6aSTomas Winkler #endif /* _MEI_HW_MEI_REGS_H_ */ 222