1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2022 Microchip Technology Inc. 3 // pci1xxxx gpio driver 4 5 #include <linux/module.h> 6 #include <linux/spinlock.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/bio.h> 9 #include <linux/mutex.h> 10 #include <linux/kthread.h> 11 #include <linux/interrupt.h> 12 13 #include "mchp_pci1xxxx_gp.h" 14 15 #define PCI1XXXX_NR_PINS 93 16 #define PERI_GEN_RESET 0 17 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400) 18 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10) 19 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20) 20 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30) 21 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40) 22 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50) 23 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60) 24 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70) 25 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80) 26 #define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0x90) 27 #define INTR_HI_TO_LO_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0xA0) 28 #define INTR_LEVEL_CONFIG_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xB0) 29 #define INTR_LEVEL_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xC0) 30 #define INTR_STAT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xD0) 31 #define DEBOUNCE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xE0) 32 #define PIO_GLOBAL_CONFIG_OFFSET (0x400 + 0xF0) 33 #define PIO_PCI_CTRL_REG_OFFSET (0x400 + 0xF4) 34 #define INTR_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x100) 35 #define INTR_STATUS_OFFSET(x) (((x) * 4) + 0x400 + 0xD0) 36 37 struct pci1xxxx_gpio { 38 struct auxiliary_device *aux_dev; 39 void __iomem *reg_base; 40 struct gpio_chip gpio; 41 spinlock_t lock; 42 int irq_base; 43 }; 44 45 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr) 46 { 47 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 48 u32 data; 49 int ret = -EINVAL; 50 51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); 52 if (data & BIT(nr % 32)) { 53 ret = 1; 54 } else { 55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); 56 if (data & BIT(nr % 32)) 57 ret = 0; 58 } 59 60 return ret; 61 } 62 63 static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset, 64 unsigned int bitpos, bool set) 65 { 66 u32 data; 67 68 data = readl(base_addr + reg_offset); 69 if (set) 70 data |= BIT(bitpos); 71 else 72 data &= ~BIT(bitpos); 73 writel(data, base_addr + reg_offset); 74 } 75 76 static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr) 77 { 78 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 79 unsigned long flags; 80 81 spin_lock_irqsave(&priv->lock, flags); 82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); 83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); 84 spin_unlock_irqrestore(&priv->lock, flags); 85 86 return 0; 87 } 88 89 static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr) 90 { 91 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 92 93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; 94 } 95 96 static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio, 97 unsigned int nr, int val) 98 { 99 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 100 unsigned long flags; 101 u32 data; 102 103 spin_lock_irqsave(&priv->lock, flags); 104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); 105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); 106 data = readl(priv->reg_base + OUT_OFFSET(nr)); 107 if (val) 108 data |= (1 << (nr % 32)); 109 else 110 data &= ~(1 << (nr % 32)); 111 writel(data, priv->reg_base + OUT_OFFSET(nr)); 112 spin_unlock_irqrestore(&priv->lock, flags); 113 114 return 0; 115 } 116 117 static void pci1xxxx_gpio_set(struct gpio_chip *gpio, 118 unsigned int nr, int val) 119 { 120 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 121 unsigned long flags; 122 123 spin_lock_irqsave(&priv->lock, flags); 124 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val); 125 spin_unlock_irqrestore(&priv->lock, flags); 126 } 127 128 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset, 129 unsigned long config) 130 { 131 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 132 unsigned long flags; 133 int ret = 0; 134 135 spin_lock_irqsave(&priv->lock, flags); 136 switch (pinconf_to_config_param(config)) { 137 case PIN_CONFIG_BIAS_PULL_UP: 138 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true); 139 break; 140 case PIN_CONFIG_BIAS_PULL_DOWN: 141 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true); 142 break; 143 case PIN_CONFIG_BIAS_DISABLE: 144 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false); 145 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false); 146 break; 147 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 148 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true); 149 break; 150 case PIN_CONFIG_DRIVE_PUSH_PULL: 151 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), false); 152 break; 153 default: 154 ret = -ENOTSUPP; 155 break; 156 } 157 spin_unlock_irqrestore(&priv->lock, flags); 158 159 return ret; 160 } 161 162 static void pci1xxxx_gpio_irq_ack(struct irq_data *data) 163 { 164 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 165 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip); 166 unsigned int gpio = irqd_to_hwirq(data); 167 unsigned long flags; 168 169 spin_lock_irqsave(&priv->lock, flags); 170 pci1xxx_assign_bit(priv->reg_base, INTR_STAT_OFFSET(gpio), (gpio % 32), true); 171 spin_unlock_irqrestore(&priv->lock, flags); 172 } 173 174 static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set) 175 { 176 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 177 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip); 178 unsigned int gpio = irqd_to_hwirq(data); 179 unsigned long flags; 180 181 if (!set) 182 gpiochip_enable_irq(chip, gpio); 183 spin_lock_irqsave(&priv->lock, flags); 184 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set); 185 spin_unlock_irqrestore(&priv->lock, flags); 186 if (set) 187 gpiochip_disable_irq(chip, gpio); 188 } 189 190 static void pci1xxxx_gpio_irq_mask(struct irq_data *data) 191 { 192 pci1xxxx_gpio_irq_set_mask(data, true); 193 } 194 195 static void pci1xxxx_gpio_irq_unmask(struct irq_data *data) 196 { 197 pci1xxxx_gpio_irq_set_mask(data, false); 198 } 199 200 static int pci1xxxx_gpio_set_type(struct irq_data *data, unsigned int trigger_type) 201 { 202 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 203 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip); 204 unsigned int gpio = irqd_to_hwirq(data); 205 unsigned int bitpos = gpio % 32; 206 207 if (trigger_type & IRQ_TYPE_EDGE_FALLING) { 208 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), 209 bitpos, false); 210 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), 211 bitpos, false); 212 irq_set_handler_locked(data, handle_edge_irq); 213 } else { 214 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), 215 bitpos, true); 216 } 217 218 if (trigger_type & IRQ_TYPE_EDGE_RISING) { 219 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), 220 bitpos, false); 221 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, 222 false); 223 irq_set_handler_locked(data, handle_edge_irq); 224 } else { 225 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), 226 bitpos, true); 227 } 228 229 if (trigger_type & IRQ_TYPE_LEVEL_LOW) { 230 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), 231 bitpos, true); 232 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), 233 bitpos, false); 234 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, 235 true); 236 irq_set_handler_locked(data, handle_edge_irq); 237 } 238 239 if (trigger_type & IRQ_TYPE_LEVEL_HIGH) { 240 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), 241 bitpos, false); 242 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), 243 bitpos, false); 244 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, 245 true); 246 irq_set_handler_locked(data, handle_edge_irq); 247 } 248 249 if ((!(trigger_type & IRQ_TYPE_LEVEL_LOW)) && (!(trigger_type & IRQ_TYPE_LEVEL_HIGH))) 250 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true); 251 252 return true; 253 } 254 255 static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id) 256 { 257 struct pci1xxxx_gpio *priv = dev_id; 258 struct gpio_chip *gc = &priv->gpio; 259 unsigned long int_status = 0; 260 unsigned long flags; 261 u8 pincount; 262 int bit; 263 u8 gpiobank; 264 265 spin_lock_irqsave(&priv->lock, flags); 266 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true); 267 spin_unlock_irqrestore(&priv->lock, flags); 268 for (gpiobank = 0; gpiobank < 3; gpiobank++) { 269 spin_lock_irqsave(&priv->lock, flags); 270 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); 271 spin_unlock_irqrestore(&priv->lock, flags); 272 if (gpiobank == 2) 273 pincount = 29; 274 else 275 pincount = 32; 276 for_each_set_bit(bit, &int_status, pincount) { 277 unsigned int irq; 278 279 spin_lock_irqsave(&priv->lock, flags); 280 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); 281 spin_unlock_irqrestore(&priv->lock, flags); 282 irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32))); 283 handle_nested_irq(irq); 284 } 285 } 286 spin_lock_irqsave(&priv->lock, flags); 287 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false); 288 spin_unlock_irqrestore(&priv->lock, flags); 289 290 return IRQ_HANDLED; 291 } 292 293 static const struct irq_chip pci1xxxx_gpio_irqchip = { 294 .name = "pci1xxxx_gpio", 295 .irq_ack = pci1xxxx_gpio_irq_ack, 296 .irq_mask = pci1xxxx_gpio_irq_mask, 297 .irq_unmask = pci1xxxx_gpio_irq_unmask, 298 .irq_set_type = pci1xxxx_gpio_set_type, 299 .flags = IRQCHIP_IMMUTABLE, 300 GPIOCHIP_IRQ_RESOURCE_HELPERS, 301 }; 302 303 static int pci1xxxx_gpio_suspend(struct device *dev) 304 { 305 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev); 306 unsigned long flags; 307 308 spin_lock_irqsave(&priv->lock, flags); 309 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 310 16, true); 311 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 312 17, false); 313 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true); 314 spin_unlock_irqrestore(&priv->lock, flags); 315 316 return 0; 317 } 318 319 static int pci1xxxx_gpio_resume(struct device *dev) 320 { 321 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev); 322 unsigned long flags; 323 324 spin_lock_irqsave(&priv->lock, flags); 325 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 326 17, true); 327 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 328 16, false); 329 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false); 330 spin_unlock_irqrestore(&priv->lock, flags); 331 332 return 0; 333 } 334 335 static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq) 336 { 337 struct gpio_chip *gchip = &priv->gpio; 338 struct gpio_irq_chip *girq; 339 int retval; 340 341 gchip->label = dev_name(&priv->aux_dev->dev); 342 gchip->parent = &priv->aux_dev->dev; 343 gchip->owner = THIS_MODULE; 344 gchip->direction_input = pci1xxxx_gpio_direction_input; 345 gchip->direction_output = pci1xxxx_gpio_direction_output; 346 gchip->get_direction = pci1xxxx_gpio_get_direction; 347 gchip->get = pci1xxxx_gpio_get; 348 gchip->set = pci1xxxx_gpio_set; 349 gchip->set_config = pci1xxxx_gpio_set_config; 350 gchip->dbg_show = NULL; 351 gchip->base = -1; 352 gchip->ngpio = PCI1XXXX_NR_PINS; 353 gchip->can_sleep = false; 354 355 retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq, 356 NULL, pci1xxxx_gpio_irq_handler, 357 IRQF_ONESHOT, "PCI1xxxxGPIO", priv); 358 359 if (retval) 360 return retval; 361 362 girq = &priv->gpio.irq; 363 gpio_irq_chip_set_chip(girq, &pci1xxxx_gpio_irqchip); 364 girq->parent_handler = NULL; 365 girq->num_parents = 0; 366 girq->parents = NULL; 367 girq->default_type = IRQ_TYPE_NONE; 368 girq->handler = handle_bad_irq; 369 370 return 0; 371 } 372 373 static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev, 374 const struct auxiliary_device_id *id) 375 376 { 377 struct auxiliary_device_wrapper *aux_dev_wrapper; 378 struct gp_aux_data_type *pdata; 379 struct pci1xxxx_gpio *priv; 380 int retval; 381 382 aux_dev_wrapper = (struct auxiliary_device_wrapper *) 383 container_of(aux_dev, struct auxiliary_device_wrapper, aux_dev); 384 385 pdata = &aux_dev_wrapper->gp_aux_data; 386 387 if (!pdata) 388 return -EINVAL; 389 390 priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL); 391 if (!priv) 392 return -ENOMEM; 393 394 spin_lock_init(&priv->lock); 395 priv->aux_dev = aux_dev; 396 397 if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name)) 398 return -EBUSY; 399 400 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800); 401 if (!priv->reg_base) 402 return -ENOMEM; 403 404 writel(0x0264, (priv->reg_base + 0x400 + 0xF0)); 405 406 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num); 407 408 if (retval < 0) 409 return retval; 410 411 dev_set_drvdata(&aux_dev->dev, priv); 412 413 return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv); 414 } 415 416 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_gpio_pm_ops, pci1xxxx_gpio_suspend, pci1xxxx_gpio_resume); 417 418 static const struct auxiliary_device_id pci1xxxx_gpio_auxiliary_id_table[] = { 419 {.name = "mchp_pci1xxxx_gp.gp_gpio"}, 420 {} 421 }; 422 MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_gpio_auxiliary_id_table); 423 424 static struct auxiliary_driver pci1xxxx_gpio_driver = { 425 .driver = { 426 .name = "PCI1xxxxGPIO", 427 .pm = &pci1xxxx_gpio_pm_ops, 428 }, 429 .probe = pci1xxxx_gpio_probe, 430 .id_table = pci1xxxx_gpio_auxiliary_id_table 431 }; 432 module_auxiliary_driver(pci1xxxx_gpio_driver); 433 434 MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx GPIO controller"); 435 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>"); 436 MODULE_LICENSE("GPL"); 437