1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2022 Microchip Technology Inc. 3 // pci1xxxx gpio driver 4 5 #include <linux/module.h> 6 #include <linux/spinlock.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/bio.h> 9 #include <linux/mutex.h> 10 #include <linux/kthread.h> 11 #include <linux/interrupt.h> 12 13 #include "mchp_pci1xxxx_gp.h" 14 15 #define PCI1XXXX_NR_PINS 93 16 #define PERI_GEN_RESET 0 17 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400) 18 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10) 19 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20) 20 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30) 21 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40) 22 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50) 23 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60) 24 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70) 25 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80) 26 #define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0x90) 27 #define INTR_HI_TO_LO_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0xA0) 28 #define INTR_LEVEL_CONFIG_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xB0) 29 #define INTR_LEVEL_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xC0) 30 #define INTR_STAT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xD0) 31 #define DEBOUNCE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xE0) 32 #define PIO_GLOBAL_CONFIG_OFFSET (0x400 + 0xF0) 33 #define PIO_PCI_CTRL_REG_OFFSET (0x400 + 0xF4) 34 #define INTR_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x100) 35 #define INTR_STATUS_OFFSET(x) (((x) * 4) + 0x400 + 0xD0) 36 37 struct pci1xxxx_gpio { 38 struct auxiliary_device *aux_dev; 39 void __iomem *reg_base; 40 raw_spinlock_t wa_lock; 41 struct gpio_chip gpio; 42 spinlock_t lock; 43 int irq_base; 44 }; 45 46 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr) 47 { 48 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 49 u32 data; 50 int ret = -EINVAL; 51 52 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); 53 if (data & BIT(nr % 32)) { 54 ret = 1; 55 } else { 56 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); 57 if (data & BIT(nr % 32)) 58 ret = 0; 59 } 60 61 return ret; 62 } 63 64 static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset, 65 unsigned int bitpos, bool set) 66 { 67 u32 data; 68 69 data = readl(base_addr + reg_offset); 70 if (set) 71 data |= BIT(bitpos); 72 else 73 data &= ~BIT(bitpos); 74 writel(data, base_addr + reg_offset); 75 } 76 77 static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr) 78 { 79 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 80 unsigned long flags; 81 82 spin_lock_irqsave(&priv->lock, flags); 83 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); 84 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); 85 spin_unlock_irqrestore(&priv->lock, flags); 86 87 return 0; 88 } 89 90 static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr) 91 { 92 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 93 94 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; 95 } 96 97 static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio, 98 unsigned int nr, int val) 99 { 100 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 101 unsigned long flags; 102 u32 data; 103 104 spin_lock_irqsave(&priv->lock, flags); 105 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); 106 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); 107 data = readl(priv->reg_base + OUT_OFFSET(nr)); 108 if (val) 109 data |= (1 << (nr % 32)); 110 else 111 data &= ~(1 << (nr % 32)); 112 writel(data, priv->reg_base + OUT_OFFSET(nr)); 113 spin_unlock_irqrestore(&priv->lock, flags); 114 115 return 0; 116 } 117 118 static int pci1xxxx_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val) 119 { 120 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 121 unsigned long flags; 122 123 spin_lock_irqsave(&priv->lock, flags); 124 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val); 125 spin_unlock_irqrestore(&priv->lock, flags); 126 127 return 0; 128 } 129 130 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset, 131 unsigned long config) 132 { 133 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio); 134 unsigned long flags; 135 int ret = 0; 136 137 spin_lock_irqsave(&priv->lock, flags); 138 switch (pinconf_to_config_param(config)) { 139 case PIN_CONFIG_BIAS_PULL_UP: 140 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true); 141 break; 142 case PIN_CONFIG_BIAS_PULL_DOWN: 143 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true); 144 break; 145 case PIN_CONFIG_BIAS_DISABLE: 146 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false); 147 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false); 148 break; 149 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 150 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true); 151 break; 152 case PIN_CONFIG_DRIVE_PUSH_PULL: 153 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), false); 154 break; 155 default: 156 ret = -ENOTSUPP; 157 break; 158 } 159 spin_unlock_irqrestore(&priv->lock, flags); 160 161 return ret; 162 } 163 164 static void pci1xxxx_gpio_irq_ack(struct irq_data *data) 165 { 166 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 167 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip); 168 unsigned int gpio = irqd_to_hwirq(data); 169 unsigned long flags; 170 171 spin_lock_irqsave(&priv->lock, flags); 172 writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio)); 173 spin_unlock_irqrestore(&priv->lock, flags); 174 } 175 176 static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set) 177 { 178 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 179 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip); 180 unsigned int gpio = irqd_to_hwirq(data); 181 unsigned long flags; 182 183 if (!set) 184 gpiochip_enable_irq(chip, gpio); 185 spin_lock_irqsave(&priv->lock, flags); 186 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set); 187 spin_unlock_irqrestore(&priv->lock, flags); 188 if (set) 189 gpiochip_disable_irq(chip, gpio); 190 } 191 192 static void pci1xxxx_gpio_irq_mask(struct irq_data *data) 193 { 194 pci1xxxx_gpio_irq_set_mask(data, true); 195 } 196 197 static void pci1xxxx_gpio_irq_unmask(struct irq_data *data) 198 { 199 pci1xxxx_gpio_irq_set_mask(data, false); 200 } 201 202 static int pci1xxxx_gpio_set_type(struct irq_data *data, unsigned int trigger_type) 203 { 204 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 205 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip); 206 unsigned int gpio = irqd_to_hwirq(data); 207 unsigned int bitpos = gpio % 32; 208 209 if (trigger_type & IRQ_TYPE_EDGE_FALLING) { 210 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), 211 bitpos, false); 212 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), 213 bitpos, false); 214 irq_set_handler_locked(data, handle_edge_irq); 215 } else { 216 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), 217 bitpos, true); 218 } 219 220 if (trigger_type & IRQ_TYPE_EDGE_RISING) { 221 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), 222 bitpos, false); 223 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, 224 false); 225 irq_set_handler_locked(data, handle_edge_irq); 226 } else { 227 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), 228 bitpos, true); 229 } 230 231 if (trigger_type & IRQ_TYPE_LEVEL_LOW) { 232 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), 233 bitpos, true); 234 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), 235 bitpos, false); 236 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, 237 true); 238 irq_set_handler_locked(data, handle_edge_irq); 239 } 240 241 if (trigger_type & IRQ_TYPE_LEVEL_HIGH) { 242 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), 243 bitpos, false); 244 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), 245 bitpos, false); 246 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, 247 true); 248 irq_set_handler_locked(data, handle_edge_irq); 249 } 250 251 if ((!(trigger_type & IRQ_TYPE_LEVEL_LOW)) && (!(trigger_type & IRQ_TYPE_LEVEL_HIGH))) 252 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true); 253 254 return true; 255 } 256 257 static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id) 258 { 259 struct pci1xxxx_gpio *priv = dev_id; 260 struct gpio_chip *gc = &priv->gpio; 261 unsigned long int_status = 0; 262 unsigned long wa_flags; 263 unsigned long flags; 264 u8 pincount; 265 int bit; 266 u8 gpiobank; 267 268 spin_lock_irqsave(&priv->lock, flags); 269 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true); 270 spin_unlock_irqrestore(&priv->lock, flags); 271 for (gpiobank = 0; gpiobank < 3; gpiobank++) { 272 spin_lock_irqsave(&priv->lock, flags); 273 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); 274 spin_unlock_irqrestore(&priv->lock, flags); 275 if (gpiobank == 2) 276 pincount = 29; 277 else 278 pincount = 32; 279 for_each_set_bit(bit, &int_status, pincount) { 280 unsigned int irq; 281 282 spin_lock_irqsave(&priv->lock, flags); 283 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); 284 spin_unlock_irqrestore(&priv->lock, flags); 285 irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32))); 286 raw_spin_lock_irqsave(&priv->wa_lock, wa_flags); 287 generic_handle_irq(irq); 288 raw_spin_unlock_irqrestore(&priv->wa_lock, wa_flags); 289 } 290 } 291 spin_lock_irqsave(&priv->lock, flags); 292 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false); 293 spin_unlock_irqrestore(&priv->lock, flags); 294 295 return IRQ_HANDLED; 296 } 297 298 static const struct irq_chip pci1xxxx_gpio_irqchip = { 299 .name = "pci1xxxx_gpio", 300 .irq_ack = pci1xxxx_gpio_irq_ack, 301 .irq_mask = pci1xxxx_gpio_irq_mask, 302 .irq_unmask = pci1xxxx_gpio_irq_unmask, 303 .irq_set_type = pci1xxxx_gpio_set_type, 304 .flags = IRQCHIP_IMMUTABLE, 305 GPIOCHIP_IRQ_RESOURCE_HELPERS, 306 }; 307 308 static int pci1xxxx_gpio_suspend(struct device *dev) 309 { 310 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev); 311 unsigned long flags; 312 313 spin_lock_irqsave(&priv->lock, flags); 314 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 315 16, true); 316 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 317 17, false); 318 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true); 319 spin_unlock_irqrestore(&priv->lock, flags); 320 321 return 0; 322 } 323 324 static int pci1xxxx_gpio_resume(struct device *dev) 325 { 326 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev); 327 unsigned long flags; 328 329 spin_lock_irqsave(&priv->lock, flags); 330 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 331 17, true); 332 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 333 16, false); 334 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false); 335 spin_unlock_irqrestore(&priv->lock, flags); 336 337 return 0; 338 } 339 340 static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq) 341 { 342 struct gpio_chip *gchip = &priv->gpio; 343 struct gpio_irq_chip *girq; 344 int retval; 345 346 gchip->label = dev_name(&priv->aux_dev->dev); 347 gchip->parent = &priv->aux_dev->dev; 348 gchip->owner = THIS_MODULE; 349 gchip->direction_input = pci1xxxx_gpio_direction_input; 350 gchip->direction_output = pci1xxxx_gpio_direction_output; 351 gchip->get_direction = pci1xxxx_gpio_get_direction; 352 gchip->get = pci1xxxx_gpio_get; 353 gchip->set_rv = pci1xxxx_gpio_set; 354 gchip->set_config = pci1xxxx_gpio_set_config; 355 gchip->dbg_show = NULL; 356 gchip->base = -1; 357 gchip->ngpio = PCI1XXXX_NR_PINS; 358 gchip->can_sleep = false; 359 360 retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq, 361 NULL, pci1xxxx_gpio_irq_handler, 362 IRQF_ONESHOT, "PCI1xxxxGPIO", priv); 363 364 if (retval) 365 return retval; 366 367 girq = &priv->gpio.irq; 368 gpio_irq_chip_set_chip(girq, &pci1xxxx_gpio_irqchip); 369 girq->parent_handler = NULL; 370 girq->num_parents = 0; 371 girq->parents = NULL; 372 girq->default_type = IRQ_TYPE_NONE; 373 girq->handler = handle_bad_irq; 374 375 return 0; 376 } 377 378 static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev, 379 const struct auxiliary_device_id *id) 380 381 { 382 struct auxiliary_device_wrapper *aux_dev_wrapper; 383 struct gp_aux_data_type *pdata; 384 struct pci1xxxx_gpio *priv; 385 int retval; 386 387 aux_dev_wrapper = (struct auxiliary_device_wrapper *) 388 container_of(aux_dev, struct auxiliary_device_wrapper, aux_dev); 389 390 pdata = &aux_dev_wrapper->gp_aux_data; 391 392 if (!pdata) 393 return -EINVAL; 394 395 priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL); 396 if (!priv) 397 return -ENOMEM; 398 399 spin_lock_init(&priv->lock); 400 priv->aux_dev = aux_dev; 401 402 if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name)) 403 return -EBUSY; 404 405 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800); 406 if (!priv->reg_base) 407 return -ENOMEM; 408 409 writel(0x0264, (priv->reg_base + 0x400 + 0xF0)); 410 411 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num); 412 413 if (retval < 0) 414 return retval; 415 416 dev_set_drvdata(&aux_dev->dev, priv); 417 418 return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv); 419 } 420 421 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_gpio_pm_ops, pci1xxxx_gpio_suspend, pci1xxxx_gpio_resume); 422 423 static const struct auxiliary_device_id pci1xxxx_gpio_auxiliary_id_table[] = { 424 {.name = "mchp_pci1xxxx_gp.gp_gpio"}, 425 {} 426 }; 427 MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_gpio_auxiliary_id_table); 428 429 static struct auxiliary_driver pci1xxxx_gpio_driver = { 430 .driver = { 431 .name = "PCI1xxxxGPIO", 432 .pm = &pci1xxxx_gpio_pm_ops, 433 }, 434 .probe = pci1xxxx_gpio_probe, 435 .id_table = pci1xxxx_gpio_auxiliary_id_table 436 }; 437 module_auxiliary_driver(pci1xxxx_gpio_driver); 438 439 MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx GPIO controller"); 440 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>"); 441 MODULE_LICENSE("GPL"); 442