1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) KEBA Industrial Automation Gmbh 2024 4 * 5 * Driver for KEBA system FPGA 6 * 7 * The KEBA system FPGA implements various devices. This driver registers 8 * auxiliary devices for every device within the FPGA. 9 */ 10 11 #include <linux/device.h> 12 #include <linux/i2c.h> 13 #include <linux/misc/keba.h> 14 #include <linux/module.h> 15 #include <linux/mtd/partitions.h> 16 #include <linux/nvmem-consumer.h> 17 #include <linux/nvmem-provider.h> 18 #include <linux/pci.h> 19 #include <linux/spi/flash.h> 20 #include <linux/spi/spi.h> 21 22 #define CP500 "cp500" 23 24 #define PCI_VENDOR_ID_KEBA 0xCEBA 25 #define PCI_DEVICE_ID_KEBA_CP035 0x2706 26 #define PCI_DEVICE_ID_KEBA_CP505 0x2703 27 #define PCI_DEVICE_ID_KEBA_CP520 0x2696 28 29 #define CP500_SYS_BAR 0 30 #define CP500_ECM_BAR 1 31 32 /* BAR 0 registers */ 33 #define CP500_VERSION_REG 0x00 34 #define CP500_RECONFIG_REG 0x11 /* upper 8-bits of STARTUP register */ 35 #define CP500_AXI_REG 0x40 36 37 /* Bits in BUILD_REG */ 38 #define CP500_BUILD_TEST 0x8000 /* FPGA test version */ 39 40 /* Bits in RECONFIG_REG */ 41 #define CP500_RECFG_REQ 0x01 /* reconfigure FPGA on next reset */ 42 43 /* MSIX */ 44 #define CP500_AXI_MSIX 3 45 #define CP500_NUM_MSIX 8 46 #define CP500_NUM_MSIX_NO_MMI 2 47 #define CP500_NUM_MSIX_NO_AXI 3 48 49 /* EEPROM */ 50 #define CP500_EEPROM_DA_OFFSET 0x016F 51 #define CP500_EEPROM_DA_ESC_TYPE_MASK 0x01 52 #define CP500_EEPROM_ESC_LAN9252 0x00 53 #define CP500_EEPROM_ESC_ET1100 0x01 54 #define CP500_EEPROM_CPU_NAME "cpu_eeprom" 55 #define CP500_EEPROM_CPU_OFFSET 0 56 #define CP500_EEPROM_CPU_SIZE 3072 57 #define CP500_EEPROM_USER_NAME "user_eeprom" 58 #define CP500_EEPROM_USER_OFFSET 3072 59 #define CP500_EEPROM_USER_SIZE 1024 60 61 /* SPI flash running at full speed */ 62 #define CP500_FLASH_HZ (33 * 1000 * 1000) 63 64 /* LAN9252 */ 65 #define CP500_LAN9252_HZ (10 * 1000 * 1000) 66 67 #define CP500_IS_CP035(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP035) 68 #define CP500_IS_CP505(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP505) 69 #define CP500_IS_CP520(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP520) 70 71 struct cp500_dev_info { 72 off_t offset; 73 size_t size; 74 }; 75 76 struct cp500_devs { 77 struct cp500_dev_info startup; 78 struct cp500_dev_info spi; 79 struct cp500_dev_info i2c; 80 }; 81 82 /* list of devices within FPGA of CP035 family (CP035, CP056, CP057) */ 83 static struct cp500_devs cp035_devices = { 84 .startup = { 0x0000, SZ_4K }, 85 .spi = { 0x1000, SZ_4K }, 86 .i2c = { 0x4000, SZ_4K }, 87 }; 88 89 /* list of devices within FPGA of CP505 family (CP503, CP505, CP507) */ 90 static struct cp500_devs cp505_devices = { 91 .startup = { 0x0000, SZ_4K }, 92 .spi = { 0x4000, SZ_4K }, 93 .i2c = { 0x5000, SZ_4K }, 94 }; 95 96 /* list of devices within FPGA of CP520 family (CP520, CP530) */ 97 static struct cp500_devs cp520_devices = { 98 .startup = { 0x0000, SZ_4K }, 99 .spi = { 0x4000, SZ_4K }, 100 .i2c = { 0x5000, SZ_4K }, 101 }; 102 103 struct cp500_nvmem { 104 struct nvmem_device *nvmem; 105 unsigned int offset; 106 }; 107 108 struct cp500 { 109 struct pci_dev *pci_dev; 110 struct cp500_devs *devs; 111 int msix_num; 112 struct { 113 int major; 114 int minor; 115 int build; 116 } version; 117 struct notifier_block nvmem_notifier; 118 atomic_t nvmem_notified; 119 120 /* system FPGA BAR */ 121 resource_size_t sys_hwbase; 122 struct keba_spi_auxdev *spi; 123 struct keba_i2c_auxdev *i2c; 124 125 /* ECM EtherCAT BAR */ 126 resource_size_t ecm_hwbase; 127 128 /* NVMEM devices */ 129 struct cp500_nvmem nvmem_cpu; 130 struct cp500_nvmem nvmem_user; 131 132 void __iomem *system_startup_addr; 133 }; 134 135 /* I2C devices */ 136 #define CP500_EEPROM_ADDR 0x50 137 static struct i2c_board_info cp500_i2c_info[] = { 138 { /* temperature sensor */ 139 I2C_BOARD_INFO("emc1403", 0x4c), 140 }, 141 { /* 142 * CPU EEPROM 143 * CP035 family: CPU board 144 * CP505 family: bridge board 145 * CP520 family: carrier board 146 */ 147 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR), 148 }, 149 { /* interface board EEPROM */ 150 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 1), 151 }, 152 { /* 153 * EEPROM (optional) 154 * CP505 family: CPU board 155 * CP520 family: MMI board 156 */ 157 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 2), 158 }, 159 { /* extension module 0 EEPROM (optional) */ 160 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 3), 161 }, 162 { /* extension module 1 EEPROM (optional) */ 163 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 4), 164 }, 165 { /* extension module 2 EEPROM (optional) */ 166 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 5), 167 }, 168 { /* extension module 3 EEPROM (optional) */ 169 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 6), 170 } 171 }; 172 173 /* SPI devices */ 174 static struct mtd_partition cp500_partitions[] = { 175 { 176 .name = "system-flash-parts", 177 .size = MTDPART_SIZ_FULL, 178 .offset = 0, 179 .mask_flags = 0 180 } 181 }; 182 static const struct flash_platform_data cp500_w25q32 = { 183 .type = "w25q32", 184 .name = "system-flash", 185 .parts = cp500_partitions, 186 .nr_parts = ARRAY_SIZE(cp500_partitions), 187 }; 188 static const struct flash_platform_data cp500_m25p16 = { 189 .type = "m25p16", 190 .name = "system-flash", 191 .parts = cp500_partitions, 192 .nr_parts = ARRAY_SIZE(cp500_partitions), 193 }; 194 static struct spi_board_info cp500_spi_info[] = { 195 { /* system FPGA configuration bitstream flash */ 196 .modalias = "m25p80", 197 .platform_data = &cp500_m25p16, 198 .max_speed_hz = CP500_FLASH_HZ, 199 .chip_select = 0, 200 .mode = SPI_MODE_3, 201 }, { /* LAN9252 EtherCAT slave controller */ 202 .modalias = "lan9252", 203 .platform_data = NULL, 204 .max_speed_hz = CP500_LAN9252_HZ, 205 .chip_select = 1, 206 .mode = SPI_MODE_3, 207 } 208 }; 209 210 static ssize_t cp500_get_fpga_version(struct cp500 *cp500, char *buf, 211 size_t max_len) 212 { 213 int n; 214 215 if (CP500_IS_CP035(cp500)) 216 n = scnprintf(buf, max_len, "CP035"); 217 else if (CP500_IS_CP505(cp500)) 218 n = scnprintf(buf, max_len, "CP505"); 219 else 220 n = scnprintf(buf, max_len, "CP500"); 221 222 n += scnprintf(buf + n, max_len - n, "_FPGA_%d.%02d", 223 cp500->version.major, cp500->version.minor); 224 225 /* test versions have test bit set */ 226 if (cp500->version.build & CP500_BUILD_TEST) 227 n += scnprintf(buf + n, max_len - n, "Test%d", 228 cp500->version.build & ~CP500_BUILD_TEST); 229 230 n += scnprintf(buf + n, max_len - n, "\n"); 231 232 return n; 233 } 234 235 static ssize_t version_show(struct device *dev, struct device_attribute *attr, 236 char *buf) 237 { 238 struct cp500 *cp500 = dev_get_drvdata(dev); 239 240 return cp500_get_fpga_version(cp500, buf, PAGE_SIZE); 241 } 242 static DEVICE_ATTR_RO(version); 243 244 static ssize_t keep_cfg_show(struct device *dev, struct device_attribute *attr, 245 char *buf) 246 { 247 struct cp500 *cp500 = dev_get_drvdata(dev); 248 unsigned long keep_cfg = 1; 249 250 /* 251 * FPGA configuration stream is kept during reset when RECONFIG bit is 252 * zero 253 */ 254 if (ioread8(cp500->system_startup_addr + CP500_RECONFIG_REG) & 255 CP500_RECFG_REQ) 256 keep_cfg = 0; 257 258 return sysfs_emit(buf, "%lu\n", keep_cfg); 259 } 260 261 static ssize_t keep_cfg_store(struct device *dev, struct device_attribute *attr, 262 const char *buf, size_t count) 263 { 264 struct cp500 *cp500 = dev_get_drvdata(dev); 265 unsigned long keep_cfg; 266 267 if (kstrtoul(buf, 10, &keep_cfg) < 0) 268 return -EINVAL; 269 270 /* 271 * In normal operation "keep_cfg" is "1". This means that the FPGA keeps 272 * its configuration stream during a reset. 273 * In case of a firmware update of the FPGA, the configuration stream 274 * needs to be reloaded. This can be done without a powercycle by 275 * writing a "0" into the "keep_cfg" attribute. After a reset/reboot th 276 * new configuration stream will be loaded. 277 */ 278 if (keep_cfg) 279 iowrite8(0, cp500->system_startup_addr + CP500_RECONFIG_REG); 280 else 281 iowrite8(CP500_RECFG_REQ, 282 cp500->system_startup_addr + CP500_RECONFIG_REG); 283 284 return count; 285 } 286 static DEVICE_ATTR_RW(keep_cfg); 287 288 static struct attribute *cp500_attrs[] = { 289 &dev_attr_version.attr, 290 &dev_attr_keep_cfg.attr, 291 NULL 292 }; 293 ATTRIBUTE_GROUPS(cp500); 294 295 static void cp500_i2c_release(struct device *dev) 296 { 297 struct keba_i2c_auxdev *i2c = 298 container_of(dev, struct keba_i2c_auxdev, auxdev.dev); 299 300 kfree(i2c); 301 } 302 303 static int cp500_register_i2c(struct cp500 *cp500) 304 { 305 int ret; 306 307 cp500->i2c = kzalloc(sizeof(*cp500->i2c), GFP_KERNEL); 308 if (!cp500->i2c) 309 return -ENOMEM; 310 311 cp500->i2c->auxdev.name = "i2c"; 312 cp500->i2c->auxdev.id = 0; 313 cp500->i2c->auxdev.dev.release = cp500_i2c_release; 314 cp500->i2c->auxdev.dev.parent = &cp500->pci_dev->dev; 315 cp500->i2c->io = (struct resource) { 316 /* I2C register area */ 317 .start = (resource_size_t) cp500->sys_hwbase + 318 cp500->devs->i2c.offset, 319 .end = (resource_size_t) cp500->sys_hwbase + 320 cp500->devs->i2c.offset + 321 cp500->devs->i2c.size - 1, 322 .flags = IORESOURCE_MEM, 323 }; 324 cp500->i2c->info_size = ARRAY_SIZE(cp500_i2c_info); 325 cp500->i2c->info = cp500_i2c_info; 326 327 ret = auxiliary_device_init(&cp500->i2c->auxdev); 328 if (ret) { 329 kfree(cp500->i2c); 330 cp500->i2c = NULL; 331 332 return ret; 333 } 334 ret = __auxiliary_device_add(&cp500->i2c->auxdev, "keba"); 335 if (ret) { 336 auxiliary_device_uninit(&cp500->i2c->auxdev); 337 cp500->i2c = NULL; 338 339 return ret; 340 } 341 342 return 0; 343 } 344 345 static void cp500_spi_release(struct device *dev) 346 { 347 struct keba_spi_auxdev *spi = 348 container_of(dev, struct keba_spi_auxdev, auxdev.dev); 349 350 kfree(spi); 351 } 352 353 static int cp500_register_spi(struct cp500 *cp500, u8 esc_type) 354 { 355 int info_size; 356 int ret; 357 358 cp500->spi = kzalloc(sizeof(*cp500->spi), GFP_KERNEL); 359 if (!cp500->spi) 360 return -ENOMEM; 361 362 if (CP500_IS_CP035(cp500)) 363 cp500_spi_info[0].platform_data = &cp500_w25q32; 364 if (esc_type == CP500_EEPROM_ESC_LAN9252) 365 info_size = ARRAY_SIZE(cp500_spi_info); 366 else 367 info_size = ARRAY_SIZE(cp500_spi_info) - 1; 368 369 cp500->spi->auxdev.name = "spi"; 370 cp500->spi->auxdev.id = 0; 371 cp500->spi->auxdev.dev.release = cp500_spi_release; 372 cp500->spi->auxdev.dev.parent = &cp500->pci_dev->dev; 373 cp500->spi->io = (struct resource) { 374 /* SPI register area */ 375 .start = (resource_size_t) cp500->sys_hwbase + 376 cp500->devs->spi.offset, 377 .end = (resource_size_t) cp500->sys_hwbase + 378 cp500->devs->spi.offset + 379 cp500->devs->spi.size - 1, 380 .flags = IORESOURCE_MEM, 381 }; 382 cp500->spi->info_size = info_size; 383 cp500->spi->info = cp500_spi_info; 384 385 ret = auxiliary_device_init(&cp500->spi->auxdev); 386 if (ret) { 387 kfree(cp500->spi); 388 cp500->spi = NULL; 389 390 return ret; 391 } 392 ret = __auxiliary_device_add(&cp500->spi->auxdev, "keba"); 393 if (ret) { 394 auxiliary_device_uninit(&cp500->spi->auxdev); 395 cp500->spi = NULL; 396 397 return ret; 398 } 399 400 return 0; 401 } 402 403 static int cp500_nvmem_read(void *priv, unsigned int offset, void *val, 404 size_t bytes) 405 { 406 struct cp500_nvmem *nvmem = priv; 407 int ret; 408 409 ret = nvmem_device_read(nvmem->nvmem, nvmem->offset + offset, bytes, 410 val); 411 if (ret != bytes) 412 return ret; 413 414 return 0; 415 } 416 417 static int cp500_nvmem_write(void *priv, unsigned int offset, void *val, 418 size_t bytes) 419 { 420 struct cp500_nvmem *nvmem = priv; 421 int ret; 422 423 ret = nvmem_device_write(nvmem->nvmem, nvmem->offset + offset, bytes, 424 val); 425 if (ret != bytes) 426 return ret; 427 428 return 0; 429 } 430 431 static int cp500_nvmem_register(struct cp500 *cp500, struct nvmem_device *nvmem) 432 { 433 struct device *dev = &cp500->pci_dev->dev; 434 struct nvmem_config nvmem_config = {}; 435 struct nvmem_device *tmp; 436 437 /* 438 * The main EEPROM of CP500 devices is logically split into two EEPROMs. 439 * The first logical EEPROM with 3 kB contains the type label which is 440 * programmed during production of the device. The second logical EEPROM 441 * with 1 kB is not programmed during production and can be used for 442 * arbitrary user data. 443 */ 444 445 nvmem_config.dev = dev; 446 nvmem_config.owner = THIS_MODULE; 447 nvmem_config.id = NVMEM_DEVID_NONE; 448 nvmem_config.type = NVMEM_TYPE_EEPROM; 449 nvmem_config.root_only = true; 450 nvmem_config.reg_read = cp500_nvmem_read; 451 nvmem_config.reg_write = cp500_nvmem_write; 452 453 cp500->nvmem_cpu.nvmem = nvmem; 454 cp500->nvmem_cpu.offset = CP500_EEPROM_CPU_OFFSET; 455 nvmem_config.name = CP500_EEPROM_CPU_NAME; 456 nvmem_config.size = CP500_EEPROM_CPU_SIZE; 457 nvmem_config.priv = &cp500->nvmem_cpu; 458 tmp = devm_nvmem_register(dev, &nvmem_config); 459 if (IS_ERR(tmp)) 460 return PTR_ERR(tmp); 461 462 cp500->nvmem_user.nvmem = nvmem; 463 cp500->nvmem_user.offset = CP500_EEPROM_USER_OFFSET; 464 nvmem_config.name = CP500_EEPROM_USER_NAME; 465 nvmem_config.size = CP500_EEPROM_USER_SIZE; 466 nvmem_config.priv = &cp500->nvmem_user; 467 tmp = devm_nvmem_register(dev, &nvmem_config); 468 if (IS_ERR(tmp)) 469 return PTR_ERR(tmp); 470 471 return 0; 472 } 473 474 static int cp500_nvmem_match(struct device *dev, const void *data) 475 { 476 const struct cp500 *cp500 = data; 477 struct i2c_client *client; 478 479 /* match only CPU EEPROM below the cp500 device */ 480 dev = dev->parent; 481 client = i2c_verify_client(dev); 482 if (!client || client->addr != CP500_EEPROM_ADDR) 483 return 0; 484 while ((dev = dev->parent)) 485 if (dev == &cp500->pci_dev->dev) 486 return 1; 487 488 return 0; 489 } 490 491 static void cp500_devm_nvmem_put(void *data) 492 { 493 struct nvmem_device *nvmem = data; 494 495 nvmem_device_put(nvmem); 496 } 497 498 static int cp500_nvmem(struct notifier_block *nb, unsigned long action, 499 void *data) 500 { 501 struct nvmem_device *nvmem; 502 struct cp500 *cp500; 503 struct device *dev; 504 int notified; 505 u8 esc_type; 506 int ret; 507 508 if (action != NVMEM_ADD) 509 return NOTIFY_DONE; 510 cp500 = container_of(nb, struct cp500, nvmem_notifier); 511 dev = &cp500->pci_dev->dev; 512 513 /* process CPU EEPROM content only once */ 514 notified = atomic_read(&cp500->nvmem_notified); 515 if (notified) 516 return NOTIFY_DONE; 517 nvmem = nvmem_device_find(cp500, cp500_nvmem_match); 518 if (IS_ERR_OR_NULL(nvmem)) 519 return NOTIFY_DONE; 520 if (!atomic_try_cmpxchg_relaxed(&cp500->nvmem_notified, ¬ified, 1)) { 521 nvmem_device_put(nvmem); 522 523 return NOTIFY_DONE; 524 } 525 526 ret = devm_add_action_or_reset(dev, cp500_devm_nvmem_put, nvmem); 527 if (ret) 528 return ret; 529 530 ret = cp500_nvmem_register(cp500, nvmem); 531 if (ret) 532 return ret; 533 534 ret = nvmem_device_read(nvmem, CP500_EEPROM_DA_OFFSET, sizeof(esc_type), 535 (void *)&esc_type); 536 if (ret != sizeof(esc_type)) { 537 dev_warn(dev, "Failed to read device assembly!\n"); 538 539 return NOTIFY_DONE; 540 } 541 esc_type &= CP500_EEPROM_DA_ESC_TYPE_MASK; 542 543 if (cp500_register_spi(cp500, esc_type)) 544 dev_warn(dev, "Failed to register SPI!\n"); 545 546 return NOTIFY_OK; 547 } 548 549 static void cp500_register_auxiliary_devs(struct cp500 *cp500) 550 { 551 struct device *dev = &cp500->pci_dev->dev; 552 553 if (cp500_register_i2c(cp500)) 554 dev_warn(dev, "Failed to register I2C!\n"); 555 } 556 557 static void cp500_unregister_dev(struct auxiliary_device *auxdev) 558 { 559 auxiliary_device_delete(auxdev); 560 auxiliary_device_uninit(auxdev); 561 } 562 563 static void cp500_unregister_auxiliary_devs(struct cp500 *cp500) 564 { 565 if (cp500->spi) { 566 cp500_unregister_dev(&cp500->spi->auxdev); 567 cp500->spi = NULL; 568 } 569 if (cp500->i2c) { 570 cp500_unregister_dev(&cp500->i2c->auxdev); 571 cp500->i2c = NULL; 572 } 573 } 574 575 static irqreturn_t cp500_axi_handler(int irq, void *dev) 576 { 577 struct cp500 *cp500 = dev; 578 u32 axi_address = ioread32(cp500->system_startup_addr + CP500_AXI_REG); 579 580 /* 581 * FPGA signals AXI response error, print AXI address to indicate which 582 * IP core was affected 583 */ 584 dev_err(&cp500->pci_dev->dev, "AXI response error at 0x%08x\n", 585 axi_address); 586 587 return IRQ_HANDLED; 588 } 589 590 static int cp500_enable(struct cp500 *cp500) 591 { 592 int axi_irq = -1; 593 int ret; 594 595 if (cp500->msix_num > CP500_NUM_MSIX_NO_AXI) { 596 axi_irq = pci_irq_vector(cp500->pci_dev, CP500_AXI_MSIX); 597 ret = request_irq(axi_irq, cp500_axi_handler, 0, 598 CP500, cp500); 599 if (ret != 0) { 600 dev_err(&cp500->pci_dev->dev, 601 "Failed to register AXI response error!\n"); 602 return ret; 603 } 604 } 605 606 return 0; 607 } 608 609 static void cp500_disable(struct cp500 *cp500) 610 { 611 int axi_irq; 612 613 if (cp500->msix_num > CP500_NUM_MSIX_NO_AXI) { 614 axi_irq = pci_irq_vector(cp500->pci_dev, CP500_AXI_MSIX); 615 free_irq(axi_irq, cp500); 616 } 617 } 618 619 static int cp500_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) 620 { 621 struct device *dev = &pci_dev->dev; 622 struct resource startup; 623 struct cp500 *cp500; 624 u32 cp500_vers; 625 char buf[64]; 626 int ret; 627 628 cp500 = devm_kzalloc(dev, sizeof(*cp500), GFP_KERNEL); 629 if (!cp500) 630 return -ENOMEM; 631 cp500->pci_dev = pci_dev; 632 cp500->sys_hwbase = pci_resource_start(pci_dev, CP500_SYS_BAR); 633 cp500->ecm_hwbase = pci_resource_start(pci_dev, CP500_ECM_BAR); 634 if (!cp500->sys_hwbase || !cp500->ecm_hwbase) 635 return -ENODEV; 636 637 if (CP500_IS_CP035(cp500)) 638 cp500->devs = &cp035_devices; 639 else if (CP500_IS_CP505(cp500)) 640 cp500->devs = &cp505_devices; 641 else if (CP500_IS_CP520(cp500)) 642 cp500->devs = &cp520_devices; 643 else 644 return -ENODEV; 645 646 ret = pci_enable_device(pci_dev); 647 if (ret) 648 return ret; 649 pci_set_master(pci_dev); 650 651 startup = *pci_resource_n(pci_dev, CP500_SYS_BAR); 652 startup.end = startup.start + cp500->devs->startup.size - 1; 653 cp500->system_startup_addr = devm_ioremap_resource(&pci_dev->dev, 654 &startup); 655 if (IS_ERR(cp500->system_startup_addr)) { 656 ret = PTR_ERR(cp500->system_startup_addr); 657 goto out_disable; 658 } 659 660 cp500->msix_num = pci_alloc_irq_vectors(pci_dev, CP500_NUM_MSIX_NO_MMI, 661 CP500_NUM_MSIX, PCI_IRQ_MSIX); 662 if (cp500->msix_num < CP500_NUM_MSIX_NO_MMI) { 663 dev_err(&pci_dev->dev, 664 "Hardware does not support enough MSI-X interrupts\n"); 665 ret = -ENODEV; 666 goto out_disable; 667 } 668 669 cp500_vers = ioread32(cp500->system_startup_addr + CP500_VERSION_REG); 670 cp500->version.major = (cp500_vers & 0xff); 671 cp500->version.minor = (cp500_vers >> 8) & 0xff; 672 cp500->version.build = (cp500_vers >> 16) & 0xffff; 673 cp500_get_fpga_version(cp500, buf, sizeof(buf)); 674 675 dev_info(&pci_dev->dev, "FPGA version %s", buf); 676 677 pci_set_drvdata(pci_dev, cp500); 678 679 cp500->nvmem_notifier.notifier_call = cp500_nvmem; 680 ret = nvmem_register_notifier(&cp500->nvmem_notifier); 681 if (ret != 0) 682 goto out_free_irq; 683 684 ret = cp500_enable(cp500); 685 if (ret != 0) 686 goto out_unregister_nvmem; 687 688 cp500_register_auxiliary_devs(cp500); 689 690 return 0; 691 692 out_unregister_nvmem: 693 nvmem_unregister_notifier(&cp500->nvmem_notifier); 694 out_free_irq: 695 pci_free_irq_vectors(pci_dev); 696 out_disable: 697 pci_clear_master(pci_dev); 698 pci_disable_device(pci_dev); 699 700 return ret; 701 } 702 703 static void cp500_remove(struct pci_dev *pci_dev) 704 { 705 struct cp500 *cp500 = pci_get_drvdata(pci_dev); 706 707 cp500_unregister_auxiliary_devs(cp500); 708 709 cp500_disable(cp500); 710 711 nvmem_unregister_notifier(&cp500->nvmem_notifier); 712 713 pci_set_drvdata(pci_dev, 0); 714 715 pci_free_irq_vectors(pci_dev); 716 717 pci_clear_master(pci_dev); 718 pci_disable_device(pci_dev); 719 } 720 721 static struct pci_device_id cp500_ids[] = { 722 { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP035) }, 723 { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP505) }, 724 { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP520) }, 725 { } 726 }; 727 MODULE_DEVICE_TABLE(pci, cp500_ids); 728 729 static struct pci_driver cp500_driver = { 730 .name = CP500, 731 .id_table = cp500_ids, 732 .probe = cp500_probe, 733 .remove = cp500_remove, 734 .dev_groups = cp500_groups, 735 }; 736 module_pci_driver(cp500_driver); 737 738 MODULE_AUTHOR("Gerhard Engleder <eg@keba.com>"); 739 MODULE_DESCRIPTION("KEBA CP500 system FPGA driver"); 740 MODULE_LICENSE("GPL"); 741