1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models 4 * 5 * Copyright (C) 2006 David Brownell 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/sched.h> 14 15 #include <linux/nvmem-provider.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spi/eeprom.h> 18 #include <linux/property.h> 19 20 /* 21 * NOTE: this is an *EEPROM* driver. The vagaries of product naming 22 * mean that some AT25 products are EEPROMs, and others are FLASH. 23 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, 24 * not this one! 25 * 26 * EEPROMs that can be used with this driver include, for example: 27 * AT25M02, AT25128B 28 */ 29 30 struct at25_data { 31 struct spi_device *spi; 32 struct mutex lock; 33 struct spi_eeprom chip; 34 unsigned addrlen; 35 struct nvmem_config nvmem_config; 36 struct nvmem_device *nvmem; 37 }; 38 39 #define AT25_WREN 0x06 /* latch the write enable */ 40 #define AT25_WRDI 0x04 /* reset the write enable */ 41 #define AT25_RDSR 0x05 /* read status register */ 42 #define AT25_WRSR 0x01 /* write status register */ 43 #define AT25_READ 0x03 /* read byte(s) */ 44 #define AT25_WRITE 0x02 /* write byte(s)/sector */ 45 46 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ 47 #define AT25_SR_WEN 0x02 /* write enable (latched) */ 48 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ 49 #define AT25_SR_BP1 0x08 50 #define AT25_SR_WPEN 0x80 /* writeprotect enable */ 51 52 #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */ 53 54 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ 55 56 /* Specs often allow 5 msec for a page write, sometimes 20 msec; 57 * it's important to recover from write timeouts. 58 */ 59 #define EE_TIMEOUT 25 60 61 /*-------------------------------------------------------------------------*/ 62 63 #define io_limit PAGE_SIZE /* bytes */ 64 65 static int at25_ee_read(void *priv, unsigned int offset, 66 void *val, size_t count) 67 { 68 struct at25_data *at25 = priv; 69 char *buf = val; 70 u8 command[EE_MAXADDRLEN + 1]; 71 u8 *cp; 72 ssize_t status; 73 struct spi_transfer t[2]; 74 struct spi_message m; 75 u8 instr; 76 77 if (unlikely(offset >= at25->chip.byte_len)) 78 return -EINVAL; 79 if ((offset + count) > at25->chip.byte_len) 80 count = at25->chip.byte_len - offset; 81 if (unlikely(!count)) 82 return -EINVAL; 83 84 cp = command; 85 86 instr = AT25_READ; 87 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 88 if (offset >= (1U << (at25->addrlen * 8))) 89 instr |= AT25_INSTR_BIT3; 90 *cp++ = instr; 91 92 /* 8/16/24-bit address is written MSB first */ 93 switch (at25->addrlen) { 94 default: /* case 3 */ 95 *cp++ = offset >> 16; 96 fallthrough; 97 case 2: 98 *cp++ = offset >> 8; 99 fallthrough; 100 case 1: 101 case 0: /* can't happen: for better codegen */ 102 *cp++ = offset >> 0; 103 } 104 105 spi_message_init(&m); 106 memset(t, 0, sizeof(t)); 107 108 t[0].tx_buf = command; 109 t[0].len = at25->addrlen + 1; 110 spi_message_add_tail(&t[0], &m); 111 112 t[1].rx_buf = buf; 113 t[1].len = count; 114 spi_message_add_tail(&t[1], &m); 115 116 mutex_lock(&at25->lock); 117 118 /* Read it all at once. 119 * 120 * REVISIT that's potentially a problem with large chips, if 121 * other devices on the bus need to be accessed regularly or 122 * this chip is clocked very slowly 123 */ 124 status = spi_sync(at25->spi, &m); 125 dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n", 126 count, offset, status); 127 128 mutex_unlock(&at25->lock); 129 return status; 130 } 131 132 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) 133 { 134 struct at25_data *at25 = priv; 135 const char *buf = val; 136 int status = 0; 137 unsigned buf_size; 138 u8 *bounce; 139 140 if (unlikely(off >= at25->chip.byte_len)) 141 return -EFBIG; 142 if ((off + count) > at25->chip.byte_len) 143 count = at25->chip.byte_len - off; 144 if (unlikely(!count)) 145 return -EINVAL; 146 147 /* Temp buffer starts with command and address */ 148 buf_size = at25->chip.page_size; 149 if (buf_size > io_limit) 150 buf_size = io_limit; 151 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); 152 if (!bounce) 153 return -ENOMEM; 154 155 /* For write, rollover is within the page ... so we write at 156 * most one page, then manually roll over to the next page. 157 */ 158 mutex_lock(&at25->lock); 159 do { 160 unsigned long timeout, retries; 161 unsigned segment; 162 unsigned offset = (unsigned) off; 163 u8 *cp = bounce; 164 int sr; 165 u8 instr; 166 167 *cp = AT25_WREN; 168 status = spi_write(at25->spi, cp, 1); 169 if (status < 0) { 170 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status); 171 break; 172 } 173 174 instr = AT25_WRITE; 175 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 176 if (offset >= (1U << (at25->addrlen * 8))) 177 instr |= AT25_INSTR_BIT3; 178 *cp++ = instr; 179 180 /* 8/16/24-bit address is written MSB first */ 181 switch (at25->addrlen) { 182 default: /* case 3 */ 183 *cp++ = offset >> 16; 184 fallthrough; 185 case 2: 186 *cp++ = offset >> 8; 187 fallthrough; 188 case 1: 189 case 0: /* can't happen: for better codegen */ 190 *cp++ = offset >> 0; 191 } 192 193 /* Write as much of a page as we can */ 194 segment = buf_size - (offset % buf_size); 195 if (segment > count) 196 segment = count; 197 memcpy(cp, buf, segment); 198 status = spi_write(at25->spi, bounce, 199 segment + at25->addrlen + 1); 200 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n", 201 segment, offset, status); 202 if (status < 0) 203 break; 204 205 /* REVISIT this should detect (or prevent) failed writes 206 * to readonly sections of the EEPROM... 207 */ 208 209 /* Wait for non-busy status */ 210 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); 211 retries = 0; 212 do { 213 214 sr = spi_w8r8(at25->spi, AT25_RDSR); 215 if (sr < 0 || (sr & AT25_SR_nRDY)) { 216 dev_dbg(&at25->spi->dev, 217 "rdsr --> %d (%02x)\n", sr, sr); 218 /* at HZ=100, this is sloooow */ 219 msleep(1); 220 continue; 221 } 222 if (!(sr & AT25_SR_nRDY)) 223 break; 224 } while (retries++ < 3 || time_before_eq(jiffies, timeout)); 225 226 if ((sr < 0) || (sr & AT25_SR_nRDY)) { 227 dev_err(&at25->spi->dev, 228 "write %u bytes offset %u, timeout after %u msecs\n", 229 segment, offset, 230 jiffies_to_msecs(jiffies - 231 (timeout - EE_TIMEOUT))); 232 status = -ETIMEDOUT; 233 break; 234 } 235 236 off += segment; 237 buf += segment; 238 count -= segment; 239 240 } while (count > 0); 241 242 mutex_unlock(&at25->lock); 243 244 kfree(bounce); 245 return status; 246 } 247 248 /*-------------------------------------------------------------------------*/ 249 250 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) 251 { 252 u32 val; 253 254 memset(chip, 0, sizeof(*chip)); 255 strncpy(chip->name, "at25", sizeof(chip->name)); 256 257 if (device_property_read_u32(dev, "size", &val) == 0 || 258 device_property_read_u32(dev, "at25,byte-len", &val) == 0) { 259 chip->byte_len = val; 260 } else { 261 dev_err(dev, "Error: missing \"size\" property\n"); 262 return -ENODEV; 263 } 264 265 if (device_property_read_u32(dev, "pagesize", &val) == 0 || 266 device_property_read_u32(dev, "at25,page-size", &val) == 0) { 267 chip->page_size = val; 268 } else { 269 dev_err(dev, "Error: missing \"pagesize\" property\n"); 270 return -ENODEV; 271 } 272 273 if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) { 274 chip->flags = (u16)val; 275 } else { 276 if (device_property_read_u32(dev, "address-width", &val)) { 277 dev_err(dev, 278 "Error: missing \"address-width\" property\n"); 279 return -ENODEV; 280 } 281 switch (val) { 282 case 9: 283 chip->flags |= EE_INSTR_BIT3_IS_ADDR; 284 fallthrough; 285 case 8: 286 chip->flags |= EE_ADDR1; 287 break; 288 case 16: 289 chip->flags |= EE_ADDR2; 290 break; 291 case 24: 292 chip->flags |= EE_ADDR3; 293 break; 294 default: 295 dev_err(dev, 296 "Error: bad \"address-width\" property: %u\n", 297 val); 298 return -ENODEV; 299 } 300 if (device_property_present(dev, "read-only")) 301 chip->flags |= EE_READONLY; 302 } 303 return 0; 304 } 305 306 static int at25_probe(struct spi_device *spi) 307 { 308 struct at25_data *at25 = NULL; 309 struct spi_eeprom chip; 310 int err; 311 int sr; 312 int addrlen; 313 314 /* Chip description */ 315 if (!spi->dev.platform_data) { 316 err = at25_fw_to_chip(&spi->dev, &chip); 317 if (err) 318 return err; 319 } else 320 chip = *(struct spi_eeprom *)spi->dev.platform_data; 321 322 /* For now we only support 8/16/24 bit addressing */ 323 if (chip.flags & EE_ADDR1) 324 addrlen = 1; 325 else if (chip.flags & EE_ADDR2) 326 addrlen = 2; 327 else if (chip.flags & EE_ADDR3) 328 addrlen = 3; 329 else { 330 dev_dbg(&spi->dev, "unsupported address type\n"); 331 return -EINVAL; 332 } 333 334 /* Ping the chip ... the status register is pretty portable, 335 * unlike probing manufacturer IDs. We do expect that system 336 * firmware didn't write it in the past few milliseconds! 337 */ 338 sr = spi_w8r8(spi, AT25_RDSR); 339 if (sr < 0 || sr & AT25_SR_nRDY) { 340 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); 341 return -ENXIO; 342 } 343 344 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL); 345 if (!at25) 346 return -ENOMEM; 347 348 mutex_init(&at25->lock); 349 at25->chip = chip; 350 at25->spi = spi; 351 spi_set_drvdata(spi, at25); 352 at25->addrlen = addrlen; 353 354 at25->nvmem_config.type = NVMEM_TYPE_EEPROM; 355 at25->nvmem_config.name = dev_name(&spi->dev); 356 at25->nvmem_config.dev = &spi->dev; 357 at25->nvmem_config.read_only = chip.flags & EE_READONLY; 358 at25->nvmem_config.root_only = true; 359 at25->nvmem_config.owner = THIS_MODULE; 360 at25->nvmem_config.compat = true; 361 at25->nvmem_config.base_dev = &spi->dev; 362 at25->nvmem_config.reg_read = at25_ee_read; 363 at25->nvmem_config.reg_write = at25_ee_write; 364 at25->nvmem_config.priv = at25; 365 at25->nvmem_config.stride = 1; 366 at25->nvmem_config.word_size = 1; 367 at25->nvmem_config.size = chip.byte_len; 368 369 at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config); 370 if (IS_ERR(at25->nvmem)) 371 return PTR_ERR(at25->nvmem); 372 373 dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n", 374 (chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024), 375 (chip.byte_len < 1024) ? "Byte" : "KByte", 376 at25->chip.name, 377 (chip.flags & EE_READONLY) ? " (readonly)" : "", 378 at25->chip.page_size); 379 return 0; 380 } 381 382 /*-------------------------------------------------------------------------*/ 383 384 static const struct of_device_id at25_of_match[] = { 385 { .compatible = "atmel,at25", }, 386 { } 387 }; 388 MODULE_DEVICE_TABLE(of, at25_of_match); 389 390 static struct spi_driver at25_driver = { 391 .driver = { 392 .name = "at25", 393 .of_match_table = at25_of_match, 394 }, 395 .probe = at25_probe, 396 }; 397 398 module_spi_driver(at25_driver); 399 400 MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); 401 MODULE_AUTHOR("David Brownell"); 402 MODULE_LICENSE("GPL"); 403 MODULE_ALIAS("spi:at25"); 404