1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for most of the SPI EEPROMs, such as Atmel AT25 models 4 * and Cypress FRAMs FM25 models. 5 * 6 * Copyright (C) 2006 David Brownell 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/property.h> 15 #include <linux/sched.h> 16 #include <linux/slab.h> 17 18 #include <linux/spi/eeprom.h> 19 #include <linux/spi/spi.h> 20 21 #include <linux/nvmem-provider.h> 22 23 /* 24 * NOTE: this is an *EEPROM* driver. The vagaries of product naming 25 * mean that some AT25 products are EEPROMs, and others are FLASH. 26 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, 27 * not this one! 28 * 29 * EEPROMs that can be used with this driver include, for example: 30 * AT25M02, AT25128B 31 */ 32 33 #define FM25_SN_LEN 8 /* serial number length */ 34 struct at25_data { 35 struct spi_eeprom chip; 36 struct spi_device *spi; 37 struct mutex lock; 38 unsigned addrlen; 39 struct nvmem_config nvmem_config; 40 struct nvmem_device *nvmem; 41 u8 sernum[FM25_SN_LEN]; 42 }; 43 44 #define AT25_WREN 0x06 /* latch the write enable */ 45 #define AT25_WRDI 0x04 /* reset the write enable */ 46 #define AT25_RDSR 0x05 /* read status register */ 47 #define AT25_WRSR 0x01 /* write status register */ 48 #define AT25_READ 0x03 /* read byte(s) */ 49 #define AT25_WRITE 0x02 /* write byte(s)/sector */ 50 #define FM25_SLEEP 0xb9 /* enter sleep mode */ 51 #define FM25_RDID 0x9f /* read device ID */ 52 #define FM25_RDSN 0xc3 /* read S/N */ 53 54 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ 55 #define AT25_SR_WEN 0x02 /* write enable (latched) */ 56 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ 57 #define AT25_SR_BP1 0x08 58 #define AT25_SR_WPEN 0x80 /* writeprotect enable */ 59 60 #define AT25_INSTR_BIT3 0x08 /* additional address bit in instr */ 61 62 #define FM25_ID_LEN 9 /* ID length */ 63 64 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ 65 66 /* 67 * Specs often allow 5ms for a page write, sometimes 20ms; 68 * it's important to recover from write timeouts. 69 */ 70 #define EE_TIMEOUT 25 71 72 /*-------------------------------------------------------------------------*/ 73 74 #define io_limit PAGE_SIZE /* bytes */ 75 76 static int at25_ee_read(void *priv, unsigned int offset, 77 void *val, size_t count) 78 { 79 struct at25_data *at25 = priv; 80 char *buf = val; 81 u8 command[EE_MAXADDRLEN + 1]; 82 u8 *cp; 83 ssize_t status; 84 struct spi_transfer t[2]; 85 struct spi_message m; 86 u8 instr; 87 88 if (unlikely(offset >= at25->chip.byte_len)) 89 return -EINVAL; 90 if ((offset + count) > at25->chip.byte_len) 91 count = at25->chip.byte_len - offset; 92 if (unlikely(!count)) 93 return -EINVAL; 94 95 cp = command; 96 97 instr = AT25_READ; 98 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 99 if (offset >= BIT(at25->addrlen * 8)) 100 instr |= AT25_INSTR_BIT3; 101 *cp++ = instr; 102 103 /* 8/16/24-bit address is written MSB first */ 104 switch (at25->addrlen) { 105 default: /* case 3 */ 106 *cp++ = offset >> 16; 107 fallthrough; 108 case 2: 109 *cp++ = offset >> 8; 110 fallthrough; 111 case 1: 112 case 0: /* can't happen: for better code generation */ 113 *cp++ = offset >> 0; 114 } 115 116 spi_message_init(&m); 117 memset(t, 0, sizeof(t)); 118 119 t[0].tx_buf = command; 120 t[0].len = at25->addrlen + 1; 121 spi_message_add_tail(&t[0], &m); 122 123 t[1].rx_buf = buf; 124 t[1].len = count; 125 spi_message_add_tail(&t[1], &m); 126 127 mutex_lock(&at25->lock); 128 129 /* 130 * Read it all at once. 131 * 132 * REVISIT that's potentially a problem with large chips, if 133 * other devices on the bus need to be accessed regularly or 134 * this chip is clocked very slowly. 135 */ 136 status = spi_sync(at25->spi, &m); 137 dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n", 138 count, offset, status); 139 140 mutex_unlock(&at25->lock); 141 return status; 142 } 143 144 /* Read extra registers as ID or serial number */ 145 static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command, 146 int len) 147 { 148 int status; 149 struct spi_transfer t[2]; 150 struct spi_message m; 151 152 spi_message_init(&m); 153 memset(t, 0, sizeof(t)); 154 155 t[0].tx_buf = &command; 156 t[0].len = 1; 157 spi_message_add_tail(&t[0], &m); 158 159 t[1].rx_buf = buf; 160 t[1].len = len; 161 spi_message_add_tail(&t[1], &m); 162 163 mutex_lock(&at25->lock); 164 165 status = spi_sync(at25->spi, &m); 166 dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status); 167 168 mutex_unlock(&at25->lock); 169 return status; 170 } 171 172 static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf) 173 { 174 struct at25_data *at25; 175 176 at25 = dev_get_drvdata(dev); 177 return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum); 178 } 179 static DEVICE_ATTR_RO(sernum); 180 181 static struct attribute *sernum_attrs[] = { 182 &dev_attr_sernum.attr, 183 NULL, 184 }; 185 ATTRIBUTE_GROUPS(sernum); 186 187 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) 188 { 189 struct at25_data *at25 = priv; 190 const char *buf = val; 191 int status = 0; 192 unsigned buf_size; 193 u8 *bounce; 194 195 if (unlikely(off >= at25->chip.byte_len)) 196 return -EFBIG; 197 if ((off + count) > at25->chip.byte_len) 198 count = at25->chip.byte_len - off; 199 if (unlikely(!count)) 200 return -EINVAL; 201 202 /* Temp buffer starts with command and address */ 203 buf_size = at25->chip.page_size; 204 if (buf_size > io_limit) 205 buf_size = io_limit; 206 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); 207 if (!bounce) 208 return -ENOMEM; 209 210 /* 211 * For write, rollover is within the page ... so we write at 212 * most one page, then manually roll over to the next page. 213 */ 214 mutex_lock(&at25->lock); 215 do { 216 unsigned long timeout, retries; 217 unsigned segment; 218 unsigned offset = (unsigned) off; 219 u8 *cp = bounce; 220 int sr; 221 u8 instr; 222 223 *cp = AT25_WREN; 224 status = spi_write(at25->spi, cp, 1); 225 if (status < 0) { 226 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status); 227 break; 228 } 229 230 instr = AT25_WRITE; 231 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) 232 if (offset >= BIT(at25->addrlen * 8)) 233 instr |= AT25_INSTR_BIT3; 234 *cp++ = instr; 235 236 /* 8/16/24-bit address is written MSB first */ 237 switch (at25->addrlen) { 238 default: /* case 3 */ 239 *cp++ = offset >> 16; 240 fallthrough; 241 case 2: 242 *cp++ = offset >> 8; 243 fallthrough; 244 case 1: 245 case 0: /* can't happen: for better code generation */ 246 *cp++ = offset >> 0; 247 } 248 249 /* Write as much of a page as we can */ 250 segment = buf_size - (offset % buf_size); 251 if (segment > count) 252 segment = count; 253 memcpy(cp, buf, segment); 254 status = spi_write(at25->spi, bounce, 255 segment + at25->addrlen + 1); 256 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n", 257 segment, offset, status); 258 if (status < 0) 259 break; 260 261 /* 262 * REVISIT this should detect (or prevent) failed writes 263 * to read-only sections of the EEPROM... 264 */ 265 266 /* Wait for non-busy status */ 267 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); 268 retries = 0; 269 do { 270 271 sr = spi_w8r8(at25->spi, AT25_RDSR); 272 if (sr < 0 || (sr & AT25_SR_nRDY)) { 273 dev_dbg(&at25->spi->dev, 274 "rdsr --> %d (%02x)\n", sr, sr); 275 /* at HZ=100, this is sloooow */ 276 msleep(1); 277 continue; 278 } 279 if (!(sr & AT25_SR_nRDY)) 280 break; 281 } while (retries++ < 3 || time_before_eq(jiffies, timeout)); 282 283 if ((sr < 0) || (sr & AT25_SR_nRDY)) { 284 dev_err(&at25->spi->dev, 285 "write %u bytes offset %u, timeout after %u msecs\n", 286 segment, offset, 287 jiffies_to_msecs(jiffies - 288 (timeout - EE_TIMEOUT))); 289 status = -ETIMEDOUT; 290 break; 291 } 292 293 off += segment; 294 buf += segment; 295 count -= segment; 296 297 } while (count > 0); 298 299 mutex_unlock(&at25->lock); 300 301 kfree(bounce); 302 return status; 303 } 304 305 /*-------------------------------------------------------------------------*/ 306 307 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) 308 { 309 u32 val; 310 int err; 311 312 strncpy(chip->name, "at25", sizeof(chip->name)); 313 314 err = device_property_read_u32(dev, "size", &val); 315 if (err) 316 err = device_property_read_u32(dev, "at25,byte-len", &val); 317 if (err) { 318 dev_err(dev, "Error: missing \"size\" property\n"); 319 return err; 320 } 321 chip->byte_len = val; 322 323 err = device_property_read_u32(dev, "pagesize", &val); 324 if (err) 325 err = device_property_read_u32(dev, "at25,page-size", &val); 326 if (err) { 327 dev_err(dev, "Error: missing \"pagesize\" property\n"); 328 return err; 329 } 330 chip->page_size = val; 331 332 err = device_property_read_u32(dev, "address-width", &val); 333 if (err) { 334 err = device_property_read_u32(dev, "at25,addr-mode", &val); 335 if (err) { 336 dev_err(dev, "Error: missing \"address-width\" property\n"); 337 return err; 338 } 339 chip->flags = (u16)val; 340 } else { 341 switch (val) { 342 case 9: 343 chip->flags |= EE_INSTR_BIT3_IS_ADDR; 344 fallthrough; 345 case 8: 346 chip->flags |= EE_ADDR1; 347 break; 348 case 16: 349 chip->flags |= EE_ADDR2; 350 break; 351 case 24: 352 chip->flags |= EE_ADDR3; 353 break; 354 default: 355 dev_err(dev, 356 "Error: bad \"address-width\" property: %u\n", 357 val); 358 return -ENODEV; 359 } 360 if (device_property_present(dev, "read-only")) 361 chip->flags |= EE_READONLY; 362 } 363 return 0; 364 } 365 366 static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip) 367 { 368 struct at25_data *at25 = container_of(chip, struct at25_data, chip); 369 u8 sernum[FM25_SN_LEN]; 370 u8 id[FM25_ID_LEN]; 371 int i; 372 373 strncpy(chip->name, "fm25", sizeof(chip->name)); 374 375 /* Get ID of chip */ 376 fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN); 377 if (id[6] != 0xc2) { 378 dev_err(dev, "Error: no Cypress FRAM (id %02x)\n", id[6]); 379 return -ENODEV; 380 } 381 /* Set size found in ID */ 382 if (id[7] < 0x21 || id[7] > 0x26) { 383 dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]); 384 return -ENODEV; 385 } 386 387 chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024; 388 if (chip->byte_len > 64 * 1024) 389 chip->flags |= EE_ADDR3; 390 else 391 chip->flags |= EE_ADDR2; 392 393 if (id[8]) { 394 fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN); 395 /* Swap byte order */ 396 for (i = 0; i < FM25_SN_LEN; i++) 397 at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i]; 398 } 399 400 chip->page_size = PAGE_SIZE; 401 return 0; 402 } 403 404 static const struct of_device_id at25_of_match[] = { 405 { .compatible = "atmel,at25" }, 406 { .compatible = "cypress,fm25" }, 407 { } 408 }; 409 MODULE_DEVICE_TABLE(of, at25_of_match); 410 411 static const struct spi_device_id at25_spi_ids[] = { 412 { .name = "at25" }, 413 { .name = "fm25" }, 414 { } 415 }; 416 MODULE_DEVICE_TABLE(spi, at25_spi_ids); 417 418 static int at25_probe(struct spi_device *spi) 419 { 420 struct at25_data *at25 = NULL; 421 int err; 422 int sr; 423 struct spi_eeprom *pdata; 424 bool is_fram; 425 426 err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25"); 427 if (err >= 0) 428 is_fram = true; 429 else 430 is_fram = false; 431 432 /* 433 * Ping the chip ... the status register is pretty portable, 434 * unlike probing manufacturer IDs. We do expect that system 435 * firmware didn't write it in the past few milliseconds! 436 */ 437 sr = spi_w8r8(spi, AT25_RDSR); 438 if (sr < 0 || sr & AT25_SR_nRDY) { 439 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); 440 return -ENXIO; 441 } 442 443 at25 = devm_kzalloc(&spi->dev, sizeof(*at25), GFP_KERNEL); 444 if (!at25) 445 return -ENOMEM; 446 447 mutex_init(&at25->lock); 448 at25->spi = spi; 449 spi_set_drvdata(spi, at25); 450 451 /* Chip description */ 452 pdata = dev_get_platdata(&spi->dev); 453 if (pdata) { 454 at25->chip = *pdata; 455 } else { 456 if (is_fram) 457 err = at25_fram_to_chip(&spi->dev, &at25->chip); 458 else 459 err = at25_fw_to_chip(&spi->dev, &at25->chip); 460 if (err) 461 return err; 462 } 463 464 /* For now we only support 8/16/24 bit addressing */ 465 if (at25->chip.flags & EE_ADDR1) 466 at25->addrlen = 1; 467 else if (at25->chip.flags & EE_ADDR2) 468 at25->addrlen = 2; 469 else if (at25->chip.flags & EE_ADDR3) 470 at25->addrlen = 3; 471 else { 472 dev_dbg(&spi->dev, "unsupported address type\n"); 473 return -EINVAL; 474 } 475 476 at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM; 477 at25->nvmem_config.name = dev_name(&spi->dev); 478 at25->nvmem_config.dev = &spi->dev; 479 at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY; 480 at25->nvmem_config.root_only = true; 481 at25->nvmem_config.owner = THIS_MODULE; 482 at25->nvmem_config.compat = true; 483 at25->nvmem_config.base_dev = &spi->dev; 484 at25->nvmem_config.reg_read = at25_ee_read; 485 at25->nvmem_config.reg_write = at25_ee_write; 486 at25->nvmem_config.priv = at25; 487 at25->nvmem_config.stride = 1; 488 at25->nvmem_config.word_size = 1; 489 at25->nvmem_config.size = at25->chip.byte_len; 490 491 at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config); 492 if (IS_ERR(at25->nvmem)) 493 return PTR_ERR(at25->nvmem); 494 495 dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n", 496 (at25->chip.byte_len < 1024) ? 497 at25->chip.byte_len : (at25->chip.byte_len / 1024), 498 (at25->chip.byte_len < 1024) ? "Byte" : "KByte", 499 at25->chip.name, is_fram ? "fram" : "eeprom", 500 (at25->chip.flags & EE_READONLY) ? " (readonly)" : "", 501 at25->chip.page_size); 502 return 0; 503 } 504 505 /*-------------------------------------------------------------------------*/ 506 507 static struct spi_driver at25_driver = { 508 .driver = { 509 .name = "at25", 510 .of_match_table = at25_of_match, 511 .dev_groups = sernum_groups, 512 }, 513 .probe = at25_probe, 514 .id_table = at25_spi_ids, 515 }; 516 517 module_spi_driver(at25_driver); 518 519 MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); 520 MODULE_AUTHOR("David Brownell"); 521 MODULE_LICENSE("GPL"); 522 MODULE_ALIAS("spi:at25"); 523