1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/pci.h> 11 #include <misc/cxl.h> 12 #include <asm/pnv-pci.h> 13 #include "cxl.h" 14 15 static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 16 { 17 if (dma_mask < DMA_BIT_MASK(64)) { 18 pr_info("%s only 64bit DMA supported on CXL", __func__); 19 return -EIO; 20 } 21 22 *(pdev->dev.dma_mask) = dma_mask; 23 return 0; 24 } 25 26 static int cxl_pci_probe_mode(struct pci_bus *bus) 27 { 28 return PCI_PROBE_NORMAL; 29 } 30 31 static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 32 { 33 return -ENODEV; 34 } 35 36 static void cxl_teardown_msi_irqs(struct pci_dev *pdev) 37 { 38 /* 39 * MSI should never be set but need still need to provide this call 40 * back. 41 */ 42 } 43 44 static bool cxl_pci_enable_device_hook(struct pci_dev *dev) 45 { 46 struct pci_controller *phb; 47 struct cxl_afu *afu; 48 49 phb = pci_bus_to_host(dev->bus); 50 afu = (struct cxl_afu *)phb->private_data; 51 52 if (!cxl_ops->link_ok(afu->adapter, afu)) { 53 dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__); 54 return false; 55 } 56 57 set_dma_ops(&dev->dev, &dma_nommu_ops); 58 set_dma_offset(&dev->dev, PAGE_OFFSET); 59 60 return _cxl_pci_associate_default_context(dev, afu); 61 } 62 63 static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus, 64 unsigned long type) 65 { 66 return 1; 67 } 68 69 static void cxl_pci_reset_secondary_bus(struct pci_dev *dev) 70 { 71 /* Should we do an AFU reset here ? */ 72 } 73 74 static int cxl_pcie_cfg_record(u8 bus, u8 devfn) 75 { 76 return (bus << 8) + devfn; 77 } 78 79 static inline struct cxl_afu *pci_bus_to_afu(struct pci_bus *bus) 80 { 81 struct pci_controller *phb = bus ? pci_bus_to_host(bus) : NULL; 82 83 return phb ? phb->private_data : NULL; 84 } 85 86 static void cxl_afu_configured_put(struct cxl_afu *afu) 87 { 88 atomic_dec_if_positive(&afu->configured_state); 89 } 90 91 static bool cxl_afu_configured_get(struct cxl_afu *afu) 92 { 93 return atomic_inc_unless_negative(&afu->configured_state); 94 } 95 96 static inline int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn, 97 struct cxl_afu *afu, int *_record) 98 { 99 int record; 100 101 record = cxl_pcie_cfg_record(bus->number, devfn); 102 if (record > afu->crs_num) 103 return PCIBIOS_DEVICE_NOT_FOUND; 104 105 *_record = record; 106 return 0; 107 } 108 109 static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 110 int offset, int len, u32 *val) 111 { 112 int rc, record; 113 struct cxl_afu *afu; 114 u8 val8; 115 u16 val16; 116 u32 val32; 117 118 afu = pci_bus_to_afu(bus); 119 /* Grab a reader lock on afu. */ 120 if (afu == NULL || !cxl_afu_configured_get(afu)) 121 return PCIBIOS_DEVICE_NOT_FOUND; 122 123 rc = cxl_pcie_config_info(bus, devfn, afu, &record); 124 if (rc) 125 goto out; 126 127 switch (len) { 128 case 1: 129 rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8); 130 *val = val8; 131 break; 132 case 2: 133 rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16); 134 *val = val16; 135 break; 136 case 4: 137 rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32); 138 *val = val32; 139 break; 140 default: 141 WARN_ON(1); 142 } 143 144 out: 145 cxl_afu_configured_put(afu); 146 return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 147 } 148 149 static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 150 int offset, int len, u32 val) 151 { 152 int rc, record; 153 struct cxl_afu *afu; 154 155 afu = pci_bus_to_afu(bus); 156 /* Grab a reader lock on afu. */ 157 if (afu == NULL || !cxl_afu_configured_get(afu)) 158 return PCIBIOS_DEVICE_NOT_FOUND; 159 160 rc = cxl_pcie_config_info(bus, devfn, afu, &record); 161 if (rc) 162 goto out; 163 164 switch (len) { 165 case 1: 166 rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff); 167 break; 168 case 2: 169 rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff); 170 break; 171 case 4: 172 rc = cxl_ops->afu_cr_write32(afu, record, offset, val); 173 break; 174 default: 175 WARN_ON(1); 176 } 177 178 out: 179 cxl_afu_configured_put(afu); 180 return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; 181 } 182 183 static struct pci_ops cxl_pcie_pci_ops = 184 { 185 .read = cxl_pcie_read_config, 186 .write = cxl_pcie_write_config, 187 }; 188 189 190 static struct pci_controller_ops cxl_pci_controller_ops = 191 { 192 .probe_mode = cxl_pci_probe_mode, 193 .enable_device_hook = cxl_pci_enable_device_hook, 194 .disable_device = _cxl_pci_disable_device, 195 .release_device = _cxl_pci_disable_device, 196 .window_alignment = cxl_pci_window_alignment, 197 .reset_secondary_bus = cxl_pci_reset_secondary_bus, 198 .setup_msi_irqs = cxl_setup_msi_irqs, 199 .teardown_msi_irqs = cxl_teardown_msi_irqs, 200 .dma_set_mask = cxl_dma_set_mask, 201 }; 202 203 int cxl_pci_vphb_add(struct cxl_afu *afu) 204 { 205 struct pci_controller *phb; 206 struct device_node *vphb_dn; 207 struct device *parent; 208 209 /* 210 * If there are no AFU configuration records we won't have anything to 211 * expose under the vPHB, so skip creating one, returning success since 212 * this is still a valid case. This will also opt us out of EEH 213 * handling since we won't have anything special to do if there are no 214 * kernel drivers attached to the vPHB, and EEH handling is not yet 215 * supported in the peer model. 216 */ 217 if (!afu->crs_num) 218 return 0; 219 220 /* The parent device is the adapter. Reuse the device node of 221 * the adapter. 222 * We don't seem to care what device node is used for the vPHB, 223 * but tools such as lsvpd walk up the device parents looking 224 * for a valid location code, so we might as well show devices 225 * attached to the adapter as being located on that adapter. 226 */ 227 parent = afu->adapter->dev.parent; 228 vphb_dn = parent->of_node; 229 230 /* Alloc and setup PHB data structure */ 231 phb = pcibios_alloc_controller(vphb_dn); 232 if (!phb) 233 return -ENODEV; 234 235 /* Setup parent in sysfs */ 236 phb->parent = parent; 237 238 /* Setup the PHB using arch provided callback */ 239 phb->ops = &cxl_pcie_pci_ops; 240 phb->cfg_addr = NULL; 241 phb->cfg_data = NULL; 242 phb->private_data = afu; 243 phb->controller_ops = cxl_pci_controller_ops; 244 245 /* Scan the bus */ 246 pcibios_scan_phb(phb); 247 if (phb->bus == NULL) 248 return -ENXIO; 249 250 /* Set release hook on root bus */ 251 pci_set_host_bridge_release(to_pci_host_bridge(phb->bus->bridge), 252 pcibios_free_controller_deferred, 253 (void *) phb); 254 255 /* Claim resources. This might need some rework as well depending 256 * whether we are doing probe-only or not, like assigning unassigned 257 * resources etc... 258 */ 259 pcibios_claim_one_bus(phb->bus); 260 261 /* Add probed PCI devices to the device model */ 262 pci_bus_add_devices(phb->bus); 263 264 afu->phb = phb; 265 266 return 0; 267 } 268 269 void cxl_pci_vphb_remove(struct cxl_afu *afu) 270 { 271 struct pci_controller *phb; 272 273 /* If there is no configuration record we won't have one of these */ 274 if (!afu || !afu->phb) 275 return; 276 277 phb = afu->phb; 278 afu->phb = NULL; 279 280 pci_remove_root_bus(phb->bus); 281 /* 282 * We don't free phb here - that's handled by 283 * pcibios_free_controller_deferred() 284 */ 285 } 286 287 static bool _cxl_pci_is_vphb_device(struct pci_controller *phb) 288 { 289 return (phb->ops == &cxl_pcie_pci_ops); 290 } 291 292 bool cxl_pci_is_vphb_device(struct pci_dev *dev) 293 { 294 struct pci_controller *phb; 295 296 phb = pci_bus_to_host(dev->bus); 297 298 return _cxl_pci_is_vphb_device(phb); 299 } 300 301 struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev) 302 { 303 struct pci_controller *phb; 304 305 phb = pci_bus_to_host(dev->bus); 306 307 if (_cxl_pci_is_vphb_device(phb)) 308 return (struct cxl_afu *)phb->private_data; 309 310 if (pnv_pci_on_cxl_phb(dev)) 311 return pnv_cxl_phb_to_afu(phb); 312 313 return ERR_PTR(-ENODEV); 314 } 315 EXPORT_SYMBOL_GPL(cxl_pci_to_afu); 316 317 unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev) 318 { 319 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn); 320 } 321 EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record); 322