1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/pci_regs.h> 11 #include <linux/pci_ids.h> 12 #include <linux/device.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/sort.h> 17 #include <linux/pci.h> 18 #include <linux/of.h> 19 #include <linux/delay.h> 20 #include <asm/opal.h> 21 #include <asm/msi_bitmap.h> 22 #include <asm/pnv-pci.h> 23 #include <asm/io.h> 24 #include <asm/reg.h> 25 26 #include "cxl.h" 27 #include <misc/cxl.h> 28 29 30 #define CXL_PCI_VSEC_ID 0x1280 31 #define CXL_VSEC_MIN_SIZE 0x80 32 33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ 34 { \ 35 pci_read_config_word(dev, vsec + 0x6, dest); \ 36 *dest >>= 4; \ 37 } 38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ 39 pci_read_config_byte(dev, vsec + 0x8, dest) 40 41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ 42 pci_read_config_byte(dev, vsec + 0x9, dest) 43 #define CXL_STATUS_SECOND_PORT 0x80 44 #define CXL_STATUS_MSI_X_FULL 0x40 45 #define CXL_STATUS_MSI_X_SINGLE 0x20 46 #define CXL_STATUS_FLASH_RW 0x08 47 #define CXL_STATUS_FLASH_RO 0x04 48 #define CXL_STATUS_LOADABLE_AFU 0x02 49 #define CXL_STATUS_LOADABLE_PSL 0x01 50 /* If we see these features we won't try to use the card */ 51 #define CXL_UNSUPPORTED_FEATURES \ 52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) 53 54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ 55 pci_read_config_byte(dev, vsec + 0xa, dest) 56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ 57 pci_write_config_byte(dev, vsec + 0xa, val) 58 #define CXL_VSEC_PROTOCOL_MASK 0xe0 59 #define CXL_VSEC_PROTOCOL_1024TB 0x80 60 #define CXL_VSEC_PROTOCOL_512TB 0x40 61 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */ 62 #define CXL_VSEC_PROTOCOL_ENABLE 0x01 63 64 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ 65 pci_read_config_word(dev, vsec + 0xc, dest) 66 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ 67 pci_read_config_byte(dev, vsec + 0xe, dest) 68 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ 69 pci_read_config_byte(dev, vsec + 0xf, dest) 70 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ 71 pci_read_config_word(dev, vsec + 0x10, dest) 72 73 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ 74 pci_read_config_byte(dev, vsec + 0x13, dest) 75 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ 76 pci_write_config_byte(dev, vsec + 0x13, val) 77 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ 78 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ 79 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ 80 81 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ 82 pci_read_config_dword(dev, vsec + 0x20, dest) 83 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ 84 pci_read_config_dword(dev, vsec + 0x24, dest) 85 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ 86 pci_read_config_dword(dev, vsec + 0x28, dest) 87 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ 88 pci_read_config_dword(dev, vsec + 0x2c, dest) 89 90 91 /* This works a little different than the p1/p2 register accesses to make it 92 * easier to pull out individual fields */ 93 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off) 94 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off) 95 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) 96 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) 97 98 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) 99 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) 100 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) 101 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) 102 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) 103 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) 104 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) 105 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) 106 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) 107 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) 108 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 109 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) 110 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) 111 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) 112 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) 113 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 114 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) 115 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) 116 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 117 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) 118 119 static const struct pci_device_id cxl_pci_tbl[] = { 120 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, 121 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, 122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, 123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), }, 124 { PCI_DEVICE_CLASS(0x120000, ~0), }, 125 126 { } 127 }; 128 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); 129 130 131 /* 132 * Mostly using these wrappers to avoid confusion: 133 * priv 1 is BAR2, while priv 2 is BAR0 134 */ 135 static inline resource_size_t p1_base(struct pci_dev *dev) 136 { 137 return pci_resource_start(dev, 2); 138 } 139 140 static inline resource_size_t p1_size(struct pci_dev *dev) 141 { 142 return pci_resource_len(dev, 2); 143 } 144 145 static inline resource_size_t p2_base(struct pci_dev *dev) 146 { 147 return pci_resource_start(dev, 0); 148 } 149 150 static inline resource_size_t p2_size(struct pci_dev *dev) 151 { 152 return pci_resource_len(dev, 0); 153 } 154 155 static int find_cxl_vsec(struct pci_dev *dev) 156 { 157 int vsec = 0; 158 u16 val; 159 160 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { 161 pci_read_config_word(dev, vsec + 0x4, &val); 162 if (val == CXL_PCI_VSEC_ID) 163 return vsec; 164 } 165 return 0; 166 167 } 168 169 static void dump_cxl_config_space(struct pci_dev *dev) 170 { 171 int vsec; 172 u32 val; 173 174 dev_info(&dev->dev, "dump_cxl_config_space\n"); 175 176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); 177 dev_info(&dev->dev, "BAR0: %#.8x\n", val); 178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); 179 dev_info(&dev->dev, "BAR1: %#.8x\n", val); 180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); 181 dev_info(&dev->dev, "BAR2: %#.8x\n", val); 182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); 183 dev_info(&dev->dev, "BAR3: %#.8x\n", val); 184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); 185 dev_info(&dev->dev, "BAR4: %#.8x\n", val); 186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); 187 dev_info(&dev->dev, "BAR5: %#.8x\n", val); 188 189 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", 190 p1_base(dev), p1_size(dev)); 191 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", 192 p2_base(dev), p2_size(dev)); 193 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", 194 pci_resource_start(dev, 4), pci_resource_len(dev, 4)); 195 196 if (!(vsec = find_cxl_vsec(dev))) 197 return; 198 199 #define show_reg(name, what) \ 200 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) 201 202 pci_read_config_dword(dev, vsec + 0x0, &val); 203 show_reg("Cap ID", (val >> 0) & 0xffff); 204 show_reg("Cap Ver", (val >> 16) & 0xf); 205 show_reg("Next Cap Ptr", (val >> 20) & 0xfff); 206 pci_read_config_dword(dev, vsec + 0x4, &val); 207 show_reg("VSEC ID", (val >> 0) & 0xffff); 208 show_reg("VSEC Rev", (val >> 16) & 0xf); 209 show_reg("VSEC Length", (val >> 20) & 0xfff); 210 pci_read_config_dword(dev, vsec + 0x8, &val); 211 show_reg("Num AFUs", (val >> 0) & 0xff); 212 show_reg("Status", (val >> 8) & 0xff); 213 show_reg("Mode Control", (val >> 16) & 0xff); 214 show_reg("Reserved", (val >> 24) & 0xff); 215 pci_read_config_dword(dev, vsec + 0xc, &val); 216 show_reg("PSL Rev", (val >> 0) & 0xffff); 217 show_reg("CAIA Ver", (val >> 16) & 0xffff); 218 pci_read_config_dword(dev, vsec + 0x10, &val); 219 show_reg("Base Image Rev", (val >> 0) & 0xffff); 220 show_reg("Reserved", (val >> 16) & 0x0fff); 221 show_reg("Image Control", (val >> 28) & 0x3); 222 show_reg("Reserved", (val >> 30) & 0x1); 223 show_reg("Image Loaded", (val >> 31) & 0x1); 224 225 pci_read_config_dword(dev, vsec + 0x14, &val); 226 show_reg("Reserved", val); 227 pci_read_config_dword(dev, vsec + 0x18, &val); 228 show_reg("Reserved", val); 229 pci_read_config_dword(dev, vsec + 0x1c, &val); 230 show_reg("Reserved", val); 231 232 pci_read_config_dword(dev, vsec + 0x20, &val); 233 show_reg("AFU Descriptor Offset", val); 234 pci_read_config_dword(dev, vsec + 0x24, &val); 235 show_reg("AFU Descriptor Size", val); 236 pci_read_config_dword(dev, vsec + 0x28, &val); 237 show_reg("Problem State Offset", val); 238 pci_read_config_dword(dev, vsec + 0x2c, &val); 239 show_reg("Problem State Size", val); 240 241 pci_read_config_dword(dev, vsec + 0x30, &val); 242 show_reg("Reserved", val); 243 pci_read_config_dword(dev, vsec + 0x34, &val); 244 show_reg("Reserved", val); 245 pci_read_config_dword(dev, vsec + 0x38, &val); 246 show_reg("Reserved", val); 247 pci_read_config_dword(dev, vsec + 0x3c, &val); 248 show_reg("Reserved", val); 249 250 pci_read_config_dword(dev, vsec + 0x40, &val); 251 show_reg("PSL Programming Port", val); 252 pci_read_config_dword(dev, vsec + 0x44, &val); 253 show_reg("PSL Programming Control", val); 254 255 pci_read_config_dword(dev, vsec + 0x48, &val); 256 show_reg("Reserved", val); 257 pci_read_config_dword(dev, vsec + 0x4c, &val); 258 show_reg("Reserved", val); 259 260 pci_read_config_dword(dev, vsec + 0x50, &val); 261 show_reg("Flash Address Register", val); 262 pci_read_config_dword(dev, vsec + 0x54, &val); 263 show_reg("Flash Size Register", val); 264 pci_read_config_dword(dev, vsec + 0x58, &val); 265 show_reg("Flash Status/Control Register", val); 266 pci_read_config_dword(dev, vsec + 0x58, &val); 267 show_reg("Flash Data Port", val); 268 269 #undef show_reg 270 } 271 272 static void dump_afu_descriptor(struct cxl_afu *afu) 273 { 274 u64 val, afu_cr_num, afu_cr_off, afu_cr_len; 275 int i; 276 277 #define show_reg(name, what) \ 278 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) 279 280 val = AFUD_READ_INFO(afu); 281 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); 282 show_reg("num_of_processes", AFUD_NUM_PROCS(val)); 283 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); 284 show_reg("req_prog_mode", val & 0xffffULL); 285 afu_cr_num = AFUD_NUM_CRS(val); 286 287 val = AFUD_READ(afu, 0x8); 288 show_reg("Reserved", val); 289 val = AFUD_READ(afu, 0x10); 290 show_reg("Reserved", val); 291 val = AFUD_READ(afu, 0x18); 292 show_reg("Reserved", val); 293 294 val = AFUD_READ_CR(afu); 295 show_reg("Reserved", (val >> (63-7)) & 0xff); 296 show_reg("AFU_CR_len", AFUD_CR_LEN(val)); 297 afu_cr_len = AFUD_CR_LEN(val) * 256; 298 299 val = AFUD_READ_CR_OFF(afu); 300 afu_cr_off = val; 301 show_reg("AFU_CR_offset", val); 302 303 val = AFUD_READ_PPPSA(afu); 304 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); 305 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); 306 307 val = AFUD_READ_PPPSA_OFF(afu); 308 show_reg("PerProcessPSA_offset", val); 309 310 val = AFUD_READ_EB(afu); 311 show_reg("Reserved", (val >> (63-7)) & 0xff); 312 show_reg("AFU_EB_len", AFUD_EB_LEN(val)); 313 314 val = AFUD_READ_EB_OFF(afu); 315 show_reg("AFU_EB_offset", val); 316 317 for (i = 0; i < afu_cr_num; i++) { 318 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len); 319 show_reg("CR Vendor", val & 0xffff); 320 show_reg("CR Device", (val >> 16) & 0xffff); 321 } 322 #undef show_reg 323 } 324 325 #define CAPP_UNIT0_ID 0xBA 326 #define CAPP_UNIT1_ID 0XBE 327 328 static u64 get_capp_unit_id(struct device_node *np) 329 { 330 u32 phb_index; 331 332 /* 333 * For chips other than POWER8NVL, we only have CAPP 0, 334 * irrespective of which PHB is used. 335 */ 336 if (!pvr_version_is(PVR_POWER8NVL)) 337 return CAPP_UNIT0_ID; 338 339 /* 340 * For POWER8NVL, assume CAPP 0 is attached to PHB0 and 341 * CAPP 1 is attached to PHB1. 342 */ 343 if (of_property_read_u32(np, "ibm,phb-index", &phb_index)) 344 return 0; 345 346 if (phb_index == 0) 347 return CAPP_UNIT0_ID; 348 349 if (phb_index == 1) 350 return CAPP_UNIT1_ID; 351 352 return 0; 353 } 354 355 static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 356 { 357 struct device_node *np; 358 const __be32 *prop; 359 u64 psl_dsnctl; 360 u64 chipid; 361 u64 capp_unit_id; 362 363 if (!(np = pnv_pci_get_phb_node(dev))) 364 return -ENODEV; 365 366 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) 367 np = of_get_next_parent(np); 368 if (!np) 369 return -ENODEV; 370 chipid = be32_to_cpup(prop); 371 capp_unit_id = get_capp_unit_id(np); 372 of_node_put(np); 373 if (!capp_unit_id) { 374 pr_err("cxl: invalid capp unit id\n"); 375 return -ENODEV; 376 } 377 378 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */ 379 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */ 380 /* Tell PSL where to route data to */ 381 psl_dsnctl |= (chipid << (63-5)); 382 psl_dsnctl |= (capp_unit_id << (63-13)); 383 384 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); 385 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); 386 /* snoop write mask */ 387 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); 388 /* set fir_accum */ 389 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL); 390 /* for debugging with trace arrays */ 391 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); 392 393 return 0; 394 } 395 396 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6)) 397 #define _2048_250MHZ_CYCLES 1 398 399 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev) 400 { 401 u64 psl_tb; 402 int delta; 403 unsigned int retry = 0; 404 struct device_node *np; 405 406 adapter->psl_timebase_synced = false; 407 408 if (!(np = pnv_pci_get_phb_node(dev))) 409 return; 410 411 /* Do not fail when CAPP timebase sync is not supported by OPAL */ 412 of_node_get(np); 413 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) { 414 of_node_put(np); 415 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n"); 416 return; 417 } 418 of_node_put(np); 419 420 /* 421 * Setup PSL Timebase Control and Status register 422 * with the recommended Timebase Sync Count value 423 */ 424 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT, 425 TBSYNC_CNT(2 * _2048_250MHZ_CYCLES)); 426 427 /* Enable PSL Timebase */ 428 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000); 429 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb); 430 431 /* Wait until CORE TB and PSL TB difference <= 16usecs */ 432 do { 433 msleep(1); 434 if (retry++ > 5) { 435 dev_info(&dev->dev, "PSL timebase can't synchronize\n"); 436 return; 437 } 438 psl_tb = cxl_p1_read(adapter, CXL_PSL_Timebase); 439 delta = mftb() - psl_tb; 440 if (delta < 0) 441 delta = -delta; 442 } while (tb_to_ns(delta) > 16000); 443 444 adapter->psl_timebase_synced = true; 445 return; 446 } 447 448 static int init_implementation_afu_regs(struct cxl_afu *afu) 449 { 450 /* read/write masks for this slice */ 451 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); 452 /* APC read/write masks for this slice */ 453 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); 454 /* for debugging with trace arrays */ 455 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); 456 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S); 457 458 return 0; 459 } 460 461 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, 462 unsigned int virq) 463 { 464 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 465 466 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); 467 } 468 469 int cxl_update_image_control(struct cxl *adapter) 470 { 471 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 472 int rc; 473 int vsec; 474 u8 image_state; 475 476 if (!(vsec = find_cxl_vsec(dev))) { 477 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 478 return -ENODEV; 479 } 480 481 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { 482 dev_err(&dev->dev, "failed to read image state: %i\n", rc); 483 return rc; 484 } 485 486 if (adapter->perst_loads_image) 487 image_state |= CXL_VSEC_PERST_LOADS_IMAGE; 488 else 489 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE; 490 491 if (adapter->perst_select_user) 492 image_state |= CXL_VSEC_PERST_SELECT_USER; 493 else 494 image_state &= ~CXL_VSEC_PERST_SELECT_USER; 495 496 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { 497 dev_err(&dev->dev, "failed to update image control: %i\n", rc); 498 return rc; 499 } 500 501 return 0; 502 } 503 504 int cxl_pci_alloc_one_irq(struct cxl *adapter) 505 { 506 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 507 508 return pnv_cxl_alloc_hwirqs(dev, 1); 509 } 510 511 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq) 512 { 513 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 514 515 return pnv_cxl_release_hwirqs(dev, hwirq, 1); 516 } 517 518 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, 519 struct cxl *adapter, unsigned int num) 520 { 521 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 522 523 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); 524 } 525 526 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, 527 struct cxl *adapter) 528 { 529 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 530 531 pnv_cxl_release_hwirq_ranges(irqs, dev); 532 } 533 534 static int setup_cxl_bars(struct pci_dev *dev) 535 { 536 /* Safety check in case we get backported to < 3.17 without M64 */ 537 if ((p1_base(dev) < 0x100000000ULL) || 538 (p2_base(dev) < 0x100000000ULL)) { 539 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); 540 return -ENODEV; 541 } 542 543 /* 544 * BAR 4/5 has a special meaning for CXL and must be programmed with a 545 * special value corresponding to the CXL protocol address range. 546 * For POWER 8 that means bits 48:49 must be set to 10 547 */ 548 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); 549 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); 550 551 return 0; 552 } 553 554 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */ 555 static int switch_card_to_cxl(struct pci_dev *dev) 556 { 557 int vsec; 558 u8 val; 559 int rc; 560 561 dev_info(&dev->dev, "switch card to CXL\n"); 562 563 if (!(vsec = find_cxl_vsec(dev))) { 564 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 565 return -ENODEV; 566 } 567 568 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { 569 dev_err(&dev->dev, "failed to read current mode control: %i", rc); 570 return rc; 571 } 572 val &= ~CXL_VSEC_PROTOCOL_MASK; 573 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; 574 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { 575 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc); 576 return rc; 577 } 578 /* 579 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states 580 * we must wait 100ms after this mode switch before touching 581 * PCIe config space. 582 */ 583 msleep(100); 584 585 return 0; 586 } 587 588 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 589 { 590 u64 p1n_base, p2n_base, afu_desc; 591 const u64 p1n_size = 0x100; 592 const u64 p2n_size = 0x1000; 593 594 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); 595 p2n_base = p2_base(dev) + (afu->slice * p2n_size); 596 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); 597 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size); 598 599 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size))) 600 goto err; 601 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) 602 goto err1; 603 if (afu_desc) { 604 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size))) 605 goto err2; 606 } 607 608 return 0; 609 err2: 610 iounmap(afu->p2n_mmio); 611 err1: 612 iounmap(afu->native->p1n_mmio); 613 err: 614 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); 615 return -ENOMEM; 616 } 617 618 static void pci_unmap_slice_regs(struct cxl_afu *afu) 619 { 620 if (afu->p2n_mmio) { 621 iounmap(afu->p2n_mmio); 622 afu->p2n_mmio = NULL; 623 } 624 if (afu->native->p1n_mmio) { 625 iounmap(afu->native->p1n_mmio); 626 afu->native->p1n_mmio = NULL; 627 } 628 if (afu->native->afu_desc_mmio) { 629 iounmap(afu->native->afu_desc_mmio); 630 afu->native->afu_desc_mmio = NULL; 631 } 632 } 633 634 void cxl_pci_release_afu(struct device *dev) 635 { 636 struct cxl_afu *afu = to_cxl_afu(dev); 637 638 pr_devel("%s\n", __func__); 639 640 idr_destroy(&afu->contexts_idr); 641 cxl_release_spa(afu); 642 643 kfree(afu->native); 644 kfree(afu); 645 } 646 647 /* Expects AFU struct to have recently been zeroed out */ 648 static int cxl_read_afu_descriptor(struct cxl_afu *afu) 649 { 650 u64 val; 651 652 val = AFUD_READ_INFO(afu); 653 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); 654 afu->max_procs_virtualised = AFUD_NUM_PROCS(val); 655 afu->crs_num = AFUD_NUM_CRS(val); 656 657 if (AFUD_AFU_DIRECTED(val)) 658 afu->modes_supported |= CXL_MODE_DIRECTED; 659 if (AFUD_DEDICATED_PROCESS(val)) 660 afu->modes_supported |= CXL_MODE_DEDICATED; 661 if (AFUD_TIME_SLICED(val)) 662 afu->modes_supported |= CXL_MODE_TIME_SLICED; 663 664 val = AFUD_READ_PPPSA(afu); 665 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; 666 afu->psa = AFUD_PPPSA_PSA(val); 667 if ((afu->pp_psa = AFUD_PPPSA_PP(val))) 668 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); 669 670 val = AFUD_READ_CR(afu); 671 afu->crs_len = AFUD_CR_LEN(val) * 256; 672 afu->crs_offset = AFUD_READ_CR_OFF(afu); 673 674 675 /* eb_len is in multiple of 4K */ 676 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; 677 afu->eb_offset = AFUD_READ_EB_OFF(afu); 678 679 /* eb_off is 4K aligned so lower 12 bits are always zero */ 680 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { 681 dev_warn(&afu->dev, 682 "Invalid AFU error buffer offset %Lx\n", 683 afu->eb_offset); 684 dev_info(&afu->dev, 685 "Ignoring AFU error buffer in the descriptor\n"); 686 /* indicate that no afu buffer exists */ 687 afu->eb_len = 0; 688 } 689 690 return 0; 691 } 692 693 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) 694 { 695 int i, rc; 696 u32 val; 697 698 if (afu->psa && afu->adapter->ps_size < 699 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { 700 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); 701 return -ENODEV; 702 } 703 704 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) 705 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!"); 706 707 for (i = 0; i < afu->crs_num; i++) { 708 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val); 709 if (rc || val == 0) { 710 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); 711 return -EINVAL; 712 } 713 } 714 715 return 0; 716 } 717 718 static int sanitise_afu_regs(struct cxl_afu *afu) 719 { 720 u64 reg; 721 722 /* 723 * Clear out any regs that contain either an IVTE or address or may be 724 * waiting on an acknowledgement to try to be a bit safer as we bring 725 * it online 726 */ 727 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 728 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 729 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); 730 if (cxl_ops->afu_reset(afu)) 731 return -EIO; 732 if (cxl_afu_disable(afu)) 733 return -EIO; 734 if (cxl_psl_purge(afu)) 735 return -EIO; 736 } 737 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); 738 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); 739 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); 740 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); 741 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); 742 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); 743 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); 744 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); 745 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); 746 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); 747 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); 748 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 749 if (reg) { 750 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); 751 if (reg & CXL_PSL_DSISR_TRANS) 752 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 753 else 754 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 755 } 756 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); 757 if (reg) { 758 if (reg & ~0xffff) 759 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); 760 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); 761 } 762 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 763 if (reg) { 764 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); 765 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); 766 } 767 768 return 0; 769 } 770 771 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE 772 /* 773 * afu_eb_read: 774 * Called from sysfs and reads the afu error info buffer. The h/w only supports 775 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte 776 * aligned the function uses a bounce buffer which can be max PAGE_SIZE. 777 */ 778 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, 779 loff_t off, size_t count) 780 { 781 loff_t aligned_start, aligned_end; 782 size_t aligned_length; 783 void *tbuf; 784 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset; 785 786 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) 787 return 0; 788 789 /* calculate aligned read window */ 790 count = min((size_t)(afu->eb_len - off), count); 791 aligned_start = round_down(off, 8); 792 aligned_end = round_up(off + count, 8); 793 aligned_length = aligned_end - aligned_start; 794 795 /* max we can copy in one read is PAGE_SIZE */ 796 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) { 797 aligned_length = ERR_BUFF_MAX_COPY_SIZE; 798 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); 799 } 800 801 /* use bounce buffer for copy */ 802 tbuf = (void *)__get_free_page(GFP_TEMPORARY); 803 if (!tbuf) 804 return -ENOMEM; 805 806 /* perform aligned read from the mmio region */ 807 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length); 808 memcpy(buf, tbuf + (off & 0x7), count); 809 810 free_page((unsigned long)tbuf); 811 812 return count; 813 } 814 815 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 816 { 817 int rc; 818 819 if ((rc = pci_map_slice_regs(afu, adapter, dev))) 820 return rc; 821 822 if ((rc = sanitise_afu_regs(afu))) 823 goto err1; 824 825 /* We need to reset the AFU before we can read the AFU descriptor */ 826 if ((rc = cxl_ops->afu_reset(afu))) 827 goto err1; 828 829 if (cxl_verbose) 830 dump_afu_descriptor(afu); 831 832 if ((rc = cxl_read_afu_descriptor(afu))) 833 goto err1; 834 835 if ((rc = cxl_afu_descriptor_looks_ok(afu))) 836 goto err1; 837 838 if ((rc = init_implementation_afu_regs(afu))) 839 goto err1; 840 841 if ((rc = cxl_native_register_serr_irq(afu))) 842 goto err1; 843 844 if ((rc = cxl_native_register_psl_irq(afu))) 845 goto err2; 846 847 return 0; 848 849 err2: 850 cxl_native_release_serr_irq(afu); 851 err1: 852 pci_unmap_slice_regs(afu); 853 return rc; 854 } 855 856 static void pci_deconfigure_afu(struct cxl_afu *afu) 857 { 858 cxl_native_release_psl_irq(afu); 859 cxl_native_release_serr_irq(afu); 860 pci_unmap_slice_regs(afu); 861 } 862 863 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) 864 { 865 struct cxl_afu *afu; 866 int rc = -ENOMEM; 867 868 afu = cxl_alloc_afu(adapter, slice); 869 if (!afu) 870 return -ENOMEM; 871 872 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL); 873 if (!afu->native) 874 goto err_free_afu; 875 876 mutex_init(&afu->native->spa_mutex); 877 878 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); 879 if (rc) 880 goto err_free_native; 881 882 rc = pci_configure_afu(afu, adapter, dev); 883 if (rc) 884 goto err_free_native; 885 886 /* Don't care if this fails */ 887 cxl_debugfs_afu_add(afu); 888 889 /* 890 * After we call this function we must not free the afu directly, even 891 * if it returns an error! 892 */ 893 if ((rc = cxl_register_afu(afu))) 894 goto err_put1; 895 896 if ((rc = cxl_sysfs_afu_add(afu))) 897 goto err_put1; 898 899 adapter->afu[afu->slice] = afu; 900 901 if ((rc = cxl_pci_vphb_add(afu))) 902 dev_info(&afu->dev, "Can't register vPHB\n"); 903 904 return 0; 905 906 err_put1: 907 pci_deconfigure_afu(afu); 908 cxl_debugfs_afu_remove(afu); 909 device_unregister(&afu->dev); 910 return rc; 911 912 err_free_native: 913 kfree(afu->native); 914 err_free_afu: 915 kfree(afu); 916 return rc; 917 918 } 919 920 static void cxl_pci_remove_afu(struct cxl_afu *afu) 921 { 922 pr_devel("%s\n", __func__); 923 924 if (!afu) 925 return; 926 927 cxl_pci_vphb_remove(afu); 928 cxl_sysfs_afu_remove(afu); 929 cxl_debugfs_afu_remove(afu); 930 931 spin_lock(&afu->adapter->afu_list_lock); 932 afu->adapter->afu[afu->slice] = NULL; 933 spin_unlock(&afu->adapter->afu_list_lock); 934 935 cxl_context_detach_all(afu); 936 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); 937 938 pci_deconfigure_afu(afu); 939 device_unregister(&afu->dev); 940 } 941 942 int cxl_pci_reset(struct cxl *adapter) 943 { 944 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 945 int rc; 946 947 if (adapter->perst_same_image) { 948 dev_warn(&dev->dev, 949 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n"); 950 return -EINVAL; 951 } 952 953 dev_info(&dev->dev, "CXL reset\n"); 954 955 /* pcie_warm_reset requests a fundamental pci reset which includes a 956 * PERST assert/deassert. PERST triggers a loading of the image 957 * if "user" or "factory" is selected in sysfs */ 958 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { 959 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); 960 return rc; 961 } 962 963 return rc; 964 } 965 966 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 967 { 968 if (pci_request_region(dev, 2, "priv 2 regs")) 969 goto err1; 970 if (pci_request_region(dev, 0, "priv 1 regs")) 971 goto err2; 972 973 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx", 974 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); 975 976 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) 977 goto err3; 978 979 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) 980 goto err4; 981 982 return 0; 983 984 err4: 985 iounmap(adapter->native->p1_mmio); 986 adapter->native->p1_mmio = NULL; 987 err3: 988 pci_release_region(dev, 0); 989 err2: 990 pci_release_region(dev, 2); 991 err1: 992 return -ENOMEM; 993 } 994 995 static void cxl_unmap_adapter_regs(struct cxl *adapter) 996 { 997 if (adapter->native->p1_mmio) { 998 iounmap(adapter->native->p1_mmio); 999 adapter->native->p1_mmio = NULL; 1000 pci_release_region(to_pci_dev(adapter->dev.parent), 2); 1001 } 1002 if (adapter->native->p2_mmio) { 1003 iounmap(adapter->native->p2_mmio); 1004 adapter->native->p2_mmio = NULL; 1005 pci_release_region(to_pci_dev(adapter->dev.parent), 0); 1006 } 1007 } 1008 1009 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) 1010 { 1011 int vsec; 1012 u32 afu_desc_off, afu_desc_size; 1013 u32 ps_off, ps_size; 1014 u16 vseclen; 1015 u8 image_state; 1016 1017 if (!(vsec = find_cxl_vsec(dev))) { 1018 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 1019 return -ENODEV; 1020 } 1021 1022 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); 1023 if (vseclen < CXL_VSEC_MIN_SIZE) { 1024 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); 1025 return -EINVAL; 1026 } 1027 1028 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); 1029 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); 1030 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); 1031 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); 1032 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); 1033 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); 1034 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1035 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1036 1037 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); 1038 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); 1039 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); 1040 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); 1041 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); 1042 1043 /* Convert everything to bytes, because there is NO WAY I'd look at the 1044 * code a month later and forget what units these are in ;-) */ 1045 adapter->native->ps_off = ps_off * 64 * 1024; 1046 adapter->ps_size = ps_size * 64 * 1024; 1047 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024; 1048 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024; 1049 1050 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ 1051 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; 1052 1053 return 0; 1054 } 1055 1056 /* 1057 * Workaround a PCIe Host Bridge defect on some cards, that can cause 1058 * malformed Transaction Layer Packet (TLP) errors to be erroneously 1059 * reported. Mask this error in the Uncorrectable Error Mask Register. 1060 * 1061 * The upper nibble of the PSL revision is used to distinguish between 1062 * different cards. The affected ones have it set to 0. 1063 */ 1064 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev) 1065 { 1066 int aer; 1067 u32 data; 1068 1069 if (adapter->psl_rev & 0xf000) 1070 return; 1071 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))) 1072 return; 1073 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data); 1074 if (data & PCI_ERR_UNC_MALF_TLP) 1075 if (data & PCI_ERR_UNC_INTN) 1076 return; 1077 data |= PCI_ERR_UNC_MALF_TLP; 1078 data |= PCI_ERR_UNC_INTN; 1079 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data); 1080 } 1081 1082 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) 1083 { 1084 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) 1085 return -EBUSY; 1086 1087 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { 1088 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); 1089 return -EINVAL; 1090 } 1091 1092 if (!adapter->slices) { 1093 /* Once we support dynamic reprogramming we can use the card if 1094 * it supports loadable AFUs */ 1095 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); 1096 return -EINVAL; 1097 } 1098 1099 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) { 1100 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); 1101 return -EINVAL; 1102 } 1103 1104 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) { 1105 dev_err(&dev->dev, "ABORTING: Problem state size larger than " 1106 "available in BAR2: 0x%llx > 0x%llx\n", 1107 adapter->ps_size, p2_size(dev) - adapter->native->ps_off); 1108 return -EINVAL; 1109 } 1110 1111 return 0; 1112 } 1113 1114 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len) 1115 { 1116 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf); 1117 } 1118 1119 static void cxl_release_adapter(struct device *dev) 1120 { 1121 struct cxl *adapter = to_cxl_adapter(dev); 1122 1123 pr_devel("cxl_release_adapter\n"); 1124 1125 cxl_remove_adapter_nr(adapter); 1126 1127 kfree(adapter->native); 1128 kfree(adapter); 1129 } 1130 1131 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31)) 1132 1133 static int sanitise_adapter_regs(struct cxl *adapter) 1134 { 1135 /* Clear PSL tberror bit by writing 1 to it */ 1136 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror); 1137 return cxl_tlb_slb_invalidate(adapter); 1138 } 1139 1140 /* This should contain *only* operations that can safely be done in 1141 * both creation and recovery. 1142 */ 1143 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev) 1144 { 1145 int rc; 1146 1147 adapter->dev.parent = &dev->dev; 1148 adapter->dev.release = cxl_release_adapter; 1149 pci_set_drvdata(dev, adapter); 1150 1151 rc = pci_enable_device(dev); 1152 if (rc) { 1153 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); 1154 return rc; 1155 } 1156 1157 if ((rc = cxl_read_vsec(adapter, dev))) 1158 return rc; 1159 1160 if ((rc = cxl_vsec_looks_ok(adapter, dev))) 1161 return rc; 1162 1163 cxl_fixup_malformed_tlp(adapter, dev); 1164 1165 if ((rc = setup_cxl_bars(dev))) 1166 return rc; 1167 1168 if ((rc = switch_card_to_cxl(dev))) 1169 return rc; 1170 1171 if ((rc = cxl_update_image_control(adapter))) 1172 return rc; 1173 1174 if ((rc = cxl_map_adapter_regs(adapter, dev))) 1175 return rc; 1176 1177 if ((rc = sanitise_adapter_regs(adapter))) 1178 goto err; 1179 1180 if ((rc = init_implementation_adapter_regs(adapter, dev))) 1181 goto err; 1182 1183 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI))) 1184 goto err; 1185 1186 /* If recovery happened, the last step is to turn on snooping. 1187 * In the non-recovery case this has no effect */ 1188 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) 1189 goto err; 1190 1191 /* Ignore error, adapter init is not dependant on timebase sync */ 1192 cxl_setup_psl_timebase(adapter, dev); 1193 1194 if ((rc = cxl_native_register_psl_err_irq(adapter))) 1195 goto err; 1196 1197 return 0; 1198 1199 err: 1200 cxl_unmap_adapter_regs(adapter); 1201 return rc; 1202 1203 } 1204 1205 static void cxl_deconfigure_adapter(struct cxl *adapter) 1206 { 1207 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); 1208 1209 cxl_native_release_psl_err_irq(adapter); 1210 cxl_unmap_adapter_regs(adapter); 1211 1212 pci_disable_device(pdev); 1213 } 1214 1215 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev) 1216 { 1217 struct cxl *adapter; 1218 int rc; 1219 1220 adapter = cxl_alloc_adapter(); 1221 if (!adapter) 1222 return ERR_PTR(-ENOMEM); 1223 1224 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL); 1225 if (!adapter->native) { 1226 rc = -ENOMEM; 1227 goto err_release; 1228 } 1229 1230 /* Set defaults for parameters which need to persist over 1231 * configure/reconfigure 1232 */ 1233 adapter->perst_loads_image = true; 1234 adapter->perst_same_image = false; 1235 1236 rc = cxl_configure_adapter(adapter, dev); 1237 if (rc) { 1238 pci_disable_device(dev); 1239 goto err_release; 1240 } 1241 1242 /* Don't care if this one fails: */ 1243 cxl_debugfs_adapter_add(adapter); 1244 1245 /* 1246 * After we call this function we must not free the adapter directly, 1247 * even if it returns an error! 1248 */ 1249 if ((rc = cxl_register_adapter(adapter))) 1250 goto err_put1; 1251 1252 if ((rc = cxl_sysfs_adapter_add(adapter))) 1253 goto err_put1; 1254 1255 return adapter; 1256 1257 err_put1: 1258 /* This should mirror cxl_remove_adapter, except without the 1259 * sysfs parts 1260 */ 1261 cxl_debugfs_adapter_remove(adapter); 1262 cxl_deconfigure_adapter(adapter); 1263 device_unregister(&adapter->dev); 1264 return ERR_PTR(rc); 1265 1266 err_release: 1267 cxl_release_adapter(&adapter->dev); 1268 return ERR_PTR(rc); 1269 } 1270 1271 static void cxl_pci_remove_adapter(struct cxl *adapter) 1272 { 1273 pr_devel("cxl_remove_adapter\n"); 1274 1275 cxl_sysfs_adapter_remove(adapter); 1276 cxl_debugfs_adapter_remove(adapter); 1277 1278 cxl_deconfigure_adapter(adapter); 1279 1280 device_unregister(&adapter->dev); 1281 } 1282 1283 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) 1284 { 1285 struct cxl *adapter; 1286 int slice; 1287 int rc; 1288 1289 if (cxl_pci_is_vphb_device(dev)) { 1290 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n"); 1291 return -ENODEV; 1292 } 1293 1294 if (cxl_verbose) 1295 dump_cxl_config_space(dev); 1296 1297 adapter = cxl_pci_init_adapter(dev); 1298 if (IS_ERR(adapter)) { 1299 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); 1300 return PTR_ERR(adapter); 1301 } 1302 1303 for (slice = 0; slice < adapter->slices; slice++) { 1304 if ((rc = pci_init_afu(adapter, slice, dev))) { 1305 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); 1306 continue; 1307 } 1308 1309 rc = cxl_afu_select_best_mode(adapter->afu[slice]); 1310 if (rc) 1311 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); 1312 } 1313 1314 return 0; 1315 } 1316 1317 static void cxl_remove(struct pci_dev *dev) 1318 { 1319 struct cxl *adapter = pci_get_drvdata(dev); 1320 struct cxl_afu *afu; 1321 int i; 1322 1323 /* 1324 * Lock to prevent someone grabbing a ref through the adapter list as 1325 * we are removing it 1326 */ 1327 for (i = 0; i < adapter->slices; i++) { 1328 afu = adapter->afu[i]; 1329 cxl_pci_remove_afu(afu); 1330 } 1331 cxl_pci_remove_adapter(adapter); 1332 } 1333 1334 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu, 1335 pci_channel_state_t state) 1336 { 1337 struct pci_dev *afu_dev; 1338 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; 1339 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET; 1340 1341 /* There should only be one entry, but go through the list 1342 * anyway 1343 */ 1344 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1345 if (!afu_dev->driver) 1346 continue; 1347 1348 afu_dev->error_state = state; 1349 1350 if (afu_dev->driver->err_handler) 1351 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev, 1352 state); 1353 /* Disconnect trumps all, NONE trumps NEED_RESET */ 1354 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 1355 result = PCI_ERS_RESULT_DISCONNECT; 1356 else if ((afu_result == PCI_ERS_RESULT_NONE) && 1357 (result == PCI_ERS_RESULT_NEED_RESET)) 1358 result = PCI_ERS_RESULT_NONE; 1359 } 1360 return result; 1361 } 1362 1363 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, 1364 pci_channel_state_t state) 1365 { 1366 struct cxl *adapter = pci_get_drvdata(pdev); 1367 struct cxl_afu *afu; 1368 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; 1369 int i; 1370 1371 /* At this point, we could still have an interrupt pending. 1372 * Let's try to get them out of the way before they do 1373 * anything we don't like. 1374 */ 1375 schedule(); 1376 1377 /* If we're permanently dead, give up. */ 1378 if (state == pci_channel_io_perm_failure) { 1379 /* Tell the AFU drivers; but we don't care what they 1380 * say, we're going away. 1381 */ 1382 for (i = 0; i < adapter->slices; i++) { 1383 afu = adapter->afu[i]; 1384 cxl_vphb_error_detected(afu, state); 1385 } 1386 return PCI_ERS_RESULT_DISCONNECT; 1387 } 1388 1389 /* Are we reflashing? 1390 * 1391 * If we reflash, we could come back as something entirely 1392 * different, including a non-CAPI card. As such, by default 1393 * we don't participate in the process. We'll be unbound and 1394 * the slot re-probed. (TODO: check EEH doesn't blindly rebind 1395 * us!) 1396 * 1397 * However, this isn't the entire story: for reliablity 1398 * reasons, we usually want to reflash the FPGA on PERST in 1399 * order to get back to a more reliable known-good state. 1400 * 1401 * This causes us a bit of a problem: if we reflash we can't 1402 * trust that we'll come back the same - we could have a new 1403 * image and been PERSTed in order to load that 1404 * image. However, most of the time we actually *will* come 1405 * back the same - for example a regular EEH event. 1406 * 1407 * Therefore, we allow the user to assert that the image is 1408 * indeed the same and that we should continue on into EEH 1409 * anyway. 1410 */ 1411 if (adapter->perst_loads_image && !adapter->perst_same_image) { 1412 /* TODO take the PHB out of CXL mode */ 1413 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); 1414 return PCI_ERS_RESULT_NONE; 1415 } 1416 1417 /* 1418 * At this point, we want to try to recover. We'll always 1419 * need a complete slot reset: we don't trust any other reset. 1420 * 1421 * Now, we go through each AFU: 1422 * - We send the driver, if bound, an error_detected callback. 1423 * We expect it to clean up, but it can also tell us to give 1424 * up and permanently detach the card. To simplify things, if 1425 * any bound AFU driver doesn't support EEH, we give up on EEH. 1426 * 1427 * - We detach all contexts associated with the AFU. This 1428 * does not free them, but puts them into a CLOSED state 1429 * which causes any the associated files to return useful 1430 * errors to userland. It also unmaps, but does not free, 1431 * any IRQs. 1432 * 1433 * - We clean up our side: releasing and unmapping resources we hold 1434 * so we can wire them up again when the hardware comes back up. 1435 * 1436 * Driver authors should note: 1437 * 1438 * - Any contexts you create in your kernel driver (except 1439 * those associated with anonymous file descriptors) are 1440 * your responsibility to free and recreate. Likewise with 1441 * any attached resources. 1442 * 1443 * - We will take responsibility for re-initialising the 1444 * device context (the one set up for you in 1445 * cxl_pci_enable_device_hook and accessed through 1446 * cxl_get_context). If you've attached IRQs or other 1447 * resources to it, they remains yours to free. 1448 * 1449 * You can call the same functions to release resources as you 1450 * normally would: we make sure that these functions continue 1451 * to work when the hardware is down. 1452 * 1453 * Two examples: 1454 * 1455 * 1) If you normally free all your resources at the end of 1456 * each request, or if you use anonymous FDs, your 1457 * error_detected callback can simply set a flag to tell 1458 * your driver not to start any new calls. You can then 1459 * clear the flag in the resume callback. 1460 * 1461 * 2) If you normally allocate your resources on startup: 1462 * * Set a flag in error_detected as above. 1463 * * Let CXL detach your contexts. 1464 * * In slot_reset, free the old resources and allocate new ones. 1465 * * In resume, clear the flag to allow things to start. 1466 */ 1467 for (i = 0; i < adapter->slices; i++) { 1468 afu = adapter->afu[i]; 1469 1470 result = cxl_vphb_error_detected(afu, state); 1471 1472 /* Only continue if everyone agrees on NEED_RESET */ 1473 if (result != PCI_ERS_RESULT_NEED_RESET) 1474 return result; 1475 1476 cxl_context_detach_all(afu); 1477 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); 1478 pci_deconfigure_afu(afu); 1479 } 1480 cxl_deconfigure_adapter(adapter); 1481 1482 return result; 1483 } 1484 1485 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev) 1486 { 1487 struct cxl *adapter = pci_get_drvdata(pdev); 1488 struct cxl_afu *afu; 1489 struct cxl_context *ctx; 1490 struct pci_dev *afu_dev; 1491 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED; 1492 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1493 int i; 1494 1495 if (cxl_configure_adapter(adapter, pdev)) 1496 goto err; 1497 1498 for (i = 0; i < adapter->slices; i++) { 1499 afu = adapter->afu[i]; 1500 1501 if (pci_configure_afu(afu, adapter, pdev)) 1502 goto err; 1503 1504 if (cxl_afu_select_best_mode(afu)) 1505 goto err; 1506 1507 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1508 /* Reset the device context. 1509 * TODO: make this less disruptive 1510 */ 1511 ctx = cxl_get_context(afu_dev); 1512 1513 if (ctx && cxl_release_context(ctx)) 1514 goto err; 1515 1516 ctx = cxl_dev_context_init(afu_dev); 1517 if (!ctx) 1518 goto err; 1519 1520 afu_dev->dev.archdata.cxl_ctx = ctx; 1521 1522 if (cxl_ops->afu_check_and_enable(afu)) 1523 goto err; 1524 1525 afu_dev->error_state = pci_channel_io_normal; 1526 1527 /* If there's a driver attached, allow it to 1528 * chime in on recovery. Drivers should check 1529 * if everything has come back OK, but 1530 * shouldn't start new work until we call 1531 * their resume function. 1532 */ 1533 if (!afu_dev->driver) 1534 continue; 1535 1536 if (afu_dev->driver->err_handler && 1537 afu_dev->driver->err_handler->slot_reset) 1538 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev); 1539 1540 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 1541 result = PCI_ERS_RESULT_DISCONNECT; 1542 } 1543 } 1544 return result; 1545 1546 err: 1547 /* All the bits that happen in both error_detected and cxl_remove 1548 * should be idempotent, so we don't need to worry about leaving a mix 1549 * of unconfigured and reconfigured resources. 1550 */ 1551 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); 1552 return PCI_ERS_RESULT_DISCONNECT; 1553 } 1554 1555 static void cxl_pci_resume(struct pci_dev *pdev) 1556 { 1557 struct cxl *adapter = pci_get_drvdata(pdev); 1558 struct cxl_afu *afu; 1559 struct pci_dev *afu_dev; 1560 int i; 1561 1562 /* Everything is back now. Drivers should restart work now. 1563 * This is not the place to be checking if everything came back up 1564 * properly, because there's no return value: do that in slot_reset. 1565 */ 1566 for (i = 0; i < adapter->slices; i++) { 1567 afu = adapter->afu[i]; 1568 1569 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1570 if (afu_dev->driver && afu_dev->driver->err_handler && 1571 afu_dev->driver->err_handler->resume) 1572 afu_dev->driver->err_handler->resume(afu_dev); 1573 } 1574 } 1575 } 1576 1577 static const struct pci_error_handlers cxl_err_handler = { 1578 .error_detected = cxl_pci_error_detected, 1579 .slot_reset = cxl_pci_slot_reset, 1580 .resume = cxl_pci_resume, 1581 }; 1582 1583 struct pci_driver cxl_pci_driver = { 1584 .name = "cxl-pci", 1585 .id_table = cxl_pci_tbl, 1586 .probe = cxl_probe, 1587 .remove = cxl_remove, 1588 .shutdown = cxl_remove, 1589 .err_handler = &cxl_err_handler, 1590 }; 1591