1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/pci_regs.h> 11 #include <linux/pci_ids.h> 12 #include <linux/device.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/sort.h> 17 #include <linux/pci.h> 18 #include <linux/of.h> 19 #include <linux/delay.h> 20 #include <asm/opal.h> 21 #include <asm/msi_bitmap.h> 22 #include <asm/pci-bridge.h> /* for struct pci_controller */ 23 #include <asm/pnv-pci.h> 24 #include <asm/io.h> 25 26 #include "cxl.h" 27 #include <misc/cxl.h> 28 29 30 #define CXL_PCI_VSEC_ID 0x1280 31 #define CXL_VSEC_MIN_SIZE 0x80 32 33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ 34 { \ 35 pci_read_config_word(dev, vsec + 0x6, dest); \ 36 *dest >>= 4; \ 37 } 38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ 39 pci_read_config_byte(dev, vsec + 0x8, dest) 40 41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ 42 pci_read_config_byte(dev, vsec + 0x9, dest) 43 #define CXL_STATUS_SECOND_PORT 0x80 44 #define CXL_STATUS_MSI_X_FULL 0x40 45 #define CXL_STATUS_MSI_X_SINGLE 0x20 46 #define CXL_STATUS_FLASH_RW 0x08 47 #define CXL_STATUS_FLASH_RO 0x04 48 #define CXL_STATUS_LOADABLE_AFU 0x02 49 #define CXL_STATUS_LOADABLE_PSL 0x01 50 /* If we see these features we won't try to use the card */ 51 #define CXL_UNSUPPORTED_FEATURES \ 52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) 53 54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ 55 pci_read_config_byte(dev, vsec + 0xa, dest) 56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ 57 pci_write_config_byte(dev, vsec + 0xa, val) 58 #define CXL_VSEC_PROTOCOL_MASK 0xe0 59 #define CXL_VSEC_PROTOCOL_1024TB 0x80 60 #define CXL_VSEC_PROTOCOL_512TB 0x40 61 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */ 62 #define CXL_VSEC_PROTOCOL_ENABLE 0x01 63 64 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ 65 pci_read_config_word(dev, vsec + 0xc, dest) 66 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ 67 pci_read_config_byte(dev, vsec + 0xe, dest) 68 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ 69 pci_read_config_byte(dev, vsec + 0xf, dest) 70 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ 71 pci_read_config_word(dev, vsec + 0x10, dest) 72 73 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ 74 pci_read_config_byte(dev, vsec + 0x13, dest) 75 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ 76 pci_write_config_byte(dev, vsec + 0x13, val) 77 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ 78 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ 79 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ 80 81 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ 82 pci_read_config_dword(dev, vsec + 0x20, dest) 83 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ 84 pci_read_config_dword(dev, vsec + 0x24, dest) 85 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ 86 pci_read_config_dword(dev, vsec + 0x28, dest) 87 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ 88 pci_read_config_dword(dev, vsec + 0x2c, dest) 89 90 91 /* This works a little different than the p1/p2 register accesses to make it 92 * easier to pull out individual fields */ 93 #define AFUD_READ(afu, off) in_be64(afu->afu_desc_mmio + off) 94 #define AFUD_READ_LE(afu, off) in_le64(afu->afu_desc_mmio + off) 95 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) 96 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) 97 98 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) 99 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) 100 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) 101 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) 102 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) 103 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) 104 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) 105 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) 106 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) 107 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) 108 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 109 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) 110 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) 111 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) 112 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) 113 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 114 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) 115 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) 116 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 117 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) 118 119 u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off) 120 { 121 u64 aligned_off = off & ~0x3L; 122 u32 val; 123 124 val = cxl_afu_cr_read32(afu, cr, aligned_off); 125 return (val >> ((off & 0x2) * 8)) & 0xffff; 126 } 127 128 u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off) 129 { 130 u64 aligned_off = off & ~0x3L; 131 u32 val; 132 133 val = cxl_afu_cr_read32(afu, cr, aligned_off); 134 return (val >> ((off & 0x3) * 8)) & 0xff; 135 } 136 137 static const struct pci_device_id cxl_pci_tbl[] = { 138 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, 139 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, 140 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, 141 { PCI_DEVICE_CLASS(0x120000, ~0), }, 142 143 { } 144 }; 145 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); 146 147 148 /* 149 * Mostly using these wrappers to avoid confusion: 150 * priv 1 is BAR2, while priv 2 is BAR0 151 */ 152 static inline resource_size_t p1_base(struct pci_dev *dev) 153 { 154 return pci_resource_start(dev, 2); 155 } 156 157 static inline resource_size_t p1_size(struct pci_dev *dev) 158 { 159 return pci_resource_len(dev, 2); 160 } 161 162 static inline resource_size_t p2_base(struct pci_dev *dev) 163 { 164 return pci_resource_start(dev, 0); 165 } 166 167 static inline resource_size_t p2_size(struct pci_dev *dev) 168 { 169 return pci_resource_len(dev, 0); 170 } 171 172 static int find_cxl_vsec(struct pci_dev *dev) 173 { 174 int vsec = 0; 175 u16 val; 176 177 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { 178 pci_read_config_word(dev, vsec + 0x4, &val); 179 if (val == CXL_PCI_VSEC_ID) 180 return vsec; 181 } 182 return 0; 183 184 } 185 186 static void dump_cxl_config_space(struct pci_dev *dev) 187 { 188 int vsec; 189 u32 val; 190 191 dev_info(&dev->dev, "dump_cxl_config_space\n"); 192 193 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); 194 dev_info(&dev->dev, "BAR0: %#.8x\n", val); 195 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); 196 dev_info(&dev->dev, "BAR1: %#.8x\n", val); 197 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); 198 dev_info(&dev->dev, "BAR2: %#.8x\n", val); 199 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); 200 dev_info(&dev->dev, "BAR3: %#.8x\n", val); 201 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); 202 dev_info(&dev->dev, "BAR4: %#.8x\n", val); 203 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); 204 dev_info(&dev->dev, "BAR5: %#.8x\n", val); 205 206 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", 207 p1_base(dev), p1_size(dev)); 208 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", 209 p2_base(dev), p2_size(dev)); 210 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", 211 pci_resource_start(dev, 4), pci_resource_len(dev, 4)); 212 213 if (!(vsec = find_cxl_vsec(dev))) 214 return; 215 216 #define show_reg(name, what) \ 217 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) 218 219 pci_read_config_dword(dev, vsec + 0x0, &val); 220 show_reg("Cap ID", (val >> 0) & 0xffff); 221 show_reg("Cap Ver", (val >> 16) & 0xf); 222 show_reg("Next Cap Ptr", (val >> 20) & 0xfff); 223 pci_read_config_dword(dev, vsec + 0x4, &val); 224 show_reg("VSEC ID", (val >> 0) & 0xffff); 225 show_reg("VSEC Rev", (val >> 16) & 0xf); 226 show_reg("VSEC Length", (val >> 20) & 0xfff); 227 pci_read_config_dword(dev, vsec + 0x8, &val); 228 show_reg("Num AFUs", (val >> 0) & 0xff); 229 show_reg("Status", (val >> 8) & 0xff); 230 show_reg("Mode Control", (val >> 16) & 0xff); 231 show_reg("Reserved", (val >> 24) & 0xff); 232 pci_read_config_dword(dev, vsec + 0xc, &val); 233 show_reg("PSL Rev", (val >> 0) & 0xffff); 234 show_reg("CAIA Ver", (val >> 16) & 0xffff); 235 pci_read_config_dword(dev, vsec + 0x10, &val); 236 show_reg("Base Image Rev", (val >> 0) & 0xffff); 237 show_reg("Reserved", (val >> 16) & 0x0fff); 238 show_reg("Image Control", (val >> 28) & 0x3); 239 show_reg("Reserved", (val >> 30) & 0x1); 240 show_reg("Image Loaded", (val >> 31) & 0x1); 241 242 pci_read_config_dword(dev, vsec + 0x14, &val); 243 show_reg("Reserved", val); 244 pci_read_config_dword(dev, vsec + 0x18, &val); 245 show_reg("Reserved", val); 246 pci_read_config_dword(dev, vsec + 0x1c, &val); 247 show_reg("Reserved", val); 248 249 pci_read_config_dword(dev, vsec + 0x20, &val); 250 show_reg("AFU Descriptor Offset", val); 251 pci_read_config_dword(dev, vsec + 0x24, &val); 252 show_reg("AFU Descriptor Size", val); 253 pci_read_config_dword(dev, vsec + 0x28, &val); 254 show_reg("Problem State Offset", val); 255 pci_read_config_dword(dev, vsec + 0x2c, &val); 256 show_reg("Problem State Size", val); 257 258 pci_read_config_dword(dev, vsec + 0x30, &val); 259 show_reg("Reserved", val); 260 pci_read_config_dword(dev, vsec + 0x34, &val); 261 show_reg("Reserved", val); 262 pci_read_config_dword(dev, vsec + 0x38, &val); 263 show_reg("Reserved", val); 264 pci_read_config_dword(dev, vsec + 0x3c, &val); 265 show_reg("Reserved", val); 266 267 pci_read_config_dword(dev, vsec + 0x40, &val); 268 show_reg("PSL Programming Port", val); 269 pci_read_config_dword(dev, vsec + 0x44, &val); 270 show_reg("PSL Programming Control", val); 271 272 pci_read_config_dword(dev, vsec + 0x48, &val); 273 show_reg("Reserved", val); 274 pci_read_config_dword(dev, vsec + 0x4c, &val); 275 show_reg("Reserved", val); 276 277 pci_read_config_dword(dev, vsec + 0x50, &val); 278 show_reg("Flash Address Register", val); 279 pci_read_config_dword(dev, vsec + 0x54, &val); 280 show_reg("Flash Size Register", val); 281 pci_read_config_dword(dev, vsec + 0x58, &val); 282 show_reg("Flash Status/Control Register", val); 283 pci_read_config_dword(dev, vsec + 0x58, &val); 284 show_reg("Flash Data Port", val); 285 286 #undef show_reg 287 } 288 289 static void dump_afu_descriptor(struct cxl_afu *afu) 290 { 291 u64 val, afu_cr_num, afu_cr_off, afu_cr_len; 292 int i; 293 294 #define show_reg(name, what) \ 295 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) 296 297 val = AFUD_READ_INFO(afu); 298 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); 299 show_reg("num_of_processes", AFUD_NUM_PROCS(val)); 300 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); 301 show_reg("req_prog_mode", val & 0xffffULL); 302 afu_cr_num = AFUD_NUM_CRS(val); 303 304 val = AFUD_READ(afu, 0x8); 305 show_reg("Reserved", val); 306 val = AFUD_READ(afu, 0x10); 307 show_reg("Reserved", val); 308 val = AFUD_READ(afu, 0x18); 309 show_reg("Reserved", val); 310 311 val = AFUD_READ_CR(afu); 312 show_reg("Reserved", (val >> (63-7)) & 0xff); 313 show_reg("AFU_CR_len", AFUD_CR_LEN(val)); 314 afu_cr_len = AFUD_CR_LEN(val) * 256; 315 316 val = AFUD_READ_CR_OFF(afu); 317 afu_cr_off = val; 318 show_reg("AFU_CR_offset", val); 319 320 val = AFUD_READ_PPPSA(afu); 321 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); 322 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); 323 324 val = AFUD_READ_PPPSA_OFF(afu); 325 show_reg("PerProcessPSA_offset", val); 326 327 val = AFUD_READ_EB(afu); 328 show_reg("Reserved", (val >> (63-7)) & 0xff); 329 show_reg("AFU_EB_len", AFUD_EB_LEN(val)); 330 331 val = AFUD_READ_EB_OFF(afu); 332 show_reg("AFU_EB_offset", val); 333 334 for (i = 0; i < afu_cr_num; i++) { 335 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len); 336 show_reg("CR Vendor", val & 0xffff); 337 show_reg("CR Device", (val >> 16) & 0xffff); 338 } 339 #undef show_reg 340 } 341 342 static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 343 { 344 struct device_node *np; 345 const __be32 *prop; 346 u64 psl_dsnctl; 347 u64 chipid; 348 349 if (!(np = pnv_pci_get_phb_node(dev))) 350 return -ENODEV; 351 352 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) 353 np = of_get_next_parent(np); 354 if (!np) 355 return -ENODEV; 356 chipid = be32_to_cpup(prop); 357 of_node_put(np); 358 359 /* Tell PSL where to route data to */ 360 psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5)); 361 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); 362 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); 363 /* snoop write mask */ 364 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); 365 /* set fir_accum */ 366 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL); 367 /* for debugging with trace arrays */ 368 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); 369 370 return 0; 371 } 372 373 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6)) 374 #define _2048_250MHZ_CYCLES 1 375 376 static int cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev) 377 { 378 u64 psl_tb; 379 int delta; 380 unsigned int retry = 0; 381 struct device_node *np; 382 383 if (!(np = pnv_pci_get_phb_node(dev))) 384 return -ENODEV; 385 386 /* Do not fail when CAPP timebase sync is not supported by OPAL */ 387 of_node_get(np); 388 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) { 389 of_node_put(np); 390 pr_err("PSL: Timebase sync: OPAL support missing\n"); 391 return 0; 392 } 393 of_node_put(np); 394 395 /* 396 * Setup PSL Timebase Control and Status register 397 * with the recommended Timebase Sync Count value 398 */ 399 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT, 400 TBSYNC_CNT(2 * _2048_250MHZ_CYCLES)); 401 402 /* Enable PSL Timebase */ 403 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000); 404 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb); 405 406 /* Wait until CORE TB and PSL TB difference <= 16usecs */ 407 do { 408 msleep(1); 409 if (retry++ > 5) { 410 pr_err("PSL: Timebase sync: giving up!\n"); 411 return -EIO; 412 } 413 psl_tb = cxl_p1_read(adapter, CXL_PSL_Timebase); 414 delta = mftb() - psl_tb; 415 if (delta < 0) 416 delta = -delta; 417 } while (cputime_to_usecs(delta) > 16); 418 419 return 0; 420 } 421 422 static int init_implementation_afu_regs(struct cxl_afu *afu) 423 { 424 /* read/write masks for this slice */ 425 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); 426 /* APC read/write masks for this slice */ 427 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); 428 /* for debugging with trace arrays */ 429 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); 430 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S); 431 432 return 0; 433 } 434 435 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, 436 unsigned int virq) 437 { 438 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 439 440 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); 441 } 442 443 int cxl_update_image_control(struct cxl *adapter) 444 { 445 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 446 int rc; 447 int vsec; 448 u8 image_state; 449 450 if (!(vsec = find_cxl_vsec(dev))) { 451 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 452 return -ENODEV; 453 } 454 455 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { 456 dev_err(&dev->dev, "failed to read image state: %i\n", rc); 457 return rc; 458 } 459 460 if (adapter->perst_loads_image) 461 image_state |= CXL_VSEC_PERST_LOADS_IMAGE; 462 else 463 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE; 464 465 if (adapter->perst_select_user) 466 image_state |= CXL_VSEC_PERST_SELECT_USER; 467 else 468 image_state &= ~CXL_VSEC_PERST_SELECT_USER; 469 470 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { 471 dev_err(&dev->dev, "failed to update image control: %i\n", rc); 472 return rc; 473 } 474 475 return 0; 476 } 477 478 int cxl_alloc_one_irq(struct cxl *adapter) 479 { 480 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 481 482 return pnv_cxl_alloc_hwirqs(dev, 1); 483 } 484 485 void cxl_release_one_irq(struct cxl *adapter, int hwirq) 486 { 487 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 488 489 return pnv_cxl_release_hwirqs(dev, hwirq, 1); 490 } 491 492 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num) 493 { 494 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 495 496 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); 497 } 498 499 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter) 500 { 501 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 502 503 pnv_cxl_release_hwirq_ranges(irqs, dev); 504 } 505 506 static int setup_cxl_bars(struct pci_dev *dev) 507 { 508 /* Safety check in case we get backported to < 3.17 without M64 */ 509 if ((p1_base(dev) < 0x100000000ULL) || 510 (p2_base(dev) < 0x100000000ULL)) { 511 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); 512 return -ENODEV; 513 } 514 515 /* 516 * BAR 4/5 has a special meaning for CXL and must be programmed with a 517 * special value corresponding to the CXL protocol address range. 518 * For POWER 8 that means bits 48:49 must be set to 10 519 */ 520 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); 521 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); 522 523 return 0; 524 } 525 526 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */ 527 static int switch_card_to_cxl(struct pci_dev *dev) 528 { 529 int vsec; 530 u8 val; 531 int rc; 532 533 dev_info(&dev->dev, "switch card to CXL\n"); 534 535 if (!(vsec = find_cxl_vsec(dev))) { 536 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 537 return -ENODEV; 538 } 539 540 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { 541 dev_err(&dev->dev, "failed to read current mode control: %i", rc); 542 return rc; 543 } 544 val &= ~CXL_VSEC_PROTOCOL_MASK; 545 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; 546 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { 547 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc); 548 return rc; 549 } 550 /* 551 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states 552 * we must wait 100ms after this mode switch before touching 553 * PCIe config space. 554 */ 555 msleep(100); 556 557 return 0; 558 } 559 560 static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 561 { 562 u64 p1n_base, p2n_base, afu_desc; 563 const u64 p1n_size = 0x100; 564 const u64 p2n_size = 0x1000; 565 566 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); 567 p2n_base = p2_base(dev) + (afu->slice * p2n_size); 568 afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size)); 569 afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size); 570 571 if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size))) 572 goto err; 573 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) 574 goto err1; 575 if (afu_desc) { 576 if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size))) 577 goto err2; 578 } 579 580 return 0; 581 err2: 582 iounmap(afu->p2n_mmio); 583 err1: 584 iounmap(afu->p1n_mmio); 585 err: 586 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); 587 return -ENOMEM; 588 } 589 590 static void cxl_unmap_slice_regs(struct cxl_afu *afu) 591 { 592 if (afu->p2n_mmio) { 593 iounmap(afu->p2n_mmio); 594 afu->p2n_mmio = NULL; 595 } 596 if (afu->p1n_mmio) { 597 iounmap(afu->p1n_mmio); 598 afu->p1n_mmio = NULL; 599 } 600 if (afu->afu_desc_mmio) { 601 iounmap(afu->afu_desc_mmio); 602 afu->afu_desc_mmio = NULL; 603 } 604 } 605 606 static void cxl_release_afu(struct device *dev) 607 { 608 struct cxl_afu *afu = to_cxl_afu(dev); 609 610 pr_devel("cxl_release_afu\n"); 611 612 idr_destroy(&afu->contexts_idr); 613 cxl_release_spa(afu); 614 615 kfree(afu); 616 } 617 618 static struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice) 619 { 620 struct cxl_afu *afu; 621 622 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL))) 623 return NULL; 624 625 afu->adapter = adapter; 626 afu->dev.parent = &adapter->dev; 627 afu->dev.release = cxl_release_afu; 628 afu->slice = slice; 629 idr_init(&afu->contexts_idr); 630 mutex_init(&afu->contexts_lock); 631 spin_lock_init(&afu->afu_cntl_lock); 632 mutex_init(&afu->spa_mutex); 633 634 afu->prefault_mode = CXL_PREFAULT_NONE; 635 afu->irqs_max = afu->adapter->user_irqs; 636 637 return afu; 638 } 639 640 /* Expects AFU struct to have recently been zeroed out */ 641 static int cxl_read_afu_descriptor(struct cxl_afu *afu) 642 { 643 u64 val; 644 645 val = AFUD_READ_INFO(afu); 646 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); 647 afu->max_procs_virtualised = AFUD_NUM_PROCS(val); 648 afu->crs_num = AFUD_NUM_CRS(val); 649 650 if (AFUD_AFU_DIRECTED(val)) 651 afu->modes_supported |= CXL_MODE_DIRECTED; 652 if (AFUD_DEDICATED_PROCESS(val)) 653 afu->modes_supported |= CXL_MODE_DEDICATED; 654 if (AFUD_TIME_SLICED(val)) 655 afu->modes_supported |= CXL_MODE_TIME_SLICED; 656 657 val = AFUD_READ_PPPSA(afu); 658 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; 659 afu->psa = AFUD_PPPSA_PSA(val); 660 if ((afu->pp_psa = AFUD_PPPSA_PP(val))) 661 afu->pp_offset = AFUD_READ_PPPSA_OFF(afu); 662 663 val = AFUD_READ_CR(afu); 664 afu->crs_len = AFUD_CR_LEN(val) * 256; 665 afu->crs_offset = AFUD_READ_CR_OFF(afu); 666 667 668 /* eb_len is in multiple of 4K */ 669 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; 670 afu->eb_offset = AFUD_READ_EB_OFF(afu); 671 672 /* eb_off is 4K aligned so lower 12 bits are always zero */ 673 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { 674 dev_warn(&afu->dev, 675 "Invalid AFU error buffer offset %Lx\n", 676 afu->eb_offset); 677 dev_info(&afu->dev, 678 "Ignoring AFU error buffer in the descriptor\n"); 679 /* indicate that no afu buffer exists */ 680 afu->eb_len = 0; 681 } 682 683 return 0; 684 } 685 686 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) 687 { 688 int i; 689 690 if (afu->psa && afu->adapter->ps_size < 691 (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { 692 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); 693 return -ENODEV; 694 } 695 696 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) 697 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!"); 698 699 for (i = 0; i < afu->crs_num; i++) { 700 if ((cxl_afu_cr_read32(afu, i, 0) == 0)) { 701 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); 702 return -EINVAL; 703 } 704 } 705 706 return 0; 707 } 708 709 static int sanitise_afu_regs(struct cxl_afu *afu) 710 { 711 u64 reg; 712 713 /* 714 * Clear out any regs that contain either an IVTE or address or may be 715 * waiting on an acknowledgement to try to be a bit safer as we bring 716 * it online 717 */ 718 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 719 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 720 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); 721 if (__cxl_afu_reset(afu)) 722 return -EIO; 723 if (cxl_afu_disable(afu)) 724 return -EIO; 725 if (cxl_psl_purge(afu)) 726 return -EIO; 727 } 728 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); 729 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); 730 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); 731 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); 732 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); 733 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); 734 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); 735 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); 736 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); 737 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); 738 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); 739 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 740 if (reg) { 741 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); 742 if (reg & CXL_PSL_DSISR_TRANS) 743 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 744 else 745 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 746 } 747 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); 748 if (reg) { 749 if (reg & ~0xffff) 750 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); 751 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); 752 } 753 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 754 if (reg) { 755 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); 756 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); 757 } 758 759 return 0; 760 } 761 762 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE 763 /* 764 * afu_eb_read: 765 * Called from sysfs and reads the afu error info buffer. The h/w only supports 766 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte 767 * aligned the function uses a bounce buffer which can be max PAGE_SIZE. 768 */ 769 ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf, 770 loff_t off, size_t count) 771 { 772 loff_t aligned_start, aligned_end; 773 size_t aligned_length; 774 void *tbuf; 775 const void __iomem *ebuf = afu->afu_desc_mmio + afu->eb_offset; 776 777 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) 778 return 0; 779 780 /* calculate aligned read window */ 781 count = min((size_t)(afu->eb_len - off), count); 782 aligned_start = round_down(off, 8); 783 aligned_end = round_up(off + count, 8); 784 aligned_length = aligned_end - aligned_start; 785 786 /* max we can copy in one read is PAGE_SIZE */ 787 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) { 788 aligned_length = ERR_BUFF_MAX_COPY_SIZE; 789 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); 790 } 791 792 /* use bounce buffer for copy */ 793 tbuf = (void *)__get_free_page(GFP_TEMPORARY); 794 if (!tbuf) 795 return -ENOMEM; 796 797 /* perform aligned read from the mmio region */ 798 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length); 799 memcpy(buf, tbuf + (off & 0x7), count); 800 801 free_page((unsigned long)tbuf); 802 803 return count; 804 } 805 806 static int cxl_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 807 { 808 int rc; 809 810 if ((rc = cxl_map_slice_regs(afu, adapter, dev))) 811 return rc; 812 813 if ((rc = sanitise_afu_regs(afu))) 814 goto err1; 815 816 /* We need to reset the AFU before we can read the AFU descriptor */ 817 if ((rc = __cxl_afu_reset(afu))) 818 goto err1; 819 820 if (cxl_verbose) 821 dump_afu_descriptor(afu); 822 823 if ((rc = cxl_read_afu_descriptor(afu))) 824 goto err1; 825 826 if ((rc = cxl_afu_descriptor_looks_ok(afu))) 827 goto err1; 828 829 if ((rc = init_implementation_afu_regs(afu))) 830 goto err1; 831 832 if ((rc = cxl_register_serr_irq(afu))) 833 goto err1; 834 835 if ((rc = cxl_register_psl_irq(afu))) 836 goto err2; 837 838 return 0; 839 840 err2: 841 cxl_release_serr_irq(afu); 842 err1: 843 cxl_unmap_slice_regs(afu); 844 return rc; 845 } 846 847 static void cxl_deconfigure_afu(struct cxl_afu *afu) 848 { 849 cxl_release_psl_irq(afu); 850 cxl_release_serr_irq(afu); 851 cxl_unmap_slice_regs(afu); 852 } 853 854 static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) 855 { 856 struct cxl_afu *afu; 857 int rc; 858 859 afu = cxl_alloc_afu(adapter, slice); 860 if (!afu) 861 return -ENOMEM; 862 863 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); 864 if (rc) 865 goto err_free; 866 867 rc = cxl_configure_afu(afu, adapter, dev); 868 if (rc) 869 goto err_free; 870 871 /* Don't care if this fails */ 872 cxl_debugfs_afu_add(afu); 873 874 /* 875 * After we call this function we must not free the afu directly, even 876 * if it returns an error! 877 */ 878 if ((rc = cxl_register_afu(afu))) 879 goto err_put1; 880 881 if ((rc = cxl_sysfs_afu_add(afu))) 882 goto err_put1; 883 884 adapter->afu[afu->slice] = afu; 885 886 if ((rc = cxl_pci_vphb_add(afu))) 887 dev_info(&afu->dev, "Can't register vPHB\n"); 888 889 return 0; 890 891 err_put1: 892 cxl_deconfigure_afu(afu); 893 cxl_debugfs_afu_remove(afu); 894 device_unregister(&afu->dev); 895 return rc; 896 897 err_free: 898 kfree(afu); 899 return rc; 900 901 } 902 903 static void cxl_remove_afu(struct cxl_afu *afu) 904 { 905 pr_devel("cxl_remove_afu\n"); 906 907 if (!afu) 908 return; 909 910 cxl_sysfs_afu_remove(afu); 911 cxl_debugfs_afu_remove(afu); 912 913 spin_lock(&afu->adapter->afu_list_lock); 914 afu->adapter->afu[afu->slice] = NULL; 915 spin_unlock(&afu->adapter->afu_list_lock); 916 917 cxl_context_detach_all(afu); 918 cxl_afu_deactivate_mode(afu); 919 920 cxl_deconfigure_afu(afu); 921 device_unregister(&afu->dev); 922 } 923 924 int cxl_reset(struct cxl *adapter) 925 { 926 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 927 int rc; 928 929 if (adapter->perst_same_image) { 930 dev_warn(&dev->dev, 931 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n"); 932 return -EINVAL; 933 } 934 935 dev_info(&dev->dev, "CXL reset\n"); 936 937 /* pcie_warm_reset requests a fundamental pci reset which includes a 938 * PERST assert/deassert. PERST triggers a loading of the image 939 * if "user" or "factory" is selected in sysfs */ 940 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { 941 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); 942 return rc; 943 } 944 945 return rc; 946 } 947 948 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 949 { 950 if (pci_request_region(dev, 2, "priv 2 regs")) 951 goto err1; 952 if (pci_request_region(dev, 0, "priv 1 regs")) 953 goto err2; 954 955 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx", 956 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); 957 958 if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) 959 goto err3; 960 961 if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) 962 goto err4; 963 964 return 0; 965 966 err4: 967 iounmap(adapter->p1_mmio); 968 adapter->p1_mmio = NULL; 969 err3: 970 pci_release_region(dev, 0); 971 err2: 972 pci_release_region(dev, 2); 973 err1: 974 return -ENOMEM; 975 } 976 977 static void cxl_unmap_adapter_regs(struct cxl *adapter) 978 { 979 if (adapter->p1_mmio) { 980 iounmap(adapter->p1_mmio); 981 adapter->p1_mmio = NULL; 982 pci_release_region(to_pci_dev(adapter->dev.parent), 2); 983 } 984 if (adapter->p2_mmio) { 985 iounmap(adapter->p2_mmio); 986 adapter->p2_mmio = NULL; 987 pci_release_region(to_pci_dev(adapter->dev.parent), 0); 988 } 989 } 990 991 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) 992 { 993 int vsec; 994 u32 afu_desc_off, afu_desc_size; 995 u32 ps_off, ps_size; 996 u16 vseclen; 997 u8 image_state; 998 999 if (!(vsec = find_cxl_vsec(dev))) { 1000 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 1001 return -ENODEV; 1002 } 1003 1004 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); 1005 if (vseclen < CXL_VSEC_MIN_SIZE) { 1006 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); 1007 return -EINVAL; 1008 } 1009 1010 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); 1011 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); 1012 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); 1013 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); 1014 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); 1015 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); 1016 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1017 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1018 1019 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); 1020 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); 1021 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); 1022 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); 1023 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); 1024 1025 /* Convert everything to bytes, because there is NO WAY I'd look at the 1026 * code a month later and forget what units these are in ;-) */ 1027 adapter->ps_off = ps_off * 64 * 1024; 1028 adapter->ps_size = ps_size * 64 * 1024; 1029 adapter->afu_desc_off = afu_desc_off * 64 * 1024; 1030 adapter->afu_desc_size = afu_desc_size *64 * 1024; 1031 1032 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ 1033 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; 1034 1035 return 0; 1036 } 1037 1038 /* 1039 * Workaround a PCIe Host Bridge defect on some cards, that can cause 1040 * malformed Transaction Layer Packet (TLP) errors to be erroneously 1041 * reported. Mask this error in the Uncorrectable Error Mask Register. 1042 * 1043 * The upper nibble of the PSL revision is used to distinguish between 1044 * different cards. The affected ones have it set to 0. 1045 */ 1046 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev) 1047 { 1048 int aer; 1049 u32 data; 1050 1051 if (adapter->psl_rev & 0xf000) 1052 return; 1053 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))) 1054 return; 1055 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data); 1056 if (data & PCI_ERR_UNC_MALF_TLP) 1057 if (data & PCI_ERR_UNC_INTN) 1058 return; 1059 data |= PCI_ERR_UNC_MALF_TLP; 1060 data |= PCI_ERR_UNC_INTN; 1061 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data); 1062 } 1063 1064 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) 1065 { 1066 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) 1067 return -EBUSY; 1068 1069 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { 1070 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); 1071 return -EINVAL; 1072 } 1073 1074 if (!adapter->slices) { 1075 /* Once we support dynamic reprogramming we can use the card if 1076 * it supports loadable AFUs */ 1077 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); 1078 return -EINVAL; 1079 } 1080 1081 if (!adapter->afu_desc_off || !adapter->afu_desc_size) { 1082 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); 1083 return -EINVAL; 1084 } 1085 1086 if (adapter->ps_size > p2_size(dev) - adapter->ps_off) { 1087 dev_err(&dev->dev, "ABORTING: Problem state size larger than " 1088 "available in BAR2: 0x%llx > 0x%llx\n", 1089 adapter->ps_size, p2_size(dev) - adapter->ps_off); 1090 return -EINVAL; 1091 } 1092 1093 return 0; 1094 } 1095 1096 static void cxl_release_adapter(struct device *dev) 1097 { 1098 struct cxl *adapter = to_cxl_adapter(dev); 1099 1100 pr_devel("cxl_release_adapter\n"); 1101 1102 cxl_remove_adapter_nr(adapter); 1103 1104 kfree(adapter); 1105 } 1106 1107 static struct cxl *cxl_alloc_adapter(void) 1108 { 1109 struct cxl *adapter; 1110 1111 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL))) 1112 return NULL; 1113 1114 spin_lock_init(&adapter->afu_list_lock); 1115 1116 if (cxl_alloc_adapter_nr(adapter)) 1117 goto err1; 1118 1119 if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num)) 1120 goto err2; 1121 1122 return adapter; 1123 1124 err2: 1125 cxl_remove_adapter_nr(adapter); 1126 err1: 1127 kfree(adapter); 1128 return NULL; 1129 } 1130 1131 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31)) 1132 1133 static int sanitise_adapter_regs(struct cxl *adapter) 1134 { 1135 /* Clear PSL tberror bit by writing 1 to it */ 1136 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror); 1137 return cxl_tlb_slb_invalidate(adapter); 1138 } 1139 1140 /* This should contain *only* operations that can safely be done in 1141 * both creation and recovery. 1142 */ 1143 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev) 1144 { 1145 int rc; 1146 1147 adapter->dev.parent = &dev->dev; 1148 adapter->dev.release = cxl_release_adapter; 1149 pci_set_drvdata(dev, adapter); 1150 1151 rc = pci_enable_device(dev); 1152 if (rc) { 1153 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); 1154 return rc; 1155 } 1156 1157 if ((rc = cxl_read_vsec(adapter, dev))) 1158 return rc; 1159 1160 if ((rc = cxl_vsec_looks_ok(adapter, dev))) 1161 return rc; 1162 1163 cxl_fixup_malformed_tlp(adapter, dev); 1164 1165 if ((rc = setup_cxl_bars(dev))) 1166 return rc; 1167 1168 if ((rc = switch_card_to_cxl(dev))) 1169 return rc; 1170 1171 if ((rc = cxl_update_image_control(adapter))) 1172 return rc; 1173 1174 if ((rc = cxl_map_adapter_regs(adapter, dev))) 1175 return rc; 1176 1177 if ((rc = sanitise_adapter_regs(adapter))) 1178 goto err; 1179 1180 if ((rc = init_implementation_adapter_regs(adapter, dev))) 1181 goto err; 1182 1183 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI))) 1184 goto err; 1185 1186 /* If recovery happened, the last step is to turn on snooping. 1187 * In the non-recovery case this has no effect */ 1188 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) 1189 goto err; 1190 1191 if ((rc = cxl_setup_psl_timebase(adapter, dev))) 1192 goto err; 1193 1194 if ((rc = cxl_register_psl_err_irq(adapter))) 1195 goto err; 1196 1197 return 0; 1198 1199 err: 1200 cxl_unmap_adapter_regs(adapter); 1201 return rc; 1202 1203 } 1204 1205 static void cxl_deconfigure_adapter(struct cxl *adapter) 1206 { 1207 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); 1208 1209 cxl_release_psl_err_irq(adapter); 1210 cxl_unmap_adapter_regs(adapter); 1211 1212 pci_disable_device(pdev); 1213 } 1214 1215 static struct cxl *cxl_init_adapter(struct pci_dev *dev) 1216 { 1217 struct cxl *adapter; 1218 int rc; 1219 1220 adapter = cxl_alloc_adapter(); 1221 if (!adapter) 1222 return ERR_PTR(-ENOMEM); 1223 1224 /* Set defaults for parameters which need to persist over 1225 * configure/reconfigure 1226 */ 1227 adapter->perst_loads_image = true; 1228 adapter->perst_same_image = false; 1229 1230 rc = cxl_configure_adapter(adapter, dev); 1231 if (rc) { 1232 pci_disable_device(dev); 1233 cxl_release_adapter(&adapter->dev); 1234 return ERR_PTR(rc); 1235 } 1236 1237 /* Don't care if this one fails: */ 1238 cxl_debugfs_adapter_add(adapter); 1239 1240 /* 1241 * After we call this function we must not free the adapter directly, 1242 * even if it returns an error! 1243 */ 1244 if ((rc = cxl_register_adapter(adapter))) 1245 goto err_put1; 1246 1247 if ((rc = cxl_sysfs_adapter_add(adapter))) 1248 goto err_put1; 1249 1250 return adapter; 1251 1252 err_put1: 1253 /* This should mirror cxl_remove_adapter, except without the 1254 * sysfs parts 1255 */ 1256 cxl_debugfs_adapter_remove(adapter); 1257 cxl_deconfigure_adapter(adapter); 1258 device_unregister(&adapter->dev); 1259 return ERR_PTR(rc); 1260 } 1261 1262 static void cxl_remove_adapter(struct cxl *adapter) 1263 { 1264 pr_devel("cxl_remove_adapter\n"); 1265 1266 cxl_sysfs_adapter_remove(adapter); 1267 cxl_debugfs_adapter_remove(adapter); 1268 1269 cxl_deconfigure_adapter(adapter); 1270 1271 device_unregister(&adapter->dev); 1272 } 1273 1274 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) 1275 { 1276 struct cxl *adapter; 1277 int slice; 1278 int rc; 1279 1280 if (cxl_verbose) 1281 dump_cxl_config_space(dev); 1282 1283 adapter = cxl_init_adapter(dev); 1284 if (IS_ERR(adapter)) { 1285 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); 1286 return PTR_ERR(adapter); 1287 } 1288 1289 for (slice = 0; slice < adapter->slices; slice++) { 1290 if ((rc = cxl_init_afu(adapter, slice, dev))) { 1291 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); 1292 continue; 1293 } 1294 1295 rc = cxl_afu_select_best_mode(adapter->afu[slice]); 1296 if (rc) 1297 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); 1298 } 1299 1300 return 0; 1301 } 1302 1303 static void cxl_remove(struct pci_dev *dev) 1304 { 1305 struct cxl *adapter = pci_get_drvdata(dev); 1306 struct cxl_afu *afu; 1307 int i; 1308 1309 /* 1310 * Lock to prevent someone grabbing a ref through the adapter list as 1311 * we are removing it 1312 */ 1313 for (i = 0; i < adapter->slices; i++) { 1314 afu = adapter->afu[i]; 1315 cxl_pci_vphb_remove(afu); 1316 cxl_remove_afu(afu); 1317 } 1318 cxl_remove_adapter(adapter); 1319 } 1320 1321 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu, 1322 pci_channel_state_t state) 1323 { 1324 struct pci_dev *afu_dev; 1325 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; 1326 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET; 1327 1328 /* There should only be one entry, but go through the list 1329 * anyway 1330 */ 1331 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1332 if (!afu_dev->driver) 1333 continue; 1334 1335 afu_dev->error_state = state; 1336 1337 if (afu_dev->driver->err_handler) 1338 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev, 1339 state); 1340 /* Disconnect trumps all, NONE trumps NEED_RESET */ 1341 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 1342 result = PCI_ERS_RESULT_DISCONNECT; 1343 else if ((afu_result == PCI_ERS_RESULT_NONE) && 1344 (result == PCI_ERS_RESULT_NEED_RESET)) 1345 result = PCI_ERS_RESULT_NONE; 1346 } 1347 return result; 1348 } 1349 1350 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, 1351 pci_channel_state_t state) 1352 { 1353 struct cxl *adapter = pci_get_drvdata(pdev); 1354 struct cxl_afu *afu; 1355 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; 1356 int i; 1357 1358 /* At this point, we could still have an interrupt pending. 1359 * Let's try to get them out of the way before they do 1360 * anything we don't like. 1361 */ 1362 schedule(); 1363 1364 /* If we're permanently dead, give up. */ 1365 if (state == pci_channel_io_perm_failure) { 1366 /* Tell the AFU drivers; but we don't care what they 1367 * say, we're going away. 1368 */ 1369 for (i = 0; i < adapter->slices; i++) { 1370 afu = adapter->afu[i]; 1371 cxl_vphb_error_detected(afu, state); 1372 } 1373 return PCI_ERS_RESULT_DISCONNECT; 1374 } 1375 1376 /* Are we reflashing? 1377 * 1378 * If we reflash, we could come back as something entirely 1379 * different, including a non-CAPI card. As such, by default 1380 * we don't participate in the process. We'll be unbound and 1381 * the slot re-probed. (TODO: check EEH doesn't blindly rebind 1382 * us!) 1383 * 1384 * However, this isn't the entire story: for reliablity 1385 * reasons, we usually want to reflash the FPGA on PERST in 1386 * order to get back to a more reliable known-good state. 1387 * 1388 * This causes us a bit of a problem: if we reflash we can't 1389 * trust that we'll come back the same - we could have a new 1390 * image and been PERSTed in order to load that 1391 * image. However, most of the time we actually *will* come 1392 * back the same - for example a regular EEH event. 1393 * 1394 * Therefore, we allow the user to assert that the image is 1395 * indeed the same and that we should continue on into EEH 1396 * anyway. 1397 */ 1398 if (adapter->perst_loads_image && !adapter->perst_same_image) { 1399 /* TODO take the PHB out of CXL mode */ 1400 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); 1401 return PCI_ERS_RESULT_NONE; 1402 } 1403 1404 /* 1405 * At this point, we want to try to recover. We'll always 1406 * need a complete slot reset: we don't trust any other reset. 1407 * 1408 * Now, we go through each AFU: 1409 * - We send the driver, if bound, an error_detected callback. 1410 * We expect it to clean up, but it can also tell us to give 1411 * up and permanently detach the card. To simplify things, if 1412 * any bound AFU driver doesn't support EEH, we give up on EEH. 1413 * 1414 * - We detach all contexts associated with the AFU. This 1415 * does not free them, but puts them into a CLOSED state 1416 * which causes any the associated files to return useful 1417 * errors to userland. It also unmaps, but does not free, 1418 * any IRQs. 1419 * 1420 * - We clean up our side: releasing and unmapping resources we hold 1421 * so we can wire them up again when the hardware comes back up. 1422 * 1423 * Driver authors should note: 1424 * 1425 * - Any contexts you create in your kernel driver (except 1426 * those associated with anonymous file descriptors) are 1427 * your responsibility to free and recreate. Likewise with 1428 * any attached resources. 1429 * 1430 * - We will take responsibility for re-initialising the 1431 * device context (the one set up for you in 1432 * cxl_pci_enable_device_hook and accessed through 1433 * cxl_get_context). If you've attached IRQs or other 1434 * resources to it, they remains yours to free. 1435 * 1436 * You can call the same functions to release resources as you 1437 * normally would: we make sure that these functions continue 1438 * to work when the hardware is down. 1439 * 1440 * Two examples: 1441 * 1442 * 1) If you normally free all your resources at the end of 1443 * each request, or if you use anonymous FDs, your 1444 * error_detected callback can simply set a flag to tell 1445 * your driver not to start any new calls. You can then 1446 * clear the flag in the resume callback. 1447 * 1448 * 2) If you normally allocate your resources on startup: 1449 * * Set a flag in error_detected as above. 1450 * * Let CXL detach your contexts. 1451 * * In slot_reset, free the old resources and allocate new ones. 1452 * * In resume, clear the flag to allow things to start. 1453 */ 1454 for (i = 0; i < adapter->slices; i++) { 1455 afu = adapter->afu[i]; 1456 1457 result = cxl_vphb_error_detected(afu, state); 1458 1459 /* Only continue if everyone agrees on NEED_RESET */ 1460 if (result != PCI_ERS_RESULT_NEED_RESET) 1461 return result; 1462 1463 cxl_context_detach_all(afu); 1464 cxl_afu_deactivate_mode(afu); 1465 cxl_deconfigure_afu(afu); 1466 } 1467 cxl_deconfigure_adapter(adapter); 1468 1469 return result; 1470 } 1471 1472 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev) 1473 { 1474 struct cxl *adapter = pci_get_drvdata(pdev); 1475 struct cxl_afu *afu; 1476 struct cxl_context *ctx; 1477 struct pci_dev *afu_dev; 1478 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED; 1479 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1480 int i; 1481 1482 if (cxl_configure_adapter(adapter, pdev)) 1483 goto err; 1484 1485 for (i = 0; i < adapter->slices; i++) { 1486 afu = adapter->afu[i]; 1487 1488 if (cxl_configure_afu(afu, adapter, pdev)) 1489 goto err; 1490 1491 if (cxl_afu_select_best_mode(afu)) 1492 goto err; 1493 1494 cxl_pci_vphb_reconfigure(afu); 1495 1496 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1497 /* Reset the device context. 1498 * TODO: make this less disruptive 1499 */ 1500 ctx = cxl_get_context(afu_dev); 1501 1502 if (ctx && cxl_release_context(ctx)) 1503 goto err; 1504 1505 ctx = cxl_dev_context_init(afu_dev); 1506 if (!ctx) 1507 goto err; 1508 1509 afu_dev->dev.archdata.cxl_ctx = ctx; 1510 1511 if (cxl_afu_check_and_enable(afu)) 1512 goto err; 1513 1514 afu_dev->error_state = pci_channel_io_normal; 1515 1516 /* If there's a driver attached, allow it to 1517 * chime in on recovery. Drivers should check 1518 * if everything has come back OK, but 1519 * shouldn't start new work until we call 1520 * their resume function. 1521 */ 1522 if (!afu_dev->driver) 1523 continue; 1524 1525 if (afu_dev->driver->err_handler && 1526 afu_dev->driver->err_handler->slot_reset) 1527 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev); 1528 1529 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 1530 result = PCI_ERS_RESULT_DISCONNECT; 1531 } 1532 } 1533 return result; 1534 1535 err: 1536 /* All the bits that happen in both error_detected and cxl_remove 1537 * should be idempotent, so we don't need to worry about leaving a mix 1538 * of unconfigured and reconfigured resources. 1539 */ 1540 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); 1541 return PCI_ERS_RESULT_DISCONNECT; 1542 } 1543 1544 static void cxl_pci_resume(struct pci_dev *pdev) 1545 { 1546 struct cxl *adapter = pci_get_drvdata(pdev); 1547 struct cxl_afu *afu; 1548 struct pci_dev *afu_dev; 1549 int i; 1550 1551 /* Everything is back now. Drivers should restart work now. 1552 * This is not the place to be checking if everything came back up 1553 * properly, because there's no return value: do that in slot_reset. 1554 */ 1555 for (i = 0; i < adapter->slices; i++) { 1556 afu = adapter->afu[i]; 1557 1558 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1559 if (afu_dev->driver && afu_dev->driver->err_handler && 1560 afu_dev->driver->err_handler->resume) 1561 afu_dev->driver->err_handler->resume(afu_dev); 1562 } 1563 } 1564 } 1565 1566 static const struct pci_error_handlers cxl_err_handler = { 1567 .error_detected = cxl_pci_error_detected, 1568 .slot_reset = cxl_pci_slot_reset, 1569 .resume = cxl_pci_resume, 1570 }; 1571 1572 struct pci_driver cxl_pci_driver = { 1573 .name = "cxl-pci", 1574 .id_table = cxl_pci_tbl, 1575 .probe = cxl_probe, 1576 .remove = cxl_remove, 1577 .shutdown = cxl_remove, 1578 .err_handler = &cxl_err_handler, 1579 }; 1580