1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #ifndef _CXL_H_ 11 #define _CXL_H_ 12 13 #include <linux/interrupt.h> 14 #include <linux/semaphore.h> 15 #include <linux/device.h> 16 #include <linux/types.h> 17 #include <linux/cdev.h> 18 #include <linux/pid.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <linux/fs.h> 22 #include <asm/cputable.h> 23 #include <asm/mmu.h> 24 #include <asm/reg.h> 25 #include <misc/cxl-base.h> 26 27 #include <misc/cxl.h> 28 #include <uapi/misc/cxl.h> 29 30 extern uint cxl_verbose; 31 32 #define CXL_TIMEOUT 5 33 34 /* 35 * Bump version each time a user API change is made, whether it is 36 * backwards compatible ot not. 37 */ 38 #define CXL_API_VERSION 3 39 #define CXL_API_VERSION_COMPATIBLE 1 40 41 /* 42 * Opaque types to avoid accidentally passing registers for the wrong MMIO 43 * 44 * At the end of the day, I'm not married to using typedef here, but it might 45 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and 46 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write. 47 * 48 * I'm quite happy if these are changed back to #defines before upstreaming, it 49 * should be little more than a regexp search+replace operation in this file. 50 */ 51 typedef struct { 52 const int x; 53 } cxl_p1_reg_t; 54 typedef struct { 55 const int x; 56 } cxl_p1n_reg_t; 57 typedef struct { 58 const int x; 59 } cxl_p2n_reg_t; 60 #define cxl_reg_off(reg) \ 61 (reg.x) 62 63 /* Memory maps. Ref CXL Appendix A */ 64 65 /* PSL Privilege 1 Memory Map */ 66 /* Configuration and Control area */ 67 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000}; 68 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008}; 69 static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010}; 70 static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018}; 71 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020}; 72 /* Downloading */ 73 static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060}; 74 static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068}; 75 76 /* PSL Lookaside Buffer Management Area */ 77 static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080}; 78 static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088}; 79 static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090}; 80 static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0}; 81 static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8}; 82 static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0}; 83 84 /* 0x00C0:7EFF Implementation dependent area */ 85 /* PSL registers */ 86 static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100}; 87 static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108}; 88 static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110}; 89 static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118}; 90 static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128}; 91 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140}; 92 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148}; 93 static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150}; 94 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158}; 95 static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170}; 96 /* XSL registers (Mellanox CX4) */ 97 static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100}; 98 static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108}; 99 static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158}; 100 static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168}; 101 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */ 102 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */ 103 104 /* PSL Slice Privilege 1 Memory Map */ 105 /* Configuration Area */ 106 static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00}; 107 static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08}; 108 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10}; 109 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18}; 110 static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20}; 111 static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28}; 112 /* Memory Management and Lookaside Buffer Management */ 113 static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30}; 114 static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38}; 115 /* Pointer Area */ 116 static const cxl_p1n_reg_t CXL_HAURP_An = {0x80}; 117 static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88}; 118 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90}; 119 /* Control Area */ 120 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0}; 121 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8}; 122 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0}; 123 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8}; 124 /* 0xC0:FF Implementation Dependent Area */ 125 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0}; 126 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8}; 127 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0}; 128 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8}; 129 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0}; 130 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8}; 131 132 /* PSL Slice Privilege 2 Memory Map */ 133 /* Configuration and Control Area */ 134 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000}; 135 static const cxl_p2n_reg_t CXL_CSRP_An = {0x008}; 136 static const cxl_p2n_reg_t CXL_AURP0_An = {0x010}; 137 static const cxl_p2n_reg_t CXL_AURP1_An = {0x018}; 138 static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020}; 139 static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028}; 140 static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030}; 141 /* Segment Lookaside Buffer Management */ 142 static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040}; 143 static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048}; 144 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050}; 145 /* Interrupt Registers */ 146 static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060}; 147 static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068}; 148 static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070}; 149 static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078}; 150 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080}; 151 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088}; 152 /* AFU Registers */ 153 static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090}; 154 static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098}; 155 /* Work Element Descriptor */ 156 static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0}; 157 /* 0x0C0:FFF Implementation Dependent Area */ 158 159 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL 160 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL 161 #define CXL_PSL_SPAP_Size_Shift 4 162 #define CXL_PSL_SPAP_V 0x0000000000000001ULL 163 164 /****** CXL_PSL_Control ****************************************************/ 165 #define CXL_PSL_Control_tb 0x0000000000000001ULL 166 167 /****** CXL_PSL_DLCNTL *****************************************************/ 168 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28)) 169 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29)) 170 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30)) 171 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31)) 172 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E) 173 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S) 174 175 /****** CXL_PSL_SR_An ******************************************************/ 176 #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */ 177 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */ 178 #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */ 179 #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */ 180 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */ 181 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */ 182 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */ 183 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */ 184 #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */ 185 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */ 186 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */ 187 188 /****** CXL_PSL_ID_An ****************************************************/ 189 #define CXL_PSL_ID_An_F (1ull << (63-31)) 190 #define CXL_PSL_ID_An_L (1ull << (63-30)) 191 192 /****** CXL_PSL_SERR_An ****************************************************/ 193 #define CXL_PSL_SERR_An_afuto (1ull << (63-0)) 194 #define CXL_PSL_SERR_An_afudis (1ull << (63-1)) 195 #define CXL_PSL_SERR_An_afuov (1ull << (63-2)) 196 #define CXL_PSL_SERR_An_badsrc (1ull << (63-3)) 197 #define CXL_PSL_SERR_An_badctx (1ull << (63-4)) 198 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5)) 199 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6)) 200 #define CXL_PSL_SERR_An_afupar (1ull << (63-7)) 201 #define CXL_PSL_SERR_An_afudup (1ull << (63-8)) 202 #define CXL_PSL_SERR_An_AE (1ull << (63-30)) 203 204 /****** CXL_PSL_SCNTL_An ****************************************************/ 205 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15)) 206 /* Programming Modes: */ 207 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31)) 208 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31)) 209 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31)) 210 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31)) 211 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31)) 212 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31)) 213 /* Purge Status (ro) */ 214 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39)) 215 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39)) 216 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39)) 217 /* Purge */ 218 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48)) 219 /* Suspend Status (ro) */ 220 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55)) 221 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55)) 222 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55)) 223 /* Suspend Control */ 224 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63)) 225 226 /* AFU Slice Enable Status (ro) */ 227 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2)) 228 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2)) 229 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2)) 230 /* AFU Slice Enable */ 231 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3)) 232 /* AFU Slice Reset status (ro) */ 233 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5)) 234 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5)) 235 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5)) 236 /* AFU Slice Reset */ 237 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7)) 238 239 /****** CXL_SSTP0/1_An ******************************************************/ 240 /* These top bits are for the segment that CONTAINS the segment table */ 241 #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT 242 #define CXL_SSTP0_An_KS (1ull << (63-2)) 243 #define CXL_SSTP0_An_KP (1ull << (63-3)) 244 #define CXL_SSTP0_An_N (1ull << (63-4)) 245 #define CXL_SSTP0_An_L (1ull << (63-5)) 246 #define CXL_SSTP0_An_C (1ull << (63-6)) 247 #define CXL_SSTP0_An_TA (1ull << (63-7)) 248 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */ 249 /* And finally, the virtual address & size of the segment table: */ 250 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */ 251 #define CXL_SSTP0_An_SegTableSize_MASK \ 252 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT) 253 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1) 254 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1)) 255 #define CXL_SSTP1_An_V (1ull << (63-63)) 256 257 /****** CXL_PSL_SLBIE_[An] **************************************************/ 258 /* write: */ 259 #define CXL_SLBIE_C PPC_BIT(36) /* Class */ 260 #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */ 261 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38) 262 #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */ 263 /* read: */ 264 #define CXL_SLBIE_MAX PPC_BITMASK(24, 31) 265 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63) 266 267 /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/ 268 #define CXL_TLB_SLB_P (1ull) /* Pending (read) */ 269 270 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/ 271 #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */ 272 #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */ 273 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */ 274 275 /****** CXL_PSL_AFUSEL ******************************************************/ 276 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */ 277 278 /****** CXL_PSL_DSISR_An ****************************************************/ 279 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */ 280 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */ 281 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */ 282 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */ 283 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR) 284 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */ 285 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */ 286 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */ 287 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC) 288 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */ 289 #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */ 290 #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */ 291 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */ 292 #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */ 293 #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */ 294 295 /****** CXL_PSL_TFC_An ******************************************************/ 296 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */ 297 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */ 298 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */ 299 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */ 300 301 /* cxl_process_element->software_status */ 302 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */ 303 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */ 304 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */ 305 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */ 306 307 /****** CXL_PSL_RXCTL_An (Implementation Specific) ************************** 308 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to 309 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x 310 * of the hang pulse frequency. 311 */ 312 #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL 313 314 /* SPA->sw_command_status */ 315 #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL 316 #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL 317 #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL 318 #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL 319 #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL 320 #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL 321 #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL 322 #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL 323 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL 324 #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL 325 #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL 326 #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL 327 #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL 328 #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL 329 #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL 330 #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL 331 332 #define CXL_MAX_SLICES 4 333 #define MAX_AFU_MMIO_REGS 3 334 335 #define CXL_MODE_TIME_SLICED 0x4 336 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED) 337 338 #define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */ 339 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS) 340 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS) 341 342 enum cxl_context_status { 343 CLOSED, 344 OPENED, 345 STARTED 346 }; 347 348 enum prefault_modes { 349 CXL_PREFAULT_NONE, 350 CXL_PREFAULT_WED, 351 CXL_PREFAULT_ALL, 352 }; 353 354 enum cxl_attrs { 355 CXL_ADAPTER_ATTRS, 356 CXL_AFU_MASTER_ATTRS, 357 CXL_AFU_ATTRS, 358 }; 359 360 struct cxl_sste { 361 __be64 esid_data; 362 __be64 vsid_data; 363 }; 364 365 #define to_cxl_adapter(d) container_of(d, struct cxl, dev) 366 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev) 367 368 struct cxl_afu_native { 369 void __iomem *p1n_mmio; 370 void __iomem *afu_desc_mmio; 371 irq_hw_number_t psl_hwirq; 372 unsigned int psl_virq; 373 struct mutex spa_mutex; 374 /* 375 * Only the first part of the SPA is used for the process element 376 * linked list. The only other part that software needs to worry about 377 * is sw_command_status, which we store a separate pointer to. 378 * Everything else in the SPA is only used by hardware 379 */ 380 struct cxl_process_element *spa; 381 __be64 *sw_command_status; 382 unsigned int spa_size; 383 int spa_order; 384 int spa_max_procs; 385 u64 pp_offset; 386 }; 387 388 struct cxl_afu_guest { 389 struct cxl_afu *parent; 390 u64 handle; 391 phys_addr_t p2n_phys; 392 u64 p2n_size; 393 int max_ints; 394 bool handle_err; 395 struct delayed_work work_err; 396 int previous_state; 397 }; 398 399 struct cxl_afu { 400 struct cxl_afu_native *native; 401 struct cxl_afu_guest *guest; 402 irq_hw_number_t serr_hwirq; 403 unsigned int serr_virq; 404 char *psl_irq_name; 405 char *err_irq_name; 406 void __iomem *p2n_mmio; 407 phys_addr_t psn_phys; 408 u64 pp_size; 409 410 struct cxl *adapter; 411 struct device dev; 412 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d; 413 struct device *chardev_s, *chardev_m, *chardev_d; 414 struct idr contexts_idr; 415 struct dentry *debugfs; 416 struct mutex contexts_lock; 417 spinlock_t afu_cntl_lock; 418 419 /* AFU error buffer fields and bin attribute for sysfs */ 420 u64 eb_len, eb_offset; 421 struct bin_attribute attr_eb; 422 423 /* pointer to the vphb */ 424 struct pci_controller *phb; 425 426 int pp_irqs; 427 int irqs_max; 428 int num_procs; 429 int max_procs_virtualised; 430 int slice; 431 int modes_supported; 432 int current_mode; 433 int crs_num; 434 u64 crs_len; 435 u64 crs_offset; 436 struct list_head crs; 437 enum prefault_modes prefault_mode; 438 bool psa; 439 bool pp_psa; 440 bool enabled; 441 }; 442 443 444 struct cxl_irq_name { 445 struct list_head list; 446 char *name; 447 }; 448 449 struct irq_avail { 450 irq_hw_number_t offset; 451 irq_hw_number_t range; 452 unsigned long *bitmap; 453 }; 454 455 /* 456 * This is a cxl context. If the PSL is in dedicated mode, there will be one 457 * of these per AFU. If in AFU directed there can be lots of these. 458 */ 459 struct cxl_context { 460 struct cxl_afu *afu; 461 462 /* Problem state MMIO */ 463 phys_addr_t psn_phys; 464 u64 psn_size; 465 466 /* Used to unmap any mmaps when force detaching */ 467 struct address_space *mapping; 468 struct mutex mapping_lock; 469 struct page *ff_page; 470 bool mmio_err_ff; 471 bool kernelapi; 472 473 spinlock_t sste_lock; /* Protects segment table entries */ 474 struct cxl_sste *sstp; 475 u64 sstp0, sstp1; 476 unsigned int sst_size, sst_lru; 477 478 wait_queue_head_t wq; 479 /* pid of the group leader associated with the pid */ 480 struct pid *glpid; 481 /* use mm context associated with this pid for ds faults */ 482 struct pid *pid; 483 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */ 484 /* Only used in PR mode */ 485 u64 process_token; 486 487 /* driver private data */ 488 void *priv; 489 490 unsigned long *irq_bitmap; /* Accessed from IRQ context */ 491 struct cxl_irq_ranges irqs; 492 struct list_head irq_names; 493 u64 fault_addr; 494 u64 fault_dsisr; 495 u64 afu_err; 496 497 /* 498 * This status and it's lock pretects start and detach context 499 * from racing. It also prevents detach from racing with 500 * itself 501 */ 502 enum cxl_context_status status; 503 struct mutex status_mutex; 504 505 506 /* XXX: Is it possible to need multiple work items at once? */ 507 struct work_struct fault_work; 508 u64 dsisr; 509 u64 dar; 510 511 struct cxl_process_element *elem; 512 513 /* 514 * pe is the process element handle, assigned by this driver when the 515 * context is initialized. 516 * 517 * external_pe is the PE shown outside of cxl. 518 * On bare-metal, pe=external_pe, because we decide what the handle is. 519 * In a guest, we only find out about the pe used by pHyp when the 520 * context is attached, and that's the value we want to report outside 521 * of cxl. 522 */ 523 int pe; 524 int external_pe; 525 526 u32 irq_count; 527 bool pe_inserted; 528 bool master; 529 bool kernel; 530 bool real_mode; 531 bool pending_irq; 532 bool pending_fault; 533 bool pending_afu_err; 534 535 /* Used by AFU drivers for driver specific event delivery */ 536 struct cxl_afu_driver_ops *afu_driver_ops; 537 atomic_t afu_driver_events; 538 539 struct rcu_head rcu; 540 541 /* 542 * Only used when more interrupts are allocated via 543 * pci_enable_msix_range than are supported in the default context, to 544 * use additional contexts to overcome the limitation. i.e. Mellanox 545 * CX4 only: 546 */ 547 struct list_head extra_irq_contexts; 548 }; 549 550 struct cxl_service_layer_ops { 551 int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev); 552 int (*afu_regs_init)(struct cxl_afu *afu); 553 int (*register_serr_irq)(struct cxl_afu *afu); 554 void (*release_serr_irq)(struct cxl_afu *afu); 555 void (*debugfs_add_adapter_sl_regs)(struct cxl *adapter, struct dentry *dir); 556 void (*debugfs_add_afu_sl_regs)(struct cxl_afu *afu, struct dentry *dir); 557 void (*psl_irq_dump_registers)(struct cxl_context *ctx); 558 void (*err_irq_dump_registers)(struct cxl *adapter); 559 void (*debugfs_stop_trace)(struct cxl *adapter); 560 void (*write_timebase_ctrl)(struct cxl *adapter); 561 u64 (*timebase_read)(struct cxl *adapter); 562 int capi_mode; 563 bool needs_reset_before_disable; 564 int min_pe; 565 }; 566 567 struct cxl_native { 568 u64 afu_desc_off; 569 u64 afu_desc_size; 570 void __iomem *p1_mmio; 571 void __iomem *p2_mmio; 572 irq_hw_number_t err_hwirq; 573 unsigned int err_virq; 574 u64 ps_off; 575 const struct cxl_service_layer_ops *sl_ops; 576 }; 577 578 struct cxl_guest { 579 struct platform_device *pdev; 580 int irq_nranges; 581 struct cdev cdev; 582 irq_hw_number_t irq_base_offset; 583 struct irq_avail *irq_avail; 584 spinlock_t irq_alloc_lock; 585 u64 handle; 586 char *status; 587 u16 vendor; 588 u16 device; 589 u16 subsystem_vendor; 590 u16 subsystem; 591 }; 592 593 struct cxl { 594 struct cxl_native *native; 595 struct cxl_guest *guest; 596 spinlock_t afu_list_lock; 597 struct cxl_afu *afu[CXL_MAX_SLICES]; 598 struct device dev; 599 struct dentry *trace; 600 struct dentry *psl_err_chk; 601 struct dentry *debugfs; 602 char *irq_name; 603 struct bin_attribute cxl_attr; 604 int adapter_num; 605 int user_irqs; 606 u64 ps_size; 607 u16 psl_rev; 608 u16 base_image; 609 u8 vsec_status; 610 u8 caia_major; 611 u8 caia_minor; 612 u8 slices; 613 bool user_image_loaded; 614 bool perst_loads_image; 615 bool perst_select_user; 616 bool perst_same_image; 617 bool psl_timebase_synced; 618 }; 619 620 int cxl_pci_alloc_one_irq(struct cxl *adapter); 621 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq); 622 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num); 623 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter); 624 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq); 625 int cxl_update_image_control(struct cxl *adapter); 626 int cxl_pci_reset(struct cxl *adapter); 627 void cxl_pci_release_afu(struct device *dev); 628 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len); 629 630 /* common == phyp + powernv */ 631 struct cxl_process_element_common { 632 __be32 tid; 633 __be32 pid; 634 __be64 csrp; 635 __be64 aurp0; 636 __be64 aurp1; 637 __be64 sstp0; 638 __be64 sstp1; 639 __be64 amr; 640 u8 reserved3[4]; 641 __be64 wed; 642 } __packed; 643 644 /* just powernv */ 645 struct cxl_process_element { 646 __be64 sr; 647 __be64 SPOffset; 648 __be64 sdr; 649 __be64 haurp; 650 __be32 ctxtime; 651 __be16 ivte_offsets[4]; 652 __be16 ivte_ranges[4]; 653 __be32 lpid; 654 struct cxl_process_element_common common; 655 __be32 software_state; 656 } __packed; 657 658 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu) 659 { 660 struct pci_dev *pdev; 661 662 if (cpu_has_feature(CPU_FTR_HVMODE)) { 663 pdev = to_pci_dev(cxl->dev.parent); 664 return !pci_channel_offline(pdev); 665 } 666 return true; 667 } 668 669 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg) 670 { 671 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); 672 return cxl->native->p1_mmio + cxl_reg_off(reg); 673 } 674 675 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val) 676 { 677 if (likely(cxl_adapter_link_ok(cxl, NULL))) 678 out_be64(_cxl_p1_addr(cxl, reg), val); 679 } 680 681 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg) 682 { 683 if (likely(cxl_adapter_link_ok(cxl, NULL))) 684 return in_be64(_cxl_p1_addr(cxl, reg)); 685 else 686 return ~0ULL; 687 } 688 689 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg) 690 { 691 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); 692 return afu->native->p1n_mmio + cxl_reg_off(reg); 693 } 694 695 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val) 696 { 697 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) 698 out_be64(_cxl_p1n_addr(afu, reg), val); 699 } 700 701 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg) 702 { 703 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) 704 return in_be64(_cxl_p1n_addr(afu, reg)); 705 else 706 return ~0ULL; 707 } 708 709 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg) 710 { 711 return afu->p2n_mmio + cxl_reg_off(reg); 712 } 713 714 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val) 715 { 716 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) 717 out_be64(_cxl_p2n_addr(afu, reg), val); 718 } 719 720 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg) 721 { 722 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) 723 return in_be64(_cxl_p2n_addr(afu, reg)); 724 else 725 return ~0ULL; 726 } 727 728 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, 729 loff_t off, size_t count); 730 731 /* Internal functions wrapped in cxl_base to allow PHB to call them */ 732 bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu); 733 void _cxl_pci_disable_device(struct pci_dev *dev); 734 int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq); 735 int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 736 void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 737 738 struct cxl_calls { 739 void (*cxl_slbia)(struct mm_struct *mm); 740 bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu); 741 void (*cxl_pci_disable_device)(struct pci_dev *dev); 742 int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq); 743 int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type); 744 void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev); 745 746 struct module *owner; 747 }; 748 int register_cxl_calls(struct cxl_calls *calls); 749 void unregister_cxl_calls(struct cxl_calls *calls); 750 int cxl_update_properties(struct device_node *dn, struct property *new_prop); 751 752 void cxl_remove_adapter_nr(struct cxl *adapter); 753 754 int cxl_alloc_spa(struct cxl_afu *afu); 755 void cxl_release_spa(struct cxl_afu *afu); 756 757 dev_t cxl_get_dev(void); 758 int cxl_file_init(void); 759 void cxl_file_exit(void); 760 int cxl_register_adapter(struct cxl *adapter); 761 int cxl_register_afu(struct cxl_afu *afu); 762 int cxl_chardev_d_afu_add(struct cxl_afu *afu); 763 int cxl_chardev_m_afu_add(struct cxl_afu *afu); 764 int cxl_chardev_s_afu_add(struct cxl_afu *afu); 765 void cxl_chardev_afu_remove(struct cxl_afu *afu); 766 767 void cxl_context_detach_all(struct cxl_afu *afu); 768 void cxl_context_free(struct cxl_context *ctx); 769 void cxl_context_detach(struct cxl_context *ctx); 770 771 int cxl_sysfs_adapter_add(struct cxl *adapter); 772 void cxl_sysfs_adapter_remove(struct cxl *adapter); 773 int cxl_sysfs_afu_add(struct cxl_afu *afu); 774 void cxl_sysfs_afu_remove(struct cxl_afu *afu); 775 int cxl_sysfs_afu_m_add(struct cxl_afu *afu); 776 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu); 777 778 struct cxl *cxl_alloc_adapter(void); 779 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice); 780 int cxl_afu_select_best_mode(struct cxl_afu *afu); 781 782 int cxl_native_register_psl_irq(struct cxl_afu *afu); 783 void cxl_native_release_psl_irq(struct cxl_afu *afu); 784 int cxl_native_register_psl_err_irq(struct cxl *adapter); 785 void cxl_native_release_psl_err_irq(struct cxl *adapter); 786 int cxl_native_register_serr_irq(struct cxl_afu *afu); 787 void cxl_native_release_serr_irq(struct cxl_afu *afu); 788 int afu_register_irqs(struct cxl_context *ctx, u32 count); 789 void afu_release_irqs(struct cxl_context *ctx, void *cookie); 790 void afu_irq_name_free(struct cxl_context *ctx); 791 792 int cxl_debugfs_init(void); 793 void cxl_debugfs_exit(void); 794 int cxl_debugfs_adapter_add(struct cxl *adapter); 795 void cxl_debugfs_adapter_remove(struct cxl *adapter); 796 int cxl_debugfs_afu_add(struct cxl_afu *afu); 797 void cxl_debugfs_afu_remove(struct cxl_afu *afu); 798 799 void cxl_handle_fault(struct work_struct *work); 800 void cxl_prefault(struct cxl_context *ctx, u64 wed); 801 802 struct cxl *get_cxl_adapter(int num); 803 int cxl_alloc_sst(struct cxl_context *ctx); 804 void cxl_dump_debug_buffer(void *addr, size_t size); 805 806 void init_cxl_native(void); 807 808 struct cxl_context *cxl_context_alloc(void); 809 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master, 810 struct address_space *mapping); 811 void cxl_context_free(struct cxl_context *ctx); 812 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma); 813 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, 814 irq_handler_t handler, void *cookie, const char *name); 815 void cxl_unmap_irq(unsigned int virq, void *cookie); 816 int __detach_context(struct cxl_context *ctx); 817 818 /* 819 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined 820 * in PAPR. 821 * A word about endianness: a pointer to this structure is passed when 822 * calling the hcall. However, it is not a block of memory filled up by 823 * the hypervisor. The return values are found in registers, and copied 824 * one by one when returning from the hcall. See the end of the call to 825 * plpar_hcall9() in hvCall.S 826 * As a consequence: 827 * - we don't need to do any endianness conversion 828 * - the pid and tid are an exception. They are 32-bit values returned in 829 * the same 64-bit register. So we do need to worry about byte ordering. 830 */ 831 struct cxl_irq_info { 832 u64 dsisr; 833 u64 dar; 834 u64 dsr; 835 #ifndef CONFIG_CPU_LITTLE_ENDIAN 836 u32 pid; 837 u32 tid; 838 #else 839 u32 tid; 840 u32 pid; 841 #endif 842 u64 afu_err; 843 u64 errstat; 844 u64 proc_handle; 845 u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */ 846 }; 847 848 void cxl_assign_psn_space(struct cxl_context *ctx); 849 irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info); 850 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler, 851 void *cookie, irq_hw_number_t *dest_hwirq, 852 unsigned int *dest_virq, const char *name); 853 854 int cxl_check_error(struct cxl_afu *afu); 855 int cxl_afu_slbia(struct cxl_afu *afu); 856 int cxl_tlb_slb_invalidate(struct cxl *adapter); 857 int cxl_afu_disable(struct cxl_afu *afu); 858 int cxl_psl_purge(struct cxl_afu *afu); 859 860 void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir); 861 void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter, struct dentry *dir); 862 void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir); 863 void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx); 864 void cxl_native_err_irq_dump_regs(struct cxl *adapter); 865 void cxl_stop_trace(struct cxl *cxl); 866 int cxl_pci_vphb_add(struct cxl_afu *afu); 867 void cxl_pci_vphb_remove(struct cxl_afu *afu); 868 869 extern struct pci_driver cxl_pci_driver; 870 extern struct platform_driver cxl_of_driver; 871 int afu_allocate_irqs(struct cxl_context *ctx, u32 count); 872 873 int afu_open(struct inode *inode, struct file *file); 874 int afu_release(struct inode *inode, struct file *file); 875 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 876 int afu_mmap(struct file *file, struct vm_area_struct *vm); 877 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll); 878 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off); 879 extern const struct file_operations afu_fops; 880 881 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev); 882 void cxl_guest_remove_adapter(struct cxl *adapter); 883 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np); 884 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np); 885 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len); 886 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len); 887 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np); 888 void cxl_guest_remove_afu(struct cxl_afu *afu); 889 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np); 890 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np); 891 int cxl_guest_add_chardev(struct cxl *adapter); 892 void cxl_guest_remove_chardev(struct cxl *adapter); 893 void cxl_guest_reload_module(struct cxl *adapter); 894 int cxl_of_probe(struct platform_device *pdev); 895 896 struct cxl_backend_ops { 897 struct module *module; 898 int (*adapter_reset)(struct cxl *adapter); 899 int (*alloc_one_irq)(struct cxl *adapter); 900 void (*release_one_irq)(struct cxl *adapter, int hwirq); 901 int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs, 902 struct cxl *adapter, unsigned int num); 903 void (*release_irq_ranges)(struct cxl_irq_ranges *irqs, 904 struct cxl *adapter); 905 int (*setup_irq)(struct cxl *adapter, unsigned int hwirq, 906 unsigned int virq); 907 irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx, 908 u64 dsisr, u64 errstat); 909 irqreturn_t (*psl_interrupt)(int irq, void *data); 910 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask); 911 void (*irq_wait)(struct cxl_context *ctx); 912 int (*attach_process)(struct cxl_context *ctx, bool kernel, 913 u64 wed, u64 amr); 914 int (*detach_process)(struct cxl_context *ctx); 915 void (*update_ivtes)(struct cxl_context *ctx); 916 bool (*support_attributes)(const char *attr_name, enum cxl_attrs type); 917 bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu); 918 void (*release_afu)(struct device *dev); 919 ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf, 920 loff_t off, size_t count); 921 int (*afu_check_and_enable)(struct cxl_afu *afu); 922 int (*afu_activate_mode)(struct cxl_afu *afu, int mode); 923 int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode); 924 int (*afu_reset)(struct cxl_afu *afu); 925 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val); 926 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val); 927 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val); 928 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val); 929 int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val); 930 int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val); 931 int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val); 932 ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count); 933 }; 934 extern const struct cxl_backend_ops cxl_native_ops; 935 extern const struct cxl_backend_ops cxl_guest_ops; 936 extern const struct cxl_backend_ops *cxl_ops; 937 938 /* check if the given pci_dev is on the the cxl vphb bus */ 939 bool cxl_pci_is_vphb_device(struct pci_dev *dev); 940 941 /* decode AFU error bits in the PSL register PSL_SERR_An */ 942 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr); 943 #endif 944