1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Ricky Wu <ricky_wu@realtek.com> 8 */ 9 #ifndef RTS5264_H 10 #define RTS5264_H 11 12 /*New add*/ 13 #define rts5264_vendor_setting_valid(reg) ((reg) & 0x010000) 14 #define rts5264_reg_to_aspm(reg) \ 15 (((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01)) 16 #define rts5264_reg_check_reverse_socket(reg) ((reg) & 0x04) 17 #define rts5264_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) & 0x03) 18 #define rts5264_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) & 0x03) 19 #define rts5264_reg_to_rtd3(reg) ((reg) & 0x08) 20 21 #define RTS5264_AUTOLOAD_CFG0 0xFF7B 22 #define RTS5264_AUTOLOAD_CFG1 0xFF7C 23 #define RTS5264_AUTOLOAD_CFG3 0xFF7E 24 #define RTS5264_AUTOLOAD_CFG4 0xFF7F 25 #define RTS5264_FORCE_PRSNT_LOW (1 << 6) 26 #define RTS5264_AUX_CLK_16M_EN (1 << 5) 27 #define RTS5264_F_HIGH_RC_MASK (1 << 4) 28 #define RTS5264_F_HIGH_RC_1_6M (1 << 4) 29 #define RTS5264_F_HIGH_RC_400K (0 << 4) 30 31 /* SSC_CTL2 0xFC12 */ 32 #define RTS5264_SSC_DEPTH_MASK 0x07 33 #define RTS5264_SSC_DEPTH_DISALBE 0x00 34 #define RTS5264_SSC_DEPTH_8M 0x01 35 #define RTS5264_SSC_DEPTH_4M 0x02 36 #define RTS5264_SSC_DEPTH_2M 0x03 37 #define RTS5264_SSC_DEPTH_1M 0x04 38 #define RTS5264_SSC_DEPTH_512K 0x05 39 #define RTS5264_SSC_DEPTH_256K 0x06 40 #define RTS5264_SSC_DEPTH_128K 0x07 41 42 #define RTS5264_CARD_CLK_SRC2 0xFC2F 43 #define RTS5264_REG_BIG_KVCO_A 0x20 44 45 /* efuse control register*/ 46 #define RTS5264_EFUSE_CTL 0xFC30 47 #define RTS5264_EFUSE_ENABLE 0x80 48 /* EFUSE_MODE: 0=READ 1=PROGRAM */ 49 #define RTS5264_EFUSE_MODE_MASK 0x40 50 #define RTS5264_EFUSE_PROGRAM 0x40 51 52 #define RTS5264_EFUSE_ADDR 0xFC31 53 #define RTS5264_EFUSE_ADDR_MASK 0x3F 54 55 #define RTS5264_EFUSE_WRITE_DATA 0xFC32 56 #define RTS5264_EFUSE_READ_DATA 0xFC34 57 58 #define RTS5264_SYS_DUMMY_1 0xFC35 59 #define RTS5264_REG_BIG_KVCO 0x04 60 61 /* DMACTL 0xFE2C */ 62 #define RTS5264_DMA_PACK_SIZE_MASK 0x70 63 64 #define RTS5264_FW_CFG1 0xFF55 65 #define RTS5264_SYS_CLK_SEL_MCU_CLK (0x01<<7) 66 #define RTS5264_CRC_CLK_SEL_MCU_CLK (0x01<<6) 67 #define RTS5264_FAKE_MCU_CLOCK_GATING (0x01<<5) 68 #define RTS5264_MCU_BUS_SEL_MASK (0x01<<4) 69 70 /* FW status register */ 71 #define RTS5264_FW_STATUS 0xFF56 72 #define RTS5264_EXPRESS_LINK_FAIL_MASK (0x01<<7) 73 74 /* FW control register */ 75 #define RTS5264_FW_CTL 0xFF5F 76 #define RTS5264_INFORM_RTD3_COLD (0x01<<5) 77 78 #define RTS5264_REG_FPDCTL 0xFF60 79 80 #define RTS5264_REG_LDO12_CFG 0xFF6E 81 #define RTS5264_LDO12_SR_MASK (0x03<<6) 82 #define RTS5264_LDO12_SR_1_0_MS (0x03<<6) 83 #define RTS5264_LDO12_SR_0_5_MS (0x02<<6) 84 #define RTS5264_LDO12_SR_0_2_5_MS (0x01<<6) 85 #define RTS5264_LDO12_SR_0_0_MS (0x00<<6) 86 #define RTS5264_LDO12_VO_TUNE_MASK (0x07<<1) 87 #define RTS5264_LDO12_115 (0x03<<1) 88 #define RTS5264_LDO12_120 (0x04<<1) 89 #define RTS5264_LDO12_125 (0x05<<1) 90 #define RTS5264_LDO12_130 (0x06<<1) 91 #define RTS5264_LDO12_135 (0x07<<1) 92 93 /* LDO control register */ 94 #define RTS5264_CARD_PWR_CTL 0xFD50 95 #define RTS5264_SD_CLK_ISO (0x01<<7) 96 #define RTS5264_PAD_SD_DAT_FW_CTRL (0x01<<6) 97 #define RTS5264_PUPDC (0x01<<5) 98 #define RTS5264_SD_CMD_ISO (0x01<<4) 99 100 #define RTS5264_OCP_VDD3_CTL 0xFD89 101 #define SD_VDD3_DETECT_EN 0x08 102 #define SD_VDD3_OCP_INT_EN 0x04 103 #define SD_VDD3_OCP_INT_CLR 0x02 104 #define SD_VDD3_OC_CLR 0x01 105 106 #define RTS5264_OCP_VDD3_STS 0xFD8A 107 #define SD_VDD3_OCP_DETECT 0x08 108 #define SD_VDD3_OC_NOW 0x04 109 #define SD_VDD3_OC_EVER 0x02 110 111 #define RTS5264_OVP_CTL 0xFD8D 112 #define RTS5264_OVP_TIME_MASK 0xF0 113 #define RTS5264_OVP_TIME_DFT 0x50 114 #define RTS5264_OVP_DETECT_EN 0x08 115 #define RTS5264_OVP_INT_EN 0x04 116 #define RTS5264_OVP_INT_CLR 0x02 117 #define RTS5264_OVP_CLR 0x01 118 119 #define RTS5264_OVP_STS 0xFD8E 120 #define RTS5264_OVP_GLTCH_TIME_MASK 0xF0 121 #define RTS5264_OVP_GLTCH_TIME_DFT 0x50 122 #define RTS5264_VOVER_DET 0x08 123 #define RTS5264_OVP_NOW 0x04 124 #define RTS5264_OVP_EVER 0x02 125 126 #define RTS5264_CMD_OE_START_EARLY 0xFDCB 127 #define RTS5264_CMD_OE_EARLY_LEAVE 0x08 128 #define RTS5264_CMD_OE_EARLY_CYCLE_MASK 0x06 129 #define RTS5264_CMD_OE_EARLY_4CYCLE 0x06 130 #define RTS5264_CMD_OE_EARLY_3CYCLE 0x04 131 #define RTS5264_CMD_OE_EARLY_2CYCLE 0x02 132 #define RTS5264_CMD_OE_EARLY_1CYCLE 0x00 133 #define RTS5264_CMD_OE_EARLY_EN 0x01 134 135 #define RTS5264_DAT_OE_START_EARLY 0xFDCC 136 #define RTS5264_DAT_OE_EARLY_LEAVE 0x08 137 #define RTS5264_DAT_OE_EARLY_CYCLE_MASK 0x06 138 #define RTS5264_DAT_OE_EARLY_4CYCLE 0x06 139 #define RTS5264_DAT_OE_EARLY_3CYCLE 0x04 140 #define RTS5264_DAT_OE_EARLY_2CYCLE 0x02 141 #define RTS5264_DAT_OE_EARLY_1CYCLE 0x00 142 #define RTS5264_DAT_OE_EARLY_EN 0x01 143 144 #define RTS5264_LDO1233318_POW_CTL 0xFF70 145 #define RTS5264_TUNE_REF_LDO3318 (0x03<<6) 146 #define RTS5264_TUNE_REF_LDO3318_DFT (0x02<<6) 147 #define RTS5264_LDO3318_POWERON (0x01<<3) 148 #define RTS5264_LDO3_POWERON (0x01<<2) 149 #define RTS5264_LDO2_POWERON (0x01<<1) 150 #define RTS5264_LDO1_POWERON (0x01<<0) 151 #define RTS5264_LDO_POWERON_MASK (0x0F<<0) 152 153 #define RTS5264_DV3318_CFG 0xFF71 154 #define RTS5264_DV3318_TUNE_MASK (0x07<<4) 155 #define RTS5264_DV3318_18 (0x02<<4) 156 #define RTS5264_DV3318_19 (0x04<<4) 157 #define RTS5264_DV3318_33 (0x07<<4) 158 159 #define RTS5264_LDO1_CFG0 0xFF72 160 #define RTS5264_LDO1_OCP_THD_MASK (0x07 << 5) 161 #define RTS5264_LDO1_OCP_EN (0x01 << 4) 162 #define RTS5264_LDO1_OCP_LMT_THD_MASK (0x03 << 2) 163 #define RTS5264_LDO1_OCP_LMT_EN (0x01 << 1) 164 165 #define RTS5264_LDO1_OCP_THD_850 (0x00<<5) 166 #define RTS5264_LDO1_OCP_THD_950 (0x01<<5) 167 #define RTS5264_LDO1_OCP_THD_1050 (0x02<<5) 168 #define RTS5264_LDO1_OCP_THD_1100 (0x03<<5) 169 #define RTS5264_LDO1_OCP_THD_1150 (0x04<<5) 170 #define RTS5264_LDO1_OCP_THD_1200 (0x05<<5) 171 #define RTS5264_LDO1_OCP_THD_1300 (0x06<<5) 172 #define RTS5264_LDO1_OCP_THD_1350 (0x07<<5) 173 174 #define RTS5264_LDO1_LMT_THD_1700 (0x00<<2) 175 #define RTS5264_LDO1_LMT_THD_1800 (0x01<<2) 176 #define RTS5264_LDO1_LMT_THD_1900 (0x02<<2) 177 #define RTS5264_LDO1_LMT_THD_2000 (0x03<<2) 178 179 #define RTS5264_LDO1_CFG1 0xFF73 180 #define RTS5264_LDO1_TUNE_MASK (0x07<<1) 181 #define RTS5264_LDO1_18 (0x05<<1) 182 #define RTS5264_LDO1_33 (0x07<<1) 183 #define RTS5264_LDO1_PWD_MASK (0x01<<0) 184 185 #define RTS5264_LDO2_CFG0 0xFF74 186 #define RTS5264_LDO2_OCP_THD_MASK (0x07<<5) 187 #define RTS5264_LDO2_OCP_EN (0x01<<4) 188 #define RTS5264_LDO2_OCP_LMT_THD_MASK (0x03<<2) 189 #define RTS5264_LDO2_OCP_LMT_EN (0x01<<1) 190 191 #define RTS5264_LDO2_OCP_THD_750 (0x00<<5) 192 #define RTS5264_LDO2_OCP_THD_850 (0x01<<5) 193 #define RTS5264_LDO2_OCP_THD_900 (0x02<<5) 194 #define RTS5264_LDO2_OCP_THD_950 (0x03<<5) 195 #define RTS5264_LDO2_OCP_THD_1050 (0x04<<5) 196 #define RTS5264_LDO2_OCP_THD_1100 (0x05<<5) 197 #define RTS5264_LDO2_OCP_THD_1150 (0x06<<5) 198 #define RTS5264_LDO2_OCP_THD_1200 (0x07<<5) 199 200 #define RTS5264_LDO2_LMT_THD_1700 (0x00<<2) 201 #define RTS5264_LDO2_LMT_THD_1800 (0x01<<2) 202 #define RTS5264_LDO2_LMT_THD_1900 (0x02<<2) 203 #define RTS5264_LDO2_LMT_THD_2000 (0x03<<2) 204 205 #define RTS5264_LDO2_CFG1 0xFF75 206 #define RTS5264_LDO2_TUNE_MASK (0x07<<1) 207 #define RTS5264_LDO2_18 (0x02<<1) 208 #define RTS5264_LDO2_185 (0x03<<1) 209 #define RTS5264_LDO2_19 (0x04<<1) 210 #define RTS5264_LDO2_195 (0x05<<1) 211 #define RTS5264_LDO2_33 (0x07<<1) 212 #define RTS5264_LDO2_PWD_MASK (0x01<<0) 213 214 #define RTS5264_LDO3_CFG0 0xFF76 215 #define RTS5264_LDO3_OCP_THD_MASK (0x07<<5) 216 #define RTS5264_LDO3_OCP_EN (0x01<<4) 217 #define RTS5264_LDO3_OCP_LMT_THD_MASK (0x03<<2) 218 #define RTS5264_LDO3_OCP_LMT_EN (0x01<<1) 219 220 #define RTS5264_LDO3_OCP_THD_610 (0x00<<5) 221 #define RTS5264_LDO3_OCP_THD_630 (0x01<<5) 222 #define RTS5264_LDO3_OCP_THD_670 (0x02<<5) 223 #define RTS5264_LDO3_OCP_THD_710 (0x03<<5) 224 #define RTS5264_LDO3_OCP_THD_750 (0x04<<5) 225 #define RTS5264_LDO3_OCP_THD_770 (0x05<<5) 226 #define RTS5264_LDO3_OCP_THD_810 (0x06<<5) 227 #define RTS5264_LDO3_OCP_THD_850 (0x07<<5) 228 229 #define RTS5264_LDO3_LMT_THD_1200 (0x00<<2) 230 #define RTS5264_LDO3_LMT_THD_1300 (0x01<<2) 231 #define RTS5264_LDO3_LMT_THD_1400 (0x02<<2) 232 #define RTS5264_LDO3_LMT_THD_1500 (0x03<<2) 233 234 #define RTS5264_LDO3_CFG1 0xFF77 235 #define RTS5264_LDO3_TUNE_MASK (0x07<<1) 236 #define RTS5264_LDO3_12 (0x02<<1) 237 #define RTS5264_LDO3_125 (0x03<<1) 238 #define RTS5264_LDO3_13 (0x04<<1) 239 #define RTS5264_LDO3_135 (0x05<<1) 240 #define RTS5264_LDO3_33 (0x07<<1) 241 #define RTS5264_LDO3_PWD_MASK (0x01<<0) 242 243 #define RTS5264_REG_PME_FORCE_CTL 0xFF78 244 #define FORCE_PM_CONTROL 0x20 245 #define FORCE_PM_VALUE 0x10 246 #define REG_EFUSE_BYPASS 0x08 247 #define REG_EFUSE_POR 0x04 248 #define REG_EFUSE_POWER_MASK 0x03 249 #define REG_EFUSE_POWERON 0x03 250 #define REG_EFUSE_POWEROFF 0x00 251 252 #define RTS5264_PWR_CUT 0xFF81 253 #define RTS5264_CFG_MEM_PD 0xF0 254 255 #define RTS5264_OVP_DET 0xFF8A 256 #define RTS5264_POW_VDET 0x04 257 #define RTS5264_TUNE_VROV_MASK 0x03 258 #define RTS5264_TUNE_VROV_2V 0x03 259 #define RTS5264_TUNE_VROV_1V8 0x02 260 #define RTS5264_TUNE_VROV_1V6 0x01 261 #define RTS5264_TUNE_VROV_1V4 0x00 262 263 #define RTS5264_CKMUX_MBIAS_PWR 0xFF8B 264 #define RTS5264_NON_XTAL_SEL 0x80 265 #define RTS5264_POW_CKMUX 0x40 266 #define RTS5264_LVD_MASK 0x04 267 #define RTS5264_POW_PSW_MASK 0x03 268 #define RTS5264_POW_PSW_DFT 0x03 269 270 /* Single LUN, support SD/SD EXPRESS */ 271 #define DEFAULT_SINGLE 0 272 #define SD_LUN 1 273 #define SD_EXPRESS_LUN 2 274 275 int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 276 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); 277 278 #endif /* RTS5264_H */ 279