1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/delay.h> 12 #include <linux/rtsx_pci.h> 13 14 #include "rtsx_pcr.h" 15 16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) 17 { 18 u8 val; 19 20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 21 return val & 0x0F; 22 } 23 24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 25 { 26 u8 driving_3v3[4][3] = { 27 {0x11, 0x11, 0x18}, 28 {0x55, 0x55, 0x5C}, 29 {0xFF, 0xFF, 0xFF}, 30 {0x96, 0x96, 0x96}, 31 }; 32 u8 driving_1v8[4][3] = { 33 {0xC4, 0xC4, 0xC4}, 34 {0x3C, 0x3C, 0x3C}, 35 {0xFE, 0xFE, 0xFE}, 36 {0xB3, 0xB3, 0xB3}, 37 }; 38 u8 (*driving)[3], drive_sel; 39 40 if (voltage == OUTPUT_3V3) { 41 driving = driving_3v3; 42 drive_sel = pcr->sd30_drive_sel_3v3; 43 } else { 44 driving = driving_1v8; 45 drive_sel = pcr->sd30_drive_sel_1v8; 46 } 47 48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, 49 0xFF, driving[drive_sel][0]); 50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, 51 0xFF, driving[drive_sel][1]); 52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, 53 0xFF, driving[drive_sel][2]); 54 } 55 56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) 57 { 58 u32 reg; 59 60 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 61 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 62 63 if (!rtsx_vendor_setting_valid(reg)) { 64 pcr_dbg(pcr, "skip fetch vendor setting\n"); 65 return; 66 } 67 68 pcr->aspm_en = rtsx_reg_to_aspm(reg); 69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); 70 pcr->card_drive_sel &= 0x3F; 71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); 72 73 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); 74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 75 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); 76 if (rtsx_reg_check_reverse_socket(reg)) 77 pcr->flags |= PCR_REVERSE_SOCKET; 78 } 79 80 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 81 { 82 /* Set relink_time to 0 */ 83 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0); 84 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0); 85 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0); 86 87 if (pm_state == HOST_ENTER_S3) 88 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 89 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 90 91 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03); 92 } 93 94 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) 95 { 96 struct rtsx_cr_option *option = &(pcr->option); 97 u32 lval; 98 99 if (CHK_PCI_PID(pcr, PID_524A)) 100 rtsx_pci_read_config_dword(pcr, 101 PCR_ASPM_SETTING_REG1, &lval); 102 else 103 rtsx_pci_read_config_dword(pcr, 104 PCR_ASPM_SETTING_REG2, &lval); 105 106 if (lval & ASPM_L1_1_EN_MASK) 107 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 108 109 if (lval & ASPM_L1_2_EN_MASK) 110 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 111 112 if (lval & PM_L1_1_EN_MASK) 113 rtsx_set_dev_flag(pcr, PM_L1_1_EN); 114 115 if (lval & PM_L1_2_EN_MASK) 116 rtsx_set_dev_flag(pcr, PM_L1_2_EN); 117 118 if (option->ltr_en) { 119 u16 val; 120 121 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); 122 if (val & PCI_EXP_DEVCTL2_LTR_EN) { 123 option->ltr_enabled = true; 124 option->ltr_active = true; 125 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 126 } else { 127 option->ltr_enabled = false; 128 } 129 } 130 } 131 132 static int rts5249_init_from_hw(struct rtsx_pcr *pcr) 133 { 134 struct rtsx_cr_option *option = &(pcr->option); 135 136 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 137 | PM_L1_1_EN | PM_L1_2_EN)) 138 option->force_clkreq_0 = false; 139 else 140 option->force_clkreq_0 = true; 141 142 return 0; 143 } 144 145 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) 146 { 147 struct rtsx_cr_option *option = &(pcr->option); 148 149 rts5249_init_from_cfg(pcr); 150 rts5249_init_from_hw(pcr); 151 152 rtsx_pci_init_cmd(pcr); 153 154 /* Rest L1SUB Config */ 155 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); 156 /* Configure GPIO as output */ 157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); 158 /* Reset ASPM state to default value */ 159 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); 160 /* Switch LDO3318 source from DV33 to card_3v3 */ 161 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); 162 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); 163 /* LED shine disabled, set initial shine cycle period */ 164 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); 165 /* Configure driving */ 166 rts5249_fill_driving(pcr, OUTPUT_3V3); 167 if (pcr->flags & PCR_REVERSE_SOCKET) 168 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); 169 else 170 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); 171 172 /* 173 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 174 * to drive low, and we forcibly request clock. 175 */ 176 if (option->force_clkreq_0) 177 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 178 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 179 else 180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 181 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 182 183 return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); 184 } 185 186 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) 187 { 188 int err; 189 190 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); 191 if (err < 0) 192 return err; 193 194 err = rtsx_pci_write_phy_register(pcr, PHY_REV, 195 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED | 196 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN | 197 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST | 198 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD | 199 PHY_REV_STOP_CLKWR); 200 if (err < 0) 201 return err; 202 203 msleep(1); 204 205 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, 206 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL | 207 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN); 208 if (err < 0) 209 return err; 210 211 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, 212 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 213 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | 214 PHY_PCR_RSSI_EN | PHY_PCR_RX10K); 215 if (err < 0) 216 return err; 217 218 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, 219 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR | 220 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 | 221 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE); 222 if (err < 0) 223 return err; 224 225 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, 226 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF | 227 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA | 228 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER | 229 PHY_FLD4_BER_CHK_EN); 230 if (err < 0) 231 return err; 232 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, 233 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD); 234 if (err < 0) 235 return err; 236 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, 237 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE); 238 if (err < 0) 239 return err; 240 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, 241 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 | 242 PHY_FLD3_RXDELINK); 243 if (err < 0) 244 return err; 245 246 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, 247 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 | 248 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 | 249 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12); 250 } 251 252 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) 253 { 254 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); 255 } 256 257 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) 258 { 259 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); 260 } 261 262 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) 263 { 264 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); 265 } 266 267 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) 268 { 269 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); 270 } 271 272 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) 273 { 274 int err; 275 struct rtsx_cr_option *option = &pcr->option; 276 277 if (option->ocp_en) 278 rtsx_pci_enable_ocp(pcr); 279 280 rtsx_pci_init_cmd(pcr); 281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 282 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON); 283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 284 LDO3318_PWR_MASK, 0x02); 285 err = rtsx_pci_send_cmd(pcr, 100); 286 if (err < 0) 287 return err; 288 289 msleep(5); 290 291 rtsx_pci_init_cmd(pcr); 292 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 293 SD_POWER_MASK, SD_VCC_POWER_ON); 294 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 295 LDO3318_PWR_MASK, 0x06); 296 return rtsx_pci_send_cmd(pcr, 100); 297 } 298 299 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) 300 { 301 struct rtsx_cr_option *option = &pcr->option; 302 303 if (option->ocp_en) 304 rtsx_pci_disable_ocp(pcr); 305 306 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); 307 308 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); 309 return 0; 310 } 311 312 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 313 { 314 int err; 315 u16 append; 316 317 switch (voltage) { 318 case OUTPUT_3V3: 319 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 320 PHY_TUNE_VOLTAGE_3V3); 321 if (err < 0) 322 return err; 323 break; 324 case OUTPUT_1V8: 325 append = PHY_TUNE_D18_1V8; 326 if (CHK_PCI_PID(pcr, 0x5249)) { 327 err = rtsx_pci_update_phy(pcr, PHY_BACR, 328 PHY_BACR_BASIC_MASK, 0); 329 if (err < 0) 330 return err; 331 append = PHY_TUNE_D18_1V7; 332 } 333 334 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 335 append); 336 if (err < 0) 337 return err; 338 break; 339 default: 340 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); 341 return -EINVAL; 342 } 343 344 /* set pad drive */ 345 rtsx_pci_init_cmd(pcr); 346 rts5249_fill_driving(pcr, voltage); 347 return rtsx_pci_send_cmd(pcr, 100); 348 } 349 350 static const struct pcr_ops rts5249_pcr_ops = { 351 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 352 .extra_init_hw = rts5249_extra_init_hw, 353 .optimize_phy = rts5249_optimize_phy, 354 .turn_on_led = rtsx_base_turn_on_led, 355 .turn_off_led = rtsx_base_turn_off_led, 356 .enable_auto_blink = rtsx_base_enable_auto_blink, 357 .disable_auto_blink = rtsx_base_disable_auto_blink, 358 .card_power_on = rtsx_base_card_power_on, 359 .card_power_off = rtsx_base_card_power_off, 360 .switch_output_voltage = rtsx_base_switch_output_voltage, 361 .force_power_down = rtsx_base_force_power_down, 362 }; 363 364 /* SD Pull Control Enable: 365 * SD_DAT[3:0] ==> pull up 366 * SD_CD ==> pull up 367 * SD_WP ==> pull up 368 * SD_CMD ==> pull up 369 * SD_CLK ==> pull down 370 */ 371 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = { 372 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 373 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 374 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 375 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA), 376 0, 377 }; 378 379 /* SD Pull Control Disable: 380 * SD_DAT[3:0] ==> pull down 381 * SD_CD ==> pull up 382 * SD_WP ==> pull down 383 * SD_CMD ==> pull down 384 * SD_CLK ==> pull down 385 */ 386 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = { 387 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 388 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 389 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 390 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 391 0, 392 }; 393 394 /* MS Pull Control Enable: 395 * MS CD ==> pull up 396 * others ==> pull down 397 */ 398 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = { 399 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 400 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 401 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 402 0, 403 }; 404 405 /* MS Pull Control Disable: 406 * MS CD ==> pull up 407 * others ==> pull down 408 */ 409 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = { 410 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 411 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 412 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 413 0, 414 }; 415 416 void rts5249_init_params(struct rtsx_pcr *pcr) 417 { 418 struct rtsx_cr_option *option = &(pcr->option); 419 420 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 421 pcr->num_slots = 2; 422 pcr->ops = &rts5249_pcr_ops; 423 424 pcr->flags = 0; 425 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 426 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 427 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 428 pcr->aspm_en = ASPM_L1_EN; 429 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); 430 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 431 432 pcr->ic_version = rts5249_get_ic_version(pcr); 433 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; 434 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; 435 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; 436 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; 437 438 pcr->reg_pm_ctrl3 = PM_CTRL3; 439 440 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 441 | LTR_L1SS_PWR_GATE_EN); 442 option->ltr_en = true; 443 444 /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 445 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 446 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 447 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 448 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 449 option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF; 450 option->ltr_l1off_snooze_sspwrgate = 451 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF; 452 } 453 454 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) 455 { 456 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 457 458 return __rtsx_pci_write_phy_register(pcr, addr, val); 459 } 460 461 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) 462 { 463 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 464 465 return __rtsx_pci_read_phy_register(pcr, addr, val); 466 } 467 468 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) 469 { 470 int err; 471 472 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 473 D3_DELINK_MODE_EN, 0x00); 474 if (err < 0) 475 return err; 476 477 rtsx_pci_write_phy_register(pcr, PHY_PCR, 478 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 479 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN); 480 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 481 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 482 483 if (is_version(pcr, 0x524A, IC_VER_A)) { 484 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 485 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 486 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, 487 PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 | 488 PHY_SSCCR2_TIME2_WIDTH); 489 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, 490 PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST | 491 PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV); 492 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, 493 PHY_ANA1D_DEBUG_ADDR); 494 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, 495 PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 | 496 PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST | 497 PHY_DIG1E_RCLK_TX_EN_KEEP | 498 PHY_DIG1E_RCLK_TX_TERM_KEEP | 499 PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP | 500 PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP | 501 PHY_DIG1E_RX_EN_KEEP); 502 } 503 504 rtsx_pci_write_phy_register(pcr, PHY_ANA08, 505 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN | 506 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI); 507 508 return 0; 509 } 510 511 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) 512 { 513 rts5249_extra_init_hw(pcr); 514 515 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 516 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN); 517 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 518 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, 519 LDO_VCC_LMT_EN); 520 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 521 if (is_version(pcr, 0x524A, IC_VER_A)) { 522 rtsx_pci_write_register(pcr, LDO_DV18_CFG, 523 LDO_DV18_SR_MASK, LDO_DV18_SR_DF); 524 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 525 LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2); 526 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 527 LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2); 528 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 529 LDO_VIO_SR_MASK, LDO_VIO_SR_DF); 530 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 531 LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF); 532 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, 533 SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7); 534 } 535 536 return 0; 537 } 538 539 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 540 { 541 struct rtsx_cr_option *option = &(pcr->option); 542 543 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); 544 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST); 545 int aspm_L1_1, aspm_L1_2; 546 u8 val = 0; 547 548 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 549 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 550 551 if (active) { 552 /* Run, latency: 60us */ 553 if (aspm_L1_1) 554 val = option->ltr_l1off_snooze_sspwrgate; 555 } else { 556 /* L1off, latency: 300us */ 557 if (aspm_L1_2) 558 val = option->ltr_l1off_sspwrgate; 559 } 560 561 if (aspm_L1_1 || aspm_L1_2) { 562 if (rtsx_check_dev_flag(pcr, 563 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) { 564 if (card_exist) 565 val &= ~L1OFF_MBIAS2_EN_5250; 566 else 567 val |= L1OFF_MBIAS2_EN_5250; 568 } 569 } 570 rtsx_set_l1off_sub(pcr, val); 571 } 572 573 static const struct pcr_ops rts524a_pcr_ops = { 574 .write_phy = rts524a_write_phy, 575 .read_phy = rts524a_read_phy, 576 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 577 .extra_init_hw = rts524a_extra_init_hw, 578 .optimize_phy = rts524a_optimize_phy, 579 .turn_on_led = rtsx_base_turn_on_led, 580 .turn_off_led = rtsx_base_turn_off_led, 581 .enable_auto_blink = rtsx_base_enable_auto_blink, 582 .disable_auto_blink = rtsx_base_disable_auto_blink, 583 .card_power_on = rtsx_base_card_power_on, 584 .card_power_off = rtsx_base_card_power_off, 585 .switch_output_voltage = rtsx_base_switch_output_voltage, 586 .force_power_down = rtsx_base_force_power_down, 587 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 588 }; 589 590 void rts524a_init_params(struct rtsx_pcr *pcr) 591 { 592 rts5249_init_params(pcr); 593 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); 594 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 595 pcr->option.ltr_l1off_snooze_sspwrgate = 596 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 597 598 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 599 pcr->ops = &rts524a_pcr_ops; 600 601 pcr->option.ocp_en = 1; 602 if (pcr->option.ocp_en) 603 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 604 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 605 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; 606 607 } 608 609 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) 610 { 611 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 612 LDO_VCC_TUNE_MASK, LDO_VCC_3V3); 613 return rtsx_base_card_power_on(pcr, card); 614 } 615 616 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 617 { 618 switch (voltage) { 619 case OUTPUT_3V3: 620 rtsx_pci_write_register(pcr, LDO_CONFIG2, 621 LDO_D3318_MASK, LDO_D3318_33V); 622 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); 623 break; 624 case OUTPUT_1V8: 625 rtsx_pci_write_register(pcr, LDO_CONFIG2, 626 LDO_D3318_MASK, LDO_D3318_18V); 627 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 628 SD_IO_USING_1V8); 629 break; 630 default: 631 return -EINVAL; 632 } 633 634 rtsx_pci_init_cmd(pcr); 635 rts5249_fill_driving(pcr, voltage); 636 return rtsx_pci_send_cmd(pcr, 100); 637 } 638 639 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) 640 { 641 int err; 642 643 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 644 D3_DELINK_MODE_EN, 0x00); 645 if (err < 0) 646 return err; 647 648 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, 649 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN | 650 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT | 651 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN); 652 653 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, 654 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN | 655 _PHY_CMU_DEBUG_EN); 656 657 if (is_version(pcr, 0x525A, IC_VER_A)) 658 rtsx_pci_write_phy_register(pcr, _PHY_REV0, 659 _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD | 660 _PHY_REV0_CDR_RX_IDLE_BYPASS); 661 662 return 0; 663 } 664 665 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) 666 { 667 rts5249_extra_init_hw(pcr); 668 669 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 670 if (is_version(pcr, 0x525A, IC_VER_A)) { 671 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, 672 L1SUB_AUTO_CFG, L1SUB_AUTO_CFG); 673 rtsx_pci_write_register(pcr, RREF_CFG, 674 RREF_VBGSEL_MASK, RREF_VBGSEL_1V25); 675 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 676 LDO_VIO_TUNE_MASK, LDO_VIO_1V7); 677 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 678 LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF); 679 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, 680 LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF); 681 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 682 LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A); 683 rtsx_pci_write_register(pcr, OOBS_CONFIG, 684 OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89); 685 } 686 687 return 0; 688 } 689 690 static const struct pcr_ops rts525a_pcr_ops = { 691 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 692 .extra_init_hw = rts525a_extra_init_hw, 693 .optimize_phy = rts525a_optimize_phy, 694 .turn_on_led = rtsx_base_turn_on_led, 695 .turn_off_led = rtsx_base_turn_off_led, 696 .enable_auto_blink = rtsx_base_enable_auto_blink, 697 .disable_auto_blink = rtsx_base_disable_auto_blink, 698 .card_power_on = rts525a_card_power_on, 699 .card_power_off = rtsx_base_card_power_off, 700 .switch_output_voltage = rts525a_switch_output_voltage, 701 .force_power_down = rtsx_base_force_power_down, 702 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 703 }; 704 705 void rts525a_init_params(struct rtsx_pcr *pcr) 706 { 707 rts5249_init_params(pcr); 708 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); 709 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 710 pcr->option.ltr_l1off_snooze_sspwrgate = 711 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 712 713 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 714 pcr->ops = &rts525a_pcr_ops; 715 716 pcr->option.ocp_en = 1; 717 if (pcr->option.ocp_en) 718 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 719 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 720 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; 721 } 722